STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_i2c.h 00004 * @author MCD Application Team 00005 * @brief Header file of I2C LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_I2C_H 00038 #define __STM32L4xx_LL_I2C_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4) 00052 00053 /** @defgroup I2C_LL I2C 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 00060 /* Private constants ---------------------------------------------------------*/ 00061 /** @defgroup I2C_LL_Private_Constants I2C Private Constants 00062 * @{ 00063 */ 00064 /** 00065 * @} 00066 */ 00067 00068 /* Private macros ------------------------------------------------------------*/ 00069 #if defined(USE_FULL_LL_DRIVER) 00070 /** @defgroup I2C_LL_Private_Macros I2C Private Macros 00071 * @{ 00072 */ 00073 /** 00074 * @} 00075 */ 00076 #endif /*USE_FULL_LL_DRIVER*/ 00077 00078 /* Exported types ------------------------------------------------------------*/ 00079 #if defined(USE_FULL_LL_DRIVER) 00080 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure 00081 * @{ 00082 */ 00083 typedef struct 00084 { 00085 uint32_t PeripheralMode; /*!< Specifies the peripheral mode. 00086 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE 00087 00088 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ 00089 00090 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values. 00091 This parameter must be set by referring to the STM32CubeMX Tool and 00092 the helper macro @ref __LL_I2C_CONVERT_TIMINGS() 00093 00094 This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */ 00095 00096 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. 00097 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION 00098 00099 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ 00100 00101 uint32_t DigitalFilter; /*!< Configures the digital noise filter. 00102 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F 00103 00104 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ 00105 00106 uint32_t OwnAddress1; /*!< Specifies the device own address 1. 00107 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF 00108 00109 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ 00110 00111 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. 00112 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE 00113 00114 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ 00115 00116 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). 00117 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 00118 00119 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ 00120 } LL_I2C_InitTypeDef; 00121 /** 00122 * @} 00123 */ 00124 #endif /*USE_FULL_LL_DRIVER*/ 00125 00126 /* Exported constants --------------------------------------------------------*/ 00127 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants 00128 * @{ 00129 */ 00130 00131 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines 00132 * @brief Flags defines which can be used with LL_I2C_WriteReg function 00133 * @{ 00134 */ 00135 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */ 00136 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */ 00137 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */ 00138 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */ 00139 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */ 00140 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */ 00141 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */ 00142 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */ 00143 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */ 00144 /** 00145 * @} 00146 */ 00147 00148 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines 00149 * @brief Flags defines which can be used with LL_I2C_ReadReg function 00150 * @{ 00151 */ 00152 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */ 00153 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */ 00154 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */ 00155 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */ 00156 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */ 00157 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */ 00158 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */ 00159 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */ 00160 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */ 00161 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */ 00162 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */ 00163 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ 00164 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ 00165 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */ 00166 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */ 00167 /** 00168 * @} 00169 */ 00170 00171 /** @defgroup I2C_LL_EC_IT IT Defines 00172 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions 00173 * @{ 00174 */ 00175 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */ 00176 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */ 00177 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */ 00178 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */ 00179 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */ 00180 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */ 00181 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */ 00182 /** 00183 * @} 00184 */ 00185 00186 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode 00187 * @{ 00188 */ 00189 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ 00190 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */ 00191 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */ 00192 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */ 00193 /** 00194 * @} 00195 */ 00196 00197 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection 00198 * @{ 00199 */ 00200 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ 00201 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */ 00202 /** 00203 * @} 00204 */ 00205 00206 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode 00207 * @{ 00208 */ 00209 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */ 00210 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/ 00211 /** 00212 * @} 00213 */ 00214 00215 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length 00216 * @{ 00217 */ 00218 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */ 00219 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/ 00220 /** 00221 * @} 00222 */ 00223 00224 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks 00225 * @{ 00226 */ 00227 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */ 00228 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */ 00229 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */ 00230 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */ 00231 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */ 00232 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */ 00233 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */ 00234 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/ 00235 /** 00236 * @} 00237 */ 00238 00239 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation 00240 * @{ 00241 */ 00242 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */ 00243 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/ 00244 /** 00245 * @} 00246 */ 00247 00248 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length 00249 * @{ 00250 */ 00251 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */ 00252 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/ 00253 /** 00254 * @} 00255 */ 00256 00257 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction 00258 * @{ 00259 */ 00260 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */ 00261 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */ 00262 /** 00263 * @} 00264 */ 00265 00266 /** @defgroup I2C_LL_EC_MODE Transfer End Mode 00267 * @{ 00268 */ 00269 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */ 00270 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */ 00271 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */ 00272 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ 00273 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ 00274 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */ 00275 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */ 00276 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */ 00277 /** 00278 * @} 00279 */ 00280 00281 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation 00282 * @{ 00283 */ 00284 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */ 00285 #define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */ 00286 #define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */ 00287 #define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */ 00288 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */ 00289 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */ 00290 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */ 00291 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/ 00292 /** 00293 * @} 00294 */ 00295 00296 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction 00297 * @{ 00298 */ 00299 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */ 00300 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/ 00301 /** 00302 * @} 00303 */ 00304 00305 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data 00306 * @{ 00307 */ 00308 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ 00309 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ 00310 /** 00311 * @} 00312 */ 00313 00314 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout 00315 * @{ 00316 */ 00317 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */ 00318 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/ 00319 /** 00320 * @} 00321 */ 00322 00323 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection 00324 * @{ 00325 */ 00326 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */ 00327 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */ 00328 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */ 00329 /** 00330 * @} 00331 */ 00332 00333 /** 00334 * @} 00335 */ 00336 00337 /* Exported macro ------------------------------------------------------------*/ 00338 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros 00339 * @{ 00340 */ 00341 00342 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros 00343 * @{ 00344 */ 00345 00346 /** 00347 * @brief Write a value in I2C register 00348 * @param __INSTANCE__ I2C Instance 00349 * @param __REG__ Register to be written 00350 * @param __VALUE__ Value to be written in the register 00351 * @retval None 00352 */ 00353 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00354 00355 /** 00356 * @brief Read a value in I2C register 00357 * @param __INSTANCE__ I2C Instance 00358 * @param __REG__ Register to be read 00359 * @retval Register value 00360 */ 00361 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00362 /** 00363 * @} 00364 */ 00365 00366 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings 00367 * @{ 00368 */ 00369 /** 00370 * @brief Configure the SDA setup, hold time and the SCL high, low period. 00371 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. 00372 * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc) 00373 * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc) 00374 * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc) 00375 * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc) 00376 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF 00377 */ 00378 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \ 00379 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \ 00380 (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \ 00381 (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \ 00382 (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \ 00383 (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL)) 00384 /** 00385 * @} 00386 */ 00387 00388 /** 00389 * @} 00390 */ 00391 00392 /* Exported functions --------------------------------------------------------*/ 00393 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions 00394 * @{ 00395 */ 00396 00397 /** @defgroup I2C_LL_EF_Configuration Configuration 00398 * @{ 00399 */ 00400 00401 /** 00402 * @brief Enable I2C peripheral (PE = 1). 00403 * @rmtoll CR1 PE LL_I2C_Enable 00404 * @param I2Cx I2C Instance. 00405 * @retval None 00406 */ 00407 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) 00408 { 00409 SET_BIT(I2Cx->CR1, I2C_CR1_PE); 00410 } 00411 00412 /** 00413 * @brief Disable I2C peripheral (PE = 0). 00414 * @note When PE = 0, the I2C SCL and SDA lines are released. 00415 * Internal state machines and status bits are put back to their reset value. 00416 * When cleared, PE must be kept low for at least 3 APB clock cycles. 00417 * @rmtoll CR1 PE LL_I2C_Disable 00418 * @param I2Cx I2C Instance. 00419 * @retval None 00420 */ 00421 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) 00422 { 00423 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); 00424 } 00425 00426 /** 00427 * @brief Check if the I2C peripheral is enabled or disabled. 00428 * @rmtoll CR1 PE LL_I2C_IsEnabled 00429 * @param I2Cx I2C Instance. 00430 * @retval State of bit (1 or 0). 00431 */ 00432 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) 00433 { 00434 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); 00435 } 00436 00437 /** 00438 * @brief Configure Noise Filters (Analog and Digital). 00439 * @note If the analog filter is also enabled, the digital filter is added to analog filter. 00440 * The filters can only be programmed when the I2C is disabled (PE = 0). 00441 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n 00442 * CR1 DNF LL_I2C_ConfigFilters 00443 * @param I2Cx I2C Instance. 00444 * @param AnalogFilter This parameter can be one of the following values: 00445 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE 00446 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE 00447 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). 00448 * This parameter is used to configure the digital noise filter on SDA and SCL input. 00449 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. 00450 * @retval None 00451 */ 00452 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) 00453 { 00454 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos)); 00455 } 00456 00457 /** 00458 * @brief Configure Digital Noise Filter. 00459 * @note If the analog filter is also enabled, the digital filter is added to analog filter. 00460 * This filter can only be programmed when the I2C is disabled (PE = 0). 00461 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter 00462 * @param I2Cx I2C Instance. 00463 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk). 00464 * This parameter is used to configure the digital noise filter on SDA and SCL input. 00465 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk. 00466 * @retval None 00467 */ 00468 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) 00469 { 00470 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos); 00471 } 00472 00473 /** 00474 * @brief Get the current Digital Noise Filter configuration. 00475 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter 00476 * @param I2Cx I2C Instance. 00477 * @retval Value between Min_Data=0x0 and Max_Data=0xF 00478 */ 00479 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) 00480 { 00481 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos); 00482 } 00483 00484 /** 00485 * @brief Enable Analog Noise Filter. 00486 * @note This filter can only be programmed when the I2C is disabled (PE = 0). 00487 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter 00488 * @param I2Cx I2C Instance. 00489 * @retval None 00490 */ 00491 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) 00492 { 00493 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); 00494 } 00495 00496 /** 00497 * @brief Disable Analog Noise Filter. 00498 * @note This filter can only be programmed when the I2C is disabled (PE = 0). 00499 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter 00500 * @param I2Cx I2C Instance. 00501 * @retval None 00502 */ 00503 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) 00504 { 00505 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF); 00506 } 00507 00508 /** 00509 * @brief Check if Analog Noise Filter is enabled or disabled. 00510 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter 00511 * @param I2Cx I2C Instance. 00512 * @retval State of bit (1 or 0). 00513 */ 00514 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) 00515 { 00516 return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)); 00517 } 00518 00519 /** 00520 * @brief Enable DMA transmission requests. 00521 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX 00522 * @param I2Cx I2C Instance. 00523 * @retval None 00524 */ 00525 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) 00526 { 00527 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); 00528 } 00529 00530 /** 00531 * @brief Disable DMA transmission requests. 00532 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX 00533 * @param I2Cx I2C Instance. 00534 * @retval None 00535 */ 00536 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) 00537 { 00538 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN); 00539 } 00540 00541 /** 00542 * @brief Check if DMA transmission requests are enabled or disabled. 00543 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX 00544 * @param I2Cx I2C Instance. 00545 * @retval State of bit (1 or 0). 00546 */ 00547 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) 00548 { 00549 return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)); 00550 } 00551 00552 /** 00553 * @brief Enable DMA reception requests. 00554 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX 00555 * @param I2Cx I2C Instance. 00556 * @retval None 00557 */ 00558 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) 00559 { 00560 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); 00561 } 00562 00563 /** 00564 * @brief Disable DMA reception requests. 00565 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX 00566 * @param I2Cx I2C Instance. 00567 * @retval None 00568 */ 00569 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) 00570 { 00571 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN); 00572 } 00573 00574 /** 00575 * @brief Check if DMA reception requests are enabled or disabled. 00576 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX 00577 * @param I2Cx I2C Instance. 00578 * @retval State of bit (1 or 0). 00579 */ 00580 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) 00581 { 00582 return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)); 00583 } 00584 00585 /** 00586 * @brief Get the data register address used for DMA transfer 00587 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n 00588 * RXDR RXDATA LL_I2C_DMA_GetRegAddr 00589 * @param I2Cx I2C Instance 00590 * @param Direction This parameter can be one of the following values: 00591 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT 00592 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE 00593 * @retval Address of data register 00594 */ 00595 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction) 00596 { 00597 register uint32_t data_reg_addr; 00598 00599 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT) 00600 { 00601 /* return address of TXDR register */ 00602 data_reg_addr = (uint32_t) & (I2Cx->TXDR); 00603 } 00604 else 00605 { 00606 /* return address of RXDR register */ 00607 data_reg_addr = (uint32_t) & (I2Cx->RXDR); 00608 } 00609 00610 return data_reg_addr; 00611 } 00612 00613 /** 00614 * @brief Enable Clock stretching. 00615 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 00616 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching 00617 * @param I2Cx I2C Instance. 00618 * @retval None 00619 */ 00620 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) 00621 { 00622 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); 00623 } 00624 00625 /** 00626 * @brief Disable Clock stretching. 00627 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 00628 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching 00629 * @param I2Cx I2C Instance. 00630 * @retval None 00631 */ 00632 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) 00633 { 00634 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); 00635 } 00636 00637 /** 00638 * @brief Check if Clock stretching is enabled or disabled. 00639 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching 00640 * @param I2Cx I2C Instance. 00641 * @retval State of bit (1 or 0). 00642 */ 00643 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) 00644 { 00645 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); 00646 } 00647 00648 /** 00649 * @brief Enable hardware byte control in slave mode. 00650 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl 00651 * @param I2Cx I2C Instance. 00652 * @retval None 00653 */ 00654 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx) 00655 { 00656 SET_BIT(I2Cx->CR1, I2C_CR1_SBC); 00657 } 00658 00659 /** 00660 * @brief Disable hardware byte control in slave mode. 00661 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl 00662 * @param I2Cx I2C Instance. 00663 * @retval None 00664 */ 00665 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx) 00666 { 00667 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC); 00668 } 00669 00670 /** 00671 * @brief Check if hardware byte control in slave mode is enabled or disabled. 00672 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl 00673 * @param I2Cx I2C Instance. 00674 * @retval State of bit (1 or 0). 00675 */ 00676 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx) 00677 { 00678 return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)); 00679 } 00680 00681 /** 00682 * @brief Enable Wakeup from STOP. 00683 * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not 00684 * WakeUpFromStop feature is supported by the I2Cx Instance. 00685 * @note This bit can only be programmed when Digital Filter is disabled. 00686 * @rmtoll CR1 WUPEN LL_I2C_EnableWakeUpFromStop 00687 * @param I2Cx I2C Instance. 00688 * @retval None 00689 */ 00690 __STATIC_INLINE void LL_I2C_EnableWakeUpFromStop(I2C_TypeDef *I2Cx) 00691 { 00692 SET_BIT(I2Cx->CR1, I2C_CR1_WUPEN); 00693 } 00694 00695 /** 00696 * @brief Disable Wakeup from STOP. 00697 * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not 00698 * WakeUpFromStop feature is supported by the I2Cx Instance. 00699 * @rmtoll CR1 WUPEN LL_I2C_DisableWakeUpFromStop 00700 * @param I2Cx I2C Instance. 00701 * @retval None 00702 */ 00703 __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx) 00704 { 00705 CLEAR_BIT(I2Cx->CR1, I2C_CR1_WUPEN); 00706 } 00707 00708 /** 00709 * @brief Check if Wakeup from STOP is enabled or disabled. 00710 * @note Macro @ref IS_I2C_WAKEUP_FROMSTOP_INSTANCE(I2Cx) can be used to check whether or not 00711 * WakeUpFromStop feature is supported by the I2Cx Instance. 00712 * @rmtoll CR1 WUPEN LL_I2C_IsEnabledWakeUpFromStop 00713 * @param I2Cx I2C Instance. 00714 * @retval State of bit (1 or 0). 00715 */ 00716 __STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx) 00717 { 00718 return (READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)); 00719 } 00720 00721 /** 00722 * @brief Enable General Call. 00723 * @note When enabled the Address 0x00 is ACKed. 00724 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall 00725 * @param I2Cx I2C Instance. 00726 * @retval None 00727 */ 00728 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) 00729 { 00730 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN); 00731 } 00732 00733 /** 00734 * @brief Disable General Call. 00735 * @note When disabled the Address 0x00 is NACKed. 00736 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall 00737 * @param I2Cx I2C Instance. 00738 * @retval None 00739 */ 00740 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) 00741 { 00742 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN); 00743 } 00744 00745 /** 00746 * @brief Check if General Call is enabled or disabled. 00747 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall 00748 * @param I2Cx I2C Instance. 00749 * @retval State of bit (1 or 0). 00750 */ 00751 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) 00752 { 00753 return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)); 00754 } 00755 00756 /** 00757 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode. 00758 * @note Changing this bit is not allowed, when the START bit is set. 00759 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode 00760 * @param I2Cx I2C Instance. 00761 * @param AddressingMode This parameter can be one of the following values: 00762 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT 00763 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT 00764 * @retval None 00765 */ 00766 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode) 00767 { 00768 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode); 00769 } 00770 00771 /** 00772 * @brief Get the Master addressing mode. 00773 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode 00774 * @param I2Cx I2C Instance. 00775 * @retval Returned value can be one of the following values: 00776 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT 00777 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT 00778 */ 00779 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx) 00780 { 00781 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10)); 00782 } 00783 00784 /** 00785 * @brief Set the Own Address1. 00786 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n 00787 * OAR1 OA1MODE LL_I2C_SetOwnAddress1 00788 * @param I2Cx I2C Instance. 00789 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. 00790 * @param OwnAddrSize This parameter can be one of the following values: 00791 * @arg @ref LL_I2C_OWNADDRESS1_7BIT 00792 * @arg @ref LL_I2C_OWNADDRESS1_10BIT 00793 * @retval None 00794 */ 00795 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) 00796 { 00797 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize); 00798 } 00799 00800 /** 00801 * @brief Enable acknowledge on Own Address1 match address. 00802 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1 00803 * @param I2Cx I2C Instance. 00804 * @retval None 00805 */ 00806 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx) 00807 { 00808 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); 00809 } 00810 00811 /** 00812 * @brief Disable acknowledge on Own Address1 match address. 00813 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1 00814 * @param I2Cx I2C Instance. 00815 * @retval None 00816 */ 00817 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx) 00818 { 00819 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN); 00820 } 00821 00822 /** 00823 * @brief Check if Own Address1 acknowledge is enabled or disabled. 00824 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1 00825 * @param I2Cx I2C Instance. 00826 * @retval State of bit (1 or 0). 00827 */ 00828 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx) 00829 { 00830 return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)); 00831 } 00832 00833 /** 00834 * @brief Set the 7bits Own Address2. 00835 * @note This action has no effect if own address2 is enabled. 00836 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n 00837 * OAR2 OA2MSK LL_I2C_SetOwnAddress2 00838 * @param I2Cx I2C Instance. 00839 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F. 00840 * @param OwnAddrMask This parameter can be one of the following values: 00841 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK 00842 * @arg @ref LL_I2C_OWNADDRESS2_MASK01 00843 * @arg @ref LL_I2C_OWNADDRESS2_MASK02 00844 * @arg @ref LL_I2C_OWNADDRESS2_MASK03 00845 * @arg @ref LL_I2C_OWNADDRESS2_MASK04 00846 * @arg @ref LL_I2C_OWNADDRESS2_MASK05 00847 * @arg @ref LL_I2C_OWNADDRESS2_MASK06 00848 * @arg @ref LL_I2C_OWNADDRESS2_MASK07 00849 * @retval None 00850 */ 00851 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask) 00852 { 00853 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask); 00854 } 00855 00856 /** 00857 * @brief Enable acknowledge on Own Address2 match address. 00858 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2 00859 * @param I2Cx I2C Instance. 00860 * @retval None 00861 */ 00862 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) 00863 { 00864 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); 00865 } 00866 00867 /** 00868 * @brief Disable acknowledge on Own Address2 match address. 00869 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2 00870 * @param I2Cx I2C Instance. 00871 * @retval None 00872 */ 00873 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) 00874 { 00875 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN); 00876 } 00877 00878 /** 00879 * @brief Check if Own Address1 acknowledge is enabled or disabled. 00880 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2 00881 * @param I2Cx I2C Instance. 00882 * @retval State of bit (1 or 0). 00883 */ 00884 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) 00885 { 00886 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)); 00887 } 00888 00889 /** 00890 * @brief Configure the SDA setup, hold time and the SCL high, low period. 00891 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 00892 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming 00893 * @param I2Cx I2C Instance. 00894 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF. 00895 * @note This parameter is computed with the STM32CubeMX Tool. 00896 * @retval None 00897 */ 00898 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing) 00899 { 00900 WRITE_REG(I2Cx->TIMINGR, Timing); 00901 } 00902 00903 /** 00904 * @brief Get the Timing Prescaler setting. 00905 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler 00906 * @param I2Cx I2C Instance. 00907 * @retval Value between Min_Data=0x0 and Max_Data=0xF 00908 */ 00909 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx) 00910 { 00911 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos); 00912 } 00913 00914 /** 00915 * @brief Get the SCL low period setting. 00916 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod 00917 * @param I2Cx I2C Instance. 00918 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 00919 */ 00920 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx) 00921 { 00922 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos); 00923 } 00924 00925 /** 00926 * @brief Get the SCL high period setting. 00927 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod 00928 * @param I2Cx I2C Instance. 00929 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 00930 */ 00931 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx) 00932 { 00933 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos); 00934 } 00935 00936 /** 00937 * @brief Get the SDA hold time. 00938 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime 00939 * @param I2Cx I2C Instance. 00940 * @retval Value between Min_Data=0x0 and Max_Data=0xF 00941 */ 00942 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx) 00943 { 00944 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos); 00945 } 00946 00947 /** 00948 * @brief Get the SDA setup time. 00949 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime 00950 * @param I2Cx I2C Instance. 00951 * @retval Value between Min_Data=0x0 and Max_Data=0xF 00952 */ 00953 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx) 00954 { 00955 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos); 00956 } 00957 00958 /** 00959 * @brief Configure peripheral mode. 00960 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 00961 * SMBus feature is supported by the I2Cx Instance. 00962 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n 00963 * CR1 SMBDEN LL_I2C_SetMode 00964 * @param I2Cx I2C Instance. 00965 * @param PeripheralMode This parameter can be one of the following values: 00966 * @arg @ref LL_I2C_MODE_I2C 00967 * @arg @ref LL_I2C_MODE_SMBUS_HOST 00968 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE 00969 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP 00970 * @retval None 00971 */ 00972 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) 00973 { 00974 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode); 00975 } 00976 00977 /** 00978 * @brief Get peripheral mode. 00979 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 00980 * SMBus feature is supported by the I2Cx Instance. 00981 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n 00982 * CR1 SMBDEN LL_I2C_GetMode 00983 * @param I2Cx I2C Instance. 00984 * @retval Returned value can be one of the following values: 00985 * @arg @ref LL_I2C_MODE_I2C 00986 * @arg @ref LL_I2C_MODE_SMBUS_HOST 00987 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE 00988 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP 00989 */ 00990 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) 00991 { 00992 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN)); 00993 } 00994 00995 /** 00996 * @brief Enable SMBus alert (Host or Device mode) 00997 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 00998 * SMBus feature is supported by the I2Cx Instance. 00999 * @note SMBus Device mode: 01000 * - SMBus Alert pin is drived low and 01001 * Alert Response Address Header acknowledge is enabled. 01002 * SMBus Host mode: 01003 * - SMBus Alert pin management is supported. 01004 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert 01005 * @param I2Cx I2C Instance. 01006 * @retval None 01007 */ 01008 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) 01009 { 01010 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); 01011 } 01012 01013 /** 01014 * @brief Disable SMBus alert (Host or Device mode) 01015 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01016 * SMBus feature is supported by the I2Cx Instance. 01017 * @note SMBus Device mode: 01018 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and 01019 * Alert Response Address Header acknowledge is disabled. 01020 * SMBus Host mode: 01021 * - SMBus Alert pin management is not supported. 01022 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert 01023 * @param I2Cx I2C Instance. 01024 * @retval None 01025 */ 01026 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) 01027 { 01028 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN); 01029 } 01030 01031 /** 01032 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. 01033 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01034 * SMBus feature is supported by the I2Cx Instance. 01035 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert 01036 * @param I2Cx I2C Instance. 01037 * @retval State of bit (1 or 0). 01038 */ 01039 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) 01040 { 01041 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)); 01042 } 01043 01044 /** 01045 * @brief Enable SMBus Packet Error Calculation (PEC). 01046 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01047 * SMBus feature is supported by the I2Cx Instance. 01048 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC 01049 * @param I2Cx I2C Instance. 01050 * @retval None 01051 */ 01052 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) 01053 { 01054 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN); 01055 } 01056 01057 /** 01058 * @brief Disable SMBus Packet Error Calculation (PEC). 01059 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01060 * SMBus feature is supported by the I2Cx Instance. 01061 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC 01062 * @param I2Cx I2C Instance. 01063 * @retval None 01064 */ 01065 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) 01066 { 01067 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN); 01068 } 01069 01070 /** 01071 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. 01072 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01073 * SMBus feature is supported by the I2Cx Instance. 01074 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC 01075 * @param I2Cx I2C Instance. 01076 * @retval State of bit (1 or 0). 01077 */ 01078 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) 01079 { 01080 return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)); 01081 } 01082 01083 /** 01084 * @brief Configure the SMBus Clock Timeout. 01085 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01086 * SMBus feature is supported by the I2Cx Instance. 01087 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB). 01088 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n 01089 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n 01090 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout 01091 * @param I2Cx I2C Instance. 01092 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. 01093 * @param TimeoutAMode This parameter can be one of the following values: 01094 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 01095 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH 01096 * @param TimeoutB 01097 * @retval None 01098 */ 01099 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode, 01100 uint32_t TimeoutB) 01101 { 01102 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB, 01103 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos)); 01104 } 01105 01106 /** 01107 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode). 01108 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01109 * SMBus feature is supported by the I2Cx Instance. 01110 * @note These bits can only be programmed when TimeoutA is disabled. 01111 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA 01112 * @param I2Cx I2C Instance. 01113 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. 01114 * @retval None 01115 */ 01116 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA) 01117 { 01118 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA); 01119 } 01120 01121 /** 01122 * @brief Get the SMBus Clock TimeoutA setting. 01123 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01124 * SMBus feature is supported by the I2Cx Instance. 01125 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA 01126 * @param I2Cx I2C Instance. 01127 * @retval Value between Min_Data=0 and Max_Data=0xFFF 01128 */ 01129 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx) 01130 { 01131 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA)); 01132 } 01133 01134 /** 01135 * @brief Set the SMBus Clock TimeoutA mode. 01136 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01137 * SMBus feature is supported by the I2Cx Instance. 01138 * @note This bit can only be programmed when TimeoutA is disabled. 01139 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode 01140 * @param I2Cx I2C Instance. 01141 * @param TimeoutAMode This parameter can be one of the following values: 01142 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 01143 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH 01144 * @retval None 01145 */ 01146 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode) 01147 { 01148 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode); 01149 } 01150 01151 /** 01152 * @brief Get the SMBus Clock TimeoutA mode. 01153 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01154 * SMBus feature is supported by the I2Cx Instance. 01155 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode 01156 * @param I2Cx I2C Instance. 01157 * @retval Returned value can be one of the following values: 01158 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 01159 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH 01160 */ 01161 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx) 01162 { 01163 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE)); 01164 } 01165 01166 /** 01167 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode). 01168 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01169 * SMBus feature is supported by the I2Cx Instance. 01170 * @note These bits can only be programmed when TimeoutB is disabled. 01171 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB 01172 * @param I2Cx I2C Instance. 01173 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF. 01174 * @retval None 01175 */ 01176 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB) 01177 { 01178 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos); 01179 } 01180 01181 /** 01182 * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting. 01183 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01184 * SMBus feature is supported by the I2Cx Instance. 01185 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB 01186 * @param I2Cx I2C Instance. 01187 * @retval Value between Min_Data=0 and Max_Data=0xFFF 01188 */ 01189 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx) 01190 { 01191 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos); 01192 } 01193 01194 /** 01195 * @brief Enable the SMBus Clock Timeout. 01196 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01197 * SMBus feature is supported by the I2Cx Instance. 01198 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n 01199 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout 01200 * @param I2Cx I2C Instance. 01201 * @param ClockTimeout This parameter can be one of the following values: 01202 * @arg @ref LL_I2C_SMBUS_TIMEOUTA 01203 * @arg @ref LL_I2C_SMBUS_TIMEOUTB 01204 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT 01205 * @retval None 01206 */ 01207 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) 01208 { 01209 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout); 01210 } 01211 01212 /** 01213 * @brief Disable the SMBus Clock Timeout. 01214 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01215 * SMBus feature is supported by the I2Cx Instance. 01216 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n 01217 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout 01218 * @param I2Cx I2C Instance. 01219 * @param ClockTimeout This parameter can be one of the following values: 01220 * @arg @ref LL_I2C_SMBUS_TIMEOUTA 01221 * @arg @ref LL_I2C_SMBUS_TIMEOUTB 01222 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT 01223 * @retval None 01224 */ 01225 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) 01226 { 01227 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout); 01228 } 01229 01230 /** 01231 * @brief Check if the SMBus Clock Timeout is enabled or disabled. 01232 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01233 * SMBus feature is supported by the I2Cx Instance. 01234 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n 01235 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout 01236 * @param I2Cx I2C Instance. 01237 * @param ClockTimeout This parameter can be one of the following values: 01238 * @arg @ref LL_I2C_SMBUS_TIMEOUTA 01239 * @arg @ref LL_I2C_SMBUS_TIMEOUTB 01240 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT 01241 * @retval State of bit (1 or 0). 01242 */ 01243 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout) 01244 { 01245 return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout)); 01246 } 01247 01248 /** 01249 * @} 01250 */ 01251 01252 /** @defgroup I2C_LL_EF_IT_Management IT_Management 01253 * @{ 01254 */ 01255 01256 /** 01257 * @brief Enable TXIS interrupt. 01258 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX 01259 * @param I2Cx I2C Instance. 01260 * @retval None 01261 */ 01262 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) 01263 { 01264 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE); 01265 } 01266 01267 /** 01268 * @brief Disable TXIS interrupt. 01269 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX 01270 * @param I2Cx I2C Instance. 01271 * @retval None 01272 */ 01273 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) 01274 { 01275 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE); 01276 } 01277 01278 /** 01279 * @brief Check if the TXIS Interrupt is enabled or disabled. 01280 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX 01281 * @param I2Cx I2C Instance. 01282 * @retval State of bit (1 or 0). 01283 */ 01284 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) 01285 { 01286 return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)); 01287 } 01288 01289 /** 01290 * @brief Enable RXNE interrupt. 01291 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX 01292 * @param I2Cx I2C Instance. 01293 * @retval None 01294 */ 01295 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) 01296 { 01297 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE); 01298 } 01299 01300 /** 01301 * @brief Disable RXNE interrupt. 01302 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX 01303 * @param I2Cx I2C Instance. 01304 * @retval None 01305 */ 01306 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) 01307 { 01308 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE); 01309 } 01310 01311 /** 01312 * @brief Check if the RXNE Interrupt is enabled or disabled. 01313 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX 01314 * @param I2Cx I2C Instance. 01315 * @retval State of bit (1 or 0). 01316 */ 01317 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) 01318 { 01319 return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)); 01320 } 01321 01322 /** 01323 * @brief Enable Address match interrupt (slave mode only). 01324 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR 01325 * @param I2Cx I2C Instance. 01326 * @retval None 01327 */ 01328 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx) 01329 { 01330 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); 01331 } 01332 01333 /** 01334 * @brief Disable Address match interrupt (slave mode only). 01335 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR 01336 * @param I2Cx I2C Instance. 01337 * @retval None 01338 */ 01339 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx) 01340 { 01341 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE); 01342 } 01343 01344 /** 01345 * @brief Check if Address match interrupt is enabled or disabled. 01346 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR 01347 * @param I2Cx I2C Instance. 01348 * @retval State of bit (1 or 0). 01349 */ 01350 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx) 01351 { 01352 return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)); 01353 } 01354 01355 /** 01356 * @brief Enable Not acknowledge received interrupt. 01357 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK 01358 * @param I2Cx I2C Instance. 01359 * @retval None 01360 */ 01361 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx) 01362 { 01363 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE); 01364 } 01365 01366 /** 01367 * @brief Disable Not acknowledge received interrupt. 01368 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK 01369 * @param I2Cx I2C Instance. 01370 * @retval None 01371 */ 01372 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx) 01373 { 01374 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE); 01375 } 01376 01377 /** 01378 * @brief Check if Not acknowledge received interrupt is enabled or disabled. 01379 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK 01380 * @param I2Cx I2C Instance. 01381 * @retval State of bit (1 or 0). 01382 */ 01383 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx) 01384 { 01385 return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)); 01386 } 01387 01388 /** 01389 * @brief Enable STOP detection interrupt. 01390 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP 01391 * @param I2Cx I2C Instance. 01392 * @retval None 01393 */ 01394 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx) 01395 { 01396 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE); 01397 } 01398 01399 /** 01400 * @brief Disable STOP detection interrupt. 01401 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP 01402 * @param I2Cx I2C Instance. 01403 * @retval None 01404 */ 01405 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx) 01406 { 01407 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE); 01408 } 01409 01410 /** 01411 * @brief Check if STOP detection interrupt is enabled or disabled. 01412 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP 01413 * @param I2Cx I2C Instance. 01414 * @retval State of bit (1 or 0). 01415 */ 01416 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx) 01417 { 01418 return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)); 01419 } 01420 01421 /** 01422 * @brief Enable Transfer Complete interrupt. 01423 * @note Any of these events will generate interrupt : 01424 * Transfer Complete (TC) 01425 * Transfer Complete Reload (TCR) 01426 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC 01427 * @param I2Cx I2C Instance. 01428 * @retval None 01429 */ 01430 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx) 01431 { 01432 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE); 01433 } 01434 01435 /** 01436 * @brief Disable Transfer Complete interrupt. 01437 * @note Any of these events will generate interrupt : 01438 * Transfer Complete (TC) 01439 * Transfer Complete Reload (TCR) 01440 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC 01441 * @param I2Cx I2C Instance. 01442 * @retval None 01443 */ 01444 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx) 01445 { 01446 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE); 01447 } 01448 01449 /** 01450 * @brief Check if Transfer Complete interrupt is enabled or disabled. 01451 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC 01452 * @param I2Cx I2C Instance. 01453 * @retval State of bit (1 or 0). 01454 */ 01455 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx) 01456 { 01457 return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)); 01458 } 01459 01460 /** 01461 * @brief Enable Error interrupts. 01462 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01463 * SMBus feature is supported by the I2Cx Instance. 01464 * @note Any of these errors will generate interrupt : 01465 * Arbitration Loss (ARLO) 01466 * Bus Error detection (BERR) 01467 * Overrun/Underrun (OVR) 01468 * SMBus Timeout detection (TIMEOUT) 01469 * SMBus PEC error detection (PECERR) 01470 * SMBus Alert pin event detection (ALERT) 01471 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR 01472 * @param I2Cx I2C Instance. 01473 * @retval None 01474 */ 01475 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) 01476 { 01477 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE); 01478 } 01479 01480 /** 01481 * @brief Disable Error interrupts. 01482 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01483 * SMBus feature is supported by the I2Cx Instance. 01484 * @note Any of these errors will generate interrupt : 01485 * Arbitration Loss (ARLO) 01486 * Bus Error detection (BERR) 01487 * Overrun/Underrun (OVR) 01488 * SMBus Timeout detection (TIMEOUT) 01489 * SMBus PEC error detection (PECERR) 01490 * SMBus Alert pin event detection (ALERT) 01491 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR 01492 * @param I2Cx I2C Instance. 01493 * @retval None 01494 */ 01495 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) 01496 { 01497 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE); 01498 } 01499 01500 /** 01501 * @brief Check if Error interrupts are enabled or disabled. 01502 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR 01503 * @param I2Cx I2C Instance. 01504 * @retval State of bit (1 or 0). 01505 */ 01506 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) 01507 { 01508 return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)); 01509 } 01510 01511 /** 01512 * @} 01513 */ 01514 01515 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management 01516 * @{ 01517 */ 01518 01519 /** 01520 * @brief Indicate the status of Transmit data register empty flag. 01521 * @note RESET: When next data is written in Transmit data register. 01522 * SET: When Transmit data register is empty. 01523 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE 01524 * @param I2Cx I2C Instance. 01525 * @retval State of bit (1 or 0). 01526 */ 01527 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) 01528 { 01529 return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)); 01530 } 01531 01532 /** 01533 * @brief Indicate the status of Transmit interrupt flag. 01534 * @note RESET: When next data is written in Transmit data register. 01535 * SET: When Transmit data register is empty. 01536 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS 01537 * @param I2Cx I2C Instance. 01538 * @retval State of bit (1 or 0). 01539 */ 01540 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx) 01541 { 01542 return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)); 01543 } 01544 01545 /** 01546 * @brief Indicate the status of Receive data register not empty flag. 01547 * @note RESET: When Receive data register is read. 01548 * SET: When the received data is copied in Receive data register. 01549 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE 01550 * @param I2Cx I2C Instance. 01551 * @retval State of bit (1 or 0). 01552 */ 01553 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) 01554 { 01555 return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)); 01556 } 01557 01558 /** 01559 * @brief Indicate the status of Address matched flag (slave mode). 01560 * @note RESET: Clear default value. 01561 * SET: When the received slave address matched with one of the enabled slave address. 01562 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR 01563 * @param I2Cx I2C Instance. 01564 * @retval State of bit (1 or 0). 01565 */ 01566 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) 01567 { 01568 return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)); 01569 } 01570 01571 /** 01572 * @brief Indicate the status of Not Acknowledge received flag. 01573 * @note RESET: Clear default value. 01574 * SET: When a NACK is received after a byte transmission. 01575 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK 01576 * @param I2Cx I2C Instance. 01577 * @retval State of bit (1 or 0). 01578 */ 01579 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx) 01580 { 01581 return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)); 01582 } 01583 01584 /** 01585 * @brief Indicate the status of Stop detection flag. 01586 * @note RESET: Clear default value. 01587 * SET: When a Stop condition is detected. 01588 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP 01589 * @param I2Cx I2C Instance. 01590 * @retval State of bit (1 or 0). 01591 */ 01592 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) 01593 { 01594 return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)); 01595 } 01596 01597 /** 01598 * @brief Indicate the status of Transfer complete flag (master mode). 01599 * @note RESET: Clear default value. 01600 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred. 01601 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC 01602 * @param I2Cx I2C Instance. 01603 * @retval State of bit (1 or 0). 01604 */ 01605 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx) 01606 { 01607 return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)); 01608 } 01609 01610 /** 01611 * @brief Indicate the status of Transfer complete flag (master mode). 01612 * @note RESET: Clear default value. 01613 * SET: When RELOAD=1 and NBYTES date have been transferred. 01614 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR 01615 * @param I2Cx I2C Instance. 01616 * @retval State of bit (1 or 0). 01617 */ 01618 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx) 01619 { 01620 return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)); 01621 } 01622 01623 /** 01624 * @brief Indicate the status of Bus error flag. 01625 * @note RESET: Clear default value. 01626 * SET: When a misplaced Start or Stop condition is detected. 01627 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR 01628 * @param I2Cx I2C Instance. 01629 * @retval State of bit (1 or 0). 01630 */ 01631 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) 01632 { 01633 return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)); 01634 } 01635 01636 /** 01637 * @brief Indicate the status of Arbitration lost flag. 01638 * @note RESET: Clear default value. 01639 * SET: When arbitration lost. 01640 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO 01641 * @param I2Cx I2C Instance. 01642 * @retval State of bit (1 or 0). 01643 */ 01644 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) 01645 { 01646 return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)); 01647 } 01648 01649 /** 01650 * @brief Indicate the status of Overrun/Underrun flag (slave mode). 01651 * @note RESET: Clear default value. 01652 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). 01653 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR 01654 * @param I2Cx I2C Instance. 01655 * @retval State of bit (1 or 0). 01656 */ 01657 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) 01658 { 01659 return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)); 01660 } 01661 01662 /** 01663 * @brief Indicate the status of SMBus PEC error flag in reception. 01664 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01665 * SMBus feature is supported by the I2Cx Instance. 01666 * @note RESET: Clear default value. 01667 * SET: When the received PEC does not match with the PEC register content. 01668 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR 01669 * @param I2Cx I2C Instance. 01670 * @retval State of bit (1 or 0). 01671 */ 01672 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) 01673 { 01674 return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)); 01675 } 01676 01677 /** 01678 * @brief Indicate the status of SMBus Timeout detection flag. 01679 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01680 * SMBus feature is supported by the I2Cx Instance. 01681 * @note RESET: Clear default value. 01682 * SET: When a timeout or extended clock timeout occurs. 01683 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT 01684 * @param I2Cx I2C Instance. 01685 * @retval State of bit (1 or 0). 01686 */ 01687 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) 01688 { 01689 return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)); 01690 } 01691 01692 /** 01693 * @brief Indicate the status of SMBus alert flag. 01694 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01695 * SMBus feature is supported by the I2Cx Instance. 01696 * @note RESET: Clear default value. 01697 * SET: When SMBus host configuration, SMBus alert enabled and 01698 * a falling edge event occurs on SMBA pin. 01699 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT 01700 * @param I2Cx I2C Instance. 01701 * @retval State of bit (1 or 0). 01702 */ 01703 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) 01704 { 01705 return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)); 01706 } 01707 01708 /** 01709 * @brief Indicate the status of Bus Busy flag. 01710 * @note RESET: Clear default value. 01711 * SET: When a Start condition is detected. 01712 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY 01713 * @param I2Cx I2C Instance. 01714 * @retval State of bit (1 or 0). 01715 */ 01716 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) 01717 { 01718 return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)); 01719 } 01720 01721 /** 01722 * @brief Clear Address Matched flag. 01723 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR 01724 * @param I2Cx I2C Instance. 01725 * @retval None 01726 */ 01727 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) 01728 { 01729 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF); 01730 } 01731 01732 /** 01733 * @brief Clear Not Acknowledge flag. 01734 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK 01735 * @param I2Cx I2C Instance. 01736 * @retval None 01737 */ 01738 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx) 01739 { 01740 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF); 01741 } 01742 01743 /** 01744 * @brief Clear Stop detection flag. 01745 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP 01746 * @param I2Cx I2C Instance. 01747 * @retval None 01748 */ 01749 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) 01750 { 01751 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF); 01752 } 01753 01754 /** 01755 * @brief Clear Transmit data register empty flag (TXE). 01756 * @note This bit can be clear by software in order to flush the transmit data register (TXDR). 01757 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE 01758 * @param I2Cx I2C Instance. 01759 * @retval None 01760 */ 01761 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx) 01762 { 01763 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE); 01764 } 01765 01766 /** 01767 * @brief Clear Bus error flag. 01768 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR 01769 * @param I2Cx I2C Instance. 01770 * @retval None 01771 */ 01772 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) 01773 { 01774 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF); 01775 } 01776 01777 /** 01778 * @brief Clear Arbitration lost flag. 01779 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO 01780 * @param I2Cx I2C Instance. 01781 * @retval None 01782 */ 01783 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) 01784 { 01785 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF); 01786 } 01787 01788 /** 01789 * @brief Clear Overrun/Underrun flag. 01790 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR 01791 * @param I2Cx I2C Instance. 01792 * @retval None 01793 */ 01794 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) 01795 { 01796 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF); 01797 } 01798 01799 /** 01800 * @brief Clear SMBus PEC error flag. 01801 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01802 * SMBus feature is supported by the I2Cx Instance. 01803 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR 01804 * @param I2Cx I2C Instance. 01805 * @retval None 01806 */ 01807 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) 01808 { 01809 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF); 01810 } 01811 01812 /** 01813 * @brief Clear SMBus Timeout detection flag. 01814 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01815 * SMBus feature is supported by the I2Cx Instance. 01816 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT 01817 * @param I2Cx I2C Instance. 01818 * @retval None 01819 */ 01820 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) 01821 { 01822 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF); 01823 } 01824 01825 /** 01826 * @brief Clear SMBus Alert flag. 01827 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01828 * SMBus feature is supported by the I2Cx Instance. 01829 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT 01830 * @param I2Cx I2C Instance. 01831 * @retval None 01832 */ 01833 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) 01834 { 01835 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF); 01836 } 01837 01838 /** 01839 * @} 01840 */ 01841 01842 /** @defgroup I2C_LL_EF_Data_Management Data_Management 01843 * @{ 01844 */ 01845 01846 /** 01847 * @brief Enable automatic STOP condition generation (master mode). 01848 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred. 01849 * This bit has no effect in slave mode or when RELOAD bit is set. 01850 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode 01851 * @param I2Cx I2C Instance. 01852 * @retval None 01853 */ 01854 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx) 01855 { 01856 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); 01857 } 01858 01859 /** 01860 * @brief Disable automatic STOP condition generation (master mode). 01861 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low. 01862 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode 01863 * @param I2Cx I2C Instance. 01864 * @retval None 01865 */ 01866 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx) 01867 { 01868 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND); 01869 } 01870 01871 /** 01872 * @brief Check if automatic STOP condition is enabled or disabled. 01873 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode 01874 * @param I2Cx I2C Instance. 01875 * @retval State of bit (1 or 0). 01876 */ 01877 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx) 01878 { 01879 return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)); 01880 } 01881 01882 /** 01883 * @brief Enable reload mode (master mode). 01884 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set. 01885 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode 01886 * @param I2Cx I2C Instance. 01887 * @retval None 01888 */ 01889 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx) 01890 { 01891 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD); 01892 } 01893 01894 /** 01895 * @brief Disable reload mode (master mode). 01896 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow). 01897 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode 01898 * @param I2Cx I2C Instance. 01899 * @retval None 01900 */ 01901 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx) 01902 { 01903 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD); 01904 } 01905 01906 /** 01907 * @brief Check if reload mode is enabled or disabled. 01908 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode 01909 * @param I2Cx I2C Instance. 01910 * @retval State of bit (1 or 0). 01911 */ 01912 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx) 01913 { 01914 return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)); 01915 } 01916 01917 /** 01918 * @brief Configure the number of bytes for transfer. 01919 * @note Changing these bits when START bit is set is not allowed. 01920 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize 01921 * @param I2Cx I2C Instance. 01922 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF. 01923 * @retval None 01924 */ 01925 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize) 01926 { 01927 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos); 01928 } 01929 01930 /** 01931 * @brief Get the number of bytes configured for transfer. 01932 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize 01933 * @param I2Cx I2C Instance. 01934 * @retval Value between Min_Data=0x0 and Max_Data=0xFF 01935 */ 01936 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx) 01937 { 01938 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos); 01939 } 01940 01941 /** 01942 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. 01943 * @note Usage in Slave mode only. 01944 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData 01945 * @param I2Cx I2C Instance. 01946 * @param TypeAcknowledge This parameter can be one of the following values: 01947 * @arg @ref LL_I2C_ACK 01948 * @arg @ref LL_I2C_NACK 01949 * @retval None 01950 */ 01951 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) 01952 { 01953 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge); 01954 } 01955 01956 /** 01957 * @brief Generate a START or RESTART condition 01958 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. 01959 * This action has no effect when RELOAD is set. 01960 * @rmtoll CR2 START LL_I2C_GenerateStartCondition 01961 * @param I2Cx I2C Instance. 01962 * @retval None 01963 */ 01964 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) 01965 { 01966 SET_BIT(I2Cx->CR2, I2C_CR2_START); 01967 } 01968 01969 /** 01970 * @brief Generate a STOP condition after the current byte transfer (master mode). 01971 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition 01972 * @param I2Cx I2C Instance. 01973 * @retval None 01974 */ 01975 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) 01976 { 01977 SET_BIT(I2Cx->CR2, I2C_CR2_STOP); 01978 } 01979 01980 /** 01981 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode). 01982 * @note The master sends the complete 10bit slave address read sequence : 01983 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction. 01984 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead 01985 * @param I2Cx I2C Instance. 01986 * @retval None 01987 */ 01988 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx) 01989 { 01990 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); 01991 } 01992 01993 /** 01994 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode). 01995 * @note The master only sends the first 7 bits of 10bit address in Read direction. 01996 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead 01997 * @param I2Cx I2C Instance. 01998 * @retval None 01999 */ 02000 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx) 02001 { 02002 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R); 02003 } 02004 02005 /** 02006 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled. 02007 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead 02008 * @param I2Cx I2C Instance. 02009 * @retval State of bit (1 or 0). 02010 */ 02011 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx) 02012 { 02013 return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)); 02014 } 02015 02016 /** 02017 * @brief Configure the transfer direction (master mode). 02018 * @note Changing these bits when START bit is set is not allowed. 02019 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest 02020 * @param I2Cx I2C Instance. 02021 * @param TransferRequest This parameter can be one of the following values: 02022 * @arg @ref LL_I2C_REQUEST_WRITE 02023 * @arg @ref LL_I2C_REQUEST_READ 02024 * @retval None 02025 */ 02026 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest) 02027 { 02028 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest); 02029 } 02030 02031 /** 02032 * @brief Get the transfer direction requested (master mode). 02033 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest 02034 * @param I2Cx I2C Instance. 02035 * @retval Returned value can be one of the following values: 02036 * @arg @ref LL_I2C_REQUEST_WRITE 02037 * @arg @ref LL_I2C_REQUEST_READ 02038 */ 02039 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx) 02040 { 02041 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN)); 02042 } 02043 02044 /** 02045 * @brief Configure the slave address for transfer (master mode). 02046 * @note Changing these bits when START bit is set is not allowed. 02047 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr 02048 * @param I2Cx I2C Instance. 02049 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F. 02050 * @retval None 02051 */ 02052 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr) 02053 { 02054 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr); 02055 } 02056 02057 /** 02058 * @brief Get the slave address programmed for transfer. 02059 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr 02060 * @param I2Cx I2C Instance. 02061 * @retval Value between Min_Data=0x0 and Max_Data=0x3F 02062 */ 02063 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx) 02064 { 02065 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD)); 02066 } 02067 02068 /** 02069 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set). 02070 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n 02071 * CR2 ADD10 LL_I2C_HandleTransfer\n 02072 * CR2 RD_WRN LL_I2C_HandleTransfer\n 02073 * CR2 START LL_I2C_HandleTransfer\n 02074 * CR2 STOP LL_I2C_HandleTransfer\n 02075 * CR2 RELOAD LL_I2C_HandleTransfer\n 02076 * CR2 NBYTES LL_I2C_HandleTransfer\n 02077 * CR2 AUTOEND LL_I2C_HandleTransfer\n 02078 * CR2 HEAD10R LL_I2C_HandleTransfer 02079 * @param I2Cx I2C Instance. 02080 * @param SlaveAddr Specifies the slave address to be programmed. 02081 * @param SlaveAddrSize This parameter can be one of the following values: 02082 * @arg @ref LL_I2C_ADDRSLAVE_7BIT 02083 * @arg @ref LL_I2C_ADDRSLAVE_10BIT 02084 * @param TransferSize Specifies the number of bytes to be programmed. 02085 * This parameter must be a value between Min_Data=0 and Max_Data=255. 02086 * @param EndMode This parameter can be one of the following values: 02087 * @arg @ref LL_I2C_MODE_RELOAD 02088 * @arg @ref LL_I2C_MODE_AUTOEND 02089 * @arg @ref LL_I2C_MODE_SOFTEND 02090 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD 02091 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC 02092 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC 02093 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC 02094 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC 02095 * @param Request This parameter can be one of the following values: 02096 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP 02097 * @arg @ref LL_I2C_GENERATE_STOP 02098 * @arg @ref LL_I2C_GENERATE_START_READ 02099 * @arg @ref LL_I2C_GENERATE_START_WRITE 02100 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ 02101 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE 02102 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ 02103 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE 02104 * @retval None 02105 */ 02106 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize, 02107 uint32_t TransferSize, uint32_t EndMode, uint32_t Request) 02108 { 02109 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD | 02110 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R, 02111 SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request); 02112 } 02113 02114 /** 02115 * @brief Indicate the value of transfer direction (slave mode). 02116 * @note RESET: Write transfer, Slave enters in receiver mode. 02117 * SET: Read transfer, Slave enters in transmitter mode. 02118 * @rmtoll ISR DIR LL_I2C_GetTransferDirection 02119 * @param I2Cx I2C Instance. 02120 * @retval Returned value can be one of the following values: 02121 * @arg @ref LL_I2C_DIRECTION_WRITE 02122 * @arg @ref LL_I2C_DIRECTION_READ 02123 */ 02124 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) 02125 { 02126 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR)); 02127 } 02128 02129 /** 02130 * @brief Return the slave matched address. 02131 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode 02132 * @param I2Cx I2C Instance. 02133 * @retval Value between Min_Data=0x00 and Max_Data=0x3F 02134 */ 02135 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx) 02136 { 02137 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1); 02138 } 02139 02140 /** 02141 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode). 02142 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 02143 * SMBus feature is supported by the I2Cx Instance. 02144 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received. 02145 * This bit has no effect when RELOAD bit is set. 02146 * This bit has no effect in device mode when SBC bit is not set. 02147 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare 02148 * @param I2Cx I2C Instance. 02149 * @retval None 02150 */ 02151 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) 02152 { 02153 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE); 02154 } 02155 02156 /** 02157 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not. 02158 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 02159 * SMBus feature is supported by the I2Cx Instance. 02160 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare 02161 * @param I2Cx I2C Instance. 02162 * @retval State of bit (1 or 0). 02163 */ 02164 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) 02165 { 02166 return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)); 02167 } 02168 02169 /** 02170 * @brief Get the SMBus Packet Error byte calculated. 02171 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 02172 * SMBus feature is supported by the I2Cx Instance. 02173 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC 02174 * @param I2Cx I2C Instance. 02175 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 02176 */ 02177 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) 02178 { 02179 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC)); 02180 } 02181 02182 /** 02183 * @brief Read Receive Data register. 02184 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8 02185 * @param I2Cx I2C Instance. 02186 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 02187 */ 02188 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) 02189 { 02190 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA)); 02191 } 02192 02193 /** 02194 * @brief Write in Transmit Data Register . 02195 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8 02196 * @param I2Cx I2C Instance. 02197 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF 02198 * @retval None 02199 */ 02200 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) 02201 { 02202 WRITE_REG(I2Cx->TXDR, Data); 02203 } 02204 02205 /** 02206 * @} 02207 */ 02208 02209 #if defined(USE_FULL_LL_DRIVER) 02210 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions 02211 * @{ 02212 */ 02213 02214 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); 02215 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); 02216 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); 02217 02218 02219 /** 02220 * @} 02221 */ 02222 #endif /* USE_FULL_LL_DRIVER */ 02223 02224 /** 02225 * @} 02226 */ 02227 02228 /** 02229 * @} 02230 */ 02231 02232 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */ 02233 02234 /** 02235 * @} 02236 */ 02237 02238 #ifdef __cplusplus 02239 } 02240 #endif 02241 02242 #endif /* __STM32L4xx_LL_I2C_H */ 02243 02244 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/