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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_bus.h 00004 * @author MCD Application Team 00005 * @brief Header file of BUS LL module. 00006 00007 @verbatim 00008 ##### RCC Limitations ##### 00009 ============================================================================== 00010 [..] 00011 A delay between an RCC peripheral clock enable and the effective peripheral 00012 enabling should be taken into account in order to manage the peripheral read/write 00013 from/to registers. 00014 (+) This delay depends on the peripheral mapping. 00015 (++) AHB & APB peripherals, 1 dummy read is necessary 00016 00017 [..] 00018 Workarounds: 00019 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been 00020 inserted in each LL_{BUS}_GRP{x}_EnableClock() function. 00021 00022 @endverbatim 00023 ****************************************************************************** 00024 * @attention 00025 * 00026 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00027 * 00028 * Redistribution and use in source and binary forms, with or without modification, 00029 * are permitted provided that the following conditions are met: 00030 * 1. Redistributions of source code must retain the above copyright notice, 00031 * this list of conditions and the following disclaimer. 00032 * 2. Redistributions in binary form must reproduce the above copyright notice, 00033 * this list of conditions and the following disclaimer in the documentation 00034 * and/or other materials provided with the distribution. 00035 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00036 * may be used to endorse or promote products derived from this software 00037 * without specific prior written permission. 00038 * 00039 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00040 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00041 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00042 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00043 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00044 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00045 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00046 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00047 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00048 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00049 * 00050 ****************************************************************************** 00051 */ 00052 00053 /* Define to prevent recursive inclusion -------------------------------------*/ 00054 #ifndef __STM32L4xx_LL_BUS_H 00055 #define __STM32L4xx_LL_BUS_H 00056 00057 #ifdef __cplusplus 00058 extern "C" { 00059 #endif 00060 00061 /* Includes ------------------------------------------------------------------*/ 00062 #include "stm32l4xx.h" 00063 00064 /** @addtogroup STM32L4xx_LL_Driver 00065 * @{ 00066 */ 00067 00068 #if defined(RCC) 00069 00070 /** @defgroup BUS_LL BUS 00071 * @{ 00072 */ 00073 00074 /* Private types -------------------------------------------------------------*/ 00075 /* Private variables ---------------------------------------------------------*/ 00076 00077 /* Private constants ---------------------------------------------------------*/ 00078 00079 /* Private macros ------------------------------------------------------------*/ 00080 00081 /* Exported types ------------------------------------------------------------*/ 00082 /* Exported constants --------------------------------------------------------*/ 00083 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants 00084 * @{ 00085 */ 00086 00087 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH 00088 * @{ 00089 */ 00090 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 00091 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN 00092 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN 00093 #if defined(DMAMUX1) 00094 #define LL_AHB1_GRP1_PERIPH_DMAMUX1 RCC_AHB1ENR_DMAMUX1EN 00095 #endif /* DMAMUX1 */ 00096 #define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHB1ENR_FLASHEN 00097 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN 00098 #define LL_AHB1_GRP1_PERIPH_TSC RCC_AHB1ENR_TSCEN 00099 #if defined(DMA2D) 00100 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN 00101 #endif /* DMA2D */ 00102 #if defined(GFXMMU) 00103 #define LL_AHB1_GRP1_PERIPH_GFXMMU RCC_AHB1ENR_GFXMMUEN 00104 #endif /* GFXMMU */ 00105 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1SMENR_SRAM1SMEN 00106 /** 00107 * @} 00108 */ 00109 00110 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH 00111 * @{ 00112 */ 00113 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 00114 #define LL_AHB2_GRP1_PERIPH_GPIOA RCC_AHB2ENR_GPIOAEN 00115 #define LL_AHB2_GRP1_PERIPH_GPIOB RCC_AHB2ENR_GPIOBEN 00116 #define LL_AHB2_GRP1_PERIPH_GPIOC RCC_AHB2ENR_GPIOCEN 00117 #if defined(GPIOD) 00118 #define LL_AHB2_GRP1_PERIPH_GPIOD RCC_AHB2ENR_GPIODEN 00119 #endif /*GPIOD*/ 00120 #if defined(GPIOE) 00121 #define LL_AHB2_GRP1_PERIPH_GPIOE RCC_AHB2ENR_GPIOEEN 00122 #endif /*GPIOE*/ 00123 #if defined(GPIOF) 00124 #define LL_AHB2_GRP1_PERIPH_GPIOF RCC_AHB2ENR_GPIOFEN 00125 #endif /* GPIOF */ 00126 #if defined(GPIOG) 00127 #define LL_AHB2_GRP1_PERIPH_GPIOG RCC_AHB2ENR_GPIOGEN 00128 #endif /* GPIOG */ 00129 #define LL_AHB2_GRP1_PERIPH_GPIOH RCC_AHB2ENR_GPIOHEN 00130 #if defined(GPIOI) 00131 #define LL_AHB2_GRP1_PERIPH_GPIOI RCC_AHB2ENR_GPIOIEN 00132 #endif /* GPIOI */ 00133 #if defined(USB_OTG_FS) 00134 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN 00135 #endif /* USB_OTG_FS */ 00136 #define LL_AHB2_GRP1_PERIPH_ADC RCC_AHB2ENR_ADCEN 00137 #if defined(DCMI) 00138 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN 00139 #endif /* DCMI */ 00140 #if defined(AES) 00141 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN 00142 #endif /* AES */ 00143 #if defined(HASH) 00144 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN 00145 #endif /* HASH */ 00146 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN 00147 #if defined(OCTOSPIM) 00148 #define LL_AHB2_GRP1_PERIPH_OSPIM RCC_AHB2ENR_OSPIMEN 00149 #endif /* OCTOSPIM */ 00150 #if defined(SDMMC1) && defined(RCC_AHB2ENR_SDMMC1EN) 00151 #define LL_AHB2_GRP1_PERIPH_SDMMC1 RCC_AHB2ENR_SDMMC1EN 00152 #endif /* SDMMC1 && RCC_AHB2ENR_SDMMC1EN */ 00153 #define LL_AHB2_GRP1_PERIPH_SRAM2 RCC_AHB2SMENR_SRAM2SMEN 00154 #if defined(SRAM3_BASE) 00155 #define LL_AHB2_GRP1_PERIPH_SRAM3 RCC_AHB2SMENR_SRAM3SMEN 00156 #endif /* SRAM3_BASE */ 00157 /** 00158 * @} 00159 */ 00160 00161 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH 00162 * @{ 00163 */ 00164 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU 00165 #if defined(FMC_Bank1_R) 00166 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN 00167 #endif /* FMC_Bank1_R */ 00168 #if defined(QUADSPI) 00169 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN 00170 #endif /* QUADSPI */ 00171 #if defined(OCTOSPI1) 00172 #define LL_AHB3_GRP1_PERIPH_OSPI1 RCC_AHB3ENR_OSPI1EN 00173 #endif /* OCTOSPI1 */ 00174 #if defined(OCTOSPI2) 00175 #define LL_AHB3_GRP1_PERIPH_OSPI2 RCC_AHB3ENR_OSPI2EN 00176 #endif /* OCTOSPI2 */ 00177 /** 00178 * @} 00179 */ 00180 00181 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH 00182 * @{ 00183 */ 00184 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU 00185 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR1_TIM2EN 00186 #if defined(TIM3) 00187 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR1_TIM3EN 00188 #endif /* TIM3 */ 00189 #if defined(TIM4) 00190 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR1_TIM4EN 00191 #endif /* TIM4 */ 00192 #if defined(TIM5) 00193 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR1_TIM5EN 00194 #endif /* TIM5 */ 00195 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR1_TIM6EN 00196 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR1_TIM7EN 00197 #if defined(LCD) 00198 #define LL_APB1_GRP1_PERIPH_LCD RCC_APB1ENR1_LCDEN 00199 #endif /* LCD */ 00200 #if defined(RCC_APB1ENR1_RTCAPBEN) 00201 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR1_RTCAPBEN 00202 #endif /* RCC_APB1ENR1_RTCAPBEN */ 00203 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR1_WWDGEN 00204 #if defined(SPI2) 00205 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR1_SPI2EN 00206 #endif /* SPI2 */ 00207 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR1_SPI3EN 00208 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR1_USART2EN 00209 #if defined(USART3) 00210 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR1_USART3EN 00211 #endif /* USART3 */ 00212 #if defined(UART4) 00213 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR1_UART4EN 00214 #endif /* UART4 */ 00215 #if defined(UART5) 00216 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR1_UART5EN 00217 #endif /* UART5 */ 00218 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR1_I2C1EN 00219 #if defined(I2C2) 00220 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR1_I2C2EN 00221 #endif /* I2C2 */ 00222 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR1_I2C3EN 00223 #if defined(CRS) 00224 #define LL_APB1_GRP1_PERIPH_CRS RCC_APB1ENR1_CRSEN 00225 #endif /* CRS */ 00226 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR1_CAN1EN 00227 #if defined(CAN2) 00228 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR1_CAN2EN 00229 #endif /* CAN2 */ 00230 #if defined(USB) 00231 #define LL_APB1_GRP1_PERIPH_USB RCC_APB1ENR1_USBFSEN 00232 #endif /* USB */ 00233 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR1_PWREN 00234 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR1_DAC1EN 00235 #define LL_APB1_GRP1_PERIPH_OPAMP RCC_APB1ENR1_OPAMPEN 00236 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR1_LPTIM1EN 00237 /** 00238 * @} 00239 */ 00240 00241 00242 /** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH 00243 * @{ 00244 */ 00245 #define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU 00246 #define LL_APB1_GRP2_PERIPH_LPUART1 RCC_APB1ENR2_LPUART1EN 00247 #if defined(I2C4) 00248 #define LL_APB1_GRP2_PERIPH_I2C4 RCC_APB1ENR2_I2C4EN 00249 #endif /* I2C4 */ 00250 #if defined(SWPMI1) 00251 #define LL_APB1_GRP2_PERIPH_SWPMI1 RCC_APB1ENR2_SWPMI1EN 00252 #endif /* SWPMI1 */ 00253 #define LL_APB1_GRP2_PERIPH_LPTIM2 RCC_APB1ENR2_LPTIM2EN 00254 /** 00255 * @} 00256 */ 00257 00258 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH 00259 * @{ 00260 */ 00261 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU 00262 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN 00263 #define LL_APB2_GRP1_PERIPH_FW RCC_APB2ENR_FWEN 00264 #if defined(SDMMC1) && defined(RCC_APB2ENR_SDMMC1EN) 00265 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN 00266 #endif /* SDMMC1 && RCC_APB2ENR_SDMMC1EN */ 00267 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN 00268 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN 00269 #if defined(TIM8) 00270 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN 00271 #endif /* TIM8 */ 00272 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN 00273 #define LL_APB2_GRP1_PERIPH_TIM15 RCC_APB2ENR_TIM15EN 00274 #define LL_APB2_GRP1_PERIPH_TIM16 RCC_APB2ENR_TIM16EN 00275 #if defined(TIM17) 00276 #define LL_APB2_GRP1_PERIPH_TIM17 RCC_APB2ENR_TIM17EN 00277 #endif /* TIM17 */ 00278 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN 00279 #if defined(SAI2) 00280 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN 00281 #endif /* SAI2 */ 00282 #if defined(DFSDM1_Channel0) 00283 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN 00284 #endif /* DFSDM1_Channel0 */ 00285 #if defined(LTDC) 00286 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN 00287 #endif /* LTDC */ 00288 #if defined(DSI) 00289 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN 00290 #endif /* DSI */ 00291 /** 00292 * @} 00293 */ 00294 00295 /** Legacy definitions for compatibility purpose 00296 @cond 0 00297 */ 00298 #if defined(DFSDM1_Channel0) 00299 #define LL_APB2_GRP1_PERIPH_DFSDM LL_APB2_GRP1_PERIPH_DFSDM1 00300 #endif /* DFSDM1_Channel0 */ 00301 /** 00302 @endcond 00303 */ 00304 00305 /** 00306 * @} 00307 */ 00308 00309 /* Exported macro ------------------------------------------------------------*/ 00310 /* Exported functions --------------------------------------------------------*/ 00311 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions 00312 * @{ 00313 */ 00314 00315 /** @defgroup BUS_LL_EF_AHB1 AHB1 00316 * @{ 00317 */ 00318 00319 /** 00320 * @brief Enable AHB1 peripherals clock. 00321 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n 00322 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n 00323 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_EnableClock\n 00324 * AHB1ENR FLASHEN LL_AHB1_GRP1_EnableClock\n 00325 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n 00326 * AHB1ENR TSCEN LL_AHB1_GRP1_EnableClock\n 00327 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n 00328 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_EnableClock 00329 * @param Periphs This parameter can be a combination of the following values: 00330 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00331 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00332 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00333 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00334 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00335 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00336 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00337 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00338 * 00339 * (*) value not defined in all devices. 00340 * @retval None 00341 */ 00342 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) 00343 { 00344 __IO uint32_t tmpreg; 00345 SET_BIT(RCC->AHB1ENR, Periphs); 00346 /* Delay after an RCC peripheral clock enabling */ 00347 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs); 00348 (void)tmpreg; 00349 } 00350 00351 /** 00352 * @brief Check if AHB1 peripheral clock is enabled or not 00353 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n 00354 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n 00355 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_IsEnabledClock\n 00356 * AHB1ENR FLASHEN LL_AHB1_GRP1_IsEnabledClock\n 00357 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n 00358 * AHB1ENR TSCEN LL_AHB1_GRP1_IsEnabledClock\n 00359 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n 00360 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_IsEnabledClock 00361 * @param Periphs This parameter can be a combination of the following values: 00362 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00363 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00364 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00365 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00366 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00367 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00368 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00369 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00370 * 00371 * (*) value not defined in all devices. 00372 * @retval State of Periphs (1 or 0). 00373 */ 00374 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) 00375 { 00376 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs); 00377 } 00378 00379 /** 00380 * @brief Disable AHB1 peripherals clock. 00381 * @rmtoll AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n 00382 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n 00383 * AHB1ENR DMAMUX1EN LL_AHB1_GRP1_DisableClock\n 00384 * AHB1ENR FLASHEN LL_AHB1_GRP1_DisableClock\n 00385 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n 00386 * AHB1ENR TSCEN LL_AHB1_GRP1_DisableClock\n 00387 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n 00388 * AHB1ENR GFXMMUEN LL_AHB1_GRP1_DisableClock 00389 * @param Periphs This parameter can be a combination of the following values: 00390 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00391 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00392 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00393 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00394 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00395 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00396 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00397 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00398 * 00399 * (*) value not defined in all devices. 00400 * @retval None 00401 */ 00402 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) 00403 { 00404 CLEAR_BIT(RCC->AHB1ENR, Periphs); 00405 } 00406 00407 /** 00408 * @brief Force AHB1 peripherals reset. 00409 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n 00410 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n 00411 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ForceReset\n 00412 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ForceReset\n 00413 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n 00414 * AHB1RSTR TSCRST LL_AHB1_GRP1_ForceReset\n 00415 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n 00416 * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ForceReset 00417 * @param Periphs This parameter can be a combination of the following values: 00418 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00419 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00420 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00421 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00422 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00423 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00424 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00425 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00426 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00427 * 00428 * (*) value not defined in all devices. 00429 * @retval None 00430 */ 00431 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) 00432 { 00433 SET_BIT(RCC->AHB1RSTR, Periphs); 00434 } 00435 00436 /** 00437 * @brief Release AHB1 peripherals reset. 00438 * @rmtoll AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n 00439 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n 00440 * AHB1RSTR DMAMUX1RST LL_AHB1_GRP1_ReleaseReset\n 00441 * AHB1RSTR FLASHRST LL_AHB1_GRP1_ReleaseReset\n 00442 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n 00443 * AHB1RSTR TSCRST LL_AHB1_GRP1_ReleaseReset\n 00444 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n 00445 * AHB1RSTR GFXMMURST LL_AHB1_GRP1_ReleaseReset 00446 * @param Periphs This parameter can be a combination of the following values: 00447 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL 00448 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00449 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00450 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00451 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00452 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00453 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00454 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00455 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00456 * 00457 * (*) value not defined in all devices. 00458 * @retval None 00459 */ 00460 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) 00461 { 00462 CLEAR_BIT(RCC->AHB1RSTR, Periphs); 00463 } 00464 00465 /** 00466 * @brief Enable AHB1 peripheral clocks in Sleep and Stop modes 00467 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00468 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00469 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00470 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00471 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00472 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00473 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00474 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_EnableClockStopSleep\n 00475 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_EnableClockStopSleep 00476 * @param Periphs This parameter can be a combination of the following values: 00477 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00478 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00479 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00480 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00481 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00482 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00483 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00484 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00485 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00486 * 00487 * (*) value not defined in all devices. 00488 * @retval None 00489 */ 00490 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockStopSleep(uint32_t Periphs) 00491 { 00492 __IO uint32_t tmpreg; 00493 SET_BIT(RCC->AHB1SMENR, Periphs); 00494 /* Delay after an RCC peripheral clock enabling */ 00495 tmpreg = READ_BIT(RCC->AHB1SMENR, Periphs); 00496 (void)tmpreg; 00497 } 00498 00499 /** 00500 * @brief Disable AHB1 peripheral clocks in Sleep and Stop modes 00501 * @rmtoll AHB1SMENR DMA1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00502 * AHB1SMENR DMA2SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00503 * AHB1SMENR DMAMUX1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00504 * AHB1SMENR FLASHSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00505 * AHB1SMENR SRAM1SMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00506 * AHB1SMENR CRCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00507 * AHB1SMENR TSCSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00508 * AHB1SMENR DMA2DSMEN LL_AHB1_GRP1_DisableClockStopSleep\n 00509 * AHB1SMENR GFXMMUSMEN LL_AHB1_GRP1_DisableClockStopSleep 00510 * @param Periphs This parameter can be a combination of the following values: 00511 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 00512 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2 00513 * @arg @ref LL_AHB1_GRP1_PERIPH_DMAMUX1 (*) 00514 * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH 00515 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1 00516 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC 00517 * @arg @ref LL_AHB1_GRP1_PERIPH_TSC 00518 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*) 00519 * @arg @ref LL_AHB1_GRP1_PERIPH_GFXMMU (*) 00520 * 00521 * (*) value not defined in all devices. 00522 * @retval None 00523 */ 00524 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockStopSleep(uint32_t Periphs) 00525 { 00526 CLEAR_BIT(RCC->AHB1SMENR, Periphs); 00527 } 00528 00529 /** 00530 * @} 00531 */ 00532 00533 /** @defgroup BUS_LL_EF_AHB2 AHB2 00534 * @{ 00535 */ 00536 00537 /** 00538 * @brief Enable AHB2 peripherals clock. 00539 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_EnableClock\n 00540 * AHB2ENR GPIOBEN LL_AHB2_GRP1_EnableClock\n 00541 * AHB2ENR GPIOCEN LL_AHB2_GRP1_EnableClock\n 00542 * AHB2ENR GPIODEN LL_AHB2_GRP1_EnableClock\n 00543 * AHB2ENR GPIOEEN LL_AHB2_GRP1_EnableClock\n 00544 * AHB2ENR GPIOFEN LL_AHB2_GRP1_EnableClock\n 00545 * AHB2ENR GPIOGEN LL_AHB2_GRP1_EnableClock\n 00546 * AHB2ENR GPIOHEN LL_AHB2_GRP1_EnableClock\n 00547 * AHB2ENR GPIOIEN LL_AHB2_GRP1_EnableClock\n 00548 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock\n 00549 * AHB2ENR ADCEN LL_AHB2_GRP1_EnableClock\n 00550 * AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n 00551 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n 00552 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n 00553 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n 00554 * AHB2ENR OSPIMEN LL_AHB2_GRP1_EnableClock\n 00555 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_EnableClock 00556 * @param Periphs This parameter can be a combination of the following values: 00557 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00558 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00559 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00560 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00561 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00562 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00563 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00564 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00565 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00566 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00567 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00568 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00569 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00570 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00571 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00572 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00573 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00574 * 00575 * (*) value not defined in all devices. 00576 * @retval None 00577 */ 00578 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs) 00579 { 00580 __IO uint32_t tmpreg; 00581 SET_BIT(RCC->AHB2ENR, Periphs); 00582 /* Delay after an RCC peripheral clock enabling */ 00583 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs); 00584 (void)tmpreg; 00585 } 00586 00587 /** 00588 * @brief Check if AHB2 peripheral clock is enabled or not 00589 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_IsEnabledClock\n 00590 * AHB2ENR GPIOBEN LL_AHB2_GRP1_IsEnabledClock\n 00591 * AHB2ENR GPIOCEN LL_AHB2_GRP1_IsEnabledClock\n 00592 * AHB2ENR GPIODEN LL_AHB2_GRP1_IsEnabledClock\n 00593 * AHB2ENR GPIOEEN LL_AHB2_GRP1_IsEnabledClock\n 00594 * AHB2ENR GPIOFEN LL_AHB2_GRP1_IsEnabledClock\n 00595 * AHB2ENR GPIOGEN LL_AHB2_GRP1_IsEnabledClock\n 00596 * AHB2ENR GPIOHEN LL_AHB2_GRP1_IsEnabledClock\n 00597 * AHB2ENR GPIOIEN LL_AHB2_GRP1_IsEnabledClock\n 00598 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock\n 00599 * AHB2ENR ADCEN LL_AHB2_GRP1_IsEnabledClock\n 00600 * AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n 00601 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n 00602 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n 00603 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n 00604 * AHB2ENR OSPIMEN LL_AHB2_GRP1_IsEnabledClock\n 00605 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_IsEnabledClock 00606 * @param Periphs This parameter can be a combination of the following values: 00607 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00608 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00609 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00610 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00611 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00612 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00613 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00614 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00615 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00616 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00617 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00618 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00619 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00620 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00621 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00622 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00623 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00624 * 00625 * (*) value not defined in all devices. 00626 * @retval State of Periphs (1 or 0). 00627 */ 00628 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs) 00629 { 00630 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs); 00631 } 00632 00633 /** 00634 * @brief Disable AHB2 peripherals clock. 00635 * @rmtoll AHB2ENR GPIOAEN LL_AHB2_GRP1_DisableClock\n 00636 * AHB2ENR GPIOBEN LL_AHB2_GRP1_DisableClock\n 00637 * AHB2ENR GPIOCEN LL_AHB2_GRP1_DisableClock\n 00638 * AHB2ENR GPIODEN LL_AHB2_GRP1_DisableClock\n 00639 * AHB2ENR GPIOEEN LL_AHB2_GRP1_DisableClock\n 00640 * AHB2ENR GPIOFEN LL_AHB2_GRP1_DisableClock\n 00641 * AHB2ENR GPIOGEN LL_AHB2_GRP1_DisableClock\n 00642 * AHB2ENR GPIOHEN LL_AHB2_GRP1_DisableClock\n 00643 * AHB2ENR GPIOIEN LL_AHB2_GRP1_DisableClock\n 00644 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock\n 00645 * AHB2ENR ADCEN LL_AHB2_GRP1_DisableClock\n 00646 * AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n 00647 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n 00648 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n 00649 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n 00650 * AHB2ENR OSPIMEN LL_AHB2_GRP1_DisableClock\n 00651 * AHB2ENR SDMMC1EN LL_AHB2_GRP1_DisableClock 00652 * @param Periphs This parameter can be a combination of the following values: 00653 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00654 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00655 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00656 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00657 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00658 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00659 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00660 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00661 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00662 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00663 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00664 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00665 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00666 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00667 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00668 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00669 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00670 * 00671 * (*) value not defined in all devices. 00672 * @retval None 00673 */ 00674 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs) 00675 { 00676 CLEAR_BIT(RCC->AHB2ENR, Periphs); 00677 } 00678 00679 /** 00680 * @brief Force AHB2 peripherals reset. 00681 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ForceReset\n 00682 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ForceReset\n 00683 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ForceReset\n 00684 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ForceReset\n 00685 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ForceReset\n 00686 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ForceReset\n 00687 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ForceReset\n 00688 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ForceReset\n 00689 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ForceReset\n 00690 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset\n 00691 * AHB2RSTR ADCRST LL_AHB2_GRP1_ForceReset\n 00692 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n 00693 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n 00694 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n 00695 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n 00696 * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ForceReset\n 00697 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ForceReset 00698 * @param Periphs This parameter can be a combination of the following values: 00699 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00700 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00701 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00702 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00703 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00704 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00705 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00706 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00707 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00708 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00709 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00710 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00711 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00712 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00713 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00714 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00715 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00716 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00717 * 00718 * (*) value not defined in all devices. 00719 * @retval None 00720 */ 00721 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs) 00722 { 00723 SET_BIT(RCC->AHB2RSTR, Periphs); 00724 } 00725 00726 /** 00727 * @brief Release AHB2 peripherals reset. 00728 * @rmtoll AHB2RSTR GPIOARST LL_AHB2_GRP1_ReleaseReset\n 00729 * AHB2RSTR GPIOBRST LL_AHB2_GRP1_ReleaseReset\n 00730 * AHB2RSTR GPIOCRST LL_AHB2_GRP1_ReleaseReset\n 00731 * AHB2RSTR GPIODRST LL_AHB2_GRP1_ReleaseReset\n 00732 * AHB2RSTR GPIOERST LL_AHB2_GRP1_ReleaseReset\n 00733 * AHB2RSTR GPIOFRST LL_AHB2_GRP1_ReleaseReset\n 00734 * AHB2RSTR GPIOGRST LL_AHB2_GRP1_ReleaseReset\n 00735 * AHB2RSTR GPIOHRST LL_AHB2_GRP1_ReleaseReset\n 00736 * AHB2RSTR GPIOIRST LL_AHB2_GRP1_ReleaseReset\n 00737 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset\n 00738 * AHB2RSTR ADCRST LL_AHB2_GRP1_ReleaseReset\n 00739 * AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n 00740 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n 00741 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n 00742 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n 00743 * AHB2RSTR OSPIMRST LL_AHB2_GRP1_ReleaseReset\n 00744 * AHB2RSTR SDMMC1RST LL_AHB2_GRP1_ReleaseReset 00745 * @param Periphs This parameter can be a combination of the following values: 00746 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00747 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00748 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00749 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00750 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00751 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00752 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00753 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00754 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00755 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00756 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00757 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00758 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00759 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00760 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00761 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00762 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00763 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00764 * 00765 * (*) value not defined in all devices. 00766 * @retval None 00767 */ 00768 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs) 00769 { 00770 CLEAR_BIT(RCC->AHB2RSTR, Periphs); 00771 } 00772 00773 /** 00774 * @brief Enable AHB2 peripheral clocks in Sleep and Stop modes 00775 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00776 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00777 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00778 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00779 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00780 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00781 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00782 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00783 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00784 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00785 * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00786 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00787 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00788 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00789 * AHB2SMENR AESSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00790 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00791 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00792 * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_EnableClockStopSleep\n 00793 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_EnableClockStopSleep 00794 * @param Periphs This parameter can be a combination of the following values: 00795 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00796 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00797 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00798 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00799 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00800 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00801 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00802 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00803 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00804 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 00805 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) 00806 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00807 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00808 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00809 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00810 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00811 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00812 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00813 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00814 * 00815 * (*) value not defined in all devices. 00816 * @retval None 00817 */ 00818 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockStopSleep(uint32_t Periphs) 00819 { 00820 __IO uint32_t tmpreg; 00821 SET_BIT(RCC->AHB2SMENR, Periphs); 00822 /* Delay after an RCC peripheral clock enabling */ 00823 tmpreg = READ_BIT(RCC->AHB2SMENR, Periphs); 00824 (void)tmpreg; 00825 } 00826 00827 /** 00828 * @brief Disable AHB2 peripheral clocks in Sleep and Stop modes 00829 * @rmtoll AHB2SMENR GPIOASMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00830 * AHB2SMENR GPIOBSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00831 * AHB2SMENR GPIOCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00832 * AHB2SMENR GPIODSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00833 * AHB2SMENR GPIOESMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00834 * AHB2SMENR GPIOFSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00835 * AHB2SMENR GPIOGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00836 * AHB2SMENR GPIOHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00837 * AHB2SMENR GPIOISMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00838 * AHB2SMENR SRAM2SMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00839 * AHB2SMENR SRAM3SMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00840 * AHB2SMENR OTGFSSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00841 * AHB2SMENR ADCSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00842 * AHB2SMENR DCMISMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00843 * AHB2SMENR AESSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00844 * AHB2SMENR HASHSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00845 * AHB2SMENR RNGSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00846 * AHB2SMENR OSPIMSMEN LL_AHB2_GRP1_DisableClockStopSleep\n 00847 * AHB2SMENR SDMMC1SMEN LL_AHB2_GRP1_DisableClockStopSleep 00848 * @param Periphs This parameter can be a combination of the following values: 00849 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOA 00850 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOB 00851 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOC 00852 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOD (*) 00853 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOE (*) 00854 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOF (*) 00855 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOG (*) 00856 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOH 00857 * @arg @ref LL_AHB2_GRP1_PERIPH_GPIOI (*) 00858 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM2 00859 * @arg @ref LL_AHB2_GRP1_PERIPH_SRAM3 (*) 00860 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS (*) 00861 * @arg @ref LL_AHB2_GRP1_PERIPH_ADC 00862 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*) 00863 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*) 00864 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*) 00865 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG 00866 * @arg @ref LL_AHB2_GRP1_PERIPH_OSPIM (*) 00867 * @arg @ref LL_AHB2_GRP1_PERIPH_SDMMC1 (*) 00868 * 00869 * (*) value not defined in all devices. 00870 * @retval None 00871 */ 00872 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockStopSleep(uint32_t Periphs) 00873 { 00874 CLEAR_BIT(RCC->AHB2SMENR, Periphs); 00875 } 00876 00877 /** 00878 * @} 00879 */ 00880 00881 /** @defgroup BUS_LL_EF_AHB3 AHB3 00882 * @{ 00883 */ 00884 00885 /** 00886 * @brief Enable AHB3 peripherals clock. 00887 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n 00888 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock\n 00889 * AHB3ENR OSPI1EN LL_AHB3_GRP1_EnableClock\n 00890 * AHB3ENR OSPI2EN LL_AHB3_GRP1_EnableClock 00891 * @param Periphs This parameter can be a combination of the following values: 00892 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00893 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00894 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00895 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00896 * 00897 * (*) value not defined in all devices. 00898 * @retval None 00899 */ 00900 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs) 00901 { 00902 __IO uint32_t tmpreg; 00903 SET_BIT(RCC->AHB3ENR, Periphs); 00904 /* Delay after an RCC peripheral clock enabling */ 00905 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs); 00906 (void)tmpreg; 00907 } 00908 00909 /** 00910 * @brief Check if AHB3 peripheral clock is enabled or not 00911 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n 00912 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock\n 00913 * AHB3ENR OSPI1EN LL_AHB3_GRP1_IsEnabledClock\n 00914 * AHB3ENR OSPI2EN LL_AHB3_GRP1_IsEnabledClock 00915 * @param Periphs This parameter can be a combination of the following values: 00916 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00917 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00918 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00919 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00920 * 00921 * (*) value not defined in all devices. 00922 * @retval State of Periphs (1 or 0). 00923 */ 00924 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs) 00925 { 00926 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs); 00927 } 00928 00929 /** 00930 * @brief Disable AHB3 peripherals clock. 00931 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n 00932 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock\n 00933 * AHB3ENR OSPI1EN LL_AHB3_GRP1_DisableClock\n 00934 * AHB3ENR OSPI2EN LL_AHB3_GRP1_DisableClock 00935 * @param Periphs This parameter can be a combination of the following values: 00936 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00937 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00938 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00939 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00940 * 00941 * (*) value not defined in all devices. 00942 * @retval None 00943 */ 00944 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs) 00945 { 00946 CLEAR_BIT(RCC->AHB3ENR, Periphs); 00947 } 00948 00949 /** 00950 * @brief Force AHB3 peripherals reset. 00951 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n 00952 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset\n 00953 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ForceReset\n 00954 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ForceReset 00955 * @param Periphs This parameter can be a combination of the following values: 00956 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL 00957 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00958 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00959 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00960 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00961 * 00962 * (*) value not defined in all devices. 00963 * @retval None 00964 */ 00965 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs) 00966 { 00967 SET_BIT(RCC->AHB3RSTR, Periphs); 00968 } 00969 00970 /** 00971 * @brief Release AHB3 peripherals reset. 00972 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n 00973 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset\n 00974 * AHB3RSTR OSPI1RST LL_AHB3_GRP1_ReleaseReset\n 00975 * AHB3RSTR OSPI2RST LL_AHB3_GRP1_ReleaseReset 00976 * @param Periphs This parameter can be a combination of the following values: 00977 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL 00978 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00979 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 00980 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 00981 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 00982 * 00983 * (*) value not defined in all devices. 00984 * @retval None 00985 */ 00986 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs) 00987 { 00988 CLEAR_BIT(RCC->AHB3RSTR, Periphs); 00989 } 00990 00991 /** 00992 * @brief Enable AHB3 peripheral clocks in Sleep and Stop modes 00993 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_EnableClockStopSleep\n 00994 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_EnableClockStopSleep\n 00995 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_EnableClockStopSleep\n 00996 * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_EnableClockStopSleep 00997 * @param Periphs This parameter can be a combination of the following values: 00998 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 00999 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01000 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 01001 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 01002 * 01003 * (*) value not defined in all devices. 01004 * @retval None 01005 */ 01006 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockStopSleep(uint32_t Periphs) 01007 { 01008 __IO uint32_t tmpreg; 01009 SET_BIT(RCC->AHB3SMENR, Periphs); 01010 /* Delay after an RCC peripheral clock enabling */ 01011 tmpreg = READ_BIT(RCC->AHB3SMENR, Periphs); 01012 (void)tmpreg; 01013 } 01014 01015 /** 01016 * @brief Disable AHB3 peripheral clocks in Sleep and Stop modes 01017 * @rmtoll AHB3SMENR FMCSMEN LL_AHB3_GRP1_DisableClockStopSleep\n 01018 * AHB3SMENR QSPISMEN LL_AHB3_GRP1_DisableClockStopSleep\n 01019 * AHB3SMENR OSPI1SMEN LL_AHB3_GRP1_DisableClockStopSleep\n 01020 * AHB3SMENR OSPI2SMEN LL_AHB3_GRP1_DisableClockStopSleep\n 01021 * @param Periphs This parameter can be a combination of the following values: 01022 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*) 01023 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI (*) 01024 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI1 (*) 01025 * @arg @ref LL_AHB3_GRP1_PERIPH_OSPI2 (*) 01026 * 01027 * (*) value not defined in all devices. 01028 * @retval None 01029 */ 01030 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockStopSleep(uint32_t Periphs) 01031 { 01032 CLEAR_BIT(RCC->AHB3SMENR, Periphs); 01033 } 01034 01035 /** 01036 * @} 01037 */ 01038 01039 /** @defgroup BUS_LL_EF_APB1 APB1 01040 * @{ 01041 */ 01042 01043 /** 01044 * @brief Enable APB1 peripherals clock. 01045 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_EnableClock\n 01046 * APB1ENR1 TIM3EN LL_APB1_GRP1_EnableClock\n 01047 * APB1ENR1 TIM4EN LL_APB1_GRP1_EnableClock\n 01048 * APB1ENR1 TIM5EN LL_APB1_GRP1_EnableClock\n 01049 * APB1ENR1 TIM6EN LL_APB1_GRP1_EnableClock\n 01050 * APB1ENR1 TIM7EN LL_APB1_GRP1_EnableClock\n 01051 * APB1ENR1 LCDEN LL_APB1_GRP1_EnableClock\n 01052 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_EnableClock\n 01053 * APB1ENR1 WWDGEN LL_APB1_GRP1_EnableClock\n 01054 * APB1ENR1 SPI2EN LL_APB1_GRP1_EnableClock\n 01055 * APB1ENR1 SPI3EN LL_APB1_GRP1_EnableClock\n 01056 * APB1ENR1 USART2EN LL_APB1_GRP1_EnableClock\n 01057 * APB1ENR1 USART3EN LL_APB1_GRP1_EnableClock\n 01058 * APB1ENR1 UART4EN LL_APB1_GRP1_EnableClock\n 01059 * APB1ENR1 UART5EN LL_APB1_GRP1_EnableClock\n 01060 * APB1ENR1 I2C1EN LL_APB1_GRP1_EnableClock\n 01061 * APB1ENR1 I2C2EN LL_APB1_GRP1_EnableClock\n 01062 * APB1ENR1 I2C3EN LL_APB1_GRP1_EnableClock\n 01063 * APB1ENR1 CRSEN LL_APB1_GRP1_EnableClock\n 01064 * APB1ENR1 CAN1EN LL_APB1_GRP1_EnableClock\n 01065 * APB1ENR1 USBFSEN LL_APB1_GRP1_EnableClock\n 01066 * APB1ENR1 CAN2EN LL_APB1_GRP1_EnableClock\n 01067 * APB1ENR1 PWREN LL_APB1_GRP1_EnableClock\n 01068 * APB1ENR1 DAC1EN LL_APB1_GRP1_EnableClock\n 01069 * APB1ENR1 OPAMPEN LL_APB1_GRP1_EnableClock\n 01070 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_EnableClock 01071 * @param Periphs This parameter can be a combination of the following values: 01072 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01073 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01074 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01075 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01076 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01077 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01078 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01079 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01080 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01081 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01082 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01083 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01084 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01085 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01086 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01087 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01088 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01089 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01090 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01091 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01092 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01093 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01094 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01095 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01096 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01097 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01098 * 01099 * (*) value not defined in all devices. 01100 * @retval None 01101 */ 01102 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) 01103 { 01104 __IO uint32_t tmpreg; 01105 SET_BIT(RCC->APB1ENR1, Periphs); 01106 /* Delay after an RCC peripheral clock enabling */ 01107 tmpreg = READ_BIT(RCC->APB1ENR1, Periphs); 01108 (void)tmpreg; 01109 } 01110 01111 /** 01112 * @brief Enable APB1 peripherals clock. 01113 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_EnableClock\n 01114 * APB1ENR2 I2C4EN LL_APB1_GRP2_EnableClock\n 01115 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_EnableClock\n 01116 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_EnableClock 01117 * @param Periphs This parameter can be a combination of the following values: 01118 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01119 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01120 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01121 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01122 * 01123 * (*) value not defined in all devices. 01124 * @retval None 01125 */ 01126 __STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) 01127 { 01128 __IO uint32_t tmpreg; 01129 SET_BIT(RCC->APB1ENR2, Periphs); 01130 /* Delay after an RCC peripheral clock enabling */ 01131 tmpreg = READ_BIT(RCC->APB1ENR2, Periphs); 01132 (void)tmpreg; 01133 } 01134 01135 /** 01136 * @brief Check if APB1 peripheral clock is enabled or not 01137 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_IsEnabledClock\n 01138 * APB1ENR1 TIM3EN LL_APB1_GRP1_IsEnabledClock\n 01139 * APB1ENR1 TIM4EN LL_APB1_GRP1_IsEnabledClock\n 01140 * APB1ENR1 TIM5EN LL_APB1_GRP1_IsEnabledClock\n 01141 * APB1ENR1 TIM6EN LL_APB1_GRP1_IsEnabledClock\n 01142 * APB1ENR1 TIM7EN LL_APB1_GRP1_IsEnabledClock\n 01143 * APB1ENR1 LCDEN LL_APB1_GRP1_IsEnabledClock\n 01144 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_IsEnabledClock\n 01145 * APB1ENR1 WWDGEN LL_APB1_GRP1_IsEnabledClock\n 01146 * APB1ENR1 SPI2EN LL_APB1_GRP1_IsEnabledClock\n 01147 * APB1ENR1 SPI3EN LL_APB1_GRP1_IsEnabledClock\n 01148 * APB1ENR1 USART2EN LL_APB1_GRP1_IsEnabledClock\n 01149 * APB1ENR1 USART3EN LL_APB1_GRP1_IsEnabledClock\n 01150 * APB1ENR1 UART4EN LL_APB1_GRP1_IsEnabledClock\n 01151 * APB1ENR1 UART5EN LL_APB1_GRP1_IsEnabledClock\n 01152 * APB1ENR1 I2C1EN LL_APB1_GRP1_IsEnabledClock\n 01153 * APB1ENR1 I2C2EN LL_APB1_GRP1_IsEnabledClock\n 01154 * APB1ENR1 I2C3EN LL_APB1_GRP1_IsEnabledClock\n 01155 * APB1ENR1 CRSEN LL_APB1_GRP1_IsEnabledClock\n 01156 * APB1ENR1 CAN1EN LL_APB1_GRP1_IsEnabledClock\n 01157 * APB1ENR1 USBFSEN LL_APB1_GRP1_IsEnabledClock\n 01158 * APB1ENR1 CAN2EN LL_APB1_GRP1_IsEnabledClock\n 01159 * APB1ENR1 PWREN LL_APB1_GRP1_IsEnabledClock\n 01160 * APB1ENR1 DAC1EN LL_APB1_GRP1_IsEnabledClock\n 01161 * APB1ENR1 OPAMPEN LL_APB1_GRP1_IsEnabledClock\n 01162 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_IsEnabledClock 01163 * @param Periphs This parameter can be a combination of the following values: 01164 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01165 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01166 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01167 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01168 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01169 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01170 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01171 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01172 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01173 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01174 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01175 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01176 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01177 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01178 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01179 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01180 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01181 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01182 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01183 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01184 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01185 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01186 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01187 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01188 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01189 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01190 * 01191 * (*) value not defined in all devices. 01192 * @retval State of Periphs (1 or 0). 01193 */ 01194 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) 01195 { 01196 return (READ_BIT(RCC->APB1ENR1, Periphs) == Periphs); 01197 } 01198 01199 /** 01200 * @brief Check if APB1 peripheral clock is enabled or not 01201 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_IsEnabledClock\n 01202 * APB1ENR2 I2C4EN LL_APB1_GRP2_IsEnabledClock\n 01203 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_IsEnabledClock\n 01204 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_IsEnabledClock 01205 * @param Periphs This parameter can be a combination of the following values: 01206 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01207 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01208 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01209 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01210 * 01211 * (*) value not defined in all devices. 01212 * @retval State of Periphs (1 or 0). 01213 */ 01214 __STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) 01215 { 01216 return (READ_BIT(RCC->APB1ENR2, Periphs) == Periphs); 01217 } 01218 01219 /** 01220 * @brief Disable APB1 peripherals clock. 01221 * @rmtoll APB1ENR1 TIM2EN LL_APB1_GRP1_DisableClock\n 01222 * APB1ENR1 TIM3EN LL_APB1_GRP1_DisableClock\n 01223 * APB1ENR1 TIM4EN LL_APB1_GRP1_DisableClock\n 01224 * APB1ENR1 TIM5EN LL_APB1_GRP1_DisableClock\n 01225 * APB1ENR1 TIM6EN LL_APB1_GRP1_DisableClock\n 01226 * APB1ENR1 TIM7EN LL_APB1_GRP1_DisableClock\n 01227 * APB1ENR1 LCDEN LL_APB1_GRP1_DisableClock\n 01228 * APB1ENR1 RTCAPBEN LL_APB1_GRP1_DisableClock\n 01229 * APB1ENR1 WWDGEN LL_APB1_GRP1_DisableClock\n 01230 * APB1ENR1 SPI2EN LL_APB1_GRP1_DisableClock\n 01231 * APB1ENR1 SPI3EN LL_APB1_GRP1_DisableClock\n 01232 * APB1ENR1 USART2EN LL_APB1_GRP1_DisableClock\n 01233 * APB1ENR1 USART3EN LL_APB1_GRP1_DisableClock\n 01234 * APB1ENR1 UART4EN LL_APB1_GRP1_DisableClock\n 01235 * APB1ENR1 UART5EN LL_APB1_GRP1_DisableClock\n 01236 * APB1ENR1 I2C1EN LL_APB1_GRP1_DisableClock\n 01237 * APB1ENR1 I2C2EN LL_APB1_GRP1_DisableClock\n 01238 * APB1ENR1 I2C3EN LL_APB1_GRP1_DisableClock\n 01239 * APB1ENR1 CRSEN LL_APB1_GRP1_DisableClock\n 01240 * APB1ENR1 CAN1EN LL_APB1_GRP1_DisableClock\n 01241 * APB1ENR1 USBFSEN LL_APB1_GRP1_DisableClock\n 01242 * APB1ENR1 CAN2EN LL_APB1_GRP1_DisableClock\n 01243 * APB1ENR1 PWREN LL_APB1_GRP1_DisableClock\n 01244 * APB1ENR1 DAC1EN LL_APB1_GRP1_DisableClock\n 01245 * APB1ENR1 OPAMPEN LL_APB1_GRP1_DisableClock\n 01246 * APB1ENR1 LPTIM1EN LL_APB1_GRP1_DisableClock 01247 * @param Periphs This parameter can be a combination of the following values: 01248 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01249 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01250 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01251 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01252 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01253 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01254 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01255 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01256 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01257 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01258 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01259 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01260 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01261 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01262 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01263 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01264 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01265 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01266 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01267 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01268 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01269 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01270 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01271 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01272 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01273 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01274 * 01275 * (*) value not defined in all devices. 01276 * @retval None 01277 */ 01278 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) 01279 { 01280 CLEAR_BIT(RCC->APB1ENR1, Periphs); 01281 } 01282 01283 /** 01284 * @brief Disable APB1 peripherals clock. 01285 * @rmtoll APB1ENR2 LPUART1EN LL_APB1_GRP2_DisableClock\n 01286 * APB1ENR2 I2C4EN LL_APB1_GRP2_DisableClock\n 01287 * APB1ENR2 SWPMI1EN LL_APB1_GRP2_DisableClock\n 01288 * APB1ENR2 LPTIM2EN LL_APB1_GRP2_DisableClock 01289 * @param Periphs This parameter can be a combination of the following values: 01290 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01291 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01292 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01293 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01294 * 01295 * (*) value not defined in all devices. 01296 * @retval None 01297 */ 01298 __STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) 01299 { 01300 CLEAR_BIT(RCC->APB1ENR2, Periphs); 01301 } 01302 01303 /** 01304 * @brief Force APB1 peripherals reset. 01305 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ForceReset\n 01306 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ForceReset\n 01307 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ForceReset\n 01308 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ForceReset\n 01309 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ForceReset\n 01310 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ForceReset\n 01311 * APB1RSTR1 LCDRST LL_APB1_GRP1_ForceReset\n 01312 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ForceReset\n 01313 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ForceReset\n 01314 * APB1RSTR1 USART2RST LL_APB1_GRP1_ForceReset\n 01315 * APB1RSTR1 USART3RST LL_APB1_GRP1_ForceReset\n 01316 * APB1RSTR1 UART4RST LL_APB1_GRP1_ForceReset\n 01317 * APB1RSTR1 UART5RST LL_APB1_GRP1_ForceReset\n 01318 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ForceReset\n 01319 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ForceReset\n 01320 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ForceReset\n 01321 * APB1RSTR1 CRSRST LL_APB1_GRP1_ForceReset\n 01322 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ForceReset\n 01323 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ForceReset\n 01324 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ForceReset\n 01325 * APB1RSTR1 PWRRST LL_APB1_GRP1_ForceReset\n 01326 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ForceReset\n 01327 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ForceReset\n 01328 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ForceReset 01329 * @param Periphs This parameter can be a combination of the following values: 01330 * @arg @ref LL_APB1_GRP1_PERIPH_ALL 01331 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01332 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01333 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01334 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01335 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01336 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01337 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01338 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01339 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01340 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01341 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01342 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01343 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01344 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01345 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01346 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01347 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01348 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01349 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01350 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01351 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01352 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01353 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01354 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01355 * 01356 * (*) value not defined in all devices. 01357 * @retval None 01358 */ 01359 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) 01360 { 01361 SET_BIT(RCC->APB1RSTR1, Periphs); 01362 } 01363 01364 /** 01365 * @brief Force APB1 peripherals reset. 01366 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ForceReset\n 01367 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ForceReset\n 01368 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ForceReset\n 01369 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ForceReset 01370 * @param Periphs This parameter can be a combination of the following values: 01371 * @arg @ref LL_APB1_GRP2_PERIPH_ALL 01372 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01373 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01374 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01375 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01376 * 01377 * (*) value not defined in all devices. 01378 * @retval None 01379 */ 01380 __STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) 01381 { 01382 SET_BIT(RCC->APB1RSTR2, Periphs); 01383 } 01384 01385 /** 01386 * @brief Release APB1 peripherals reset. 01387 * @rmtoll APB1RSTR1 TIM2RST LL_APB1_GRP1_ReleaseReset\n 01388 * APB1RSTR1 TIM3RST LL_APB1_GRP1_ReleaseReset\n 01389 * APB1RSTR1 TIM4RST LL_APB1_GRP1_ReleaseReset\n 01390 * APB1RSTR1 TIM5RST LL_APB1_GRP1_ReleaseReset\n 01391 * APB1RSTR1 TIM6RST LL_APB1_GRP1_ReleaseReset\n 01392 * APB1RSTR1 TIM7RST LL_APB1_GRP1_ReleaseReset\n 01393 * APB1RSTR1 LCDRST LL_APB1_GRP1_ReleaseReset\n 01394 * APB1RSTR1 SPI2RST LL_APB1_GRP1_ReleaseReset\n 01395 * APB1RSTR1 SPI3RST LL_APB1_GRP1_ReleaseReset\n 01396 * APB1RSTR1 USART2RST LL_APB1_GRP1_ReleaseReset\n 01397 * APB1RSTR1 USART3RST LL_APB1_GRP1_ReleaseReset\n 01398 * APB1RSTR1 UART4RST LL_APB1_GRP1_ReleaseReset\n 01399 * APB1RSTR1 UART5RST LL_APB1_GRP1_ReleaseReset\n 01400 * APB1RSTR1 I2C1RST LL_APB1_GRP1_ReleaseReset\n 01401 * APB1RSTR1 I2C2RST LL_APB1_GRP1_ReleaseReset\n 01402 * APB1RSTR1 I2C3RST LL_APB1_GRP1_ReleaseReset\n 01403 * APB1RSTR1 CRSRST LL_APB1_GRP1_ReleaseReset\n 01404 * APB1RSTR1 CAN1RST LL_APB1_GRP1_ReleaseReset\n 01405 * APB1RSTR1 USBFSRST LL_APB1_GRP1_ReleaseReset\n 01406 * APB1RSTR1 CAN2RST LL_APB1_GRP1_ReleaseReset\n 01407 * APB1RSTR1 PWRRST LL_APB1_GRP1_ReleaseReset\n 01408 * APB1RSTR1 DAC1RST LL_APB1_GRP1_ReleaseReset\n 01409 * APB1RSTR1 OPAMPRST LL_APB1_GRP1_ReleaseReset\n 01410 * APB1RSTR1 LPTIM1RST LL_APB1_GRP1_ReleaseReset 01411 * @param Periphs This parameter can be a combination of the following values: 01412 * @arg @ref LL_APB1_GRP1_PERIPH_ALL 01413 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01414 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01415 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01416 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01417 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01418 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01419 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01420 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01421 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01422 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01423 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01424 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01425 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01426 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01427 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01428 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01429 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01430 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01431 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01432 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01433 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01434 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01435 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01436 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01437 * 01438 * (*) value not defined in all devices. 01439 * @retval None 01440 */ 01441 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) 01442 { 01443 CLEAR_BIT(RCC->APB1RSTR1, Periphs); 01444 } 01445 01446 /** 01447 * @brief Release APB1 peripherals reset. 01448 * @rmtoll APB1RSTR2 LPUART1RST LL_APB1_GRP2_ReleaseReset\n 01449 * APB1RSTR2 I2C4RST LL_APB1_GRP2_ReleaseReset\n 01450 * APB1RSTR2 SWPMI1RST LL_APB1_GRP2_ReleaseReset\n 01451 * APB1RSTR2 LPTIM2RST LL_APB1_GRP2_ReleaseReset 01452 * @param Periphs This parameter can be a combination of the following values: 01453 * @arg @ref LL_APB1_GRP2_PERIPH_ALL 01454 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01455 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01456 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01457 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01458 * 01459 * (*) value not defined in all devices. 01460 * @retval None 01461 */ 01462 __STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) 01463 { 01464 CLEAR_BIT(RCC->APB1RSTR2, Periphs); 01465 } 01466 01467 /** 01468 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes 01469 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01470 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01471 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01472 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01473 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01474 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01475 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01476 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01477 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01478 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01479 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01480 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01481 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01482 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01483 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01484 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01485 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01486 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01487 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01488 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01489 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01490 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01491 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01492 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_EnableClockStopSleep\n 01493 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_EnableClockStopSleep\n 01494 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_EnableClockStopSleep 01495 * @param Periphs This parameter can be a combination of the following values: 01496 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01497 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01498 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01499 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01500 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01501 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01502 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01503 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01504 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01505 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01506 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01507 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01508 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01509 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01510 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01511 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01512 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01513 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01514 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01515 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01516 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01517 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01518 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01519 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01520 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01521 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01522 * 01523 * (*) value not defined in all devices. 01524 * @retval None 01525 */ 01526 __STATIC_INLINE void LL_APB1_GRP1_EnableClockStopSleep(uint32_t Periphs) 01527 { 01528 __IO uint32_t tmpreg; 01529 SET_BIT(RCC->APB1SMENR1, Periphs); 01530 /* Delay after an RCC peripheral clock enabling */ 01531 tmpreg = READ_BIT(RCC->APB1SMENR1, Periphs); 01532 (void)tmpreg; 01533 } 01534 01535 /** 01536 * @brief Enable APB1 peripheral clocks in Sleep and Stop modes 01537 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_EnableClockStopSleep\n 01538 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_EnableClockStopSleep\n 01539 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_EnableClockStopSleep\n 01540 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_EnableClockStopSleep 01541 * @param Periphs This parameter can be a combination of the following values: 01542 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01543 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01544 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01545 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01546 * 01547 * (*) value not defined in all devices. 01548 * @retval None 01549 */ 01550 __STATIC_INLINE void LL_APB1_GRP2_EnableClockStopSleep(uint32_t Periphs) 01551 { 01552 __IO uint32_t tmpreg; 01553 SET_BIT(RCC->APB1SMENR2, Periphs); 01554 /* Delay after an RCC peripheral clock enabling */ 01555 tmpreg = READ_BIT(RCC->APB1SMENR2, Periphs); 01556 (void)tmpreg; 01557 } 01558 01559 /** 01560 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes 01561 * @rmtoll APB1SMENR1 TIM2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01562 * APB1SMENR1 TIM3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01563 * APB1SMENR1 TIM4SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01564 * APB1SMENR1 TIM5SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01565 * APB1SMENR1 TIM6SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01566 * APB1SMENR1 TIM7SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01567 * APB1SMENR1 LCDSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01568 * APB1SMENR1 RTCAPBSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01569 * APB1SMENR1 WWDGSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01570 * APB1SMENR1 SPI2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01571 * APB1SMENR1 SPI3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01572 * APB1SMENR1 USART2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01573 * APB1SMENR1 USART3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01574 * APB1SMENR1 UART4SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01575 * APB1SMENR1 UART5SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01576 * APB1SMENR1 I2C1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01577 * APB1SMENR1 I2C2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01578 * APB1SMENR1 I2C3SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01579 * APB1SMENR1 CRSSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01580 * APB1SMENR1 CAN1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01581 * APB1SMENR1 USBFSSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01582 * APB1SMENR1 CAN2SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01583 * APB1SMENR1 PWRSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01584 * APB1SMENR1 DAC1SMEN LL_APB1_GRP1_DisableClockStopSleep\n 01585 * APB1SMENR1 OPAMPSMEN LL_APB1_GRP1_DisableClockStopSleep\n 01586 * APB1SMENR1 LPTIM1SMEN LL_APB1_GRP1_DisableClockStopSleep 01587 * @param Periphs This parameter can be a combination of the following values: 01588 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2 01589 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 (*) 01590 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4 (*) 01591 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5 (*) 01592 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6 01593 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7 01594 * @arg @ref LL_APB1_GRP1_PERIPH_LCD (*) 01595 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*) 01596 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG 01597 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 (*) 01598 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3 01599 * @arg @ref LL_APB1_GRP1_PERIPH_USART2 01600 * @arg @ref LL_APB1_GRP1_PERIPH_USART3 (*) 01601 * @arg @ref LL_APB1_GRP1_PERIPH_UART4 (*) 01602 * @arg @ref LL_APB1_GRP1_PERIPH_UART5 (*) 01603 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 01604 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2 (*) 01605 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3 01606 * @arg @ref LL_APB1_GRP1_PERIPH_CRS (*) 01607 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1 01608 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*) 01609 * @arg @ref LL_APB1_GRP1_PERIPH_USB (*) 01610 * @arg @ref LL_APB1_GRP1_PERIPH_PWR 01611 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1 01612 * @arg @ref LL_APB1_GRP1_PERIPH_OPAMP 01613 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 01614 * 01615 * (*) value not defined in all devices. 01616 * @retval None 01617 */ 01618 __STATIC_INLINE void LL_APB1_GRP1_DisableClockStopSleep(uint32_t Periphs) 01619 { 01620 CLEAR_BIT(RCC->APB1SMENR1, Periphs); 01621 } 01622 01623 /** 01624 * @brief Disable APB1 peripheral clocks in Sleep and Stop modes 01625 * @rmtoll APB1SMENR2 LPUART1SMEN LL_APB1_GRP2_DisableClockStopSleep\n 01626 * APB1SMENR2 I2C4SMEN LL_APB1_GRP2_DisableClockStopSleep\n 01627 * APB1SMENR2 SWPMI1SMEN LL_APB1_GRP2_DisableClockStopSleep\n 01628 * APB1SMENR2 LPTIM2SMEN LL_APB1_GRP2_DisableClockStopSleep 01629 * @param Periphs This parameter can be a combination of the following values: 01630 * @arg @ref LL_APB1_GRP2_PERIPH_LPUART1 01631 * @arg @ref LL_APB1_GRP2_PERIPH_I2C4 (*) 01632 * @arg @ref LL_APB1_GRP2_PERIPH_SWPMI1 (*) 01633 * @arg @ref LL_APB1_GRP2_PERIPH_LPTIM2 01634 * 01635 * (*) value not defined in all devices. 01636 * @retval None 01637 */ 01638 __STATIC_INLINE void LL_APB1_GRP2_DisableClockStopSleep(uint32_t Periphs) 01639 { 01640 CLEAR_BIT(RCC->APB1SMENR2, Periphs); 01641 } 01642 01643 /** 01644 * @} 01645 */ 01646 01647 /** @defgroup BUS_LL_EF_APB2 APB2 01648 * @{ 01649 */ 01650 01651 /** 01652 * @brief Enable APB2 peripherals clock. 01653 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n 01654 * APB2ENR FWEN LL_APB2_GRP1_EnableClock\n 01655 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n 01656 * APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n 01657 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n 01658 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n 01659 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n 01660 * APB2ENR TIM15EN LL_APB2_GRP1_EnableClock\n 01661 * APB2ENR TIM16EN LL_APB2_GRP1_EnableClock\n 01662 * APB2ENR TIM17EN LL_APB2_GRP1_EnableClock\n 01663 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n 01664 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n 01665 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n 01666 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n 01667 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock 01668 * @param Periphs This parameter can be a combination of the following values: 01669 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01670 * @arg @ref LL_APB2_GRP1_PERIPH_FW 01671 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01672 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01673 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01674 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01675 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01676 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01677 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01678 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01679 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01680 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01681 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01682 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01683 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01684 * 01685 * (*) value not defined in all devices. 01686 * @retval None 01687 */ 01688 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs) 01689 { 01690 __IO uint32_t tmpreg; 01691 SET_BIT(RCC->APB2ENR, Periphs); 01692 /* Delay after an RCC peripheral clock enabling */ 01693 tmpreg = READ_BIT(RCC->APB2ENR, Periphs); 01694 (void)tmpreg; 01695 } 01696 01697 /** 01698 * @brief Check if APB2 peripheral clock is enabled or not 01699 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n 01700 * APB2ENR FWEN LL_APB2_GRP1_IsEnabledClock\n 01701 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n 01702 * APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n 01703 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n 01704 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n 01705 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n 01706 * APB2ENR TIM15EN LL_APB2_GRP1_IsEnabledClock\n 01707 * APB2ENR TIM16EN LL_APB2_GRP1_IsEnabledClock\n 01708 * APB2ENR TIM17EN LL_APB2_GRP1_IsEnabledClock\n 01709 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n 01710 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n 01711 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n 01712 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n 01713 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock 01714 * @param Periphs This parameter can be a combination of the following values: 01715 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01716 * @arg @ref LL_APB2_GRP1_PERIPH_FW 01717 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01718 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01719 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01720 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01721 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01722 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01723 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01724 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01725 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01726 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01727 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01728 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01729 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01730 * 01731 * (*) value not defined in all devices. 01732 * @retval State of Periphs (1 or 0). 01733 */ 01734 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs) 01735 { 01736 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs); 01737 } 01738 01739 /** 01740 * @brief Disable APB2 peripherals clock. 01741 * @rmtoll APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n 01742 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n 01743 * APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n 01744 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n 01745 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n 01746 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n 01747 * APB2ENR TIM15EN LL_APB2_GRP1_DisableClock\n 01748 * APB2ENR TIM16EN LL_APB2_GRP1_DisableClock\n 01749 * APB2ENR TIM17EN LL_APB2_GRP1_DisableClock\n 01750 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n 01751 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n 01752 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n 01753 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n 01754 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock 01755 * @param Periphs This parameter can be a combination of the following values: 01756 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01757 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01758 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01759 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01760 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01761 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01762 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01763 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01764 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01765 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01766 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01767 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01768 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01769 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01770 * 01771 * (*) value not defined in all devices. 01772 * @retval None 01773 */ 01774 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs) 01775 { 01776 CLEAR_BIT(RCC->APB2ENR, Periphs); 01777 } 01778 01779 /** 01780 * @brief Force APB2 peripherals reset. 01781 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n 01782 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n 01783 * APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n 01784 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n 01785 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n 01786 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n 01787 * APB2RSTR TIM15RST LL_APB2_GRP1_ForceReset\n 01788 * APB2RSTR TIM16RST LL_APB2_GRP1_ForceReset\n 01789 * APB2RSTR TIM17RST LL_APB2_GRP1_ForceReset\n 01790 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n 01791 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n 01792 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n 01793 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n 01794 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset 01795 * @param Periphs This parameter can be a combination of the following values: 01796 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01797 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01798 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01799 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01800 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01801 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01802 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01803 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01804 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01805 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01806 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01807 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01808 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01809 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01810 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01811 * 01812 * (*) value not defined in all devices. 01813 * @retval None 01814 */ 01815 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs) 01816 { 01817 SET_BIT(RCC->APB2RSTR, Periphs); 01818 } 01819 01820 /** 01821 * @brief Release APB2 peripherals reset. 01822 * @rmtoll APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n 01823 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n 01824 * APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n 01825 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n 01826 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n 01827 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n 01828 * APB2RSTR TIM15RST LL_APB2_GRP1_ReleaseReset\n 01829 * APB2RSTR TIM16RST LL_APB2_GRP1_ReleaseReset\n 01830 * APB2RSTR TIM17RST LL_APB2_GRP1_ReleaseReset\n 01831 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n 01832 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n 01833 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n 01834 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n 01835 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset 01836 * @param Periphs This parameter can be a combination of the following values: 01837 * @arg @ref LL_APB2_GRP1_PERIPH_ALL 01838 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01839 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01840 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01841 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01842 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01843 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01844 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01845 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01846 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01847 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01848 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01849 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01850 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01851 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01852 * 01853 * (*) value not defined in all devices. 01854 * @retval None 01855 */ 01856 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs) 01857 { 01858 CLEAR_BIT(RCC->APB2RSTR, Periphs); 01859 } 01860 01861 /** 01862 * @brief Enable APB2 peripheral clocks in Sleep and Stop modes 01863 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_EnableClockStopSleep\n 01864 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01865 * APB2SMENR TIM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01866 * APB2SMENR SPI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01867 * APB2SMENR TIM8SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01868 * APB2SMENR USART1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01869 * APB2SMENR TIM15SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01870 * APB2SMENR TIM16SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01871 * APB2SMENR TIM17SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01872 * APB2SMENR SAI1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01873 * APB2SMENR SAI2SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01874 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_EnableClockStopSleep\n 01875 * APB2SMENR LTDCSMEN LL_APB2_GRP1_EnableClockStopSleep\n 01876 * APB2SMENR DSISMEN LL_APB2_GRP1_EnableClockStopSleep 01877 * @param Periphs This parameter can be a combination of the following values: 01878 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01879 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01880 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01881 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01882 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01883 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01884 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01885 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01886 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01887 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01888 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01889 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01890 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01891 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01892 * 01893 * (*) value not defined in all devices. 01894 * @retval None 01895 */ 01896 __STATIC_INLINE void LL_APB2_GRP1_EnableClockStopSleep(uint32_t Periphs) 01897 { 01898 __IO uint32_t tmpreg; 01899 SET_BIT(RCC->APB2SMENR, Periphs); 01900 /* Delay after an RCC peripheral clock enabling */ 01901 tmpreg = READ_BIT(RCC->APB2SMENR, Periphs); 01902 (void)tmpreg; 01903 } 01904 01905 /** 01906 * @brief Disable APB2 peripheral clocks in Sleep and Stop modes 01907 * @rmtoll APB2SMENR SYSCFGSMEN LL_APB2_GRP1_DisableClockStopSleep\n 01908 * APB2SMENR SDMMC1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01909 * APB2SMENR TIM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01910 * APB2SMENR SPI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01911 * APB2SMENR TIM8SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01912 * APB2SMENR USART1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01913 * APB2SMENR TIM15SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01914 * APB2SMENR TIM16SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01915 * APB2SMENR TIM17SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01916 * APB2SMENR SAI1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01917 * APB2SMENR SAI2SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01918 * APB2SMENR DFSDM1SMEN LL_APB2_GRP1_DisableClockStopSleep\n 01919 * APB2SMENR LTDCSMEN LL_APB2_GRP1_DisableClockStopSleep\n 01920 * APB2SMENR DSISMEN LL_APB2_GRP1_DisableClockStopSleep 01921 * @param Periphs This parameter can be a combination of the following values: 01922 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG 01923 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*) 01924 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1 01925 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1 01926 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8 (*) 01927 * @arg @ref LL_APB2_GRP1_PERIPH_USART1 01928 * @arg @ref LL_APB2_GRP1_PERIPH_TIM15 01929 * @arg @ref LL_APB2_GRP1_PERIPH_TIM16 01930 * @arg @ref LL_APB2_GRP1_PERIPH_TIM17 (*) 01931 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1 01932 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2 (*) 01933 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*) 01934 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*) 01935 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*) 01936 * 01937 * (*) value not defined in all devices. 01938 * @retval None 01939 */ 01940 __STATIC_INLINE void LL_APB2_GRP1_DisableClockStopSleep(uint32_t Periphs) 01941 { 01942 CLEAR_BIT(RCC->APB2SMENR, Periphs); 01943 } 01944 01945 /** 01946 * @} 01947 */ 01948 01949 01950 /** 01951 * @} 01952 */ 01953 01954 /** 01955 * @} 01956 */ 01957 01958 #endif /* defined(RCC) */ 01959 01960 /** 01961 * @} 01962 */ 01963 01964 #ifdef __cplusplus 01965 } 01966 #endif 01967 01968 #endif /* __STM32L4xx_LL_BUS_H */ 01969 01970 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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