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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_smbus.h 00004 * @author MCD Application Team 00005 * @brief Header file of SMBUS HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef STM32L4xx_HAL_SMBUS_H 00038 #define STM32L4xx_HAL_SMBUS_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /** @addtogroup STM32L4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup SMBUS 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types 00057 * @{ 00058 */ 00059 00060 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition 00061 * @brief SMBUS Configuration Structure definition 00062 * @{ 00063 */ 00064 typedef struct 00065 { 00066 uint32_t Timing; /*!< Specifies the SMBUS_TIMINGR_register value. 00067 This parameter calculated by referring to SMBUS initialization 00068 section in Reference manual */ 00069 uint32_t AnalogFilter; /*!< Specifies if Analog Filter is enable or not. 00070 This parameter can be a value of @ref SMBUS_Analog_Filter */ 00071 00072 uint32_t OwnAddress1; /*!< Specifies the first device own address. 00073 This parameter can be a 7-bit or 10-bit address. */ 00074 00075 uint32_t AddressingMode; /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected. 00076 This parameter can be a value of @ref SMBUS_addressing_mode */ 00077 00078 uint32_t DualAddressMode; /*!< Specifies if dual addressing mode is selected. 00079 This parameter can be a value of @ref SMBUS_dual_addressing_mode */ 00080 00081 uint32_t OwnAddress2; /*!< Specifies the second device own address if dual addressing mode is selected 00082 This parameter can be a 7-bit address. */ 00083 00084 uint32_t OwnAddress2Masks; /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected 00085 This parameter can be a value of @ref SMBUS_own_address2_masks. */ 00086 00087 uint32_t GeneralCallMode; /*!< Specifies if general call mode is selected. 00088 This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */ 00089 00090 uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected. 00091 This parameter can be a value of @ref SMBUS_nostretch_mode */ 00092 00093 uint32_t PacketErrorCheckMode; /*!< Specifies if Packet Error Check mode is selected. 00094 This parameter can be a value of @ref SMBUS_packet_error_check_mode */ 00095 00096 uint32_t PeripheralMode; /*!< Specifies which mode of Periphal is selected. 00097 This parameter can be a value of @ref SMBUS_peripheral_mode */ 00098 00099 uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value. 00100 (Enable bits and different timeout values) 00101 This parameter calculated by referring to SMBUS initialization 00102 section in Reference manual */ 00103 } SMBUS_InitTypeDef; 00104 /** 00105 * @} 00106 */ 00107 00108 /** @defgroup HAL_state_definition HAL state definition 00109 * @brief HAL State definition 00110 * @{ 00111 */ 00112 #define HAL_SMBUS_STATE_RESET (0x00000000U) /*!< SMBUS not yet initialized or disabled */ 00113 #define HAL_SMBUS_STATE_READY (0x00000001U) /*!< SMBUS initialized and ready for use */ 00114 #define HAL_SMBUS_STATE_BUSY (0x00000002U) /*!< SMBUS internal process is ongoing */ 00115 #define HAL_SMBUS_STATE_MASTER_BUSY_TX (0x00000012U) /*!< Master Data Transmission process is ongoing */ 00116 #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ 00117 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ 00118 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ 00119 #define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ 00120 #define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ 00121 #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ 00122 /** 00123 * @} 00124 */ 00125 00126 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition 00127 * @brief SMBUS Error Code definition 00128 * @{ 00129 */ 00130 #define HAL_SMBUS_ERROR_NONE (0x00000000U) /*!< No error */ 00131 #define HAL_SMBUS_ERROR_BERR (0x00000001U) /*!< BERR error */ 00132 #define HAL_SMBUS_ERROR_ARLO (0x00000002U) /*!< ARLO error */ 00133 #define HAL_SMBUS_ERROR_ACKF (0x00000004U) /*!< ACKF error */ 00134 #define HAL_SMBUS_ERROR_OVR (0x00000008U) /*!< OVR error */ 00135 #define HAL_SMBUS_ERROR_HALTIMEOUT (0x00000010U) /*!< Timeout error */ 00136 #define HAL_SMBUS_ERROR_BUSTIMEOUT (0x00000020U) /*!< Bus Timeout error */ 00137 #define HAL_SMBUS_ERROR_ALERT (0x00000040U) /*!< Alert error */ 00138 #define HAL_SMBUS_ERROR_PECERR (0x00000080U) /*!< PEC error */ 00139 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00140 #define HAL_SMBUS_ERROR_INVALID_CALLBACK (0x00000100U) /*!< Invalid Callback error */ 00141 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 00142 /** 00143 * @} 00144 */ 00145 00146 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition 00147 * @brief SMBUS handle Structure definition 00148 * @{ 00149 */ 00150 typedef struct __SMBUS_HandleTypeDef 00151 { 00152 I2C_TypeDef *Instance; /*!< SMBUS registers base address */ 00153 00154 SMBUS_InitTypeDef Init; /*!< SMBUS communication parameters */ 00155 00156 uint8_t *pBuffPtr; /*!< Pointer to SMBUS transfer buffer */ 00157 00158 uint16_t XferSize; /*!< SMBUS transfer size */ 00159 00160 __IO uint16_t XferCount; /*!< SMBUS transfer counter */ 00161 00162 __IO uint32_t XferOptions; /*!< SMBUS transfer options */ 00163 00164 __IO uint32_t PreviousState; /*!< SMBUS communication Previous state */ 00165 00166 HAL_LockTypeDef Lock; /*!< SMBUS locking object */ 00167 00168 __IO uint32_t State; /*!< SMBUS communication state */ 00169 00170 __IO uint32_t ErrorCode; /*!< SMBUS Error code */ 00171 00172 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00173 void (* MasterTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Tx Transfer completed callback */ 00174 void (* MasterRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Master Rx Transfer completed callback */ 00175 void (* SlaveTxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Tx Transfer completed callback */ 00176 void (* SlaveRxCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Slave Rx Transfer completed callback */ 00177 void (* ListenCpltCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Listen Complete callback */ 00178 void (* ErrorCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Error callback */ 00179 00180 void (* AddrCallback)(struct __SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< SMBUS Slave Address Match callback */ 00181 00182 void (* MspInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp Init callback */ 00183 void (* MspDeInitCallback)(struct __SMBUS_HandleTypeDef *hsmbus); /*!< SMBUS Msp DeInit callback */ 00184 00185 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 00186 } SMBUS_HandleTypeDef; 00187 00188 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00189 /** 00190 * @brief HAL SMBUS Callback ID enumeration definition 00191 */ 00192 typedef enum 00193 { 00194 HAL_SMBUS_MASTER_TX_COMPLETE_CB_ID = 0x00U, /*!< SMBUS Master Tx Transfer completed callback ID */ 00195 HAL_SMBUS_MASTER_RX_COMPLETE_CB_ID = 0x01U, /*!< SMBUS Master Rx Transfer completed callback ID */ 00196 HAL_SMBUS_SLAVE_TX_COMPLETE_CB_ID = 0x02U, /*!< SMBUS Slave Tx Transfer completed callback ID */ 00197 HAL_SMBUS_SLAVE_RX_COMPLETE_CB_ID = 0x03U, /*!< SMBUS Slave Rx Transfer completed callback ID */ 00198 HAL_SMBUS_LISTEN_COMPLETE_CB_ID = 0x04U, /*!< SMBUS Listen Complete callback ID */ 00199 HAL_SMBUS_ERROR_CB_ID = 0x05U, /*!< SMBUS Error callback ID */ 00200 00201 HAL_SMBUS_MSPINIT_CB_ID = 0x06U, /*!< SMBUS Msp Init callback ID */ 00202 HAL_SMBUS_MSPDEINIT_CB_ID = 0x07U /*!< SMBUS Msp DeInit callback ID */ 00203 00204 } HAL_SMBUS_CallbackIDTypeDef; 00205 00206 /** 00207 * @brief HAL SMBUS Callback pointer definition 00208 */ 00209 typedef void (*pSMBUS_CallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus); /*!< pointer to an SMBUS callback function */ 00210 typedef void (*pSMBUS_AddrCallbackTypeDef)(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); /*!< pointer to an SMBUS Address Match callback function */ 00211 00212 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 00213 /** 00214 * @} 00215 */ 00216 00217 /** 00218 * @} 00219 */ 00220 /* Exported constants --------------------------------------------------------*/ 00221 00222 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants 00223 * @{ 00224 */ 00225 00226 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter 00227 * @{ 00228 */ 00229 #define SMBUS_ANALOGFILTER_ENABLE (0x00000000U) 00230 #define SMBUS_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF 00231 /** 00232 * @} 00233 */ 00234 00235 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode 00236 * @{ 00237 */ 00238 #define SMBUS_ADDRESSINGMODE_7BIT (0x00000001U) 00239 #define SMBUS_ADDRESSINGMODE_10BIT (0x00000002U) 00240 /** 00241 * @} 00242 */ 00243 00244 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode 00245 * @{ 00246 */ 00247 00248 #define SMBUS_DUALADDRESS_DISABLE (0x00000000U) 00249 #define SMBUS_DUALADDRESS_ENABLE I2C_OAR2_OA2EN 00250 /** 00251 * @} 00252 */ 00253 00254 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks 00255 * @{ 00256 */ 00257 00258 #define SMBUS_OA2_NOMASK ((uint8_t)0x00U) 00259 #define SMBUS_OA2_MASK01 ((uint8_t)0x01U) 00260 #define SMBUS_OA2_MASK02 ((uint8_t)0x02U) 00261 #define SMBUS_OA2_MASK03 ((uint8_t)0x03U) 00262 #define SMBUS_OA2_MASK04 ((uint8_t)0x04U) 00263 #define SMBUS_OA2_MASK05 ((uint8_t)0x05U) 00264 #define SMBUS_OA2_MASK06 ((uint8_t)0x06U) 00265 #define SMBUS_OA2_MASK07 ((uint8_t)0x07U) 00266 /** 00267 * @} 00268 */ 00269 00270 00271 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode 00272 * @{ 00273 */ 00274 #define SMBUS_GENERALCALL_DISABLE (0x00000000U) 00275 #define SMBUS_GENERALCALL_ENABLE I2C_CR1_GCEN 00276 /** 00277 * @} 00278 */ 00279 00280 /** @defgroup SMBUS_nostretch_mode SMBUS nostretch mode 00281 * @{ 00282 */ 00283 #define SMBUS_NOSTRETCH_DISABLE (0x00000000U) 00284 #define SMBUS_NOSTRETCH_ENABLE I2C_CR1_NOSTRETCH 00285 /** 00286 * @} 00287 */ 00288 00289 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode 00290 * @{ 00291 */ 00292 #define SMBUS_PEC_DISABLE (0x00000000U) 00293 #define SMBUS_PEC_ENABLE I2C_CR1_PECEN 00294 /** 00295 * @} 00296 */ 00297 00298 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode 00299 * @{ 00300 */ 00301 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST I2C_CR1_SMBHEN 00302 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE (0x00000000U) 00303 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP I2C_CR1_SMBDEN 00304 /** 00305 * @} 00306 */ 00307 00308 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition 00309 * @{ 00310 */ 00311 00312 #define SMBUS_SOFTEND_MODE (0x00000000U) 00313 #define SMBUS_RELOAD_MODE I2C_CR2_RELOAD 00314 #define SMBUS_AUTOEND_MODE I2C_CR2_AUTOEND 00315 #define SMBUS_SENDPEC_MODE I2C_CR2_PECBYTE 00316 /** 00317 * @} 00318 */ 00319 00320 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition 00321 * @{ 00322 */ 00323 00324 #define SMBUS_NO_STARTSTOP (0x00000000U) 00325 #define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) 00326 #define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) 00327 #define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) 00328 /** 00329 * @} 00330 */ 00331 00332 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition 00333 * @{ 00334 */ 00335 00336 /* List of XferOptions in usage of : 00337 * 1- Restart condition when direction change 00338 * 2- No Restart condition in other use cases 00339 */ 00340 #define SMBUS_FIRST_FRAME SMBUS_SOFTEND_MODE 00341 #define SMBUS_NEXT_FRAME ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE)) 00342 #define SMBUS_FIRST_AND_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 00343 #define SMBUS_LAST_FRAME_NO_PEC SMBUS_AUTOEND_MODE 00344 #define SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 00345 #define SMBUS_LAST_FRAME_WITH_PEC ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) 00346 00347 /* List of XferOptions in usage of : 00348 * 1- Restart condition in all use cases (direction change or not) 00349 */ 00350 #define SMBUS_OTHER_FRAME_NO_PEC (0x000000AAU) 00351 #define SMBUS_OTHER_FRAME_WITH_PEC (0x0000AA00U) 00352 #define SMBUS_OTHER_AND_LAST_FRAME_NO_PEC (0x00AA0000U) 00353 #define SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC (0xAA000000U) 00354 /** 00355 * @} 00356 */ 00357 00358 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition 00359 * @brief SMBUS Interrupt definition 00360 * Elements values convention: 0xXXXXXXXX 00361 * - XXXXXXXX : Interrupt control mask 00362 * @{ 00363 */ 00364 #define SMBUS_IT_ERRI I2C_CR1_ERRIE 00365 #define SMBUS_IT_TCI I2C_CR1_TCIE 00366 #define SMBUS_IT_STOPI I2C_CR1_STOPIE 00367 #define SMBUS_IT_NACKI I2C_CR1_NACKIE 00368 #define SMBUS_IT_ADDRI I2C_CR1_ADDRIE 00369 #define SMBUS_IT_RXI I2C_CR1_RXIE 00370 #define SMBUS_IT_TXI I2C_CR1_TXIE 00371 #define SMBUS_IT_TX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI) 00372 #define SMBUS_IT_RX (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI) 00373 #define SMBUS_IT_ALERT (SMBUS_IT_ERRI) 00374 #define SMBUS_IT_ADDR (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI) 00375 /** 00376 * @} 00377 */ 00378 00379 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition 00380 * @brief Flag definition 00381 * Elements values convention: 0xXXXXYYYY 00382 * - XXXXXXXX : Flag mask 00383 * @{ 00384 */ 00385 00386 #define SMBUS_FLAG_TXE I2C_ISR_TXE 00387 #define SMBUS_FLAG_TXIS I2C_ISR_TXIS 00388 #define SMBUS_FLAG_RXNE I2C_ISR_RXNE 00389 #define SMBUS_FLAG_ADDR I2C_ISR_ADDR 00390 #define SMBUS_FLAG_AF I2C_ISR_NACKF 00391 #define SMBUS_FLAG_STOPF I2C_ISR_STOPF 00392 #define SMBUS_FLAG_TC I2C_ISR_TC 00393 #define SMBUS_FLAG_TCR I2C_ISR_TCR 00394 #define SMBUS_FLAG_BERR I2C_ISR_BERR 00395 #define SMBUS_FLAG_ARLO I2C_ISR_ARLO 00396 #define SMBUS_FLAG_OVR I2C_ISR_OVR 00397 #define SMBUS_FLAG_PECERR I2C_ISR_PECERR 00398 #define SMBUS_FLAG_TIMEOUT I2C_ISR_TIMEOUT 00399 #define SMBUS_FLAG_ALERT I2C_ISR_ALERT 00400 #define SMBUS_FLAG_BUSY I2C_ISR_BUSY 00401 #define SMBUS_FLAG_DIR I2C_ISR_DIR 00402 /** 00403 * @} 00404 */ 00405 00406 /** 00407 * @} 00408 */ 00409 00410 /* Exported macros ------------------------------------------------------------*/ 00411 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros 00412 * @{ 00413 */ 00414 00415 /** @brief Reset SMBUS handle state. 00416 * @param __HANDLE__ specifies the SMBUS Handle. 00417 * @retval None 00418 */ 00419 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00420 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00421 (__HANDLE__)->State = HAL_SMBUS_STATE_RESET; \ 00422 (__HANDLE__)->MspInitCallback = NULL; \ 00423 (__HANDLE__)->MspDeInitCallback = NULL; \ 00424 } while(0) 00425 #else 00426 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET) 00427 #endif 00428 00429 /** @brief Enable the specified SMBUS interrupts. 00430 * @param __HANDLE__ specifies the SMBUS Handle. 00431 * @param __INTERRUPT__ specifies the interrupt source to enable. 00432 * This parameter can be one of the following values: 00433 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 00434 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 00435 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 00436 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 00437 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 00438 * @arg @ref SMBUS_IT_RXI RX interrupt enable 00439 * @arg @ref SMBUS_IT_TXI TX interrupt enable 00440 * 00441 * @retval None 00442 */ 00443 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__)) 00444 00445 /** @brief Disable the specified SMBUS interrupts. 00446 * @param __HANDLE__ specifies the SMBUS Handle. 00447 * @param __INTERRUPT__ specifies the interrupt source to disable. 00448 * This parameter can be one of the following values: 00449 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 00450 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 00451 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 00452 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 00453 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 00454 * @arg @ref SMBUS_IT_RXI RX interrupt enable 00455 * @arg @ref SMBUS_IT_TXI TX interrupt enable 00456 * 00457 * @retval None 00458 */ 00459 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__))) 00460 00461 /** @brief Check whether the specified SMBUS interrupt source is enabled or not. 00462 * @param __HANDLE__ specifies the SMBUS Handle. 00463 * @param __INTERRUPT__ specifies the SMBUS interrupt source to check. 00464 * This parameter can be one of the following values: 00465 * @arg @ref SMBUS_IT_ERRI Errors interrupt enable 00466 * @arg @ref SMBUS_IT_TCI Transfer complete interrupt enable 00467 * @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable 00468 * @arg @ref SMBUS_IT_NACKI NACK received interrupt enable 00469 * @arg @ref SMBUS_IT_ADDRI Address match interrupt enable 00470 * @arg @ref SMBUS_IT_RXI RX interrupt enable 00471 * @arg @ref SMBUS_IT_TXI TX interrupt enable 00472 * 00473 * @retval The new state of __IT__ (TRUE or FALSE). 00474 */ 00475 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00476 00477 /** @brief Check whether the specified SMBUS flag is set or not. 00478 * @param __HANDLE__ specifies the SMBUS Handle. 00479 * @param __FLAG__ specifies the flag to check. 00480 * This parameter can be one of the following values: 00481 * @arg @ref SMBUS_FLAG_TXE Transmit data register empty 00482 * @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status 00483 * @arg @ref SMBUS_FLAG_RXNE Receive data register not empty 00484 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 00485 * @arg @ref SMBUS_FLAG_AF NACK received flag 00486 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 00487 * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode) 00488 * @arg @ref SMBUS_FLAG_TCR Transfer complete reload 00489 * @arg @ref SMBUS_FLAG_BERR Bus error 00490 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 00491 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 00492 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 00493 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 00494 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 00495 * @arg @ref SMBUS_FLAG_BUSY Bus busy 00496 * @arg @ref SMBUS_FLAG_DIR Transfer direction (slave mode) 00497 * 00498 * @retval The new state of __FLAG__ (TRUE or FALSE). 00499 */ 00500 #define SMBUS_FLAG_MASK (0x0001FFFFU) 00501 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) 00502 00503 /** @brief Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit. 00504 * @param __HANDLE__ specifies the SMBUS Handle. 00505 * @param __FLAG__ specifies the flag to clear. 00506 * This parameter can be any combination of the following values: 00507 * @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode) 00508 * @arg @ref SMBUS_FLAG_AF NACK received flag 00509 * @arg @ref SMBUS_FLAG_STOPF STOP detection flag 00510 * @arg @ref SMBUS_FLAG_BERR Bus error 00511 * @arg @ref SMBUS_FLAG_ARLO Arbitration lost 00512 * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun 00513 * @arg @ref SMBUS_FLAG_PECERR PEC error in reception 00514 * @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag 00515 * @arg @ref SMBUS_FLAG_ALERT SMBus alert 00516 * 00517 * @retval None 00518 */ 00519 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__)) 00520 00521 /** @brief Enable the specified SMBUS peripheral. 00522 * @param __HANDLE__ specifies the SMBUS Handle. 00523 * @retval None 00524 */ 00525 #define __HAL_SMBUS_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 00526 00527 /** @brief Disable the specified SMBUS peripheral. 00528 * @param __HANDLE__ specifies the SMBUS Handle. 00529 * @retval None 00530 */ 00531 #define __HAL_SMBUS_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)) 00532 00533 /** @brief Generate a Non-Acknowledge SMBUS peripheral in Slave mode. 00534 * @param __HANDLE__ specifies the SMBUS Handle. 00535 * @retval None 00536 */ 00537 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK)) 00538 00539 /** 00540 * @} 00541 */ 00542 00543 00544 /* Private constants ---------------------------------------------------------*/ 00545 00546 /* Private macros ------------------------------------------------------------*/ 00547 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros 00548 * @{ 00549 */ 00550 00551 #define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \ 00552 ((FILTER) == SMBUS_ANALOGFILTER_DISABLE)) 00553 00554 #define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU) 00555 00556 #define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \ 00557 ((MODE) == SMBUS_ADDRESSINGMODE_10BIT)) 00558 00559 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \ 00560 ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE)) 00561 00562 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK) (((MASK) == SMBUS_OA2_NOMASK) || \ 00563 ((MASK) == SMBUS_OA2_MASK01) || \ 00564 ((MASK) == SMBUS_OA2_MASK02) || \ 00565 ((MASK) == SMBUS_OA2_MASK03) || \ 00566 ((MASK) == SMBUS_OA2_MASK04) || \ 00567 ((MASK) == SMBUS_OA2_MASK05) || \ 00568 ((MASK) == SMBUS_OA2_MASK06) || \ 00569 ((MASK) == SMBUS_OA2_MASK07)) 00570 00571 #define IS_SMBUS_GENERAL_CALL(CALL) (((CALL) == SMBUS_GENERALCALL_DISABLE) || \ 00572 ((CALL) == SMBUS_GENERALCALL_ENABLE)) 00573 00574 #define IS_SMBUS_NO_STRETCH(STRETCH) (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \ 00575 ((STRETCH) == SMBUS_NOSTRETCH_ENABLE)) 00576 00577 #define IS_SMBUS_PEC(PEC) (((PEC) == SMBUS_PEC_DISABLE) || \ 00578 ((PEC) == SMBUS_PEC_ENABLE)) 00579 00580 #define IS_SMBUS_PERIPHERAL_MODE(MODE) (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST) || \ 00581 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || \ 00582 ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)) 00583 00584 #define IS_SMBUS_TRANSFER_MODE(MODE) (((MODE) == SMBUS_RELOAD_MODE) || \ 00585 ((MODE) == SMBUS_AUTOEND_MODE) || \ 00586 ((MODE) == SMBUS_SOFTEND_MODE) || \ 00587 ((MODE) == SMBUS_SENDPEC_MODE) || \ 00588 ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE)) || \ 00589 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE)) || \ 00590 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE)) || \ 00591 ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE ))) 00592 00593 00594 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST) (((REQUEST) == SMBUS_GENERATE_STOP) || \ 00595 ((REQUEST) == SMBUS_GENERATE_START_READ) || \ 00596 ((REQUEST) == SMBUS_GENERATE_START_WRITE) || \ 00597 ((REQUEST) == SMBUS_NO_STARTSTOP)) 00598 00599 00600 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_FIRST_FRAME) || \ 00601 ((REQUEST) == SMBUS_NEXT_FRAME) || \ 00602 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC) || \ 00603 ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC) || \ 00604 ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC) || \ 00605 ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC) || \ 00606 IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST)) 00607 00608 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC) || \ 00609 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC) || \ 00610 ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC) || \ 00611 ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)) 00612 00613 #define SMBUS_RESET_CR1(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN))) 00614 #define SMBUS_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN))) 00615 00616 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \ 00617 (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN))) 00618 00619 #define SMBUS_GET_ADDR_MATCH(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U) 00620 #define SMBUS_GET_DIR(__HANDLE__) (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U) 00621 #define SMBUS_GET_STOP_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND) 00622 #define SMBUS_GET_PEC_MODE(__HANDLE__) ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE) 00623 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__) ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN) 00624 00625 #define SMBUS_GET_ISR_REG(__HANDLE__) ((__HANDLE__)->Instance->ISR) 00626 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK))) 00627 00628 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU) 00629 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FFU) 00630 00631 /** 00632 * @} 00633 */ 00634 00635 /* Exported functions --------------------------------------------------------*/ 00636 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions 00637 * @{ 00638 */ 00639 00640 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions 00641 * @{ 00642 */ 00643 00644 /* Initialization and de-initialization functions ****************************/ 00645 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus); 00646 HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus); 00647 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus); 00648 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus); 00649 HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter); 00650 HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter); 00651 00652 /* Callbacks Register/UnRegister functions ***********************************/ 00653 #if (USE_HAL_SMBUS_REGISTER_CALLBACKS == 1) 00654 HAL_StatusTypeDef HAL_SMBUS_RegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID, pSMBUS_CallbackTypeDef pCallback); 00655 HAL_StatusTypeDef HAL_SMBUS_UnRegisterCallback(SMBUS_HandleTypeDef *hsmbus, HAL_SMBUS_CallbackIDTypeDef CallbackID); 00656 00657 HAL_StatusTypeDef HAL_SMBUS_RegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus, pSMBUS_AddrCallbackTypeDef pCallback); 00658 HAL_StatusTypeDef HAL_SMBUS_UnRegisterAddrCallback(SMBUS_HandleTypeDef *hsmbus); 00659 #endif /* USE_HAL_SMBUS_REGISTER_CALLBACKS */ 00660 /** 00661 * @} 00662 */ 00663 00664 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions 00665 * @{ 00666 */ 00667 00668 /* IO operation functions *****************************************************/ 00669 /** @addtogroup Blocking_mode_Polling Blocking mode Polling 00670 * @{ 00671 */ 00672 /******* Blocking mode: Polling */ 00673 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout); 00674 /** 00675 * @} 00676 */ 00677 00678 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt 00679 * @{ 00680 */ 00681 /******* Non-Blocking mode: Interrupt */ 00682 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00683 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00684 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress); 00685 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00686 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions); 00687 00688 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 00689 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus); 00690 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus); 00691 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus); 00692 /** 00693 * @} 00694 */ 00695 00696 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks 00697 * @{ 00698 */ 00699 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */ 00700 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 00701 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus); 00702 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00703 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00704 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00705 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00706 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode); 00707 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus); 00708 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus); 00709 00710 /** 00711 * @} 00712 */ 00713 00714 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions 00715 * @{ 00716 */ 00717 00718 /* Peripheral State and Errors functions **************************************************/ 00719 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus); 00720 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus); 00721 00722 /** 00723 * @} 00724 */ 00725 00726 /** 00727 * @} 00728 */ 00729 00730 /* Private Functions ---------------------------------------------------------*/ 00731 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions 00732 * @{ 00733 */ 00734 /* Private functions are defined in stm32l4xx_hal_smbus.c file */ 00735 /** 00736 * @} 00737 */ 00738 00739 /** 00740 * @} 00741 */ 00742 00743 /** 00744 * @} 00745 */ 00746 00747 /** 00748 * @} 00749 */ 00750 00751 #ifdef __cplusplus 00752 } 00753 #endif 00754 00755 00756 #endif /* STM32L4xx_HAL_SMBUS_H */ 00757 00758 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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