STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_qspi.h 00004 * @author MCD Application Team 00005 * @brief Header file of QSPI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef STM32L4xx_HAL_QSPI_H 00038 #define STM32L4xx_HAL_QSPI_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 #if defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup QSPI 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup QSPI_Exported_Types QSPI Exported Types 00059 * @{ 00060 */ 00061 00062 /** 00063 * @brief QSPI Init structure definition 00064 */ 00065 typedef struct 00066 { 00067 uint32_t ClockPrescaler; /* Specifies the prescaler factor for generating clock based on the AHB clock. 00068 This parameter can be a number between 0 and 255 */ 00069 uint32_t FifoThreshold; /* Specifies the threshold number of bytes in the FIFO (used only in indirect mode) 00070 This parameter can be a value between 1 and 16 */ 00071 uint32_t SampleShifting; /* Specifies the Sample Shift. The data is sampled 1/2 clock cycle delay later to 00072 take in account external signal delays. (It should be QSPI_SAMPLE_SHIFTING_NONE in DDR mode) 00073 This parameter can be a value of @ref QSPI_SampleShifting */ 00074 uint32_t FlashSize; /* Specifies the Flash Size. FlashSize+1 is effectively the number of address bits 00075 required to address the flash memory. The flash capacity can be up to 4GB 00076 (addressed using 32 bits) in indirect mode, but the addressable space in 00077 memory-mapped mode is limited to 256MB 00078 This parameter can be a number between 0 and 31 */ 00079 uint32_t ChipSelectHighTime; /* Specifies the Chip Select High Time. ChipSelectHighTime+1 defines the minimum number 00080 of clock cycles which the chip select must remain high between commands. 00081 This parameter can be a value of @ref QSPI_ChipSelectHighTime */ 00082 uint32_t ClockMode; /* Specifies the Clock Mode. It indicates the level that clock takes between commands. 00083 This parameter can be a value of @ref QSPI_ClockMode */ 00084 #if defined(QUADSPI_CR_DFM) 00085 uint32_t FlashID; /* Specifies the Flash which will be used, 00086 This parameter can be a value of @ref QSPI_Flash_Select */ 00087 uint32_t DualFlash; /* Specifies the Dual Flash Mode State 00088 This parameter can be a value of @ref QSPI_DualFlash_Mode */ 00089 #endif 00090 }QSPI_InitTypeDef; 00091 00092 /** 00093 * @brief HAL QSPI State structures definition 00094 */ 00095 typedef enum 00096 { 00097 HAL_QSPI_STATE_RESET = 0x00U, /*!< Peripheral not initialized */ 00098 HAL_QSPI_STATE_READY = 0x01U, /*!< Peripheral initialized and ready for use */ 00099 HAL_QSPI_STATE_BUSY = 0x02U, /*!< Peripheral in indirect mode and busy */ 00100 HAL_QSPI_STATE_BUSY_INDIRECT_TX = 0x12U, /*!< Peripheral in indirect mode with transmission ongoing */ 00101 HAL_QSPI_STATE_BUSY_INDIRECT_RX = 0x22U, /*!< Peripheral in indirect mode with reception ongoing */ 00102 HAL_QSPI_STATE_BUSY_AUTO_POLLING = 0x42U, /*!< Peripheral in auto polling mode ongoing */ 00103 HAL_QSPI_STATE_BUSY_MEM_MAPPED = 0x82U, /*!< Peripheral in memory mapped mode ongoing */ 00104 HAL_QSPI_STATE_ABORT = 0x08U, /*!< Peripheral with abort request ongoing */ 00105 HAL_QSPI_STATE_ERROR = 0x04U /*!< Peripheral in error */ 00106 }HAL_QSPI_StateTypeDef; 00107 00108 /** 00109 * @brief QSPI Handle Structure definition 00110 */ 00111 typedef struct __QSPI_HandleTypeDef 00112 { 00113 QUADSPI_TypeDef *Instance; /* QSPI registers base address */ 00114 QSPI_InitTypeDef Init; /* QSPI communication parameters */ 00115 uint8_t *pTxBuffPtr; /* Pointer to QSPI Tx transfer Buffer */ 00116 __IO uint32_t TxXferSize; /* QSPI Tx Transfer size */ 00117 __IO uint32_t TxXferCount; /* QSPI Tx Transfer Counter */ 00118 uint8_t *pRxBuffPtr; /* Pointer to QSPI Rx transfer Buffer */ 00119 __IO uint32_t RxXferSize; /* QSPI Rx Transfer size */ 00120 __IO uint32_t RxXferCount; /* QSPI Rx Transfer Counter */ 00121 DMA_HandleTypeDef *hdma; /* QSPI Rx/Tx DMA Handle parameters */ 00122 __IO HAL_LockTypeDef Lock; /* Locking object */ 00123 __IO HAL_QSPI_StateTypeDef State; /* QSPI communication state */ 00124 __IO uint32_t ErrorCode; /* QSPI Error code */ 00125 uint32_t Timeout; /* Timeout for the QSPI memory access */ 00126 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00127 void (* ErrorCallback) (struct __QSPI_HandleTypeDef *hqspi); 00128 void (* AbortCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00129 void (* FifoThresholdCallback)(struct __QSPI_HandleTypeDef *hqspi); 00130 void (* CmdCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00131 void (* RxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00132 void (* TxCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00133 void (* RxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00134 void (* TxHalfCpltCallback) (struct __QSPI_HandleTypeDef *hqspi); 00135 void (* StatusMatchCallback) (struct __QSPI_HandleTypeDef *hqspi); 00136 void (* TimeOutCallback) (struct __QSPI_HandleTypeDef *hqspi); 00137 00138 void (* MspInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 00139 void (* MspDeInitCallback) (struct __QSPI_HandleTypeDef *hqspi); 00140 #endif 00141 }QSPI_HandleTypeDef; 00142 00143 /** 00144 * @brief QSPI Command structure definition 00145 */ 00146 typedef struct 00147 { 00148 uint32_t Instruction; /* Specifies the Instruction to be sent 00149 This parameter can be a value (8-bit) between 0x00 and 0xFF */ 00150 uint32_t Address; /* Specifies the Address to be sent (Size from 1 to 4 bytes according AddressSize) 00151 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 00152 uint32_t AlternateBytes; /* Specifies the Alternate Bytes to be sent (Size from 1 to 4 bytes according AlternateBytesSize) 00153 This parameter can be a value (32-bits) between 0x0 and 0xFFFFFFFF */ 00154 uint32_t AddressSize; /* Specifies the Address Size 00155 This parameter can be a value of @ref QSPI_AddressSize */ 00156 uint32_t AlternateBytesSize; /* Specifies the Alternate Bytes Size 00157 This parameter can be a value of @ref QSPI_AlternateBytesSize */ 00158 uint32_t DummyCycles; /* Specifies the Number of Dummy Cycles. 00159 This parameter can be a number between 0 and 31 */ 00160 uint32_t InstructionMode; /* Specifies the Instruction Mode 00161 This parameter can be a value of @ref QSPI_InstructionMode */ 00162 uint32_t AddressMode; /* Specifies the Address Mode 00163 This parameter can be a value of @ref QSPI_AddressMode */ 00164 uint32_t AlternateByteMode; /* Specifies the Alternate Bytes Mode 00165 This parameter can be a value of @ref QSPI_AlternateBytesMode */ 00166 uint32_t DataMode; /* Specifies the Data Mode (used for dummy cycles and data phases) 00167 This parameter can be a value of @ref QSPI_DataMode */ 00168 uint32_t NbData; /* Specifies the number of data to transfer. (This is the number of bytes) 00169 This parameter can be any value between 0 and 0xFFFFFFFF (0 means undefined length 00170 until end of memory)*/ 00171 uint32_t DdrMode; /* Specifies the double data rate mode for address, alternate byte and data phase 00172 This parameter can be a value of @ref QSPI_DdrMode */ 00173 uint32_t DdrHoldHalfCycle; /* Specifies if the DDR hold is enabled. When enabled it delays the data 00174 output by one half of system clock in DDR mode. 00175 Not available on all devices. 00176 This parameter can be a value of @ref QSPI_DdrHoldHalfCycle */ 00177 uint32_t SIOOMode; /* Specifies the send instruction only once mode 00178 This parameter can be a value of @ref QSPI_SIOOMode */ 00179 }QSPI_CommandTypeDef; 00180 00181 /** 00182 * @brief QSPI Auto Polling mode configuration structure definition 00183 */ 00184 typedef struct 00185 { 00186 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 00187 This parameter can be any value between 0 and 0xFFFFFFFF */ 00188 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 00189 This parameter can be any value between 0 and 0xFFFFFFFF */ 00190 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 00191 This parameter can be any value between 0 and 0xFFFF */ 00192 uint32_t StatusBytesSize; /* Specifies the size of the status bytes received. 00193 This parameter can be any value between 1 and 4 */ 00194 uint32_t MatchMode; /* Specifies the method used for determining a match. 00195 This parameter can be a value of @ref QSPI_MatchMode */ 00196 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 00197 This parameter can be a value of @ref QSPI_AutomaticStop */ 00198 }QSPI_AutoPollingTypeDef; 00199 00200 /** 00201 * @brief QSPI Memory Mapped mode configuration structure definition 00202 */ 00203 typedef struct 00204 { 00205 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 00206 This parameter can be any value between 0 and 0xFFFF */ 00207 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 00208 This parameter can be a value of @ref QSPI_TimeOutActivation */ 00209 }QSPI_MemoryMappedTypeDef; 00210 00211 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00212 /** 00213 * @brief HAL QSPI Callback ID enumeration definition 00214 */ 00215 typedef enum 00216 { 00217 HAL_QSPI_ERROR_CB_ID = 0x00U, /*!< QSPI Error Callback ID */ 00218 HAL_QSPI_ABORT_CB_ID = 0x01U, /*!< QSPI Abort Callback ID */ 00219 HAL_QSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< QSPI FIFO Threshold Callback ID */ 00220 HAL_QSPI_CMD_CPLT_CB_ID = 0x03U, /*!< QSPI Command Complete Callback ID */ 00221 HAL_QSPI_RX_CPLT_CB_ID = 0x04U, /*!< QSPI Rx Complete Callback ID */ 00222 HAL_QSPI_TX_CPLT_CB_ID = 0x05U, /*!< QSPI Tx Complete Callback ID */ 00223 HAL_QSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< QSPI Rx Half Complete Callback ID */ 00224 HAL_QSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< QSPI Tx Half Complete Callback ID */ 00225 HAL_QSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< QSPI Status Match Callback ID */ 00226 HAL_QSPI_TIMEOUT_CB_ID = 0x09U, /*!< QSPI Timeout Callback ID */ 00227 00228 HAL_QSPI_MSP_INIT_CB_ID = 0x0AU, /*!< QSPI MspInit Callback ID */ 00229 HAL_QSPI_MSP_DEINIT_CB_ID = 0x0B0 /*!< QSPI MspDeInit Callback ID */ 00230 }HAL_QSPI_CallbackIDTypeDef; 00231 00232 /** 00233 * @brief HAL QSPI Callback pointer definition 00234 */ 00235 typedef void (*pQSPI_CallbackTypeDef)(QSPI_HandleTypeDef *hqspi); 00236 #endif 00237 /** 00238 * @} 00239 */ 00240 00241 /* Exported constants --------------------------------------------------------*/ 00242 /** @defgroup QSPI_Exported_Constants QSPI Exported Constants 00243 * @{ 00244 */ 00245 00246 /** @defgroup QSPI_ErrorCode QSPI Error Code 00247 * @{ 00248 */ 00249 #define HAL_QSPI_ERROR_NONE 0x00000000U /*!< No error */ 00250 #define HAL_QSPI_ERROR_TIMEOUT 0x00000001U /*!< Timeout error */ 00251 #define HAL_QSPI_ERROR_TRANSFER 0x00000002U /*!< Transfer error */ 00252 #define HAL_QSPI_ERROR_DMA 0x00000004U /*!< DMA transfer error */ 00253 #define HAL_QSPI_ERROR_INVALID_PARAM 0x00000008U /*!< Invalid parameters error */ 00254 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00255 #define HAL_QSPI_ERROR_INVALID_CALLBACK 0x00000010U /*!< Invalid callback error */ 00256 #endif 00257 /** 00258 * @} 00259 */ 00260 00261 /** @defgroup QSPI_SampleShifting QSPI Sample Shifting 00262 * @{ 00263 */ 00264 #define QSPI_SAMPLE_SHIFTING_NONE 0x00000000U /*!<No clock cycle shift to sample data*/ 00265 #define QSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)QUADSPI_CR_SSHIFT) /*!<1/2 clock cycle shift to sample data*/ 00266 /** 00267 * @} 00268 */ 00269 00270 /** @defgroup QSPI_ChipSelectHighTime QSPI ChipSelect High Time 00271 * @{ 00272 */ 00273 #define QSPI_CS_HIGH_TIME_1_CYCLE 0x00000000U /*!<nCS stay high for at least 1 clock cycle between commands*/ 00274 #define QSPI_CS_HIGH_TIME_2_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 2 clock cycles between commands*/ 00275 #define QSPI_CS_HIGH_TIME_3_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 3 clock cycles between commands*/ 00276 #define QSPI_CS_HIGH_TIME_4_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_0 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 4 clock cycles between commands*/ 00277 #define QSPI_CS_HIGH_TIME_5_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2) /*!<nCS stay high for at least 5 clock cycles between commands*/ 00278 #define QSPI_CS_HIGH_TIME_6_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_0) /*!<nCS stay high for at least 6 clock cycles between commands*/ 00279 #define QSPI_CS_HIGH_TIME_7_CYCLE ((uint32_t)QUADSPI_DCR_CSHT_2 | QUADSPI_DCR_CSHT_1) /*!<nCS stay high for at least 7 clock cycles between commands*/ 00280 #define QSPI_CS_HIGH_TIME_8_CYCLE ((uint32_t)QUADSPI_DCR_CSHT) /*!<nCS stay high for at least 8 clock cycles between commands*/ 00281 /** 00282 * @} 00283 */ 00284 00285 /** @defgroup QSPI_ClockMode QSPI Clock Mode 00286 * @{ 00287 */ 00288 #define QSPI_CLOCK_MODE_0 0x00000000U /*!<Clk stays low while nCS is released*/ 00289 #define QSPI_CLOCK_MODE_3 ((uint32_t)QUADSPI_DCR_CKMODE) /*!<Clk goes high while nCS is released*/ 00290 /** 00291 * @} 00292 */ 00293 00294 #if defined(QUADSPI_CR_DFM) 00295 /** @defgroup QSPI_Flash_Select QSPI Flash Select 00296 * @{ 00297 */ 00298 #define QSPI_FLASH_ID_1 0x00000000U /*!<FLASH 1 selected*/ 00299 #define QSPI_FLASH_ID_2 ((uint32_t)QUADSPI_CR_FSEL) /*!<FLASH 2 selected*/ 00300 /** 00301 * @} 00302 */ 00303 00304 /** @defgroup QSPI_DualFlash_Mode QSPI Dual Flash Mode 00305 * @{ 00306 */ 00307 #define QSPI_DUALFLASH_ENABLE ((uint32_t)QUADSPI_CR_DFM) /*!<Dual-flash mode enabled*/ 00308 #define QSPI_DUALFLASH_DISABLE 0x00000000U /*!<Dual-flash mode disabled*/ 00309 /** 00310 * @} 00311 */ 00312 00313 #endif 00314 /** @defgroup QSPI_AddressSize QSPI Address Size 00315 * @{ 00316 */ 00317 #define QSPI_ADDRESS_8_BITS 0x00000000U /*!<8-bit address*/ 00318 #define QSPI_ADDRESS_16_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_0) /*!<16-bit address*/ 00319 #define QSPI_ADDRESS_24_BITS ((uint32_t)QUADSPI_CCR_ADSIZE_1) /*!<24-bit address*/ 00320 #define QSPI_ADDRESS_32_BITS ((uint32_t)QUADSPI_CCR_ADSIZE) /*!<32-bit address*/ 00321 /** 00322 * @} 00323 */ 00324 00325 /** @defgroup QSPI_AlternateBytesSize QSPI Alternate Bytes Size 00326 * @{ 00327 */ 00328 #define QSPI_ALTERNATE_BYTES_8_BITS 0x00000000U /*!<8-bit alternate bytes*/ 00329 #define QSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_0) /*!<16-bit alternate bytes*/ 00330 #define QSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)QUADSPI_CCR_ABSIZE_1) /*!<24-bit alternate bytes*/ 00331 #define QSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)QUADSPI_CCR_ABSIZE) /*!<32-bit alternate bytes*/ 00332 /** 00333 * @} 00334 */ 00335 00336 /** @defgroup QSPI_InstructionMode QSPI Instruction Mode 00337 * @{ 00338 */ 00339 #define QSPI_INSTRUCTION_NONE 0x00000000U /*!<No instruction*/ 00340 #define QSPI_INSTRUCTION_1_LINE ((uint32_t)QUADSPI_CCR_IMODE_0) /*!<Instruction on a single line*/ 00341 #define QSPI_INSTRUCTION_2_LINES ((uint32_t)QUADSPI_CCR_IMODE_1) /*!<Instruction on two lines*/ 00342 #define QSPI_INSTRUCTION_4_LINES ((uint32_t)QUADSPI_CCR_IMODE) /*!<Instruction on four lines*/ 00343 /** 00344 * @} 00345 */ 00346 00347 /** @defgroup QSPI_AddressMode QSPI Address Mode 00348 * @{ 00349 */ 00350 #define QSPI_ADDRESS_NONE 0x00000000U /*!<No address*/ 00351 #define QSPI_ADDRESS_1_LINE ((uint32_t)QUADSPI_CCR_ADMODE_0) /*!<Address on a single line*/ 00352 #define QSPI_ADDRESS_2_LINES ((uint32_t)QUADSPI_CCR_ADMODE_1) /*!<Address on two lines*/ 00353 #define QSPI_ADDRESS_4_LINES ((uint32_t)QUADSPI_CCR_ADMODE) /*!<Address on four lines*/ 00354 /** 00355 * @} 00356 */ 00357 00358 /** @defgroup QSPI_AlternateBytesMode QSPI Alternate Bytes Mode 00359 * @{ 00360 */ 00361 #define QSPI_ALTERNATE_BYTES_NONE 0x00000000U /*!<No alternate bytes*/ 00362 #define QSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)QUADSPI_CCR_ABMODE_0) /*!<Alternate bytes on a single line*/ 00363 #define QSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)QUADSPI_CCR_ABMODE_1) /*!<Alternate bytes on two lines*/ 00364 #define QSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)QUADSPI_CCR_ABMODE) /*!<Alternate bytes on four lines*/ 00365 /** 00366 * @} 00367 */ 00368 00369 /** @defgroup QSPI_DataMode QSPI Data Mode 00370 * @{ 00371 */ 00372 #define QSPI_DATA_NONE 0x00000000U /*!<No data*/ 00373 #define QSPI_DATA_1_LINE ((uint32_t)QUADSPI_CCR_DMODE_0) /*!<Data on a single line*/ 00374 #define QSPI_DATA_2_LINES ((uint32_t)QUADSPI_CCR_DMODE_1) /*!<Data on two lines*/ 00375 #define QSPI_DATA_4_LINES ((uint32_t)QUADSPI_CCR_DMODE) /*!<Data on four lines*/ 00376 /** 00377 * @} 00378 */ 00379 00380 /** @defgroup QSPI_DdrMode QSPI DDR Mode 00381 * @{ 00382 */ 00383 #define QSPI_DDR_MODE_DISABLE 0x00000000U /*!<Double data rate mode disabled*/ 00384 #define QSPI_DDR_MODE_ENABLE ((uint32_t)QUADSPI_CCR_DDRM) /*!<Double data rate mode enabled*/ 00385 /** 00386 * @} 00387 */ 00388 00389 /** @defgroup QSPI_DdrHoldHalfCycle QSPI DDR Data Output Delay 00390 * @{ 00391 */ 00392 #define QSPI_DDR_HHC_ANALOG_DELAY 0x00000000U /*!<Delay the data output using analog delay in DDR mode*/ 00393 #if defined(QUADSPI_CCR_DHHC) 00394 #define QSPI_DDR_HHC_HALF_CLK_DELAY ((uint32_t)QUADSPI_CCR_DHHC) /*!<Delay the data output by one half of system clock in DDR mode*/ 00395 #endif 00396 /** 00397 * @} 00398 */ 00399 00400 /** @defgroup QSPI_SIOOMode QSPI Send Instruction Mode 00401 * @{ 00402 */ 00403 #define QSPI_SIOO_INST_EVERY_CMD 0x00000000U /*!<Send instruction on every transaction*/ 00404 #define QSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)QUADSPI_CCR_SIOO) /*!<Send instruction only for the first command*/ 00405 /** 00406 * @} 00407 */ 00408 00409 /** @defgroup QSPI_MatchMode QSPI Match Mode 00410 * @{ 00411 */ 00412 #define QSPI_MATCH_MODE_AND 0x00000000U /*!<AND match mode between unmasked bits*/ 00413 #define QSPI_MATCH_MODE_OR ((uint32_t)QUADSPI_CR_PMM) /*!<OR match mode between unmasked bits*/ 00414 /** 00415 * @} 00416 */ 00417 00418 /** @defgroup QSPI_AutomaticStop QSPI Automatic Stop 00419 * @{ 00420 */ 00421 #define QSPI_AUTOMATIC_STOP_DISABLE 0x00000000U /*!<AutoPolling stops only with abort or QSPI disabling*/ 00422 #define QSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)QUADSPI_CR_APMS) /*!<AutoPolling stops as soon as there is a match*/ 00423 /** 00424 * @} 00425 */ 00426 00427 /** @defgroup QSPI_TimeOutActivation QSPI Timeout Activation 00428 * @{ 00429 */ 00430 #define QSPI_TIMEOUT_COUNTER_DISABLE 0x00000000U /*!<Timeout counter disabled, nCS remains active*/ 00431 #define QSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)QUADSPI_CR_TCEN) /*!<Timeout counter enabled, nCS released when timeout expires*/ 00432 /** 00433 * @} 00434 */ 00435 00436 /** @defgroup QSPI_Flags QSPI Flags 00437 * @{ 00438 */ 00439 #define QSPI_FLAG_BUSY QUADSPI_SR_BUSY /*!<Busy flag: operation is ongoing*/ 00440 #define QSPI_FLAG_TO QUADSPI_SR_TOF /*!<Timeout flag: timeout occurs in memory-mapped mode*/ 00441 #define QSPI_FLAG_SM QUADSPI_SR_SMF /*!<Status match flag: received data matches in autopolling mode*/ 00442 #define QSPI_FLAG_FT QUADSPI_SR_FTF /*!<Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete*/ 00443 #define QSPI_FLAG_TC QUADSPI_SR_TCF /*!<Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted*/ 00444 #define QSPI_FLAG_TE QUADSPI_SR_TEF /*!<Transfer error flag: invalid address is being accessed*/ 00445 /** 00446 * @} 00447 */ 00448 00449 /** @defgroup QSPI_Interrupts QSPI Interrupts 00450 * @{ 00451 */ 00452 #define QSPI_IT_TO QUADSPI_CR_TOIE /*!<Interrupt on the timeout flag*/ 00453 #define QSPI_IT_SM QUADSPI_CR_SMIE /*!<Interrupt on the status match flag*/ 00454 #define QSPI_IT_FT QUADSPI_CR_FTIE /*!<Interrupt on the fifo threshold flag*/ 00455 #define QSPI_IT_TC QUADSPI_CR_TCIE /*!<Interrupt on the transfer complete flag*/ 00456 #define QSPI_IT_TE QUADSPI_CR_TEIE /*!<Interrupt on the transfer error flag*/ 00457 /** 00458 * @} 00459 */ 00460 00461 /** @defgroup QSPI_Timeout_definition QSPI Timeout definition 00462 * @brief QSPI Timeout definition 00463 * @{ 00464 */ 00465 #define HAL_QPSI_TIMEOUT_DEFAULT_VALUE 5000U /* 5 s */ 00466 /** 00467 * @} 00468 */ 00469 00470 /** 00471 * @} 00472 */ 00473 00474 /* Exported macros -----------------------------------------------------------*/ 00475 /** @defgroup QSPI_Exported_Macros QSPI Exported Macros 00476 * @{ 00477 */ 00478 /** @brief Reset QSPI handle state. 00479 * @param __HANDLE__ : QSPI handle. 00480 * @retval None 00481 */ 00482 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00483 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 00484 (__HANDLE__)->State = HAL_QSPI_STATE_RESET; \ 00485 (__HANDLE__)->MspInitCallback = NULL; \ 00486 (__HANDLE__)->MspDeInitCallback = NULL; \ 00487 } while(0) 00488 #else 00489 #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) 00490 #endif 00491 00492 /** @brief Enable the QSPI peripheral. 00493 * @param __HANDLE__ : specifies the QSPI Handle. 00494 * @retval None 00495 */ 00496 #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 00497 00498 /** @brief Disable the QSPI peripheral. 00499 * @param __HANDLE__ : specifies the QSPI Handle. 00500 * @retval None 00501 */ 00502 #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) 00503 00504 /** @brief Enable the specified QSPI interrupt. 00505 * @param __HANDLE__ : specifies the QSPI Handle. 00506 * @param __INTERRUPT__ : specifies the QSPI interrupt source to enable. 00507 * This parameter can be one of the following values: 00508 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00509 * @arg QSPI_IT_SM: QSPI Status match interrupt 00510 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00511 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00512 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00513 * @retval None 00514 */ 00515 #define __HAL_QSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00516 00517 00518 /** @brief Disable the specified QSPI interrupt. 00519 * @param __HANDLE__ : specifies the QSPI Handle. 00520 * @param __INTERRUPT__ : specifies the QSPI interrupt source to disable. 00521 * This parameter can be one of the following values: 00522 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00523 * @arg QSPI_IT_SM: QSPI Status match interrupt 00524 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00525 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00526 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00527 * @retval None 00528 */ 00529 #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00530 00531 /** @brief Check whether the specified QSPI interrupt source is enabled or not. 00532 * @param __HANDLE__ : specifies the QSPI Handle. 00533 * @param __INTERRUPT__ : specifies the QSPI interrupt source to check. 00534 * This parameter can be one of the following values: 00535 * @arg QSPI_IT_TO: QSPI Timeout interrupt 00536 * @arg QSPI_IT_SM: QSPI Status match interrupt 00537 * @arg QSPI_IT_FT: QSPI FIFO threshold interrupt 00538 * @arg QSPI_IT_TC: QSPI Transfer complete interrupt 00539 * @arg QSPI_IT_TE: QSPI Transfer error interrupt 00540 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 00541 */ 00542 #define __HAL_QSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 00543 00544 /** 00545 * @brief Check whether the selected QSPI flag is set or not. 00546 * @param __HANDLE__ : specifies the QSPI Handle. 00547 * @param __FLAG__ : specifies the QSPI flag to check. 00548 * This parameter can be one of the following values: 00549 * @arg QSPI_FLAG_BUSY: QSPI Busy flag 00550 * @arg QSPI_FLAG_TO: QSPI Timeout flag 00551 * @arg QSPI_FLAG_SM: QSPI Status match flag 00552 * @arg QSPI_FLAG_FT: QSPI FIFO threshold flag 00553 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 00554 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 00555 * @retval None 00556 */ 00557 #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 00558 00559 /** @brief Clears the specified QSPI's flag status. 00560 * @param __HANDLE__ : specifies the QSPI Handle. 00561 * @param __FLAG__ : specifies the QSPI clear register flag that needs to be set 00562 * This parameter can be one of the following values: 00563 * @arg QSPI_FLAG_TO: QSPI Timeout flag 00564 * @arg QSPI_FLAG_SM: QSPI Status match flag 00565 * @arg QSPI_FLAG_TC: QSPI Transfer complete flag 00566 * @arg QSPI_FLAG_TE: QSPI Transfer error flag 00567 * @retval None 00568 */ 00569 #define __HAL_QSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 00570 /** 00571 * @} 00572 */ 00573 00574 /* Exported functions --------------------------------------------------------*/ 00575 /** @addtogroup QSPI_Exported_Functions 00576 * @{ 00577 */ 00578 00579 /** @addtogroup QSPI_Exported_Functions_Group1 00580 * @{ 00581 */ 00582 /* Initialization/de-initialization functions ********************************/ 00583 HAL_StatusTypeDef HAL_QSPI_Init (QSPI_HandleTypeDef *hqspi); 00584 HAL_StatusTypeDef HAL_QSPI_DeInit (QSPI_HandleTypeDef *hqspi); 00585 void HAL_QSPI_MspInit (QSPI_HandleTypeDef *hqspi); 00586 void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi); 00587 /** 00588 * @} 00589 */ 00590 00591 /** @addtogroup QSPI_Exported_Functions_Group2 00592 * @{ 00593 */ 00594 /* IO operation functions *****************************************************/ 00595 /* QSPI IRQ handler method */ 00596 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi); 00597 00598 /* QSPI indirect mode */ 00599 HAL_StatusTypeDef HAL_QSPI_Command (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout); 00600 HAL_StatusTypeDef HAL_QSPI_Transmit (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 00601 HAL_StatusTypeDef HAL_QSPI_Receive (QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout); 00602 HAL_StatusTypeDef HAL_QSPI_Command_IT (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd); 00603 HAL_StatusTypeDef HAL_QSPI_Transmit_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00604 HAL_StatusTypeDef HAL_QSPI_Receive_IT (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00605 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00606 HAL_StatusTypeDef HAL_QSPI_Receive_DMA (QSPI_HandleTypeDef *hqspi, uint8_t *pData); 00607 00608 /* QSPI status flag polling mode */ 00609 HAL_StatusTypeDef HAL_QSPI_AutoPolling (QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 00610 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg); 00611 00612 /* QSPI memory-mapped mode */ 00613 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg); 00614 00615 /* Callback functions in non-blocking modes ***********************************/ 00616 void HAL_QSPI_ErrorCallback (QSPI_HandleTypeDef *hqspi); 00617 void HAL_QSPI_AbortCpltCallback (QSPI_HandleTypeDef *hqspi); 00618 void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi); 00619 00620 /* QSPI indirect mode */ 00621 void HAL_QSPI_CmdCpltCallback (QSPI_HandleTypeDef *hqspi); 00622 void HAL_QSPI_RxCpltCallback (QSPI_HandleTypeDef *hqspi); 00623 void HAL_QSPI_TxCpltCallback (QSPI_HandleTypeDef *hqspi); 00624 void HAL_QSPI_RxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 00625 void HAL_QSPI_TxHalfCpltCallback (QSPI_HandleTypeDef *hqspi); 00626 00627 /* QSPI status flag polling mode */ 00628 void HAL_QSPI_StatusMatchCallback (QSPI_HandleTypeDef *hqspi); 00629 00630 /* QSPI memory-mapped mode */ 00631 void HAL_QSPI_TimeOutCallback (QSPI_HandleTypeDef *hqspi); 00632 00633 #if (USE_HAL_QSPI_REGISTER_CALLBACKS == 1) 00634 /* QSPI callback registering/unregistering */ 00635 HAL_StatusTypeDef HAL_QSPI_RegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID, pQSPI_CallbackTypeDef pCallback); 00636 HAL_StatusTypeDef HAL_QSPI_UnRegisterCallback (QSPI_HandleTypeDef *hqspi, HAL_QSPI_CallbackIDTypeDef CallbackID); 00637 #endif 00638 /** 00639 * @} 00640 */ 00641 00642 /** @addtogroup QSPI_Exported_Functions_Group3 00643 * @{ 00644 */ 00645 /* Peripheral Control and State functions ************************************/ 00646 HAL_QSPI_StateTypeDef HAL_QSPI_GetState (QSPI_HandleTypeDef *hqspi); 00647 uint32_t HAL_QSPI_GetError (QSPI_HandleTypeDef *hqspi); 00648 HAL_StatusTypeDef HAL_QSPI_Abort (QSPI_HandleTypeDef *hqspi); 00649 HAL_StatusTypeDef HAL_QSPI_Abort_IT (QSPI_HandleTypeDef *hqspi); 00650 void HAL_QSPI_SetTimeout (QSPI_HandleTypeDef *hqspi, uint32_t Timeout); 00651 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold); 00652 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi); 00653 #if defined(QUADSPI_CR_DFM) 00654 HAL_StatusTypeDef HAL_QSPI_SetFlashID (QSPI_HandleTypeDef *hqspi, uint32_t FlashID); 00655 #endif 00656 /** 00657 * @} 00658 */ 00659 00660 /** 00661 * @} 00662 */ 00663 /* End of exported functions -------------------------------------------------*/ 00664 00665 /* Private macros ------------------------------------------------------------*/ 00666 /** @defgroup QSPI_Private_Macros QSPI Private Macros 00667 * @{ 00668 */ 00669 #define IS_QSPI_CLOCK_PRESCALER(PRESCALER) ((PRESCALER) <= 0xFFU) 00670 00671 #define IS_QSPI_FIFO_THRESHOLD(THR) (((THR) > 0U) && ((THR) <= 16U)) 00672 00673 #define IS_QSPI_SSHIFT(SSHIFT) (((SSHIFT) == QSPI_SAMPLE_SHIFTING_NONE) || \ 00674 ((SSHIFT) == QSPI_SAMPLE_SHIFTING_HALFCYCLE)) 00675 00676 #define IS_QSPI_FLASH_SIZE(FSIZE) (((FSIZE) <= 31U)) 00677 00678 #define IS_QSPI_CS_HIGH_TIME(CSHTIME) (((CSHTIME) == QSPI_CS_HIGH_TIME_1_CYCLE) || \ 00679 ((CSHTIME) == QSPI_CS_HIGH_TIME_2_CYCLE) || \ 00680 ((CSHTIME) == QSPI_CS_HIGH_TIME_3_CYCLE) || \ 00681 ((CSHTIME) == QSPI_CS_HIGH_TIME_4_CYCLE) || \ 00682 ((CSHTIME) == QSPI_CS_HIGH_TIME_5_CYCLE) || \ 00683 ((CSHTIME) == QSPI_CS_HIGH_TIME_6_CYCLE) || \ 00684 ((CSHTIME) == QSPI_CS_HIGH_TIME_7_CYCLE) || \ 00685 ((CSHTIME) == QSPI_CS_HIGH_TIME_8_CYCLE)) 00686 00687 #define IS_QSPI_CLOCK_MODE(CLKMODE) (((CLKMODE) == QSPI_CLOCK_MODE_0) || \ 00688 ((CLKMODE) == QSPI_CLOCK_MODE_3)) 00689 00690 #if defined(QUADSPI_CR_DFM) 00691 #define IS_QSPI_FLASH_ID(FLASH_ID) (((FLASH_ID) == QSPI_FLASH_ID_1) || \ 00692 ((FLASH_ID) == QSPI_FLASH_ID_2)) 00693 00694 #define IS_QSPI_DUAL_FLASH_MODE(MODE) (((MODE) == QSPI_DUALFLASH_ENABLE) || \ 00695 ((MODE) == QSPI_DUALFLASH_DISABLE)) 00696 00697 #endif 00698 #define IS_QSPI_INSTRUCTION(INSTRUCTION) ((INSTRUCTION) <= 0xFFU) 00699 00700 #define IS_QSPI_ADDRESS_SIZE(ADDR_SIZE) (((ADDR_SIZE) == QSPI_ADDRESS_8_BITS) || \ 00701 ((ADDR_SIZE) == QSPI_ADDRESS_16_BITS) || \ 00702 ((ADDR_SIZE) == QSPI_ADDRESS_24_BITS) || \ 00703 ((ADDR_SIZE) == QSPI_ADDRESS_32_BITS)) 00704 00705 #define IS_QSPI_ALTERNATE_BYTES_SIZE(SIZE) (((SIZE) == QSPI_ALTERNATE_BYTES_8_BITS) || \ 00706 ((SIZE) == QSPI_ALTERNATE_BYTES_16_BITS) || \ 00707 ((SIZE) == QSPI_ALTERNATE_BYTES_24_BITS) || \ 00708 ((SIZE) == QSPI_ALTERNATE_BYTES_32_BITS)) 00709 00710 #define IS_QSPI_DUMMY_CYCLES(DCY) ((DCY) <= 31U) 00711 00712 #define IS_QSPI_INSTRUCTION_MODE(MODE) (((MODE) == QSPI_INSTRUCTION_NONE) || \ 00713 ((MODE) == QSPI_INSTRUCTION_1_LINE) || \ 00714 ((MODE) == QSPI_INSTRUCTION_2_LINES) || \ 00715 ((MODE) == QSPI_INSTRUCTION_4_LINES)) 00716 00717 #define IS_QSPI_ADDRESS_MODE(MODE) (((MODE) == QSPI_ADDRESS_NONE) || \ 00718 ((MODE) == QSPI_ADDRESS_1_LINE) || \ 00719 ((MODE) == QSPI_ADDRESS_2_LINES) || \ 00720 ((MODE) == QSPI_ADDRESS_4_LINES)) 00721 00722 #define IS_QSPI_ALTERNATE_BYTES_MODE(MODE) (((MODE) == QSPI_ALTERNATE_BYTES_NONE) || \ 00723 ((MODE) == QSPI_ALTERNATE_BYTES_1_LINE) || \ 00724 ((MODE) == QSPI_ALTERNATE_BYTES_2_LINES) || \ 00725 ((MODE) == QSPI_ALTERNATE_BYTES_4_LINES)) 00726 00727 #define IS_QSPI_DATA_MODE(MODE) (((MODE) == QSPI_DATA_NONE) || \ 00728 ((MODE) == QSPI_DATA_1_LINE) || \ 00729 ((MODE) == QSPI_DATA_2_LINES) || \ 00730 ((MODE) == QSPI_DATA_4_LINES)) 00731 00732 #define IS_QSPI_DDR_MODE(DDR_MODE) (((DDR_MODE) == QSPI_DDR_MODE_DISABLE) || \ 00733 ((DDR_MODE) == QSPI_DDR_MODE_ENABLE)) 00734 00735 #if defined(QUADSPI_CCR_DHHC) 00736 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY) || \ 00737 ((DDR_HHC) == QSPI_DDR_HHC_HALF_CLK_DELAY)) 00738 00739 #else 00740 #define IS_QSPI_DDR_HHC(DDR_HHC) (((DDR_HHC) == QSPI_DDR_HHC_ANALOG_DELAY)) 00741 00742 #endif 00743 #define IS_QSPI_SIOO_MODE(SIOO_MODE) (((SIOO_MODE) == QSPI_SIOO_INST_EVERY_CMD) || \ 00744 ((SIOO_MODE) == QSPI_SIOO_INST_ONLY_FIRST_CMD)) 00745 00746 #define IS_QSPI_INTERVAL(INTERVAL) ((INTERVAL) <= QUADSPI_PIR_INTERVAL) 00747 00748 #define IS_QSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 00749 00750 #define IS_QSPI_MATCH_MODE(MODE) (((MODE) == QSPI_MATCH_MODE_AND) || \ 00751 ((MODE) == QSPI_MATCH_MODE_OR)) 00752 00753 #define IS_QSPI_AUTOMATIC_STOP(APMS) (((APMS) == QSPI_AUTOMATIC_STOP_DISABLE) || \ 00754 ((APMS) == QSPI_AUTOMATIC_STOP_ENABLE)) 00755 00756 #define IS_QSPI_TIMEOUT_ACTIVATION(TCEN) (((TCEN) == QSPI_TIMEOUT_COUNTER_DISABLE) || \ 00757 ((TCEN) == QSPI_TIMEOUT_COUNTER_ENABLE)) 00758 00759 #define IS_QSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 00760 /** 00761 * @} 00762 */ 00763 /* End of private macros -----------------------------------------------------*/ 00764 00765 /** 00766 * @} 00767 */ 00768 00769 /** 00770 * @} 00771 */ 00772 00773 #endif /* defined(QUADSPI) || defined(QUADSPI1) || defined(QUADSPI2) */ 00774 00775 #ifdef __cplusplus 00776 } 00777 #endif 00778 00779 #endif /* STM32L4xx_HAL_QSPI_H */ 00780 00781 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/