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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dma.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_DMA_H 00038 #define __STM32L4xx_HAL_DMA_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /** @addtogroup STM32L4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup DMA 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup DMA_Exported_Types DMA Exported Types 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief DMA Configuration Structure definition 00062 */ 00063 typedef struct 00064 { 00065 uint32_t Request; /*!< Specifies the request selected for the specified channel. 00066 This parameter can be a value of @ref DMA_request */ 00067 00068 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00069 from memory to memory or from peripheral to memory. 00070 This parameter can be a value of @ref DMA_Data_transfer_direction */ 00071 00072 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not. 00073 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */ 00074 00075 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not. 00076 This parameter can be a value of @ref DMA_Memory_incremented_mode */ 00077 00078 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width. 00079 This parameter can be a value of @ref DMA_Peripheral_data_size */ 00080 00081 uint32_t MemDataAlignment; /*!< Specifies the Memory data width. 00082 This parameter can be a value of @ref DMA_Memory_data_size */ 00083 00084 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx. 00085 This parameter can be a value of @ref DMA_mode 00086 @note The circular buffer mode cannot be used if the memory-to-memory 00087 data transfer is configured on the selected Channel */ 00088 00089 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx. 00090 This parameter can be a value of @ref DMA_Priority_level */ 00091 } DMA_InitTypeDef; 00092 00093 /** 00094 * @brief HAL DMA State structures definition 00095 */ 00096 typedef enum 00097 { 00098 HAL_DMA_STATE_RESET = 0x00U, /*!< DMA not yet initialized or disabled */ 00099 HAL_DMA_STATE_READY = 0x01U, /*!< DMA initialized and ready for use */ 00100 HAL_DMA_STATE_BUSY = 0x02U, /*!< DMA process is ongoing */ 00101 HAL_DMA_STATE_TIMEOUT = 0x03U, /*!< DMA timeout state */ 00102 }HAL_DMA_StateTypeDef; 00103 00104 /** 00105 * @brief HAL DMA Error Code structure definition 00106 */ 00107 typedef enum 00108 { 00109 HAL_DMA_FULL_TRANSFER = 0x00U, /*!< Full transfer */ 00110 HAL_DMA_HALF_TRANSFER = 0x01U /*!< Half Transfer */ 00111 }HAL_DMA_LevelCompleteTypeDef; 00112 00113 00114 /** 00115 * @brief HAL DMA Callback ID structure definition 00116 */ 00117 typedef enum 00118 { 00119 HAL_DMA_XFER_CPLT_CB_ID = 0x00U, /*!< Full transfer */ 00120 HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, /*!< Half transfer */ 00121 HAL_DMA_XFER_ERROR_CB_ID = 0x02U, /*!< Error */ 00122 HAL_DMA_XFER_ABORT_CB_ID = 0x03U, /*!< Abort */ 00123 HAL_DMA_XFER_ALL_CB_ID = 0x04U /*!< All */ 00124 }HAL_DMA_CallbackIDTypeDef; 00125 00126 /** 00127 * @brief DMA handle Structure definition 00128 */ 00129 typedef struct __DMA_HandleTypeDef 00130 { 00131 DMA_Channel_TypeDef *Instance; /*!< Register base address */ 00132 00133 DMA_InitTypeDef Init; /*!< DMA communication parameters */ 00134 00135 HAL_LockTypeDef Lock; /*!< DMA locking object */ 00136 00137 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */ 00138 00139 void *Parent; /*!< Parent object state */ 00140 00141 void (* XferCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */ 00142 00143 void (* XferHalfCpltCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */ 00144 00145 void (* XferErrorCallback)(struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */ 00146 00147 void (* XferAbortCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer abort callback */ 00148 00149 __IO uint32_t ErrorCode; /*!< DMA Error code */ 00150 00151 DMA_TypeDef *DmaBaseAddress; /*!< DMA Channel Base Address */ 00152 00153 uint32_t ChannelIndex; /*!< DMA Channel Index */ 00154 00155 #if defined(DMAMUX1) 00156 DMAMUX_Channel_TypeDef *DMAmuxChannel; /*!< Register base address */ 00157 00158 DMAMUX_ChannelStatus_TypeDef *DMAmuxChannelStatus; /*!< DMAMUX Channels Status Base Address */ 00159 00160 uint32_t DMAmuxChannelStatusMask; /*!< DMAMUX Channel Status Mask */ 00161 00162 DMAMUX_RequestGen_TypeDef *DMAmuxRequestGen; /*!< DMAMUX request generator Base Address */ 00163 00164 DMAMUX_RequestGenStatus_TypeDef *DMAmuxRequestGenStatus; /*!< DMAMUX request generator Address */ 00165 00166 uint32_t DMAmuxRequestGenStatusMask; /*!< DMAMUX request generator Status mask */ 00167 00168 #endif /* DMAMUX1 */ 00169 00170 }DMA_HandleTypeDef; 00171 00172 /** 00173 * @} 00174 */ 00175 00176 /* Exported constants --------------------------------------------------------*/ 00177 00178 /** @defgroup DMA_Exported_Constants DMA Exported Constants 00179 * @{ 00180 */ 00181 00182 /** @defgroup DMA_Error_Code DMA Error Code 00183 * @{ 00184 */ 00185 #define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */ 00186 #define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */ 00187 #define HAL_DMA_ERROR_NO_XFER 0x00000004U /*!< Abort requested with no Xfer ongoing */ 00188 #define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 00189 #define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */ 00190 #define HAL_DMA_ERROR_SYNC 0x00000200U /*!< DMAMUX sync overrun error */ 00191 #define HAL_DMA_ERROR_REQGEN 0x00000400U /*!< DMAMUX request generator overrun error */ 00192 00193 /** 00194 * @} 00195 */ 00196 00197 /** @defgroup DMA_request DMA request 00198 * @{ 00199 */ 00200 #if !defined (DMAMUX1) 00201 00202 #define DMA_REQUEST_0 0U 00203 #define DMA_REQUEST_1 1U 00204 #define DMA_REQUEST_2 2U 00205 #define DMA_REQUEST_3 3U 00206 #define DMA_REQUEST_4 4U 00207 #define DMA_REQUEST_5 5U 00208 #define DMA_REQUEST_6 6U 00209 #define DMA_REQUEST_7 7U 00210 00211 #endif 00212 00213 #if defined(DMAMUX1) 00214 00215 #define DMA_REQUEST_MEM2MEM 0U /*!< memory to memory transfer */ 00216 00217 #define DMA_REQUEST_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */ 00218 #define DMA_REQUEST_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */ 00219 #define DMA_REQUEST_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */ 00220 #define DMA_REQUEST_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */ 00221 00222 #define DMA_REQUEST_ADC1 5U /*!< DMAMUX1 ADC1 request */ 00223 00224 #define DMA_REQUEST_DAC1_CH1 6U /*!< DMAMUX1 DAC1 CH1 request */ 00225 #define DMA_REQUEST_DAC1_CH2 7U /*!< DMAMUX1 DAC1 CH2 request */ 00226 00227 #define DMA_REQUEST_TIM6_UP 8U /*!< DMAMUX1 TIM6 UP request */ 00228 #define DMA_REQUEST_TIM7_UP 9U /*!< DMAMUX1 TIM7 UP request */ 00229 00230 #define DMA_REQUEST_SPI1_RX 10U /*!< DMAMUX1 SPI1 RX request */ 00231 #define DMA_REQUEST_SPI1_TX 11U /*!< DMAMUX1 SPI1 TX request */ 00232 #define DMA_REQUEST_SPI2_RX 12U /*!< DMAMUX1 SPI2 RX request */ 00233 #define DMA_REQUEST_SPI2_TX 13U /*!< DMAMUX1 SPI2 TX request */ 00234 #define DMA_REQUEST_SPI3_RX 14U /*!< DMAMUX1 SPI3 RX request */ 00235 #define DMA_REQUEST_SPI3_TX 15U /*!< DMAMUX1 SPI3 TX request */ 00236 00237 #define DMA_REQUEST_I2C1_RX 16U /*!< DMAMUX1 I2C1 RX request */ 00238 #define DMA_REQUEST_I2C1_TX 17U /*!< DMAMUX1 I2C1 TX request */ 00239 #define DMA_REQUEST_I2C2_RX 18U /*!< DMAMUX1 I2C2 RX request */ 00240 #define DMA_REQUEST_I2C2_TX 19U /*!< DMAMUX1 I2C2 TX request */ 00241 #define DMA_REQUEST_I2C3_RX 20U /*!< DMAMUX1 I2C3 RX request */ 00242 #define DMA_REQUEST_I2C3_TX 21U /*!< DMAMUX1 I2C3 TX request */ 00243 #define DMA_REQUEST_I2C4_RX 22U /*!< DMAMUX1 I2C4 RX request */ 00244 #define DMA_REQUEST_I2C4_TX 23U /*!< DMAMUX1 I2C4 TX request */ 00245 00246 #define DMA_REQUEST_USART1_RX 24U /*!< DMAMUX1 USART1 RX request */ 00247 #define DMA_REQUEST_USART1_TX 25U /*!< DMAMUX1 USART1 TX request */ 00248 #define DMA_REQUEST_USART2_RX 26U /*!< DMAMUX1 USART2 RX request */ 00249 #define DMA_REQUEST_USART2_TX 27U /*!< DMAMUX1 USART2 TX request */ 00250 #define DMA_REQUEST_USART3_RX 28U /*!< DMAMUX1 USART3 RX request */ 00251 #define DMA_REQUEST_USART3_TX 29U /*!< DMAMUX1 USART3 TX request */ 00252 00253 #define DMA_REQUEST_UART4_RX 30U /*!< DMAMUX1 UART4 RX request */ 00254 #define DMA_REQUEST_UART4_TX 31U /*!< DMAMUX1 UART4 TX request */ 00255 #define DMA_REQUEST_UART5_RX 32U /*!< DMAMUX1 UART5 RX request */ 00256 #define DMA_REQUEST_UART5_TX 33U /*!< DMAMUX1 UART5 TX request */ 00257 00258 #define DMA_REQUEST_LPUART1_RX 34U /*!< DMAMUX1 LP_UART1_RX request */ 00259 #define DMA_REQUEST_LPUART1_TX 35U /*!< DMAMUX1 LP_UART1_RX request */ 00260 00261 #define DMA_REQUEST_SAI1_A 36U /*!< DMAMUX1 SAI1 A request */ 00262 #define DMA_REQUEST_SAI1_B 37U /*!< DMAMUX1 SAI1 B request */ 00263 #define DMA_REQUEST_SAI2_A 38U /*!< DMAMUX1 SAI2 A request */ 00264 #define DMA_REQUEST_SAI2_B 39U /*!< DMAMUX1 SAI2 B request */ 00265 00266 #define DMA_REQUEST_OCTOSPI1 40U /*!< DMAMUX1 OCTOSPI1 request */ 00267 #define DMA_REQUEST_OCTOSPI2 41U /*!< DMAMUX1 OCTOSPI2 request */ 00268 00269 #define DMA_REQUEST_TIM1_CH1 42U /*!< DMAMUX1 TIM1 CH1 request */ 00270 #define DMA_REQUEST_TIM1_CH2 43U /*!< DMAMUX1 TIM1 CH2 request */ 00271 #define DMA_REQUEST_TIM1_CH3 44U /*!< DMAMUX1 TIM1 CH3 request */ 00272 #define DMA_REQUEST_TIM1_CH4 45U /*!< DMAMUX1 TIM1 CH4 request */ 00273 #define DMA_REQUEST_TIM1_UP 46U /*!< DMAMUX1 TIM1 UP request */ 00274 #define DMA_REQUEST_TIM1_TRIG 47U /*!< DMAMUX1 TIM1 TRIG request */ 00275 #define DMA_REQUEST_TIM1_COM 48U /*!< DMAMUX1 TIM1 COM request */ 00276 00277 #define DMA_REQUEST_TIM8_CH1 49U /*!< DMAMUX1 TIM8 CH1 request */ 00278 #define DMA_REQUEST_TIM8_CH2 50U /*!< DMAMUX1 TIM8 CH2 request */ 00279 #define DMA_REQUEST_TIM8_CH3 51U /*!< DMAMUX1 TIM8 CH3 request */ 00280 #define DMA_REQUEST_TIM8_CH4 52U /*!< DMAMUX1 TIM8 CH4 request */ 00281 #define DMA_REQUEST_TIM8_UP 53U /*!< DMAMUX1 TIM8 UP request */ 00282 #define DMA_REQUEST_TIM8_TRIG 54U /*!< DMAMUX1 TIM8 TRIG request */ 00283 #define DMA_REQUEST_TIM8_COM 55U /*!< DMAMUX1 TIM8 COM request */ 00284 00285 #define DMA_REQUEST_TIM2_CH1 56U /*!< DMAMUX1 TIM2 CH1 request */ 00286 #define DMA_REQUEST_TIM2_CH2 57U /*!< DMAMUX1 TIM2 CH2 request */ 00287 #define DMA_REQUEST_TIM2_CH3 58U /*!< DMAMUX1 TIM2 CH3 request */ 00288 #define DMA_REQUEST_TIM2_CH4 59U /*!< DMAMUX1 TIM2 CH4 request */ 00289 #define DMA_REQUEST_TIM2_UP 60U /*!< DMAMUX1 TIM2 UP request */ 00290 00291 #define DMA_REQUEST_TIM3_CH1 61U /*!< DMAMUX1 TIM3 CH1 request */ 00292 #define DMA_REQUEST_TIM3_CH2 62U /*!< DMAMUX1 TIM3 CH2 request */ 00293 #define DMA_REQUEST_TIM3_CH3 63U /*!< DMAMUX1 TIM3 CH3 request */ 00294 #define DMA_REQUEST_TIM3_CH4 64U /*!< DMAMUX1 TIM3 CH4 request */ 00295 #define DMA_REQUEST_TIM3_UP 65U /*!< DMAMUX1 TIM3 UP request */ 00296 #define DMA_REQUEST_TIM3_TRIG 66U /*!< DMAMUX1 TIM3 TRIG request */ 00297 00298 #define DMA_REQUEST_TIM4_CH1 67U /*!< DMAMUX1 TIM4 CH1 request */ 00299 #define DMA_REQUEST_TIM4_CH2 68U /*!< DMAMUX1 TIM4 CH2 request */ 00300 #define DMA_REQUEST_TIM4_CH3 69U /*!< DMAMUX1 TIM4 CH3 request */ 00301 #define DMA_REQUEST_TIM4_CH4 70U /*!< DMAMUX1 TIM4 CH4 request */ 00302 #define DMA_REQUEST_TIM4_UP 71U /*!< DMAMUX1 TIM4 UP request */ 00303 00304 #define DMA_REQUEST_TIM5_CH1 72U /*!< DMAMUX1 TIM5 CH1 request */ 00305 #define DMA_REQUEST_TIM5_CH2 73U /*!< DMAMUX1 TIM5 CH2 request */ 00306 #define DMA_REQUEST_TIM5_CH3 74U /*!< DMAMUX1 TIM5 CH3 request */ 00307 #define DMA_REQUEST_TIM5_CH4 75U /*!< DMAMUX1 TIM5 CH4 request */ 00308 #define DMA_REQUEST_TIM5_UP 76U /*!< DMAMUX1 TIM5 UP request */ 00309 #define DMA_REQUEST_TIM5_TRIG 77U /*!< DMAMUX1 TIM5 TRIG request */ 00310 00311 #define DMA_REQUEST_TIM15_CH1 78U /*!< DMAMUX1 TIM15 CH1 request */ 00312 #define DMA_REQUEST_TIM15_UP 79U /*!< DMAMUX1 TIM15 UP request */ 00313 #define DMA_REQUEST_TIM15_TRIG 80U /*!< DMAMUX1 TIM15 TRIG request */ 00314 #define DMA_REQUEST_TIM15_COM 81U /*!< DMAMUX1 TIM15 COM request */ 00315 00316 #define DMA_REQUEST_TIM16_CH1 82U /*!< DMAMUX1 TIM16 CH1 request */ 00317 #define DMA_REQUEST_TIM16_UP 83U /*!< DMAMUX1 TIM16 UP request */ 00318 #define DMA_REQUEST_TIM17_CH1 84U /*!< DMAMUX1 TIM17 CH1 request */ 00319 #define DMA_REQUEST_TIM17_UP 85U /*!< DMAMUX1 TIM17 UP request */ 00320 00321 #define DMA_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX1 DFSDM1 Filter0 request */ 00322 #define DMA_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX1 DFSDM1 Filter1 request */ 00323 #define DMA_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX1 DFSDM1 Filter2 request */ 00324 #define DMA_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX1 DFSDM1 Filter3 request */ 00325 00326 #define DMA_REQUEST_DCMI 90U /*!< DMAMUX1 DCMI request */ 00327 00328 #define DMA_REQUEST_AES_IN 91U /*!< DMAMUX1 AES IN request */ 00329 #define DMA_REQUEST_AES_OUT 92U /*!< DMAMUX1 AES OUT request */ 00330 00331 #define DMA_REQUEST_HASH_IN 93U /*!< DMAMUX1 HASH IN request */ 00332 00333 #endif /* DMAMUX1 */ 00334 00335 /** 00336 * @} 00337 */ 00338 00339 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction 00340 * @{ 00341 */ 00342 #define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 00343 #define DMA_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 00344 #define DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 00345 /** 00346 * @} 00347 */ 00348 00349 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode 00350 * @{ 00351 */ 00352 #define DMA_PINC_ENABLE DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 00353 #define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode Disable */ 00354 /** 00355 * @} 00356 */ 00357 00358 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode 00359 * @{ 00360 */ 00361 #define DMA_MINC_ENABLE DMA_CCR_MINC /*!< Memory increment mode Enable */ 00362 #define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode Disable */ 00363 /** 00364 * @} 00365 */ 00366 00367 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size 00368 * @{ 00369 */ 00370 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */ 00371 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */ 00372 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */ 00373 /** 00374 * @} 00375 */ 00376 00377 /** @defgroup DMA_Memory_data_size DMA Memory data size 00378 * @{ 00379 */ 00380 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */ 00381 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */ 00382 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */ 00383 /** 00384 * @} 00385 */ 00386 00387 /** @defgroup DMA_mode DMA mode 00388 * @{ 00389 */ 00390 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */ 00391 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular mode */ 00392 /** 00393 * @} 00394 */ 00395 00396 /** @defgroup DMA_Priority_level DMA Priority level 00397 * @{ 00398 */ 00399 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */ 00400 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */ 00401 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */ 00402 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */ 00403 /** 00404 * @} 00405 */ 00406 00407 00408 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions 00409 * @{ 00410 */ 00411 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) 00412 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) 00413 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) 00414 /** 00415 * @} 00416 */ 00417 00418 /** @defgroup DMA_flag_definitions DMA flag definitions 00419 * @{ 00420 */ 00421 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) 00422 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) 00423 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) 00424 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) 00425 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) 00426 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) 00427 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) 00428 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) 00429 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) 00430 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) 00431 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) 00432 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) 00433 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) 00434 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) 00435 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) 00436 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) 00437 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) 00438 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) 00439 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) 00440 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) 00441 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) 00442 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) 00443 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) 00444 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) 00445 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) 00446 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) 00447 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) 00448 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) 00449 /** 00450 * @} 00451 */ 00452 00453 /** 00454 * @} 00455 */ 00456 00457 /* Exported macros -----------------------------------------------------------*/ 00458 /** @defgroup DMA_Exported_Macros DMA Exported Macros 00459 * @{ 00460 */ 00461 00462 /** @brief Reset DMA handle state. 00463 * @param __HANDLE__: DMA handle 00464 * @retval None 00465 */ 00466 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) 00467 00468 /** 00469 * @brief Enable the specified DMA Channel. 00470 * @param __HANDLE__: DMA handle 00471 * @retval None 00472 */ 00473 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) 00474 00475 /** 00476 * @brief Disable the specified DMA Channel. 00477 * @param __HANDLE__: DMA handle 00478 * @retval None 00479 */ 00480 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) 00481 00482 00483 /* Interrupt & Flag management */ 00484 00485 /** 00486 * @brief Return the current DMA Channel transfer complete flag. 00487 * @param __HANDLE__: DMA handle 00488 * @retval The specified transfer complete flag index. 00489 */ 00490 00491 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \ 00492 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\ 00493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\ 00494 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\ 00495 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\ 00496 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\ 00497 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\ 00498 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\ 00499 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\ 00500 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\ 00501 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TC5 :\ 00502 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\ 00503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TC6 :\ 00504 DMA_FLAG_TC7) 00505 00506 /** 00507 * @brief Return the current DMA Channel half transfer complete flag. 00508 * @param __HANDLE__: DMA handle 00509 * @retval The specified half transfer complete flag index. 00510 */ 00511 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\ 00512 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\ 00513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\ 00514 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\ 00515 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\ 00516 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\ 00517 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\ 00518 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\ 00519 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\ 00520 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\ 00521 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_HT5 :\ 00522 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\ 00523 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_HT6 :\ 00524 DMA_FLAG_HT7) 00525 00526 /** 00527 * @brief Return the current DMA Channel transfer error flag. 00528 * @param __HANDLE__: DMA handle 00529 * @retval The specified transfer error flag index. 00530 */ 00531 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\ 00532 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\ 00533 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\ 00534 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\ 00535 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\ 00536 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\ 00537 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\ 00538 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\ 00539 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\ 00540 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\ 00541 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_FLAG_TE5 :\ 00542 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\ 00543 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_FLAG_TE6 :\ 00544 DMA_FLAG_TE7) 00545 00546 /** 00547 * @brief Return the current DMA Channel Global interrupt flag. 00548 * @param __HANDLE__: DMA handle 00549 * @retval The specified transfer error flag index. 00550 */ 00551 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\ 00552 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_ISR_GIF1 :\ 00553 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_ISR_GIF1 :\ 00554 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_ISR_GIF2 :\ 00555 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_ISR_GIF2 :\ 00556 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_ISR_GIF3 :\ 00557 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_ISR_GIF3 :\ 00558 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_ISR_GIF4 :\ 00559 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_ISR_GIF4 :\ 00560 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_ISR_GIF5 :\ 00561 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel5))? DMA_ISR_GIF5 :\ 00562 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_ISR_GIF6 :\ 00563 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel6))? DMA_ISR_GIF6 :\ 00564 DMA_ISR_GIF7) 00565 00566 /** 00567 * @brief Get the DMA Channel pending flags. 00568 * @param __HANDLE__: DMA handle 00569 * @param __FLAG__: Get the specified flag. 00570 * This parameter can be any combination of the following values: 00571 * @arg DMA_FLAG_TCx: Transfer complete flag 00572 * @arg DMA_FLAG_HTx: Half transfer complete flag 00573 * @arg DMA_FLAG_TEx: Transfer error flag 00574 * @arg DMA_FLAG_GLx: Global interrupt flag 00575 * Where x can be from 1 to 7 to select the DMA Channel x flag. 00576 * @retval The state of FLAG (SET or RESET). 00577 */ 00578 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 00579 (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) 00580 00581 /** 00582 * @brief Clear the DMA Channel pending flags. 00583 * @param __HANDLE__: DMA handle 00584 * @param __FLAG__: specifies the flag to clear. 00585 * This parameter can be any combination of the following values: 00586 * @arg DMA_FLAG_TCx: Transfer complete flag 00587 * @arg DMA_FLAG_HTx: Half transfer complete flag 00588 * @arg DMA_FLAG_TEx: Transfer error flag 00589 * @arg DMA_FLAG_GLx: Global interrupt flag 00590 * Where x can be from 1 to 7 to select the DMA Channel x flag. 00591 * @retval None 00592 */ 00593 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ 00594 (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) 00595 00596 /** 00597 * @brief Enable the specified DMA Channel interrupts. 00598 * @param __HANDLE__: DMA handle 00599 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 00600 * This parameter can be any combination of the following values: 00601 * @arg DMA_IT_TC: Transfer complete interrupt mask 00602 * @arg DMA_IT_HT: Half transfer complete interrupt mask 00603 * @arg DMA_IT_TE: Transfer error interrupt mask 00604 * @retval None 00605 */ 00606 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) 00607 00608 /** 00609 * @brief Disable the specified DMA Channel interrupts. 00610 * @param __HANDLE__: DMA handle 00611 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 00612 * This parameter can be any combination of the following values: 00613 * @arg DMA_IT_TC: Transfer complete interrupt mask 00614 * @arg DMA_IT_HT: Half transfer complete interrupt mask 00615 * @arg DMA_IT_TE: Transfer error interrupt mask 00616 * @retval None 00617 */ 00618 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) 00619 00620 /** 00621 * @brief Check whether the specified DMA Channel interrupt is enabled or not. 00622 * @param __HANDLE__: DMA handle 00623 * @param __INTERRUPT__: specifies the DMA interrupt source to check. 00624 * This parameter can be one of the following values: 00625 * @arg DMA_IT_TC: Transfer complete interrupt mask 00626 * @arg DMA_IT_HT: Half transfer complete interrupt mask 00627 * @arg DMA_IT_TE: Transfer error interrupt mask 00628 * @retval The state of DMA_IT (SET or RESET). 00629 */ 00630 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) 00631 00632 /** 00633 * @brief Return the number of remaining data units in the current DMA Channel transfer. 00634 * @param __HANDLE__: DMA handle 00635 * @retval The number of remaining data units in the current DMA Channel transfer. 00636 */ 00637 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) 00638 00639 /** 00640 * @} 00641 */ 00642 00643 #if defined(DMAMUX1) 00644 /* Include DMA HAL Extension module */ 00645 #include "stm32l4xx_hal_dma_ex.h" 00646 #endif /* DMAMUX1 */ 00647 00648 /* Exported functions --------------------------------------------------------*/ 00649 00650 /** @addtogroup DMA_Exported_Functions 00651 * @{ 00652 */ 00653 00654 /** @addtogroup DMA_Exported_Functions_Group1 00655 * @{ 00656 */ 00657 /* Initialization and de-initialization functions *****************************/ 00658 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 00659 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma); 00660 /** 00661 * @} 00662 */ 00663 00664 /** @addtogroup DMA_Exported_Functions_Group2 00665 * @{ 00666 */ 00667 /* IO operation functions *****************************************************/ 00668 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00669 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00670 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); 00671 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); 00672 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); 00673 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); 00674 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)); 00675 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); 00676 00677 /** 00678 * @} 00679 */ 00680 00681 /** @addtogroup DMA_Exported_Functions_Group3 00682 * @{ 00683 */ 00684 /* Peripheral State and Error functions ***************************************/ 00685 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma); 00686 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma); 00687 /** 00688 * @} 00689 */ 00690 00691 /** 00692 * @} 00693 */ 00694 00695 /* Private macros ------------------------------------------------------------*/ 00696 /** @defgroup DMA_Private_Macros DMA Private Macros 00697 * @{ 00698 */ 00699 00700 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \ 00701 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \ 00702 ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 00703 00704 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) 00705 00706 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \ 00707 ((STATE) == DMA_PINC_DISABLE)) 00708 00709 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \ 00710 ((STATE) == DMA_MINC_DISABLE)) 00711 00712 #if !defined (DMAMUX1) 00713 00714 #define IS_DMA_ALL_REQUEST(REQUEST) (((REQUEST) == DMA_REQUEST_0) || \ 00715 ((REQUEST) == DMA_REQUEST_1) || \ 00716 ((REQUEST) == DMA_REQUEST_2) || \ 00717 ((REQUEST) == DMA_REQUEST_3) || \ 00718 ((REQUEST) == DMA_REQUEST_4) || \ 00719 ((REQUEST) == DMA_REQUEST_5) || \ 00720 ((REQUEST) == DMA_REQUEST_6) || \ 00721 ((REQUEST) == DMA_REQUEST_7)) 00722 #endif 00723 00724 #if defined(DMAMUX1) 00725 00726 #define IS_DMA_ALL_REQUEST(REQUEST)((REQUEST) <= DMA_REQUEST_HASH_IN) 00727 00728 #endif /* DMAMUX1 */ 00729 00730 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \ 00731 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \ 00732 ((SIZE) == DMA_PDATAALIGN_WORD)) 00733 00734 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \ 00735 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \ 00736 ((SIZE) == DMA_MDATAALIGN_WORD )) 00737 00738 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \ 00739 ((MODE) == DMA_CIRCULAR)) 00740 00741 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \ 00742 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \ 00743 ((PRIORITY) == DMA_PRIORITY_HIGH) || \ 00744 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 00745 00746 /** 00747 * @} 00748 */ 00749 00750 /* Private functions ---------------------------------------------------------*/ 00751 00752 /** 00753 * @} 00754 */ 00755 00756 /** 00757 * @} 00758 */ 00759 00760 #ifdef __cplusplus 00761 } 00762 #endif 00763 00764 #endif /* __STM32L4xx_HAL_DMA_H */ 00765 00766 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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