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STM32L486xx HAL User Manual
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Header file of DMA HAL module. More...
#include "stm32l4xx_hal_def.h"Go to the source code of this file.
Data Structures | |
| struct | DMA_InitTypeDef |
| DMA Configuration Structure definition. More... | |
| struct | __DMA_HandleTypeDef |
| DMA handle Structure definition. More... | |
Defines | |
| #define | HAL_DMA_ERROR_NONE 0x00000000U |
| #define | HAL_DMA_ERROR_TE 0x00000001U |
| #define | HAL_DMA_ERROR_NO_XFER 0x00000004U |
| #define | HAL_DMA_ERROR_TIMEOUT 0x00000020U |
| #define | HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U |
| #define | HAL_DMA_ERROR_SYNC 0x00000200U |
| #define | HAL_DMA_ERROR_REQGEN 0x00000400U |
| #define | DMA_REQUEST_0 0U |
| #define | DMA_REQUEST_1 1U |
| #define | DMA_REQUEST_2 2U |
| #define | DMA_REQUEST_3 3U |
| #define | DMA_REQUEST_4 4U |
| #define | DMA_REQUEST_5 5U |
| #define | DMA_REQUEST_6 6U |
| #define | DMA_REQUEST_7 7U |
| #define | DMA_PERIPH_TO_MEMORY 0x00000000U |
| #define | DMA_MEMORY_TO_PERIPH DMA_CCR_DIR |
| #define | DMA_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM |
| #define | DMA_PINC_ENABLE DMA_CCR_PINC |
| #define | DMA_PINC_DISABLE 0x00000000U |
| #define | DMA_MINC_ENABLE DMA_CCR_MINC |
| #define | DMA_MINC_DISABLE 0x00000000U |
| #define | DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) |
| #define | DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) |
| #define | DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) |
| #define | DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) |
| #define | DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) |
| #define | DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) |
| #define | DMA_NORMAL ((uint32_t)0x00000000) |
| #define | DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) |
| #define | DMA_PRIORITY_LOW ((uint32_t)0x00000000) |
| #define | DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) |
| #define | DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) |
| #define | DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) |
| #define | DMA_IT_TC ((uint32_t)DMA_CCR_TCIE) |
| #define | DMA_IT_HT ((uint32_t)DMA_CCR_HTIE) |
| #define | DMA_IT_TE ((uint32_t)DMA_CCR_TEIE) |
| #define | DMA_FLAG_GL1 ((uint32_t)0x00000001) |
| #define | DMA_FLAG_TC1 ((uint32_t)0x00000002) |
| #define | DMA_FLAG_HT1 ((uint32_t)0x00000004) |
| #define | DMA_FLAG_TE1 ((uint32_t)0x00000008) |
| #define | DMA_FLAG_GL2 ((uint32_t)0x00000010) |
| #define | DMA_FLAG_TC2 ((uint32_t)0x00000020) |
| #define | DMA_FLAG_HT2 ((uint32_t)0x00000040) |
| #define | DMA_FLAG_TE2 ((uint32_t)0x00000080) |
| #define | DMA_FLAG_GL3 ((uint32_t)0x00000100) |
| #define | DMA_FLAG_TC3 ((uint32_t)0x00000200) |
| #define | DMA_FLAG_HT3 ((uint32_t)0x00000400) |
| #define | DMA_FLAG_TE3 ((uint32_t)0x00000800) |
| #define | DMA_FLAG_GL4 ((uint32_t)0x00001000) |
| #define | DMA_FLAG_TC4 ((uint32_t)0x00002000) |
| #define | DMA_FLAG_HT4 ((uint32_t)0x00004000) |
| #define | DMA_FLAG_TE4 ((uint32_t)0x00008000) |
| #define | DMA_FLAG_GL5 ((uint32_t)0x00010000) |
| #define | DMA_FLAG_TC5 ((uint32_t)0x00020000) |
| #define | DMA_FLAG_HT5 ((uint32_t)0x00040000) |
| #define | DMA_FLAG_TE5 ((uint32_t)0x00080000) |
| #define | DMA_FLAG_GL6 ((uint32_t)0x00100000) |
| #define | DMA_FLAG_TC6 ((uint32_t)0x00200000) |
| #define | DMA_FLAG_HT6 ((uint32_t)0x00400000) |
| #define | DMA_FLAG_TE6 ((uint32_t)0x00800000) |
| #define | DMA_FLAG_GL7 ((uint32_t)0x01000000) |
| #define | DMA_FLAG_TC7 ((uint32_t)0x02000000) |
| #define | DMA_FLAG_HT7 ((uint32_t)0x04000000) |
| #define | DMA_FLAG_TE7 ((uint32_t)0x08000000) |
| #define | __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET) |
| Reset DMA handle state. | |
| #define | __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN) |
| Enable the specified DMA Channel. | |
| #define | __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN) |
| Disable the specified DMA Channel. | |
| #define | __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) |
| Return the current DMA Channel transfer complete flag. | |
| #define | __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__) |
| Return the current DMA Channel half transfer complete flag. | |
| #define | __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__) |
| Return the current DMA Channel transfer error flag. | |
| #define | __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__) |
| Return the current DMA Channel Global interrupt flag. | |
| #define | __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) |
| Get the DMA Channel pending flags. | |
| #define | __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) |
| Clear the DMA Channel pending flags. | |
| #define | __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__)) |
| Enable the specified DMA Channel interrupts. | |
| #define | __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__)) |
| Disable the specified DMA Channel interrupts. | |
| #define | __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CCR & (__INTERRUPT__))) |
| Check whether the specified DMA Channel interrupt is enabled or not. | |
| #define | __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNDTR) |
| Return the number of remaining data units in the current DMA Channel transfer. | |
| #define | IS_DMA_DIRECTION(DIRECTION) |
| #define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1U) && ((SIZE) < 0x10000U)) |
| #define | IS_DMA_PERIPHERAL_INC_STATE(STATE) |
| #define | IS_DMA_MEMORY_INC_STATE(STATE) |
| #define | IS_DMA_ALL_REQUEST(REQUEST) |
| #define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) |
| #define | IS_DMA_MEMORY_DATA_SIZE(SIZE) |
| #define | IS_DMA_MODE(MODE) |
| #define | IS_DMA_PRIORITY(PRIORITY) |
Typedefs | |
| typedef struct __DMA_HandleTypeDef | DMA_HandleTypeDef |
| DMA handle Structure definition. | |
Enumerations | |
| enum | HAL_DMA_StateTypeDef { HAL_DMA_STATE_RESET = 0x00U, HAL_DMA_STATE_READY = 0x01U, HAL_DMA_STATE_BUSY = 0x02U, HAL_DMA_STATE_TIMEOUT = 0x03U } |
| HAL DMA State structures definition. More... | |
| enum | HAL_DMA_LevelCompleteTypeDef { HAL_DMA_FULL_TRANSFER = 0x00U, HAL_DMA_HALF_TRANSFER = 0x01U } |
| HAL DMA Error Code structure definition. More... | |
| enum | HAL_DMA_CallbackIDTypeDef { HAL_DMA_XFER_CPLT_CB_ID = 0x00U, HAL_DMA_XFER_HALFCPLT_CB_ID = 0x01U, HAL_DMA_XFER_ERROR_CB_ID = 0x02U, HAL_DMA_XFER_ABORT_CB_ID = 0x03U, HAL_DMA_XFER_ALL_CB_ID = 0x04U } |
| HAL DMA Callback ID structure definition. More... | |
Functions | |
| HAL_StatusTypeDef | HAL_DMA_Init (DMA_HandleTypeDef *hdma) |
| Initialize the DMA according to the specified parameters in the DMA_InitTypeDef and initialize the associated handle. | |
| HAL_StatusTypeDef | HAL_DMA_DeInit (DMA_HandleTypeDef *hdma) |
| DeInitialize the DMA peripheral. | |
| HAL_StatusTypeDef | HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
| Start the DMA Transfer. | |
| HAL_StatusTypeDef | HAL_DMA_Start_IT (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) |
| Start the DMA Transfer with interrupt enabled. | |
| HAL_StatusTypeDef | HAL_DMA_Abort (DMA_HandleTypeDef *hdma) |
| Abort the DMA Transfer. | |
| HAL_StatusTypeDef | HAL_DMA_Abort_IT (DMA_HandleTypeDef *hdma) |
| Aborts the DMA Transfer in Interrupt mode. | |
| HAL_StatusTypeDef | HAL_DMA_PollForTransfer (DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) |
| Polling for transfer complete. | |
| void | HAL_DMA_IRQHandler (DMA_HandleTypeDef *hdma) |
| Handle DMA interrupt request. | |
| HAL_StatusTypeDef | HAL_DMA_RegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void(*pCallback)(DMA_HandleTypeDef *_hdma)) |
| Register callbacks. | |
| HAL_StatusTypeDef | HAL_DMA_UnRegisterCallback (DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) |
| UnRegister callbacks. | |
| HAL_DMA_StateTypeDef | HAL_DMA_GetState (DMA_HandleTypeDef *hdma) |
| Return the DMA hande state. | |
| uint32_t | HAL_DMA_GetError (DMA_HandleTypeDef *hdma) |
| Return the DMA error code. | |
Header file of DMA HAL module.
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Definition in file stm32l4xx_hal_dma.h.
1.7.6.1