STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dfsdm.h 00004 * @author MCD Application Team 00005 * @brief Header file of DFSDM HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef STM32L4xx_HAL_DFSDM_H 00038 #define STM32L4xx_HAL_DFSDM_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 00045 defined(STM32L471xx) || defined(STM32L475xx) || defined(STM32L476xx) || defined(STM32L485xx) || defined(STM32L486xx) || \ 00046 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 00047 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00048 00049 /* Includes ------------------------------------------------------------------*/ 00050 #include "stm32l4xx_hal_def.h" 00051 00052 /** @addtogroup STM32L4xx_HAL_Driver 00053 * @{ 00054 */ 00055 00056 /** @addtogroup DFSDM 00057 * @{ 00058 */ 00059 00060 /* Exported types ------------------------------------------------------------*/ 00061 /** @defgroup DFSDM_Exported_Types DFSDM Exported Types 00062 * @{ 00063 */ 00064 00065 /** 00066 * @brief HAL DFSDM Channel states definition 00067 */ 00068 typedef enum 00069 { 00070 HAL_DFSDM_CHANNEL_STATE_RESET = 0x00U, /*!< DFSDM channel not initialized */ 00071 HAL_DFSDM_CHANNEL_STATE_READY = 0x01U, /*!< DFSDM channel initialized and ready for use */ 00072 HAL_DFSDM_CHANNEL_STATE_ERROR = 0xFFU /*!< DFSDM channel state error */ 00073 } HAL_DFSDM_Channel_StateTypeDef; 00074 00075 /** 00076 * @brief DFSDM channel output clock structure definition 00077 */ 00078 typedef struct 00079 { 00080 FunctionalState Activation; /*!< Output clock enable/disable */ 00081 uint32_t Selection; /*!< Output clock is system clock or audio clock. 00082 This parameter can be a value of @ref DFSDM_Channel_OuputClock */ 00083 uint32_t Divider; /*!< Output clock divider. 00084 This parameter must be a number between Min_Data = 2 and Max_Data = 256 */ 00085 } DFSDM_Channel_OutputClockTypeDef; 00086 00087 /** 00088 * @brief DFSDM channel input structure definition 00089 */ 00090 typedef struct 00091 { 00092 uint32_t Multiplexer; /*!< Input is external serial inputs, internal register or ADC output. 00093 ADC output is available only on STM32L451xx, STM32L452xx, STM32L462xx, 00094 STM32L496xx, STM32L4A6xx, STM32L4R5xx, STM32L4R7xx, STM32L4R9xx, 00095 STM32L4S5xx, STM32L4S7xx and STM32L4S9xx products. 00096 This parameter can be a value of @ref DFSDM_Channel_InputMultiplexer */ 00097 uint32_t DataPacking; /*!< Standard, interleaved or dual mode for internal register. 00098 This parameter can be a value of @ref DFSDM_Channel_DataPacking */ 00099 uint32_t Pins; /*!< Input pins are taken from same or following channel. 00100 This parameter can be a value of @ref DFSDM_Channel_InputPins */ 00101 } DFSDM_Channel_InputTypeDef; 00102 00103 /** 00104 * @brief DFSDM channel serial interface structure definition 00105 */ 00106 typedef struct 00107 { 00108 uint32_t Type; /*!< SPI or Manchester modes. 00109 This parameter can be a value of @ref DFSDM_Channel_SerialInterfaceType */ 00110 uint32_t SpiClock; /*!< SPI clock select (external or internal with different sampling point). 00111 This parameter can be a value of @ref DFSDM_Channel_SpiClock */ 00112 } DFSDM_Channel_SerialInterfaceTypeDef; 00113 00114 /** 00115 * @brief DFSDM channel analog watchdog structure definition 00116 */ 00117 typedef struct 00118 { 00119 uint32_t FilterOrder; /*!< Analog watchdog Sinc filter order. 00120 This parameter can be a value of @ref DFSDM_Channel_AwdFilterOrder */ 00121 uint32_t Oversampling; /*!< Analog watchdog filter oversampling ratio. 00122 This parameter must be a number between Min_Data = 1 and Max_Data = 32 */ 00123 } DFSDM_Channel_AwdTypeDef; 00124 00125 /** 00126 * @brief DFSDM channel init structure definition 00127 */ 00128 typedef struct 00129 { 00130 DFSDM_Channel_OutputClockTypeDef OutputClock; /*!< DFSDM channel output clock parameters */ 00131 DFSDM_Channel_InputTypeDef Input; /*!< DFSDM channel input parameters */ 00132 DFSDM_Channel_SerialInterfaceTypeDef SerialInterface; /*!< DFSDM channel serial interface parameters */ 00133 DFSDM_Channel_AwdTypeDef Awd; /*!< DFSDM channel analog watchdog parameters */ 00134 int32_t Offset; /*!< DFSDM channel offset. 00135 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00136 uint32_t RightBitShift; /*!< DFSDM channel right bit shift. 00137 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */ 00138 } DFSDM_Channel_InitTypeDef; 00139 00140 /** 00141 * @brief DFSDM channel handle structure definition 00142 */ 00143 typedef struct __DFSDM_Channel_HandleTypeDef 00144 { 00145 DFSDM_Channel_TypeDef *Instance; /*!< DFSDM channel instance */ 00146 DFSDM_Channel_InitTypeDef Init; /*!< DFSDM channel init parameters */ 00147 HAL_DFSDM_Channel_StateTypeDef State; /*!< DFSDM channel state */ 00148 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00149 void (*CkabCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel clock absence detection callback */ 00150 void (*ScdCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel short circuit detection callback */ 00151 void (*MspInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP init callback */ 00152 void (*MspDeInitCallback)(struct __DFSDM_Channel_HandleTypeDef *hdfsdm_channel); /*!< DFSDM channel MSP de-init callback */ 00153 #endif 00154 } DFSDM_Channel_HandleTypeDef; 00155 00156 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00157 /** 00158 * @brief DFSDM channel callback ID enumeration definition 00159 */ 00160 typedef enum 00161 { 00162 HAL_DFSDM_CHANNEL_CKAB_CB_ID = 0x00U, /*!< DFSDM channel clock absence detection callback ID */ 00163 HAL_DFSDM_CHANNEL_SCD_CB_ID = 0x01U, /*!< DFSDM channel short circuit detection callback ID */ 00164 HAL_DFSDM_CHANNEL_MSPINIT_CB_ID = 0x02U, /*!< DFSDM channel MSP init callback ID */ 00165 HAL_DFSDM_CHANNEL_MSPDEINIT_CB_ID = 0x03U /*!< DFSDM channel MSP de-init callback ID */ 00166 } HAL_DFSDM_Channel_CallbackIDTypeDef; 00167 00168 /** 00169 * @brief DFSDM channel callback pointer definition 00170 */ 00171 typedef void (*pDFSDM_Channel_CallbackTypeDef)(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00172 #endif 00173 00174 /** 00175 * @brief HAL DFSDM Filter states definition 00176 */ 00177 typedef enum 00178 { 00179 HAL_DFSDM_FILTER_STATE_RESET = 0x00U, /*!< DFSDM filter not initialized */ 00180 HAL_DFSDM_FILTER_STATE_READY = 0x01U, /*!< DFSDM filter initialized and ready for use */ 00181 HAL_DFSDM_FILTER_STATE_REG = 0x02U, /*!< DFSDM filter regular conversion in progress */ 00182 HAL_DFSDM_FILTER_STATE_INJ = 0x03U, /*!< DFSDM filter injected conversion in progress */ 00183 HAL_DFSDM_FILTER_STATE_REG_INJ = 0x04U, /*!< DFSDM filter regular and injected conversions in progress */ 00184 HAL_DFSDM_FILTER_STATE_ERROR = 0xFFU /*!< DFSDM filter state error */ 00185 } HAL_DFSDM_Filter_StateTypeDef; 00186 00187 /** 00188 * @brief DFSDM filter regular conversion parameters structure definition 00189 */ 00190 typedef struct 00191 { 00192 uint32_t Trigger; /*!< Trigger used to start regular conversion: software or synchronous. 00193 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 00194 FunctionalState FastMode; /*!< Enable/disable fast mode for regular conversion */ 00195 FunctionalState DmaMode; /*!< Enable/disable DMA for regular conversion */ 00196 } DFSDM_Filter_RegularParamTypeDef; 00197 00198 /** 00199 * @brief DFSDM filter injected conversion parameters structure definition 00200 */ 00201 typedef struct 00202 { 00203 uint32_t Trigger; /*!< Trigger used to start injected conversion: software, external or synchronous. 00204 This parameter can be a value of @ref DFSDM_Filter_Trigger */ 00205 FunctionalState ScanMode; /*!< Enable/disable scanning mode for injected conversion */ 00206 FunctionalState DmaMode; /*!< Enable/disable DMA for injected conversion */ 00207 uint32_t ExtTrigger; /*!< External trigger. 00208 This parameter can be a value of @ref DFSDM_Filter_ExtTrigger */ 00209 uint32_t ExtTriggerEdge; /*!< External trigger edge: rising, falling or both. 00210 This parameter can be a value of @ref DFSDM_Filter_ExtTriggerEdge */ 00211 } DFSDM_Filter_InjectedParamTypeDef; 00212 00213 /** 00214 * @brief DFSDM filter parameters structure definition 00215 */ 00216 typedef struct 00217 { 00218 uint32_t SincOrder; /*!< Sinc filter order. 00219 This parameter can be a value of @ref DFSDM_Filter_SincOrder */ 00220 uint32_t Oversampling; /*!< Filter oversampling ratio. 00221 This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */ 00222 uint32_t IntOversampling; /*!< Integrator oversampling ratio. 00223 This parameter must be a number between Min_Data = 1 and Max_Data = 256 */ 00224 } DFSDM_Filter_FilterParamTypeDef; 00225 00226 /** 00227 * @brief DFSDM filter init structure definition 00228 */ 00229 typedef struct 00230 { 00231 DFSDM_Filter_RegularParamTypeDef RegularParam; /*!< DFSDM regular conversion parameters */ 00232 DFSDM_Filter_InjectedParamTypeDef InjectedParam; /*!< DFSDM injected conversion parameters */ 00233 DFSDM_Filter_FilterParamTypeDef FilterParam; /*!< DFSDM filter parameters */ 00234 } DFSDM_Filter_InitTypeDef; 00235 00236 /** 00237 * @brief DFSDM filter handle structure definition 00238 */ 00239 typedef struct __DFSDM_Filter_HandleTypeDef 00240 { 00241 DFSDM_Filter_TypeDef *Instance; /*!< DFSDM filter instance */ 00242 DFSDM_Filter_InitTypeDef Init; /*!< DFSDM filter init parameters */ 00243 DMA_HandleTypeDef *hdmaReg; /*!< Pointer on DMA handler for regular conversions */ 00244 DMA_HandleTypeDef *hdmaInj; /*!< Pointer on DMA handler for injected conversions */ 00245 uint32_t RegularContMode; /*!< Regular conversion continuous mode */ 00246 uint32_t RegularTrigger; /*!< Trigger used for regular conversion */ 00247 uint32_t InjectedTrigger; /*!< Trigger used for injected conversion */ 00248 uint32_t ExtTriggerEdge; /*!< Rising, falling or both edges selected */ 00249 FunctionalState InjectedScanMode; /*!< Injected scanning mode */ 00250 uint32_t InjectedChannelsNbr; /*!< Number of channels in injected sequence */ 00251 uint32_t InjConvRemaining; /*!< Injected conversions remaining */ 00252 HAL_DFSDM_Filter_StateTypeDef State; /*!< DFSDM filter state */ 00253 uint32_t ErrorCode; /*!< DFSDM filter error code */ 00254 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00255 void (*AwdCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00256 uint32_t Channel, uint32_t Threshold); /*!< DFSDM filter analog watchdog callback */ 00257 void (*RegConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter regular conversion complete callback */ 00258 void (*RegConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half regular conversion complete callback */ 00259 void (*InjConvCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter injected conversion complete callback */ 00260 void (*InjConvHalfCpltCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter half injected conversion complete callback */ 00261 void (*ErrorCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter error callback */ 00262 void (*MspInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP init callback */ 00263 void (*MspDeInitCallback)(struct __DFSDM_Filter_HandleTypeDef *hdfsdm_filter); /*!< DFSDM filter MSP de-init callback */ 00264 #endif 00265 } DFSDM_Filter_HandleTypeDef; 00266 00267 /** 00268 * @brief DFSDM filter analog watchdog parameters structure definition 00269 */ 00270 typedef struct 00271 { 00272 uint32_t DataSource; /*!< Values from digital filter or from channel watchdog filter. 00273 This parameter can be a value of @ref DFSDM_Filter_AwdDataSource */ 00274 uint32_t Channel; /*!< Analog watchdog channel selection. 00275 This parameter can be a values combination of @ref DFSDM_Channel_Selection */ 00276 int32_t HighThreshold; /*!< High threshold for the analog watchdog. 00277 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00278 int32_t LowThreshold; /*!< Low threshold for the analog watchdog. 00279 This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607 */ 00280 uint32_t HighBreakSignal; /*!< Break signal assigned to analog watchdog high threshold event. 00281 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 00282 uint32_t LowBreakSignal; /*!< Break signal assigned to analog watchdog low threshold event. 00283 This parameter can be a values combination of @ref DFSDM_BreakSignals */ 00284 } DFSDM_Filter_AwdParamTypeDef; 00285 00286 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00287 /** 00288 * @brief DFSDM filter callback ID enumeration definition 00289 */ 00290 typedef enum 00291 { 00292 HAL_DFSDM_FILTER_REGCONV_COMPLETE_CB_ID = 0x00U, /*!< DFSDM filter regular conversion complete callback ID */ 00293 HAL_DFSDM_FILTER_REGCONV_HALFCOMPLETE_CB_ID = 0x01U, /*!< DFSDM filter half regular conversion complete callback ID */ 00294 HAL_DFSDM_FILTER_INJCONV_COMPLETE_CB_ID = 0x02U, /*!< DFSDM filter injected conversion complete callback ID */ 00295 HAL_DFSDM_FILTER_INJCONV_HALFCOMPLETE_CB_ID = 0x03U, /*!< DFSDM filter half injected conversion complete callback ID */ 00296 HAL_DFSDM_FILTER_ERROR_CB_ID = 0x04U, /*!< DFSDM filter error callback ID */ 00297 HAL_DFSDM_FILTER_MSPINIT_CB_ID = 0x05U, /*!< DFSDM filter MSP init callback ID */ 00298 HAL_DFSDM_FILTER_MSPDEINIT_CB_ID = 0x06U /*!< DFSDM filter MSP de-init callback ID */ 00299 } HAL_DFSDM_Filter_CallbackIDTypeDef; 00300 00301 /** 00302 * @brief DFSDM filter callback pointer definition 00303 */ 00304 typedef void (*pDFSDM_Filter_CallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00305 typedef void (*pDFSDM_Filter_AwdCallbackTypeDef)(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 00306 #endif 00307 00308 /** 00309 * @} 00310 */ 00311 /* End of exported types -----------------------------------------------------*/ 00312 00313 /* Exported constants --------------------------------------------------------*/ 00314 /** @defgroup DFSDM_Exported_Constants DFSDM Exported Constants 00315 * @{ 00316 */ 00317 00318 /** @defgroup DFSDM_Channel_OuputClock DFSDM channel output clock selection 00319 * @{ 00320 */ 00321 #define DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM 0x00000000U /*!< Source for ouput clock is system clock */ 00322 #define DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO DFSDM_CHCFGR1_CKOUTSRC /*!< Source for ouput clock is audio clock */ 00323 /** 00324 * @} 00325 */ 00326 00327 /** @defgroup DFSDM_Channel_InputMultiplexer DFSDM channel input multiplexer 00328 * @{ 00329 */ 00330 #define DFSDM_CHANNEL_EXTERNAL_INPUTS 0x00000000U /*!< Data are taken from external inputs */ 00331 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 00332 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 00333 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00334 #define DFSDM_CHANNEL_ADC_OUTPUT DFSDM_CHCFGR1_DATMPX_0 /*!< Data are taken from ADC output */ 00335 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || STM32L496xx || STM32L4A6xx || STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00336 #define DFSDM_CHANNEL_INTERNAL_REGISTER DFSDM_CHCFGR1_DATMPX_1 /*!< Data are taken from internal register */ 00337 /** 00338 * @} 00339 */ 00340 00341 /** @defgroup DFSDM_Channel_DataPacking DFSDM channel input data packing 00342 * @{ 00343 */ 00344 #define DFSDM_CHANNEL_STANDARD_MODE 0x00000000U /*!< Standard data packing mode */ 00345 #define DFSDM_CHANNEL_INTERLEAVED_MODE DFSDM_CHCFGR1_DATPACK_0 /*!< Interleaved data packing mode */ 00346 #define DFSDM_CHANNEL_DUAL_MODE DFSDM_CHCFGR1_DATPACK_1 /*!< Dual data packing mode */ 00347 /** 00348 * @} 00349 */ 00350 00351 /** @defgroup DFSDM_Channel_InputPins DFSDM channel input pins 00352 * @{ 00353 */ 00354 #define DFSDM_CHANNEL_SAME_CHANNEL_PINS 0x00000000U /*!< Input from pins on same channel */ 00355 #define DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS DFSDM_CHCFGR1_CHINSEL /*!< Input from pins on following channel */ 00356 /** 00357 * @} 00358 */ 00359 00360 /** @defgroup DFSDM_Channel_SerialInterfaceType DFSDM channel serial interface type 00361 * @{ 00362 */ 00363 #define DFSDM_CHANNEL_SPI_RISING 0x00000000U /*!< SPI with rising edge */ 00364 #define DFSDM_CHANNEL_SPI_FALLING DFSDM_CHCFGR1_SITP_0 /*!< SPI with falling edge */ 00365 #define DFSDM_CHANNEL_MANCHESTER_RISING DFSDM_CHCFGR1_SITP_1 /*!< Manchester with rising edge */ 00366 #define DFSDM_CHANNEL_MANCHESTER_FALLING DFSDM_CHCFGR1_SITP /*!< Manchester with falling edge */ 00367 /** 00368 * @} 00369 */ 00370 00371 /** @defgroup DFSDM_Channel_SpiClock DFSDM channel SPI clock selection 00372 * @{ 00373 */ 00374 #define DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL 0x00000000U /*!< External SPI clock */ 00375 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL DFSDM_CHCFGR1_SPICKSEL_0 /*!< Internal SPI clock */ 00376 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING DFSDM_CHCFGR1_SPICKSEL_1 /*!< Internal SPI clock divided by 2, falling edge */ 00377 #define DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING DFSDM_CHCFGR1_SPICKSEL /*!< Internal SPI clock divided by 2, rising edge */ 00378 /** 00379 * @} 00380 */ 00381 00382 /** @defgroup DFSDM_Channel_AwdFilterOrder DFSDM channel analog watchdog filter order 00383 * @{ 00384 */ 00385 #define DFSDM_CHANNEL_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 00386 #define DFSDM_CHANNEL_SINC1_ORDER DFSDM_CHAWSCDR_AWFORD_0 /*!< Sinc 1 filter type */ 00387 #define DFSDM_CHANNEL_SINC2_ORDER DFSDM_CHAWSCDR_AWFORD_1 /*!< Sinc 2 filter type */ 00388 #define DFSDM_CHANNEL_SINC3_ORDER DFSDM_CHAWSCDR_AWFORD /*!< Sinc 3 filter type */ 00389 /** 00390 * @} 00391 */ 00392 00393 /** @defgroup DFSDM_Filter_Trigger DFSDM filter conversion trigger 00394 * @{ 00395 */ 00396 #define DFSDM_FILTER_SW_TRIGGER 0x00000000U /*!< Software trigger */ 00397 #define DFSDM_FILTER_SYNC_TRIGGER 0x00000001U /*!< Synchronous with DFSDM_FLT0 */ 00398 #define DFSDM_FILTER_EXT_TRIGGER 0x00000002U /*!< External trigger (only for injected conversion) */ 00399 /** 00400 * @} 00401 */ 00402 00403 /** @defgroup DFSDM_Filter_ExtTrigger DFSDM filter external trigger 00404 * @{ 00405 */ 00406 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 00407 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ 00408 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ 00409 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ 00410 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ 00411 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ 00412 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 00413 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ 00414 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00415 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For all DFSDM filters */ 00416 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For all DFSDM filters */ 00417 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For all DFSDM filters */ 00418 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For all DFSDM filters */ 00419 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For all DFSDM filters */ 00420 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 00421 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 00422 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1 | \ 00423 DFSDM_FLTCR1_JEXTSEL_2) /*!< For all DFSDM filters */ 00424 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO DFSDM_FLTCR1_JEXTSEL_3 /*!< For all DFSDM filters */ 00425 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_3 | DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 00426 #define DFSDM_FILTER_EXT_TRIG_EXTI15 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_3 | \ 00427 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 00428 #define DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_3 | \ 00429 DFSDM_FLTCR1_JEXTSEL_4) /*!< For all DFSDM filters */ 00430 #else 00431 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO 0x00000000U /*!< For DFSDM filter 0, 1, 2 and 3 */ 00432 #define DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2 DFSDM_FLTCR1_JEXTSEL_0 /*!< For DFSDM filter 0, 1, 2 and 3 */ 00433 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO DFSDM_FLTCR1_JEXTSEL_1 /*!< For DFSDM filter 0, 1, 2 and 3 */ 00434 #define DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2 (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 0, 1 and 2 */ 00435 #define DFSDM_FILTER_EXT_TRIG_TIM3_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_1) /*!< For DFSDM filter 3 */ 00436 #define DFSDM_FILTER_EXT_TRIG_TIM4_TRGO DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 0, 1 and 2 */ 00437 #define DFSDM_FILTER_EXT_TRIG_TIM16_OC1 DFSDM_FLTCR1_JEXTSEL_2 /*!< For DFSDM filter 3 */ 00438 #define DFSDM_FILTER_EXT_TRIG_TIM6_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0 and 1 */ 00439 #define DFSDM_FILTER_EXT_TRIG_TIM7_TRGO (DFSDM_FLTCR1_JEXTSEL_0 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 2 and 3 */ 00440 #define DFSDM_FILTER_EXT_TRIG_EXTI11 (DFSDM_FLTCR1_JEXTSEL_1 | DFSDM_FLTCR1_JEXTSEL_2) /*!< For DFSDM filter 0, 1, 2 and 3 */ 00441 #define DFSDM_FILTER_EXT_TRIG_EXTI15 DFSDM_FLTCR1_JEXTSEL /*!< For DFSDM filter 0, 1, 2 and 3 */ 00442 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 00443 /** 00444 * @} 00445 */ 00446 00447 /** @defgroup DFSDM_Filter_ExtTriggerEdge DFSDM filter external trigger edge 00448 * @{ 00449 */ 00450 #define DFSDM_FILTER_EXT_TRIG_RISING_EDGE DFSDM_FLTCR1_JEXTEN_0 /*!< External rising edge */ 00451 #define DFSDM_FILTER_EXT_TRIG_FALLING_EDGE DFSDM_FLTCR1_JEXTEN_1 /*!< External falling edge */ 00452 #define DFSDM_FILTER_EXT_TRIG_BOTH_EDGES DFSDM_FLTCR1_JEXTEN /*!< External rising and falling edges */ 00453 /** 00454 * @} 00455 */ 00456 00457 /** @defgroup DFSDM_Filter_SincOrder DFSDM filter sinc order 00458 * @{ 00459 */ 00460 #define DFSDM_FILTER_FASTSINC_ORDER 0x00000000U /*!< FastSinc filter type */ 00461 #define DFSDM_FILTER_SINC1_ORDER DFSDM_FLTFCR_FORD_0 /*!< Sinc 1 filter type */ 00462 #define DFSDM_FILTER_SINC2_ORDER DFSDM_FLTFCR_FORD_1 /*!< Sinc 2 filter type */ 00463 #define DFSDM_FILTER_SINC3_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_1) /*!< Sinc 3 filter type */ 00464 #define DFSDM_FILTER_SINC4_ORDER DFSDM_FLTFCR_FORD_2 /*!< Sinc 4 filter type */ 00465 #define DFSDM_FILTER_SINC5_ORDER (DFSDM_FLTFCR_FORD_0 | DFSDM_FLTFCR_FORD_2) /*!< Sinc 5 filter type */ 00466 /** 00467 * @} 00468 */ 00469 00470 /** @defgroup DFSDM_Filter_AwdDataSource DFSDM filter analog watchdog data source 00471 * @{ 00472 */ 00473 #define DFSDM_FILTER_AWD_FILTER_DATA 0x00000000U /*!< From digital filter */ 00474 #define DFSDM_FILTER_AWD_CHANNEL_DATA DFSDM_FLTCR1_AWFSEL /*!< From analog watchdog channel */ 00475 /** 00476 * @} 00477 */ 00478 00479 /** @defgroup DFSDM_Filter_ErrorCode DFSDM filter error code 00480 * @{ 00481 */ 00482 #define DFSDM_FILTER_ERROR_NONE 0x00000000U /*!< No error */ 00483 #define DFSDM_FILTER_ERROR_REGULAR_OVERRUN 0x00000001U /*!< Overrun occurs during regular conversion */ 00484 #define DFSDM_FILTER_ERROR_INJECTED_OVERRUN 0x00000002U /*!< Overrun occurs during injected conversion */ 00485 #define DFSDM_FILTER_ERROR_DMA 0x00000003U /*!< DMA error occurs */ 00486 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00487 #define DFSDM_FILTER_ERROR_INVALID_CALLBACK 0x00000004U /*!< Invalid callback error occurs */ 00488 #endif 00489 /** 00490 * @} 00491 */ 00492 00493 /** @defgroup DFSDM_BreakSignals DFSDM break signals 00494 * @{ 00495 */ 00496 #define DFSDM_NO_BREAK_SIGNAL 0x00000000U /*!< No break signal */ 00497 #define DFSDM_BREAK_SIGNAL_0 0x00000001U /*!< Break signal 0 */ 00498 #define DFSDM_BREAK_SIGNAL_1 0x00000002U /*!< Break signal 1 */ 00499 #define DFSDM_BREAK_SIGNAL_2 0x00000004U /*!< Break signal 2 */ 00500 #define DFSDM_BREAK_SIGNAL_3 0x00000008U /*!< Break signal 3 */ 00501 /** 00502 * @} 00503 */ 00504 00505 /** @defgroup DFSDM_Channel_Selection DFSDM Channel Selection 00506 * @{ 00507 */ 00508 /* DFSDM Channels ------------------------------------------------------------*/ 00509 /* The DFSDM channels are defined as follows: 00510 - in 16-bit LSB the channel mask is set 00511 - in 16-bit MSB the channel number is set 00512 e.g. for channel 5 definition: 00513 - the channel mask is 0x00000020 (bit 5 is set) 00514 - the channel number 5 is 0x00050000 00515 --> Consequently, channel 5 definition is 0x00000020 | 0x00050000 = 0x00050020 */ 00516 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 00517 #define DFSDM_CHANNEL_0 0x00000001U 00518 #define DFSDM_CHANNEL_1 0x00010002U 00519 #define DFSDM_CHANNEL_2 0x00020004U 00520 #define DFSDM_CHANNEL_3 0x00030008U 00521 #else 00522 #define DFSDM_CHANNEL_0 0x00000001U 00523 #define DFSDM_CHANNEL_1 0x00010002U 00524 #define DFSDM_CHANNEL_2 0x00020004U 00525 #define DFSDM_CHANNEL_3 0x00030008U 00526 #define DFSDM_CHANNEL_4 0x00040010U 00527 #define DFSDM_CHANNEL_5 0x00050020U 00528 #define DFSDM_CHANNEL_6 0x00060040U 00529 #define DFSDM_CHANNEL_7 0x00070080U 00530 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 00531 /** 00532 * @} 00533 */ 00534 00535 /** @defgroup DFSDM_ContinuousMode DFSDM Continuous Mode 00536 * @{ 00537 */ 00538 #define DFSDM_CONTINUOUS_CONV_OFF 0x00000000U /*!< Conversion are not continuous */ 00539 #define DFSDM_CONTINUOUS_CONV_ON 0x00000001U /*!< Conversion are continuous */ 00540 /** 00541 * @} 00542 */ 00543 00544 /** @defgroup DFSDM_AwdThreshold DFSDM analog watchdog threshold 00545 * @{ 00546 */ 00547 #define DFSDM_AWD_HIGH_THRESHOLD 0x00000000U /*!< Analog watchdog high threshold */ 00548 #define DFSDM_AWD_LOW_THRESHOLD 0x00000001U /*!< Analog watchdog low threshold */ 00549 /** 00550 * @} 00551 */ 00552 00553 /** 00554 * @} 00555 */ 00556 /* End of exported constants -------------------------------------------------*/ 00557 00558 /* Exported macros -----------------------------------------------------------*/ 00559 /** @defgroup DFSDM_Exported_Macros DFSDM Exported Macros 00560 * @{ 00561 */ 00562 00563 /** @brief Reset DFSDM channel handle state. 00564 * @param __HANDLE__ DFSDM channel handle. 00565 * @retval None 00566 */ 00567 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00568 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00569 (__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET; \ 00570 (__HANDLE__)->MspInitCallback = NULL; \ 00571 (__HANDLE__)->MspDeInitCallback = NULL; \ 00572 } while(0) 00573 #else 00574 #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) 00575 #endif 00576 00577 /** @brief Reset DFSDM filter handle state. 00578 * @param __HANDLE__ DFSDM filter handle. 00579 * @retval None 00580 */ 00581 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00582 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00583 (__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET; \ 00584 (__HANDLE__)->MspInitCallback = NULL; \ 00585 (__HANDLE__)->MspDeInitCallback = NULL; \ 00586 } while(0) 00587 #else 00588 #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET) 00589 #endif 00590 00591 /** 00592 * @} 00593 */ 00594 /* End of exported macros ----------------------------------------------------*/ 00595 00596 #if defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00597 /* Include DFSDM HAL Extension module */ 00598 #include "stm32l4xx_hal_dfsdm_ex.h" 00599 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00600 00601 /* Exported functions --------------------------------------------------------*/ 00602 /** @addtogroup DFSDM_Exported_Functions DFSDM Exported Functions 00603 * @{ 00604 */ 00605 00606 /** @addtogroup DFSDM_Exported_Functions_Group1_Channel Channel initialization and de-initialization functions 00607 * @{ 00608 */ 00609 /* Channel initialization and de-initialization functions *********************/ 00610 HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00611 HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00612 void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00613 void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00614 00615 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00616 /* Channel callbacks register/unregister functions ****************************/ 00617 HAL_StatusTypeDef HAL_DFSDM_Channel_RegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 00618 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID, 00619 pDFSDM_Channel_CallbackTypeDef pCallback); 00620 HAL_StatusTypeDef HAL_DFSDM_Channel_UnRegisterCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, 00621 HAL_DFSDM_Channel_CallbackIDTypeDef CallbackID); 00622 #endif 00623 /** 00624 * @} 00625 */ 00626 00627 /** @addtogroup DFSDM_Exported_Functions_Group2_Channel Channel operation functions 00628 * @{ 00629 */ 00630 /* Channel operation functions ************************************************/ 00631 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00632 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00633 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00634 HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00635 00636 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 00637 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Threshold, uint32_t BreakSignal); 00638 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00639 HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00640 00641 int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00642 HAL_StatusTypeDef HAL_DFSDM_ChannelModifyOffset(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, int32_t Offset); 00643 00644 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 00645 HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel, uint32_t Timeout); 00646 00647 void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00648 void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00649 /** 00650 * @} 00651 */ 00652 00653 /** @defgroup DFSDM_Exported_Functions_Group3_Channel Channel state function 00654 * @{ 00655 */ 00656 /* Channel state function *****************************************************/ 00657 HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel); 00658 /** 00659 * @} 00660 */ 00661 00662 /** @addtogroup DFSDM_Exported_Functions_Group1_Filter Filter initialization and de-initialization functions 00663 * @{ 00664 */ 00665 /* Filter initialization and de-initialization functions *********************/ 00666 HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00667 HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00668 void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00669 void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00670 00671 #if (USE_HAL_DFSDM_REGISTER_CALLBACKS == 1) 00672 /* Filter callbacks register/unregister functions ****************************/ 00673 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00674 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID, 00675 pDFSDM_Filter_CallbackTypeDef pCallback); 00676 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00677 HAL_DFSDM_Filter_CallbackIDTypeDef CallbackID); 00678 HAL_StatusTypeDef HAL_DFSDM_Filter_RegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00679 pDFSDM_Filter_AwdCallbackTypeDef pCallback); 00680 HAL_StatusTypeDef HAL_DFSDM_Filter_UnRegisterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00681 #endif 00682 /** 00683 * @} 00684 */ 00685 00686 /** @addtogroup DFSDM_Exported_Functions_Group2_Filter Filter control functions 00687 * @{ 00688 */ 00689 /* Filter control functions *********************/ 00690 HAL_StatusTypeDef HAL_DFSDM_FilterConfigRegChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00691 uint32_t Channel, 00692 uint32_t ContinuousMode); 00693 HAL_StatusTypeDef HAL_DFSDM_FilterConfigInjChannel(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00694 uint32_t Channel); 00695 /** 00696 * @} 00697 */ 00698 00699 /** @addtogroup DFSDM_Exported_Functions_Group3_Filter Filter operation functions 00700 * @{ 00701 */ 00702 /* Filter operation functions *********************/ 00703 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00704 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00705 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 00706 HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 00707 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00708 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00709 HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00710 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00711 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00712 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int32_t *pData, uint32_t Length); 00713 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, int16_t *pData, uint32_t Length); 00714 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00715 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00716 HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00717 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, 00718 DFSDM_Filter_AwdParamTypeDef *awdParam); 00719 HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00720 HAL_StatusTypeDef HAL_DFSDM_FilterExdStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel); 00721 HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00722 00723 int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 00724 int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 00725 int32_t HAL_DFSDM_FilterGetExdMaxValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 00726 int32_t HAL_DFSDM_FilterGetExdMinValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t *Channel); 00727 uint32_t HAL_DFSDM_FilterGetConvTimeValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00728 00729 void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00730 00731 HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 00732 HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Timeout); 00733 00734 void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00735 void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00736 void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00737 void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00738 void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter, uint32_t Channel, uint32_t Threshold); 00739 void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00740 /** 00741 * @} 00742 */ 00743 00744 /** @defgroup DFSDM_Exported_Functions_Group4_Filter Filter state functions 00745 * @{ 00746 */ 00747 /* Filter state functions *****************************************************/ 00748 HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00749 uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter); 00750 /** 00751 * @} 00752 */ 00753 00754 /** 00755 * @} 00756 */ 00757 /* End of exported functions -------------------------------------------------*/ 00758 00759 /* Private macros ------------------------------------------------------------*/ 00760 /** @defgroup DFSDM_Private_Macros DFSDM Private Macros 00761 * @{ 00762 */ 00763 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK(CLOCK) (((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_SYSTEM) || \ 00764 ((CLOCK) == DFSDM_CHANNEL_OUTPUT_CLOCK_AUDIO)) 00765 #define IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(DIVIDER) ((2U <= (DIVIDER)) && ((DIVIDER) <= 256U)) 00766 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) || \ 00767 defined(STM32L496xx) || defined(STM32L4A6xx) || \ 00768 defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00769 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 00770 ((INPUT) == DFSDM_CHANNEL_ADC_OUTPUT) || \ 00771 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 00772 #else 00773 #define IS_DFSDM_CHANNEL_INPUT(INPUT) (((INPUT) == DFSDM_CHANNEL_EXTERNAL_INPUTS) || \ 00774 ((INPUT) == DFSDM_CHANNEL_INTERNAL_REGISTER)) 00775 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ 00776 /* STM32L496xx || STM32L4A6xx || */ 00777 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00778 #define IS_DFSDM_CHANNEL_DATA_PACKING(MODE) (((MODE) == DFSDM_CHANNEL_STANDARD_MODE) || \ 00779 ((MODE) == DFSDM_CHANNEL_INTERLEAVED_MODE) || \ 00780 ((MODE) == DFSDM_CHANNEL_DUAL_MODE)) 00781 #define IS_DFSDM_CHANNEL_INPUT_PINS(PINS) (((PINS) == DFSDM_CHANNEL_SAME_CHANNEL_PINS) || \ 00782 ((PINS) == DFSDM_CHANNEL_FOLLOWING_CHANNEL_PINS)) 00783 #define IS_DFSDM_CHANNEL_SERIAL_INTERFACE_TYPE(MODE) (((MODE) == DFSDM_CHANNEL_SPI_RISING) || \ 00784 ((MODE) == DFSDM_CHANNEL_SPI_FALLING) || \ 00785 ((MODE) == DFSDM_CHANNEL_MANCHESTER_RISING) || \ 00786 ((MODE) == DFSDM_CHANNEL_MANCHESTER_FALLING)) 00787 #define IS_DFSDM_CHANNEL_SPI_CLOCK(TYPE) (((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL) || \ 00788 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL) || \ 00789 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING) || \ 00790 ((TYPE) == DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING)) 00791 #define IS_DFSDM_CHANNEL_FILTER_ORDER(ORDER) (((ORDER) == DFSDM_CHANNEL_FASTSINC_ORDER) || \ 00792 ((ORDER) == DFSDM_CHANNEL_SINC1_ORDER) || \ 00793 ((ORDER) == DFSDM_CHANNEL_SINC2_ORDER) || \ 00794 ((ORDER) == DFSDM_CHANNEL_SINC3_ORDER)) 00795 #define IS_DFSDM_CHANNEL_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 32U)) 00796 #define IS_DFSDM_CHANNEL_OFFSET(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 00797 #define IS_DFSDM_CHANNEL_RIGHT_BIT_SHIFT(VALUE) ((VALUE) <= 0x1FU) 00798 #define IS_DFSDM_CHANNEL_SCD_THRESHOLD(VALUE) ((VALUE) <= 0xFFU) 00799 #define IS_DFSDM_FILTER_REG_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 00800 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER)) 00801 #define IS_DFSDM_FILTER_INJ_TRIGGER(TRIG) (((TRIG) == DFSDM_FILTER_SW_TRIGGER) || \ 00802 ((TRIG) == DFSDM_FILTER_SYNC_TRIGGER) || \ 00803 ((TRIG) == DFSDM_FILTER_EXT_TRIGGER)) 00804 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 00805 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 00806 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 00807 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 00808 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 00809 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 00810 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 00811 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 00812 #elif defined(STM32L4R5xx) || defined(STM32L4R7xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) 00813 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 00814 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 00815 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 00816 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 00817 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 00818 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 00819 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 00820 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 00821 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 00822 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 00823 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15) || \ 00824 ((TRIG) == DFSDM_FILTER_EXT_TRIG_LPTIM1_OUT)) 00825 #else 00826 #define IS_DFSDM_FILTER_EXT_TRIG(TRIG) (((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO) || \ 00827 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM1_TRGO2) || \ 00828 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO) || \ 00829 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM8_TRGO2) || \ 00830 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM3_TRGO) || \ 00831 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM4_TRGO) || \ 00832 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM16_OC1) || \ 00833 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM6_TRGO) || \ 00834 ((TRIG) == DFSDM_FILTER_EXT_TRIG_TIM7_TRGO) || \ 00835 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI11) || \ 00836 ((TRIG) == DFSDM_FILTER_EXT_TRIG_EXTI15)) 00837 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 00838 #define IS_DFSDM_FILTER_EXT_TRIG_EDGE(EDGE) (((EDGE) == DFSDM_FILTER_EXT_TRIG_RISING_EDGE) || \ 00839 ((EDGE) == DFSDM_FILTER_EXT_TRIG_FALLING_EDGE) || \ 00840 ((EDGE) == DFSDM_FILTER_EXT_TRIG_BOTH_EDGES)) 00841 #define IS_DFSDM_FILTER_SINC_ORDER(ORDER) (((ORDER) == DFSDM_FILTER_FASTSINC_ORDER) || \ 00842 ((ORDER) == DFSDM_FILTER_SINC1_ORDER) || \ 00843 ((ORDER) == DFSDM_FILTER_SINC2_ORDER) || \ 00844 ((ORDER) == DFSDM_FILTER_SINC3_ORDER) || \ 00845 ((ORDER) == DFSDM_FILTER_SINC4_ORDER) || \ 00846 ((ORDER) == DFSDM_FILTER_SINC5_ORDER)) 00847 #define IS_DFSDM_FILTER_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 1024U)) 00848 #define IS_DFSDM_FILTER_INTEGRATOR_OVS_RATIO(RATIO) ((1U <= (RATIO)) && ((RATIO) <= 256U)) 00849 #define IS_DFSDM_FILTER_AWD_DATA_SOURCE(DATA) (((DATA) == DFSDM_FILTER_AWD_FILTER_DATA) || \ 00850 ((DATA) == DFSDM_FILTER_AWD_CHANNEL_DATA)) 00851 #define IS_DFSDM_FILTER_AWD_THRESHOLD(VALUE) ((-8388608 <= (VALUE)) && ((VALUE) <= 8388607)) 00852 #define IS_DFSDM_BREAK_SIGNALS(VALUE) ((VALUE) <= 0xFU) 00853 #if defined(STM32L451xx) || defined(STM32L452xx) || defined(STM32L462xx) 00854 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 00855 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 00856 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 00857 ((CHANNEL) == DFSDM_CHANNEL_3)) 00858 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x0003000FU)) 00859 #else 00860 #define IS_DFSDM_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == DFSDM_CHANNEL_0) || \ 00861 ((CHANNEL) == DFSDM_CHANNEL_1) || \ 00862 ((CHANNEL) == DFSDM_CHANNEL_2) || \ 00863 ((CHANNEL) == DFSDM_CHANNEL_3) || \ 00864 ((CHANNEL) == DFSDM_CHANNEL_4) || \ 00865 ((CHANNEL) == DFSDM_CHANNEL_5) || \ 00866 ((CHANNEL) == DFSDM_CHANNEL_6) || \ 00867 ((CHANNEL) == DFSDM_CHANNEL_7)) 00868 #define IS_DFSDM_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F00FFU)) 00869 #endif /* STM32L451xx || STM32L452xx || STM32L462xx */ 00870 #define IS_DFSDM_CONTINUOUS_MODE(MODE) (((MODE) == DFSDM_CONTINUOUS_CONV_OFF) || \ 00871 ((MODE) == DFSDM_CONTINUOUS_CONV_ON)) 00872 /** 00873 * @} 00874 */ 00875 /* End of private macros -----------------------------------------------------*/ 00876 00877 /** 00878 * @} 00879 */ 00880 00881 /** 00882 * @} 00883 */ 00884 #endif /* STM32L451xx || STM32L452xx || STM32L462xx || */ 00885 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 00886 /* STM32L496xx || STM32L4A6xx || */ 00887 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00888 00889 #ifdef __cplusplus 00890 } 00891 #endif 00892 00893 #endif /* STM32L4xx_HAL_DFSDM_H */ 00894 00895 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/