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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_adc.h 00004 * @author MCD Application Team 00005 * @brief Header file of ADC HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_ADC_H 00038 #define __STM32L4xx_HAL_ADC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /* Include low level driver */ 00048 #include "stm32l4xx_ll_adc.h" 00049 00050 /** @addtogroup STM32L4xx_HAL_Driver 00051 * @{ 00052 */ 00053 00054 /** @addtogroup ADC 00055 * @{ 00056 */ 00057 00058 /* Exported types ------------------------------------------------------------*/ 00059 /** @defgroup ADC_Exported_Types ADC Exported Types 00060 * @{ 00061 */ 00062 00063 /** 00064 * @brief ADC group regular oversampling structure definition 00065 */ 00066 typedef struct 00067 { 00068 uint32_t Ratio; /*!< Configures the oversampling ratio. 00069 This parameter can be a value of @ref ADC_HAL_EC_OVS_RATIO */ 00070 00071 uint32_t RightBitShift; /*!< Configures the division coefficient for the Oversampler. 00072 This parameter can be a value of @ref ADC_HAL_EC_OVS_SHIFT */ 00073 00074 uint32_t TriggeredMode; /*!< Selects the regular triggered oversampling mode. 00075 This parameter can be a value of @ref ADC_HAL_EC_OVS_DISCONT_MODE */ 00076 00077 uint32_t OversamplingStopReset; /*!< Selects the regular oversampling mode. 00078 The oversampling is either temporary stopped or reset upon an injected 00079 sequence interruption. 00080 If oversampling is enabled on both regular and injected groups, this parameter 00081 is discarded and forced to setting "ADC_REGOVERSAMPLING_RESUMED_MODE" 00082 (the oversampling buffer is zeroed during injection sequence). 00083 This parameter can be a value of @ref ADC_HAL_EC_OVS_SCOPE_REG */ 00084 00085 }ADC_OversamplingTypeDef; 00086 00087 /** 00088 * @brief Structure definition of ADC instance and ADC group regular. 00089 * @note Parameters of this structure are shared within 2 scopes: 00090 * - Scope entire ADC (affects ADC groups regular and injected): ClockPrescaler, Resolution, DataAlign, 00091 * ScanConvMode, EOCSelection, LowPowerAutoWait. 00092 * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, 00093 * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. 00094 * @note The setting of these parameters by function HAL_ADC_Init() is conditioned to ADC state. 00095 * ADC state can be either: 00096 * - For all parameters: ADC disabled 00097 * - For all parameters except 'LowPowerAutoWait', 'DMAContinuousRequests' and 'Oversampling': ADC enabled without conversion on going on group regular. 00098 * - For parameters 'LowPowerAutoWait' and 'DMAContinuousRequests': ADC enabled without conversion on going on groups regular and injected. 00099 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00100 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter 00101 * (which fulfills the ADC state condition) on the fly). 00102 */ 00103 typedef struct 00104 { 00105 uint32_t ClockPrescaler; /*!< Select ADC clock source (synchronous clock derived from APB clock or asynchronous clock derived from system clock or PLL (Refer to reference manual for list of clocks available)) and clock prescaler. 00106 This parameter can be a value of @ref ADC_HAL_EC_COMMON_CLOCK_SOURCE. 00107 Note: The ADC clock configuration is common to all ADC instances. 00108 Note: In case of usage of channels on injected group, ADC frequency should be lower than AHB clock frequency /4 for resolution 12 or 10 bits, 00109 AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits. 00110 Note: In case of synchronous clock mode based on HCLK/1, the configuration must be enabled only 00111 if the system clock has a 50% duty clock cycle (APB prescaler configured inside RCC 00112 must be bypassed and PCLK clock must have 50% duty cycle). Refer to reference manual for details. 00113 Note: In case of usage of asynchronous clock, the selected clock must be preliminarily enabled at RCC top level. 00114 Note: This parameter can be modified only if all ADC instances are disabled. */ 00115 00116 uint32_t Resolution; /*!< Configure the ADC resolution. 00117 This parameter can be a value of @ref ADC_HAL_EC_RESOLUTION */ 00118 00119 uint32_t DataAlign; /*!< Specify ADC data alignment in conversion data register (right or left). 00120 Refer to reference manual for alignments formats versus resolutions. 00121 This parameter can be a value of @ref ADC_HAL_EC_DATA_ALIGN */ 00122 00123 uint32_t ScanConvMode; /*!< Configure the sequencer of ADC groups regular and injected. 00124 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts. 00125 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1). 00126 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1). 00127 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion' or 'InjectedNbrOfConversion' and rank of each channel in sequencer). 00128 Scan direction is upward: from rank 1 to rank 'n'. 00129 This parameter can be a value of @ref ADC_Scan_mode */ 00130 00131 uint32_t EOCSelection; /*!< Specify which EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of unitary conversion or end of sequence conversions. 00132 This parameter can be a value of @ref ADC_EOCSelection. */ 00133 00134 uint32_t LowPowerAutoWait; /*!< Select the dynamic low power Auto Delay: new conversion start only when the previous 00135 conversion (for ADC group regular) or previous sequence (for ADC group injected) has been retrieved by user software, 00136 using function HAL_ADC_GetValue() or HAL_ADCEx_InjectedGetValue(). 00137 This feature automatically adapts the frequency of ADC conversions triggers to the speed of the system that reads the data. Moreover, this avoids risk of overrun 00138 for low frequency applications. 00139 This parameter can be set to ENABLE or DISABLE. 00140 Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they clear immediately the EOC flag 00141 to free the IRQ vector sequencer. 00142 Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when ADC conversion data is needed: 00143 use HAL_ADC_PollForConversion() to ensure that conversion is completed and HAL_ADC_GetValue() to retrieve conversion result and trig another conversion start. 00144 (in case of usage of ADC group injected, use the equivalent functions HAL_ADCExInjected_Start(), HAL_ADCEx_InjectedGetValue(), ...). */ 00145 00146 uint32_t ContinuousConvMode; /*!< Specify whether the conversion is performed in single mode (one conversion) or continuous mode for ADC group regular, 00147 after the first ADC conversion start trigger occurred (software start or external trigger). 00148 This parameter can be set to ENABLE or DISABLE. */ 00149 00150 uint32_t NbrOfConversion; /*!< Specify the number of ranks that will be converted within the regular group sequencer. 00151 To use the regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled. 00152 This parameter must be a number between Min_Data = 1 and Max_Data = 16. 00153 Note: This parameter must be modified when no conversion is on going on regular group (ADC disabled, or ADC enabled without 00154 continuous mode or external trigger that could launch a conversion). */ 00155 00156 uint32_t DiscontinuousConvMode; /*!< Specify whether the conversions sequence of ADC group regular is performed in Complete-sequence/Discontinuous-sequence 00157 (main sequence subdivided in successive parts). 00158 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded. 00159 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded. 00160 This parameter can be set to ENABLE or DISABLE. */ 00161 00162 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of ADC group regular (parameter NbrOfConversion) will be subdivided. 00163 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded. 00164 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */ 00165 00166 uint32_t ExternalTrigConv; /*!< Select the external event source used to trigger ADC group regular conversion start. 00167 If set to ADC_SOFTWARE_START, external triggers are disabled and software trigger is used instead. 00168 This parameter can be a value of @ref ADC_regular_external_trigger_source. 00169 Caution: external trigger source is common to all ADC instances. */ 00170 00171 uint32_t ExternalTrigConvEdge; /*!< Select the external event edge used to trigger ADC group regular conversion start. 00172 If trigger source is set to ADC_SOFTWARE_START, this parameter is discarded. 00173 This parameter can be a value of @ref ADC_regular_external_trigger_edge */ 00174 00175 uint32_t DMAContinuousRequests; /*!< Specify whether the DMA requests are performed in one shot mode (DMA transfer stops when number of conversions is reached) 00176 or in continuous mode (DMA transfer unlimited, whatever number of conversions). 00177 This parameter can be set to ENABLE or DISABLE. 00178 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached. */ 00179 00180 uint32_t Overrun; /*!< Select the behavior in case of overrun: data overwritten or preserved (default). 00181 This parameter applies to ADC group regular only. 00182 This parameter can be a value of @ref ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR. 00183 Note: In case of overrun set to data preserved and usage with programming model with interruption (HAL_Start_IT()): ADC IRQ handler has to clear 00184 end of conversion flags, this induces the release of the preserved data. If needed, this data can be saved in function 00185 HAL_ADC_ConvCpltCallback(), placed in user program code (called before end of conversion flags clear). 00186 Note: Error reporting with respect to the conversion mode: 00187 - Usage with ADC conversion by polling for event or interruption: Error is reported only if overrun is set to data preserved. If overrun is set to data 00188 overwritten, user can willingly not read all the converted data, this is not considered as an erroneous case. 00189 - Usage with ADC conversion by DMA: Error is reported whatever overrun setting (DMA is expected to process all data from data register). */ 00190 00191 uint32_t OversamplingMode; /*!< Specify whether the oversampling feature is enabled or disabled. 00192 This parameter can be set to ENABLE or DISABLE. 00193 Note: This parameter can be modified only if there is no conversion is ongoing on ADC groups regular and injected */ 00194 00195 ADC_OversamplingTypeDef Oversampling; /*!< Specify the Oversampling parameters. 00196 Caution: this setting overwrites the previous oversampling configuration if oversampling is already enabled. */ 00197 00198 #if defined(ADC_CFGR_DFSDMCFG) &&defined(DFSDM1_Channel0) 00199 uint32_t DFSDMConfig; /*!< Specify whether ADC conversion data is sent directly to DFSDM. 00200 This parameter can be a value of @ref ADC_HAL_EC_REG_DFSDM_TRANSFER. 00201 Note: This parameter can be modified only if there is no conversion is ongoing (both ADSTART and JADSTART cleared). */ 00202 00203 #endif 00204 }ADC_InitTypeDef; 00205 00206 /** 00207 * @brief Structure definition of ADC channel for regular group 00208 * @note The setting of these parameters by function HAL_ADC_ConfigChannel() is conditioned to ADC state. 00209 * ADC state can be either: 00210 * - For all parameters: ADC disabled (this is the only possible ADC state to modify parameter 'SingleDiff') 00211 * - For all except parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular group. 00212 * - For parameters 'SamplingTime', 'Offset', 'OffsetNumber': ADC enabled without conversion on going on regular and injected groups. 00213 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed 00214 * without error reporting (as it can be the expected behavior in case of intended action to update another parameter (which fulfills the ADC state condition) 00215 * on the fly). 00216 */ 00217 typedef struct 00218 { 00219 uint32_t Channel; /*!< Specify the channel to configure into ADC regular group. 00220 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL 00221 Note: Depending on devices and ADC instances, some channels may not be available on device package pins. Refer to device datasheet for channels availability. */ 00222 00223 uint32_t Rank; /*!< Specify the rank in the regular group sequencer. 00224 This parameter can be a value of @ref ADC_HAL_EC_REG_SEQ_RANKS 00225 Note: to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by 00226 the new channel setting (or parameter number of conversions adjusted) */ 00227 00228 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel. 00229 Unit: ADC clock cycles 00230 Conversion time is the addition of sampling time and processing time 00231 (12.5 ADC clock cycles at ADC resolution 12 bits, 10.5 cycles at 10 bits, 8.5 cycles at 8 bits, 6.5 cycles at 6 bits). 00232 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL_SAMPLINGTIME 00233 Caution: This parameter applies to a channel that can be used into regular and/or injected group. 00234 It overwrites the last setting. 00235 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor), 00236 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting) 00237 Refer to device datasheet for timings values. */ 00238 00239 uint32_t SingleDiff; /*!< Select single-ended or differential input. 00240 In differential mode: Differential measurement is carried out between the selected channel 'i' (positive input) and channel 'i+1' (negative input). 00241 Only channel 'i' has to be configured, channel 'i+1' is configured automatically. 00242 This parameter must be a value of @ref ADC_HAL_EC_CHANNEL_SINGLE_DIFF_ENDING 00243 Caution: This parameter applies to a channel that can be used in a regular and/or injected group. 00244 It overwrites the last setting. 00245 Note: Refer to Reference Manual to ensure the selected channel is available in differential mode. 00246 Note: When configuring a channel 'i' in differential mode, the channel 'i+1' is not usable separately. 00247 Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion). 00248 If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behavior in case 00249 of another parameter update on the fly) */ 00250 00251 uint32_t OffsetNumber; /*!< Select the offset number 00252 This parameter can be a value of @ref ADC_HAL_EC_OFFSET_NB 00253 Caution: Only one offset is allowed per channel. This parameter overwrites the last setting. */ 00254 00255 uint32_t Offset; /*!< Define the offset to be subtracted from the raw converted data. 00256 Offset value must be a positive number. 00257 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 00258 0x3FF, 0xFF or 0x3F respectively. 00259 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled 00260 without continuous mode or external trigger that could launch a conversion). */ 00261 00262 }ADC_ChannelConfTypeDef; 00263 00264 /** 00265 * @brief Structure definition of ADC analog watchdog 00266 * @note The setting of these parameters by function HAL_ADC_AnalogWDGConfig() is conditioned to ADC state. 00267 * ADC state can be either: 00268 * - For all parameters: ADC disabled or ADC enabled without conversion on going on ADC groups regular and injected. 00269 */ 00270 typedef struct 00271 { 00272 uint32_t WatchdogNumber; /*!< Select which ADC analog watchdog is monitoring the selected channel. 00273 For Analog Watchdog 1: Only 1 channel can be monitored (or overall group of channels by setting parameter 'WatchdogMode') 00274 For Analog Watchdog 2 and 3: Several channels can be monitored (by successive calls of 'HAL_ADC_AnalogWDGConfig()' for each channel) 00275 This parameter can be a value of @ref ADC_HAL_EC_AWD_NUMBER. */ 00276 00277 uint32_t WatchdogMode; /*!< Configure the ADC analog watchdog mode: single/all/none channels. 00278 For Analog Watchdog 1: Configure the ADC analog watchdog mode: single channel or all channels, ADC groups regular and-or injected. 00279 For Analog Watchdog 2 and 3: Several channels can be monitored by applying successively the AWD init structure. Channels on ADC group regular and injected are not differentiated: Set value 'ADC_ANALOGWATCHDOG_SINGLE_xxx' to monitor 1 channel, value 'ADC_ANALOGWATCHDOG_ALL_xxx' to monitor all channels, 'ADC_ANALOGWATCHDOG_NONE' to monitor no channel. 00280 This parameter can be a value of @ref ADC_analog_watchdog_mode. */ 00281 00282 uint32_t Channel; /*!< Select which ADC channel to monitor by analog watchdog. 00283 For Analog Watchdog 1: this parameter has an effect only if parameter 'WatchdogMode' is configured on single channel (only 1 channel can be monitored). 00284 For Analog Watchdog 2 and 3: Several channels can be monitored. To use this feature, call successively the function HAL_ADC_AnalogWDGConfig() for each channel to be added (or removed with value 'ADC_ANALOGWATCHDOG_NONE'). 00285 This parameter can be a value of @ref ADC_HAL_EC_CHANNEL. */ 00286 00287 uint32_t ITMode; /*!< Specify whether the analog watchdog is configured in interrupt or polling mode. 00288 This parameter can be set to ENABLE or DISABLE */ 00289 00290 uint32_t HighThreshold; /*!< Configure the ADC analog watchdog High threshold value. 00291 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 00292 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 00293 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 00294 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ 00295 00296 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog Low threshold value. 00297 Depending of ADC resolution selected (12, 10, 8 or 6 bits), this parameter must be a number 00298 between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. 00299 Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits 00300 the 4 LSB are ignored, if ADC resolution is 10 bits the 2 LSB are ignored. */ 00301 }ADC_AnalogWDGConfTypeDef; 00302 00303 /** 00304 * @brief ADC group injected contexts queue configuration 00305 * @note Structure intended to be used only through structure "ADC_HandleTypeDef" 00306 */ 00307 typedef struct 00308 { 00309 uint32_t ContextQueue; /*!< Injected channel configuration context: build-up over each 00310 HAL_ADCEx_InjectedConfigChannel() call to finally initialize 00311 JSQR register at HAL_ADCEx_InjectedConfigChannel() last call */ 00312 00313 uint32_t ChannelCount; /*!< Number of channels in the injected sequence */ 00314 }ADC_InjectionConfigTypeDef; 00315 00316 /** @defgroup ADC_States ADC States 00317 * @{ 00318 */ 00319 00320 /** 00321 * @brief HAL ADC state machine: ADC states definition (bitfields) 00322 * @note ADC state machine is managed by bitfields, state must be compared 00323 * with bit by bit. 00324 * For example: 00325 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " 00326 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " 00327 */ 00328 /* States of ADC global scope */ 00329 #define HAL_ADC_STATE_RESET (0x00000000U) /*!< ADC not yet initialized or disabled */ 00330 #define HAL_ADC_STATE_READY (0x00000001U) /*!< ADC peripheral ready for use */ 00331 #define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002U) /*!< ADC is busy due to an internal process (initialization, calibration) */ 00332 #define HAL_ADC_STATE_TIMEOUT (0x00000004U) /*!< TimeOut occurrence */ 00333 00334 /* States of ADC errors */ 00335 #define HAL_ADC_STATE_ERROR_INTERNAL (0x00000010U) /*!< Internal error occurrence */ 00336 #define HAL_ADC_STATE_ERROR_CONFIG (0x00000020U) /*!< Configuration error occurrence */ 00337 #define HAL_ADC_STATE_ERROR_DMA (0x00000040U) /*!< DMA error occurrence */ 00338 00339 /* States of ADC group regular */ 00340 #define HAL_ADC_STATE_REG_BUSY (0x00000100U) /*!< A conversion on ADC group regular is ongoing or can occur (either by continuous mode, 00341 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 00342 #define HAL_ADC_STATE_REG_EOC (0x00000200U) /*!< Conversion data available on group regular */ 00343 #define HAL_ADC_STATE_REG_OVR (0x00000400U) /*!< Overrun occurrence */ 00344 #define HAL_ADC_STATE_REG_EOSMP (0x00000800U) /*!< Not available on this STM32 serie: End Of Sampling flag raised */ 00345 00346 /* States of ADC group injected */ 00347 #define HAL_ADC_STATE_INJ_BUSY (0x00001000U) /*!< A conversion on ADC group injected is ongoing or can occur (either by auto-injection mode, 00348 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */ 00349 #define HAL_ADC_STATE_INJ_EOC (0x00002000U) /*!< Conversion data available on group injected */ 00350 #define HAL_ADC_STATE_INJ_JQOVF (0x00004000U) /*!< Injected queue overflow occurrence */ 00351 00352 /* States of ADC analog watchdogs */ 00353 #define HAL_ADC_STATE_AWD1 (0x00010000U) /*!< Out-of-window occurrence of ADC analog watchdog 1 */ 00354 #define HAL_ADC_STATE_AWD2 (0x00020000U) /*!< Out-of-window occurrence of ADC analog watchdog 2 */ 00355 #define HAL_ADC_STATE_AWD3 (0x00040000U) /*!< Out-of-window occurrence of ADC analog watchdog 3 */ 00356 00357 /* States of ADC multi-mode */ 00358 #define HAL_ADC_STATE_MULTIMODE_SLAVE (0x00100000U) /*!< ADC in multimode slave state, controlled by another ADC master (when feature available) */ 00359 00360 /** 00361 * @} 00362 */ 00363 00364 /** 00365 * @brief ADC handle Structure definition 00366 */ 00367 typedef struct __ADC_HandleTypeDef 00368 { 00369 ADC_TypeDef *Instance; /*!< Register base address */ 00370 ADC_InitTypeDef Init; /*!< ADC initialization parameters and regular conversions setting */ 00371 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */ 00372 HAL_LockTypeDef Lock; /*!< ADC locking object */ 00373 __IO uint32_t State; /*!< ADC communication state (bitmap of ADC states) */ 00374 __IO uint32_t ErrorCode; /*!< ADC Error code */ 00375 ADC_InjectionConfigTypeDef InjectionConfig ; /*!< ADC injected channel configuration build-up structure */ 00376 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00377 void (* ConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion complete callback */ 00378 void (* ConvHalfCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC conversion DMA half-transfer callback */ 00379 void (* LevelOutOfWindowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 1 callback */ 00380 void (* ErrorCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC error callback */ 00381 void (* InjectedConvCpltCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected conversion complete callback */ 00382 void (* InjectedQueueOverflowCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC group injected context queue overflow callback */ 00383 void (* LevelOutOfWindow2Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 2 callback */ 00384 void (* LevelOutOfWindow3Callback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC analog watchdog 3 callback */ 00385 void (* EndOfSamplingCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC end of sampling callback */ 00386 void (* MspInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp Init callback */ 00387 void (* MspDeInitCallback)(struct __ADC_HandleTypeDef *hadc); /*!< ADC Msp DeInit callback */ 00388 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00389 }ADC_HandleTypeDef; 00390 00391 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00392 /** 00393 * @brief HAL ADC Callback ID enumeration definition 00394 */ 00395 typedef enum 00396 { 00397 HAL_ADC_CONVERSION_COMPLETE_CB_ID = 0x00U, /*!< ADC conversion complete callback ID */ 00398 HAL_ADC_CONVERSION_HALF_CB_ID = 0x01U, /*!< ADC conversion DMA half-transfer callback ID */ 00399 HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID = 0x02U, /*!< ADC analog watchdog 1 callback ID */ 00400 HAL_ADC_ERROR_CB_ID = 0x03U, /*!< ADC error callback ID */ 00401 HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID = 0x04U, /*!< ADC group injected conversion complete callback ID */ 00402 HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID = 0x05U, /*!< ADC group injected context queue overflow callback ID */ 00403 HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID = 0x06U, /*!< ADC analog watchdog 2 callback ID */ 00404 HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID = 0x07U, /*!< ADC analog watchdog 3 callback ID */ 00405 HAL_ADC_END_OF_SAMPLING_CB_ID = 0x08U, /*!< ADC end of sampling callback ID */ 00406 HAL_ADC_MSPINIT_CB_ID = 0x09U, /*!< ADC Msp Init callback ID */ 00407 HAL_ADC_MSPDEINIT_CB_ID = 0x0AU /*!< ADC Msp DeInit callback ID */ 00408 } HAL_ADC_CallbackIDTypeDef; 00409 00410 /** 00411 * @brief HAL ADC Callback pointer definition 00412 */ 00413 typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to a ADC callback function */ 00414 00415 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00416 00417 /** 00418 * @} 00419 */ 00420 00421 00422 /* Exported constants --------------------------------------------------------*/ 00423 00424 /** @defgroup ADC_Exported_Constants ADC Exported Constants 00425 * @{ 00426 */ 00427 00428 /** @defgroup ADC_Error_Code ADC Error Code 00429 * @{ 00430 */ 00431 #define HAL_ADC_ERROR_NONE (0x00U) /*!< No error */ 00432 #define HAL_ADC_ERROR_INTERNAL (0x01U) /*!< ADC IP internal error (problem of clocking, 00433 enable/disable, erroneous state, ...) */ 00434 #define HAL_ADC_ERROR_OVR (0x02U) /*!< Overrun error */ 00435 #define HAL_ADC_ERROR_DMA (0x04U) /*!< DMA transfer error */ 00436 #define HAL_ADC_ERROR_JQOVF (0x08U) /*!< Injected context queue overflow error */ 00437 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00438 #define HAL_ADC_ERROR_INVALID_CALLBACK (0x10U) /*!< Invalid Callback error */ 00439 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00440 /** 00441 * @} 00442 */ 00443 00444 /** @defgroup ADC_HAL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source 00445 * @{ 00446 */ 00447 #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock derived from AHB clock without prescaler */ 00448 #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 2 */ 00449 #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock derived from AHB clock with prescaler division by 4 */ 00450 00451 #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without prescaler */ 00452 #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler division by 2 */ 00453 #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler division by 4 */ 00454 #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler division by 6 */ 00455 #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler division by 8 */ 00456 #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler division by 10 */ 00457 #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler division by 12 */ 00458 #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler division by 16 */ 00459 #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler division by 32 */ 00460 #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler division by 64 */ 00461 #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler division by 128 */ 00462 #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler division by 256 */ 00463 00464 #define ADC_CLOCKPRESCALER_PCLK_DIV1 ADC_CLOCK_SYNC_PCLK_DIV1 /*!< Obsolete naming, kept for compatibility with some other devices */ 00465 #define ADC_CLOCKPRESCALER_PCLK_DIV2 ADC_CLOCK_SYNC_PCLK_DIV2 /*!< Obsolete naming, kept for compatibility with some other devices */ 00466 #define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4 /*!< Obsolete naming, kept for compatibility with some other devices */ 00467 /** 00468 * @} 00469 */ 00470 00471 /** @defgroup ADC_HAL_EC_RESOLUTION ADC instance - Resolution 00472 * @{ 00473 */ 00474 #define ADC_RESOLUTION_12B (LL_ADC_RESOLUTION_12B) /*!< ADC resolution 12 bits */ 00475 #define ADC_RESOLUTION_10B (LL_ADC_RESOLUTION_10B) /*!< ADC resolution 10 bits */ 00476 #define ADC_RESOLUTION_8B (LL_ADC_RESOLUTION_8B) /*!< ADC resolution 8 bits */ 00477 #define ADC_RESOLUTION_6B (LL_ADC_RESOLUTION_6B) /*!< ADC resolution 6 bits */ 00478 /** 00479 * @} 00480 */ 00481 00482 /** @defgroup ADC_HAL_EC_DATA_ALIGN ADC conversion data alignment 00483 * @{ 00484 */ 00485 #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT)/*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ 00486 #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ 00487 /** 00488 * @} 00489 */ 00490 00491 /** @defgroup ADC_Scan_mode ADC sequencer scan mode 00492 * @{ 00493 */ 00494 #define ADC_SCAN_DISABLE (0x00000000U) /*!< Scan mode disabled */ 00495 #define ADC_SCAN_ENABLE (0x00000001U) /*!< Scan mode enabled */ 00496 /** 00497 * @} 00498 */ 00499 00500 /** @defgroup ADC_regular_external_trigger_source ADC group regular trigger source 00501 * @{ 00502 */ 00503 /* ADC group regular trigger sources for all ADC instances */ 00504 #define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion trigger internal: SW start. */ 00505 #define ADC_EXTERNALTRIG_T1_TRGO (LL_ADC_REG_TRIG_EXT_TIM1_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ 00506 #define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO2. Trigger edge set to rising edge (default setting). */ 00507 #define ADC_EXTERNALTRIG_T1_CC1 (LL_ADC_REG_TRIG_EXT_TIM1_CH1) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 1 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00508 #define ADC_EXTERNALTRIG_T1_CC2 (LL_ADC_REG_TRIG_EXT_TIM1_CH2) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00509 #define ADC_EXTERNALTRIG_T1_CC3 (LL_ADC_REG_TRIG_EXT_TIM1_CH3) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00510 #define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ 00511 #define ADC_EXTERNALTRIG_T2_CC2 (LL_ADC_REG_TRIG_EXT_TIM2_CH2) /*!< ADC group regular conversion trigger from external IP: TIM2 channel 2 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00512 #define ADC_EXTERNALTRIG_T3_TRGO (LL_ADC_REG_TRIG_EXT_TIM3_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ 00513 #define ADC_EXTERNALTRIG_T3_CC4 (LL_ADC_REG_TRIG_EXT_TIM3_CH4) /*!< ADC group regular conversion trigger from external IP: TIM3 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00514 #define ADC_EXTERNALTRIG_T4_TRGO (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 TRGO. Trigger edge set to rising edge (default setting). */ 00515 #define ADC_EXTERNALTRIG_T4_CC4 (LL_ADC_REG_TRIG_EXT_TIM4_CH4) /*!< ADC group regular conversion trigger from external IP: TIM4 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ 00516 #define ADC_EXTERNALTRIG_T6_TRGO (LL_ADC_REG_TRIG_EXT_TIM6_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM6 TRGO. Trigger edge set to rising edge (default setting). */ 00517 #define ADC_EXTERNALTRIG_T8_TRGO (LL_ADC_REG_TRIG_EXT_TIM8_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO. Trigger edge set to rising edge (default setting). */ 00518 #define ADC_EXTERNALTRIG_T8_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) /*!< ADC group regular conversion trigger from external IP: TIM8 TRGO2. Trigger edge set to rising edge (default setting). */ 00519 #define ADC_EXTERNALTRIG_T15_TRGO (LL_ADC_REG_TRIG_EXT_TIM15_TRGO) /*!< ADC group regular conversion trigger from external IP: TIM15 TRGO. Trigger edge set to rising edge (default setting). */ 00520 #define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion trigger from external IP: external interrupt line 11. Trigger edge set to rising edge (default setting). */ 00521 /** 00522 * @} 00523 */ 00524 00525 /** @defgroup ADC_regular_external_trigger_edge ADC group regular trigger edge (when external trigger is selected) 00526 * @{ 00527 */ 00528 #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000) /*!< Regular conversions hardware trigger detection disabled */ 00529 #define ADC_EXTERNALTRIGCONVEDGE_RISING (ADC_CFGR_EXTEN_0) /*!< Regular conversions hardware trigger detection on the rising edge */ 00530 #define ADC_EXTERNALTRIGCONVEDGE_FALLING (ADC_CFGR_EXTEN_1) /*!< Regular conversions hardware trigger detection on the falling edge */ 00531 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (ADC_CFGR_EXTEN) /*!< Regular conversions hardware trigger detection on both the rising and falling edges */ 00532 /** 00533 * @} 00534 */ 00535 00536 /** @defgroup ADC_EOCSelection ADC sequencer end of unitary conversion or sequence conversions 00537 * @{ 00538 */ 00539 #define ADC_EOC_SINGLE_CONV (ADC_ISR_EOC) /*!< End of unitary conversion flag */ 00540 #define ADC_EOC_SEQ_CONV (ADC_ISR_EOS) /*!< End of sequence conversions flag */ 00541 /** 00542 * @} 00543 */ 00544 00545 /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data 00546 * @{ 00547 */ 00548 #define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of overrun: data preserved */ 00549 #define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of overrun: data overwritten */ 00550 /** 00551 * @} 00552 */ 00553 00554 /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks 00555 * @{ 00556 */ 00557 #define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ 00558 #define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ 00559 #define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ 00560 #define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ 00561 #define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ 00562 #define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ 00563 #define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ 00564 #define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ 00565 #define ADC_REGULAR_RANK_9 (LL_ADC_REG_RANK_9) /*!< ADC group regular sequencer rank 9 */ 00566 #define ADC_REGULAR_RANK_10 (LL_ADC_REG_RANK_10) /*!< ADC group regular sequencer rank 10 */ 00567 #define ADC_REGULAR_RANK_11 (LL_ADC_REG_RANK_11) /*!< ADC group regular sequencer rank 11 */ 00568 #define ADC_REGULAR_RANK_12 (LL_ADC_REG_RANK_12) /*!< ADC group regular sequencer rank 12 */ 00569 #define ADC_REGULAR_RANK_13 (LL_ADC_REG_RANK_13) /*!< ADC group regular sequencer rank 13 */ 00570 #define ADC_REGULAR_RANK_14 (LL_ADC_REG_RANK_14) /*!< ADC group regular sequencer rank 14 */ 00571 #define ADC_REGULAR_RANK_15 (LL_ADC_REG_RANK_15) /*!< ADC group regular sequencer rank 15 */ 00572 #define ADC_REGULAR_RANK_16 (LL_ADC_REG_RANK_16) /*!< ADC group regular sequencer rank 16 */ 00573 /** 00574 * @} 00575 */ 00576 00577 /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time 00578 * @{ 00579 */ 00580 #define ADC_SAMPLETIME_2CYCLES_5 (LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 2.5 ADC clock cycles */ 00581 #define ADC_SAMPLETIME_6CYCLES_5 (LL_ADC_SAMPLINGTIME_6CYCLES_5) /*!< Sampling time 6.5 ADC clock cycles */ 00582 #define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ 00583 #define ADC_SAMPLETIME_24CYCLES_5 (LL_ADC_SAMPLINGTIME_24CYCLES_5) /*!< Sampling time 24.5 ADC clock cycles */ 00584 #define ADC_SAMPLETIME_47CYCLES_5 (LL_ADC_SAMPLINGTIME_47CYCLES_5) /*!< Sampling time 47.5 ADC clock cycles */ 00585 #define ADC_SAMPLETIME_92CYCLES_5 (LL_ADC_SAMPLINGTIME_92CYCLES_5) /*!< Sampling time 92.5 ADC clock cycles */ 00586 #define ADC_SAMPLETIME_247CYCLES_5 (LL_ADC_SAMPLINGTIME_247CYCLES_5) /*!< Sampling time 247.5 ADC clock cycles */ 00587 #define ADC_SAMPLETIME_640CYCLES_5 (LL_ADC_SAMPLINGTIME_640CYCLES_5) /*!< Sampling time 640.5 ADC clock cycles */ 00588 #if defined(ADC_SMPR1_SMPPLUS) 00589 #define ADC_SAMPLETIME_3CYCLES_5 (ADC_SMPR1_SMPPLUS | LL_ADC_SAMPLINGTIME_2CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles. If selected, this sampling time replaces all sampling time 2.5 ADC clock cycles. These 2 sampling times cannot be used simultaneously. */ 00590 #endif 00591 /** 00592 * @} 00593 */ 00594 00595 /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number 00596 * @{ 00597 */ 00598 /* Note: VrefInt, TempSensor and Vbat internal channels are not available on */ 00599 /* all ADC instances (refer to Reference Manual). */ 00600 #define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ 00601 #define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ 00602 #define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ 00603 #define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ 00604 #define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ 00605 #define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ 00606 #define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ 00607 #define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ 00608 #define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ 00609 #define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ 00610 #define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ 00611 #define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ 00612 #define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ 00613 #define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ 00614 #define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ 00615 #define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ 00616 #define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ 00617 #define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ 00618 #define ADC_CHANNEL_18 (LL_ADC_CHANNEL_18) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ 00619 #define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ 00620 #define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< ADC internal channel connected to Temperature sensor. */ 00621 #define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ 00622 #if defined(ADC1) && !defined(ADC2) 00623 #define ADC_CHANNEL_DAC1CH1 (LL_ADC_CHANNEL_DAC1CH1) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC1. This channel is shared with ADC internal channel connected to temperature sensor, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 00624 #define ADC_CHANNEL_DAC1CH2 (LL_ADC_CHANNEL_DAC1CH2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC1. This channel is shared with ADC internal channel connected to Vbat, selection is done using function @ref LL_ADC_SetCommonPathInternalCh(). */ 00625 #elif defined(ADC2) 00626 #define ADC_CHANNEL_DAC1CH1_ADC2 (LL_ADC_CHANNEL_DAC1CH1_ADC2) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC2 */ 00627 #define ADC_CHANNEL_DAC1CH2_ADC2 (LL_ADC_CHANNEL_DAC1CH2_ADC2) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC2 */ 00628 #if defined(ADC3) 00629 #define ADC_CHANNEL_DAC1CH1_ADC3 (LL_ADC_CHANNEL_DAC1CH1_ADC3) /*!< ADC internal channel connected to DAC1 channel 1, channel specific to ADC3 */ 00630 #define ADC_CHANNEL_DAC1CH2_ADC3 (LL_ADC_CHANNEL_DAC1CH2_ADC3) /*!< ADC internal channel connected to DAC1 channel 2, channel specific to ADC3 */ 00631 #endif 00632 #endif 00633 /** 00634 * @} 00635 */ 00636 00637 /** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number 00638 * @{ 00639 */ 00640 #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ 00641 #define ADC_ANALOGWATCHDOG_2 (LL_ADC_AWD2) /*!< ADC analog watchdog number 2 */ 00642 #define ADC_ANALOGWATCHDOG_3 (LL_ADC_AWD3) /*!< ADC analog watchdog number 3 */ 00643 /** 00644 * @} 00645 */ 00646 00647 /** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode 00648 * @{ 00649 */ 00650 #define ADC_ANALOGWATCHDOG_NONE (0x00000000U) /*!< No analog watchdog selected */ 00651 #define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to a regular group single channel */ 00652 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to an injected group single channel */ 00653 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC (ADC_CFGR_AWD1SGL | ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to a regular and injected groups single channel */ 00654 #define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR_AWD1EN) /*!< Analog watchdog applied to regular group all channels */ 00655 #define ADC_ANALOGWATCHDOG_ALL_INJEC (ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to injected group all channels */ 00656 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC (ADC_CFGR_AWD1EN | ADC_CFGR_JAWD1EN) /*!< Analog watchdog applied to regular and injected groups all channels */ 00657 /** 00658 * @} 00659 */ 00660 00661 /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio 00662 * @{ 00663 */ 00664 #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00665 #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00666 #define ADC_OVERSAMPLING_RATIO_8 (LL_ADC_OVS_RATIO_8) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00667 #define ADC_OVERSAMPLING_RATIO_16 (LL_ADC_OVS_RATIO_16) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00668 #define ADC_OVERSAMPLING_RATIO_32 (LL_ADC_OVS_RATIO_32) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00669 #define ADC_OVERSAMPLING_RATIO_64 (LL_ADC_OVS_RATIO_64) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00670 #define ADC_OVERSAMPLING_RATIO_128 (LL_ADC_OVS_RATIO_128) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00671 #define ADC_OVERSAMPLING_RATIO_256 (LL_ADC_OVS_RATIO_256) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ 00672 /** 00673 * @} 00674 */ 00675 00676 /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift 00677 * @{ 00678 */ 00679 #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ 00680 #define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ 00681 #define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ 00682 #define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ 00683 #define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ 00684 #define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ 00685 #define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ 00686 #define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ 00687 #define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ 00688 /** 00689 * @} 00690 */ 00691 00692 /** @defgroup ADC_HAL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode 00693 * @{ 00694 */ 00695 #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ 00696 #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ 00697 /** 00698 * @} 00699 */ 00700 00701 /** @defgroup ADC_HAL_EC_OVS_SCOPE_REG Oversampling - Oversampling scope for ADC group regular 00702 * @{ 00703 */ 00704 #define ADC_REGOVERSAMPLING_CONTINUED_MODE (LL_ADC_OVS_GRP_REGULAR_CONTINUED) /*!< Oversampling buffer maintained during injection sequence */ 00705 #define ADC_REGOVERSAMPLING_RESUMED_MODE (LL_ADC_OVS_GRP_REGULAR_RESUMED) /*!< Oversampling buffer zeroed during injection sequence */ 00706 /** 00707 * @} 00708 */ 00709 00710 00711 /** @defgroup ADC_Event_type ADC Event type 00712 * @{ 00713 */ 00714 #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ 00715 #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 series) */ 00716 #define ADC_AWD2_EVENT (ADC_FLAG_AWD2) /*!< ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 series) */ 00717 #define ADC_AWD3_EVENT (ADC_FLAG_AWD3) /*!< ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 series) */ 00718 #define ADC_OVR_EVENT (ADC_FLAG_OVR) /*!< ADC overrun event */ 00719 #define ADC_JQOVF_EVENT (ADC_FLAG_JQOVF) /*!< ADC Injected Context Queue Overflow event */ 00720 /** 00721 * @} 00722 */ 00723 #define ADC_AWD_EVENT ADC_AWD1_EVENT /*!< ADC Analog watchdog 1 event: Naming for compatibility with other STM32 devices having only one analog watchdog */ 00724 00725 /** @defgroup ADC_interrupts_definition ADC interrupts definition 00726 * @{ 00727 */ 00728 #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ 00729 #define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ 00730 #define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ 00731 #define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ 00732 #define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ 00733 #define ADC_IT_JEOC ADC_IER_JEOCIE /*!< ADC End of injected conversion interrupt source */ 00734 #define ADC_IT_JEOS ADC_IER_JEOSIE /*!< ADC End of injected sequence of conversions interrupt source */ 00735 #define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ 00736 #define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog watchdog) */ 00737 #define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog watchdog) */ 00738 #define ADC_IT_JQOVF ADC_IER_JQOVFIE /*!< ADC Injected Context Queue Overflow interrupt source */ 00739 00740 #define ADC_IT_AWD ADC_IT_AWD1 /*!< ADC Analog watchdog 1 interrupt source: naming for compatibility with other STM32 devices having only one analog watchdog */ 00741 00742 /** 00743 * @} 00744 */ 00745 00746 /** @defgroup ADC_flags_definition ADC flags definition 00747 * @{ 00748 */ 00749 #define ADC_FLAG_RDY ADC_ISR_ADRDY /*!< ADC Ready flag */ 00750 #define ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC End of Sampling flag */ 00751 #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ 00752 #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ 00753 #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ 00754 #define ADC_FLAG_JEOC ADC_ISR_JEOC /*!< ADC End of Injected Conversion flag */ 00755 #define ADC_FLAG_JEOS ADC_ISR_JEOS /*!< ADC End of Injected sequence of Conversions flag */ 00756 #define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ 00757 #define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ 00758 #define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ 00759 #define ADC_FLAG_JQOVF ADC_ISR_JQOVF /*!< ADC Injected Context Queue Overflow flag */ 00760 00761 #define ADC_FLAG_AWD ADC_FLAG_AWD1 /*!< ADC Analog watchdog 1 flag: Naming for compatibility with other STM32 devices having only one analog watchdog */ 00762 00763 #define ADC_FLAG_ALL (ADC_FLAG_RDY | ADC_FLAG_EOSMP | ADC_FLAG_EOC | ADC_FLAG_EOS | \ 00764 ADC_FLAG_JEOC | ADC_FLAG_JEOS | ADC_FLAG_OVR | ADC_FLAG_AWD1 | \ 00765 ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | ADC_FLAG_JQOVF) /*!< ADC all flags */ 00766 00767 /* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx, JQOVF */ 00768 #define ADC_FLAG_POSTCONV_ALL (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_JEOC | ADC_FLAG_JEOS | \ 00769 ADC_FLAG_OVR | ADC_FLAG_AWD1 | ADC_FLAG_AWD2 | ADC_FLAG_AWD3 | \ 00770 ADC_FLAG_JQOVF) /*!< ADC post-conversion all flags */ 00771 00772 /** 00773 * @} 00774 */ 00775 00776 /** 00777 * @} 00778 */ 00779 00780 /* Private macro -------------------------------------------------------------*/ 00781 00782 /** @defgroup ADC_Private_Macros ADC Private Macros 00783 * @{ 00784 */ 00785 /* Macro reserved for internal HAL driver usage, not intended to be used in */ 00786 /* code of final user. */ 00787 00788 /** 00789 * @brief Test if conversion trigger of regular group is software start 00790 * or external trigger. 00791 * @param __HANDLE__ ADC handle 00792 * @retval SET (software start) or RESET (external trigger) 00793 */ 00794 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ 00795 (((__HANDLE__)->Instance->CFGR & ADC_CFGR_EXTEN) == RESET) 00796 00797 /** 00798 * @brief Return resolution bits in CFGR register RES[1:0] field. 00799 * @param __HANDLE__ ADC handle 00800 * @retval Value of bitfield RES in CFGR register. 00801 */ 00802 #define ADC_GET_RESOLUTION(__HANDLE__) \ 00803 (LL_ADC_GetResolution((__HANDLE__)->Instance)) 00804 00805 /** 00806 * @brief Clear ADC error code (set it to no error code "HAL_ADC_ERROR_NONE"). 00807 * @param __HANDLE__ ADC handle 00808 * @retval None 00809 */ 00810 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE) 00811 00812 /** 00813 * @brief Verification of ADC state: enabled or disabled. 00814 * @param __HANDLE__ ADC handle 00815 * @retval SET (ADC enabled) or RESET (ADC disabled) 00816 */ 00817 #define ADC_IS_ENABLE(__HANDLE__) \ 00818 (( ((((__HANDLE__)->Instance->CR) & (ADC_CR_ADEN | ADC_CR_ADDIS)) == ADC_CR_ADEN) && \ 00819 ((((__HANDLE__)->Instance->ISR) & ADC_FLAG_RDY) == ADC_FLAG_RDY) \ 00820 ) ? SET : RESET) 00821 00822 /** 00823 * @brief Check if conversion is on going on regular group. 00824 * @param __HANDLE__ ADC handle 00825 * @retval SET (conversion is on going) or RESET (no conversion is on going) 00826 */ 00827 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__) \ 00828 (LL_ADC_REG_IsConversionOngoing((__HANDLE__)->Instance)) 00829 00830 /** 00831 * @brief Simultaneously clear and set specific bits of the handle State. 00832 * @note ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(), 00833 * the first parameter is the ADC handle State, the second parameter is the 00834 * bit field to clear, the third and last parameter is the bit field to set. 00835 * @retval None 00836 */ 00837 #define ADC_STATE_CLR_SET MODIFY_REG 00838 00839 /** 00840 * @brief Verify that a given value is aligned with the ADC resolution range. 00841 * @param __RESOLUTION__ ADC resolution (12, 10, 8 or 6 bits). 00842 * @param __ADC_VALUE__ value checked against the resolution. 00843 * @retval SET (__ADC_VALUE__ in line with __RESOLUTION__) or RESET (__ADC_VALUE__ not in line with __RESOLUTION__) 00844 */ 00845 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \ 00846 ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= (0x0FFF))) || \ 00847 (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= (0x03FF))) || \ 00848 (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= (0x00FF))) || \ 00849 (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= (0x003F))) ) 00850 00851 /** 00852 * @brief Verify the length of the scheduled regular conversions group. 00853 * @param __LENGTH__ number of programmed conversions. 00854 * @retval SET (__LENGTH__ is within the maximum number of possible programmable regular conversions) or RESET (__LENGTH__ is null or too large) 00855 */ 00856 #define IS_ADC_REGULAR_NB_CONV(__LENGTH__) (((__LENGTH__) >= (1U)) && ((__LENGTH__) <= (16U))) 00857 00858 00859 /** 00860 * @brief Verify the number of scheduled regular conversions in discontinuous mode. 00861 * @param NUMBER number of scheduled regular conversions in discontinuous mode. 00862 * @retval SET (NUMBER is within the maximum number of regular conversions in discontinous mode) or RESET (NUMBER is null or too large) 00863 */ 00864 #define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= (1U)) && ((NUMBER) <= (8U))) 00865 00866 00867 /** 00868 * @brief Verify the ADC clock setting. 00869 * @param __ADC_CLOCK__ programmed ADC clock. 00870 * @retval SET (__ADC_CLOCK__ is a valid value) or RESET (__ADC_CLOCK__ is invalid) 00871 */ 00872 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV1) || \ 00873 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \ 00874 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \ 00875 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV1) || \ 00876 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV2) || \ 00877 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV4) || \ 00878 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV6) || \ 00879 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV8) || \ 00880 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV10) || \ 00881 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV12) || \ 00882 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV16) || \ 00883 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV32) || \ 00884 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV64) || \ 00885 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV128) || \ 00886 ((__ADC_CLOCK__) == ADC_CLOCK_ASYNC_DIV256) ) 00887 00888 /** 00889 * @brief Verify the ADC resolution setting. 00890 * @param __RESOLUTION__ programmed ADC resolution. 00891 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 00892 */ 00893 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \ 00894 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \ 00895 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 00896 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 00897 00898 /** 00899 * @brief Verify the ADC resolution setting when limited to 6 or 8 bits. 00900 * @param __RESOLUTION__ programmed ADC resolution when limited to 6 or 8 bits. 00901 * @retval SET (__RESOLUTION__ is a valid value) or RESET (__RESOLUTION__ is invalid) 00902 */ 00903 #define IS_ADC_RESOLUTION_8_6_BITS(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_8B) || \ 00904 ((__RESOLUTION__) == ADC_RESOLUTION_6B) ) 00905 00906 /** 00907 * @brief Verify the ADC converted data alignment. 00908 * @param __ALIGN__ programmed ADC converted data alignment. 00909 * @retval SET (__ALIGN__ is a valid value) or RESET (__ALIGN__ is invalid) 00910 */ 00911 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \ 00912 ((__ALIGN__) == ADC_DATAALIGN_LEFT) ) 00913 00914 /** 00915 * @brief Verify the ADC scan mode. 00916 * @param __SCAN_MODE__ programmed ADC scan mode. 00917 * @retval SET (__SCAN_MODE__ is valid) or RESET (__SCAN_MODE__ is invalid) 00918 */ 00919 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \ 00920 ((__SCAN_MODE__) == ADC_SCAN_ENABLE) ) 00921 00922 /** 00923 * @brief Verify the ADC edge trigger setting for regular group. 00924 * @param __EDGE__ programmed ADC edge trigger setting. 00925 * @retval SET (__EDGE__ is a valid value) or RESET (__EDGE__ is invalid) 00926 */ 00927 #define IS_ADC_EXTTRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \ 00928 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \ 00929 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \ 00930 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING) ) 00931 00932 /** 00933 * @brief Verify the ADC regular conversions external trigger. 00934 * @param __HANDLE__ ADC handle 00935 * @param __REGTRIG__ programmed ADC regular conversions external trigger. 00936 * @retval SET (__REGTRIG__ is a valid value) or RESET (__REGTRIG__ is invalid) 00937 */ 00938 #define IS_ADC_EXTTRIG(__HANDLE__, __REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC1) || \ 00939 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC2) || \ 00940 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_CC3) || \ 00941 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_CC2) || \ 00942 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_TRGO) || \ 00943 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_CC4) || \ 00944 ((__REGTRIG__) == ADC_EXTERNALTRIG_EXT_IT11) || \ 00945 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO) || \ 00946 ((__REGTRIG__) == ADC_EXTERNALTRIG_T8_TRGO2) || \ 00947 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO) || \ 00948 ((__REGTRIG__) == ADC_EXTERNALTRIG_T1_TRGO2) || \ 00949 ((__REGTRIG__) == ADC_EXTERNALTRIG_T2_TRGO) || \ 00950 ((__REGTRIG__) == ADC_EXTERNALTRIG_T4_TRGO) || \ 00951 ((__REGTRIG__) == ADC_EXTERNALTRIG_T6_TRGO) || \ 00952 ((__REGTRIG__) == ADC_EXTERNALTRIG_T15_TRGO) || \ 00953 ((__REGTRIG__) == ADC_EXTERNALTRIG_T3_CC4) || \ 00954 ((__REGTRIG__) == ADC_SOFTWARE_START) ) 00955 00956 /** 00957 * @brief Verify the ADC regular conversions check for converted data availability. 00958 * @param __EOC_SELECTION__ converted data availability check. 00959 * @retval SET (__EOC_SELECTION__ is a valid value) or RESET (__EOC_SELECTION__ is invalid) 00960 */ 00961 #define IS_ADC_EOC_SELECTION(__EOC_SELECTION__) (((__EOC_SELECTION__) == ADC_EOC_SINGLE_CONV) || \ 00962 ((__EOC_SELECTION__) == ADC_EOC_SEQ_CONV) ) 00963 00964 /** 00965 * @brief Verify the ADC regular conversions overrun handling. 00966 * @param __OVR__ ADC regular conversions overrun handling. 00967 * @retval SET (__OVR__ is a valid value) or RESET (__OVR__ is invalid) 00968 */ 00969 #define IS_ADC_OVERRUN(__OVR__) (((__OVR__) == ADC_OVR_DATA_PRESERVED) || \ 00970 ((__OVR__) == ADC_OVR_DATA_OVERWRITTEN) ) 00971 00972 /** 00973 * @brief Verify the ADC conversions sampling time. 00974 * @param __TIME__ ADC conversions sampling time. 00975 * @retval SET (__TIME__ is a valid value) or RESET (__TIME__ is invalid) 00976 */ 00977 #if defined(ADC_SMPR1_SMPPLUS) 00978 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 00979 ((__TIME__) == ADC_SAMPLETIME_3CYCLES_5) || \ 00980 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 00981 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 00982 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 00983 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 00984 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 00985 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 00986 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 00987 #else 00988 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_2CYCLES_5) || \ 00989 ((__TIME__) == ADC_SAMPLETIME_6CYCLES_5) || \ 00990 ((__TIME__) == ADC_SAMPLETIME_12CYCLES_5) || \ 00991 ((__TIME__) == ADC_SAMPLETIME_24CYCLES_5) || \ 00992 ((__TIME__) == ADC_SAMPLETIME_47CYCLES_5) || \ 00993 ((__TIME__) == ADC_SAMPLETIME_92CYCLES_5) || \ 00994 ((__TIME__) == ADC_SAMPLETIME_247CYCLES_5) || \ 00995 ((__TIME__) == ADC_SAMPLETIME_640CYCLES_5) ) 00996 #endif 00997 00998 /** 00999 * @brief Verify the ADC regular channel setting. 01000 * @param __CHANNEL__ programmed ADC regular channel. 01001 * @retval SET (__CHANNEL__ is valid) or RESET (__CHANNEL__ is invalid) 01002 */ 01003 #define IS_ADC_REGULAR_RANK(__CHANNEL__) (((__CHANNEL__) == ADC_REGULAR_RANK_1 ) || \ 01004 ((__CHANNEL__) == ADC_REGULAR_RANK_2 ) || \ 01005 ((__CHANNEL__) == ADC_REGULAR_RANK_3 ) || \ 01006 ((__CHANNEL__) == ADC_REGULAR_RANK_4 ) || \ 01007 ((__CHANNEL__) == ADC_REGULAR_RANK_5 ) || \ 01008 ((__CHANNEL__) == ADC_REGULAR_RANK_6 ) || \ 01009 ((__CHANNEL__) == ADC_REGULAR_RANK_7 ) || \ 01010 ((__CHANNEL__) == ADC_REGULAR_RANK_8 ) || \ 01011 ((__CHANNEL__) == ADC_REGULAR_RANK_9 ) || \ 01012 ((__CHANNEL__) == ADC_REGULAR_RANK_10) || \ 01013 ((__CHANNEL__) == ADC_REGULAR_RANK_11) || \ 01014 ((__CHANNEL__) == ADC_REGULAR_RANK_12) || \ 01015 ((__CHANNEL__) == ADC_REGULAR_RANK_13) || \ 01016 ((__CHANNEL__) == ADC_REGULAR_RANK_14) || \ 01017 ((__CHANNEL__) == ADC_REGULAR_RANK_15) || \ 01018 ((__CHANNEL__) == ADC_REGULAR_RANK_16) ) 01019 01020 /** 01021 * @} 01022 */ 01023 01024 01025 /* Private constants ---------------------------------------------------------*/ 01026 01027 /** @defgroup ADC_Private_Constants ADC Private Constants 01028 * @{ 01029 */ 01030 01031 /* Fixed timeout values for ADC conversion (including sampling time) */ 01032 /* Maximum sampling time is 640.5 ADC clock cycle (SMPx[2:0] = 0b111 */ 01033 /* Maximum conversion time is 12.5 + Maximum sampling time */ 01034 /* or 12.5 + 640.5 = 653 ADC clock cycles */ 01035 /* Minimum ADC Clock frequency is 0.14 MHz */ 01036 /* Maximum conversion time is */ 01037 /* 653 / 0.14 MHz = 4.66 ms */ 01038 #define ADC_STOP_CONVERSION_TIMEOUT ( 5U) /*!< ADC stop time-out value */ 01039 01040 /* Delay for temperature sensor stabilization time. */ 01041 /* Maximum delay is 120us (refer device datasheet, parameter tSTART). */ 01042 /* Unit: us */ 01043 #define ADC_TEMPSENSOR_DELAY_US (LL_ADC_DELAY_TEMPSENSOR_STAB_US) 01044 01045 /** 01046 * @} 01047 */ 01048 01049 /* Exported macro ------------------------------------------------------------*/ 01050 01051 /** @defgroup ADC_Exported_Macros ADC Exported Macros 01052 * @{ 01053 */ 01054 /* Macro for internal HAL driver usage, and possibly can be used into code of */ 01055 /* final user. */ 01056 01057 /** @defgroup ADC_HAL_EM_HANDLE_IT_FLAG HAL ADC macro to manage HAL ADC handle, IT and flags. 01058 * @{ 01059 */ 01060 01061 /** @brief Reset ADC handle state. 01062 * @param __HANDLE__ ADC handle 01063 * @retval None 01064 */ 01065 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 01066 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 01067 do{ \ 01068 (__HANDLE__)->State = HAL_ADC_STATE_RESET; \ 01069 (__HANDLE__)->MspInitCallback = NULL; \ 01070 (__HANDLE__)->MspDeInitCallback = NULL; \ 01071 } while(0) 01072 #else 01073 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) \ 01074 ((__HANDLE__)->State = HAL_ADC_STATE_RESET) 01075 #endif 01076 01077 /** 01078 * @brief Enable ADC interrupt. 01079 * @param __HANDLE__ ADC handle 01080 * @param __INTERRUPT__ ADC Interrupt 01081 * This parameter can be one of the following values: 01082 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 01083 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 01084 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 01085 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 01086 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 01087 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 01088 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 01089 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 01090 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 01091 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 01092 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 01093 * @retval None 01094 */ 01095 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ 01096 (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__)) 01097 01098 /** 01099 * @brief Disable ADC interrupt. 01100 * @param __HANDLE__ ADC handle 01101 * @param __INTERRUPT__ ADC Interrupt 01102 * This parameter can be one of the following values: 01103 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 01104 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 01105 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 01106 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 01107 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 01108 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 01109 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 01110 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 01111 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 01112 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 01113 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 01114 * @retval None 01115 */ 01116 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ 01117 (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__)) 01118 01119 /** @brief Checks if the specified ADC interrupt source is enabled or disabled. 01120 * @param __HANDLE__ ADC handle 01121 * @param __INTERRUPT__ ADC interrupt source to check 01122 * This parameter can be one of the following values: 01123 * @arg @ref ADC_IT_RDY ADC Ready interrupt source 01124 * @arg @ref ADC_IT_EOSMP ADC End of Sampling interrupt source 01125 * @arg @ref ADC_IT_EOC ADC End of Regular Conversion interrupt source 01126 * @arg @ref ADC_IT_EOS ADC End of Regular sequence of Conversions interrupt source 01127 * @arg @ref ADC_IT_OVR ADC overrun interrupt source 01128 * @arg @ref ADC_IT_JEOC ADC End of Injected Conversion interrupt source 01129 * @arg @ref ADC_IT_JEOS ADC End of Injected sequence of Conversions interrupt source 01130 * @arg @ref ADC_IT_AWD1 ADC Analog watchdog 1 interrupt source (main analog watchdog) 01131 * @arg @ref ADC_IT_AWD2 ADC Analog watchdog 2 interrupt source (additional analog watchdog) 01132 * @arg @ref ADC_IT_AWD3 ADC Analog watchdog 3 interrupt source (additional analog watchdog) 01133 * @arg @ref ADC_IT_JQOVF ADC Injected Context Queue Overflow interrupt source. 01134 * @retval State of interruption (SET or RESET) 01135 */ 01136 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ 01137 (((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) 01138 01139 /** 01140 * @brief Check whether the specified ADC flag is set or not. 01141 * @param __HANDLE__ ADC handle 01142 * @param __FLAG__ ADC flag 01143 * This parameter can be one of the following values: 01144 * @arg @ref ADC_FLAG_RDY ADC Ready flag 01145 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 01146 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 01147 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 01148 * @arg @ref ADC_FLAG_OVR ADC overrun flag 01149 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 01150 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 01151 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 01152 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 01153 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 01154 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 01155 * @retval State of flag (TRUE or FALSE). 01156 */ 01157 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) \ 01158 ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__)) 01159 01160 /** 01161 * @brief Clear the specified ADC flag. 01162 * @param __HANDLE__ ADC handle 01163 * @param __FLAG__ ADC flag 01164 * This parameter can be one of the following values: 01165 * @arg @ref ADC_FLAG_RDY ADC Ready flag 01166 * @arg @ref ADC_FLAG_EOSMP ADC End of Sampling flag 01167 * @arg @ref ADC_FLAG_EOC ADC End of Regular Conversion flag 01168 * @arg @ref ADC_FLAG_EOS ADC End of Regular sequence of Conversions flag 01169 * @arg @ref ADC_FLAG_OVR ADC overrun flag 01170 * @arg @ref ADC_FLAG_JEOC ADC End of Injected Conversion flag 01171 * @arg @ref ADC_FLAG_JEOS ADC End of Injected sequence of Conversions flag 01172 * @arg @ref ADC_FLAG_AWD1 ADC Analog watchdog 1 flag (main analog watchdog) 01173 * @arg @ref ADC_FLAG_AWD2 ADC Analog watchdog 2 flag (additional analog watchdog) 01174 * @arg @ref ADC_FLAG_AWD3 ADC Analog watchdog 3 flag (additional analog watchdog) 01175 * @arg @ref ADC_FLAG_JQOVF ADC Injected Context Queue Overflow flag. 01176 * @retval None 01177 */ 01178 /* Note: bit cleared bit by writing 1 (writing 0 has no effect on any bit of register ISR) */ 01179 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) \ 01180 (((__HANDLE__)->Instance->ISR) = (__FLAG__)) 01181 01182 /** 01183 * @} 01184 */ 01185 01186 /** @defgroup ADC_HAL_EM_HELPER_MACRO HAL ADC helper macro 01187 * @{ 01188 */ 01189 01190 /** 01191 * @brief Helper macro to get ADC channel number in decimal format 01192 * from literals ADC_CHANNEL_x. 01193 * @note Example: 01194 * __HAL_ADC_CHANNEL_TO_DECIMAL_NB(ADC_CHANNEL_4) 01195 * will return decimal number "4". 01196 * @note The input can be a value from functions where a channel 01197 * number is returned, either defined with number 01198 * or with bitfield (only one bit must be set). 01199 * @param __CHANNEL__ This parameter can be one of the following values: 01200 * @arg @ref ADC_CHANNEL_0 01201 * @arg @ref ADC_CHANNEL_1 (7) 01202 * @arg @ref ADC_CHANNEL_2 (7) 01203 * @arg @ref ADC_CHANNEL_3 (7) 01204 * @arg @ref ADC_CHANNEL_4 (7) 01205 * @arg @ref ADC_CHANNEL_5 (7) 01206 * @arg @ref ADC_CHANNEL_6 01207 * @arg @ref ADC_CHANNEL_7 01208 * @arg @ref ADC_CHANNEL_8 01209 * @arg @ref ADC_CHANNEL_9 01210 * @arg @ref ADC_CHANNEL_10 01211 * @arg @ref ADC_CHANNEL_11 01212 * @arg @ref ADC_CHANNEL_12 01213 * @arg @ref ADC_CHANNEL_13 01214 * @arg @ref ADC_CHANNEL_14 01215 * @arg @ref ADC_CHANNEL_15 01216 * @arg @ref ADC_CHANNEL_16 01217 * @arg @ref ADC_CHANNEL_17 01218 * @arg @ref ADC_CHANNEL_18 01219 * @arg @ref ADC_CHANNEL_VREFINT (1) 01220 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 01221 * @arg @ref ADC_CHANNEL_VBAT (4) 01222 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 01223 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 01224 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01225 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01226 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01227 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01228 * 01229 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01230 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01231 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01232 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01233 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01234 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01235 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01236 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01237 * @retval Value between Min_Data=0 and Max_Data=18 01238 */ 01239 #define __HAL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 01240 __LL_ADC_CHANNEL_TO_DECIMAL_NB((__CHANNEL__)) 01241 01242 /** 01243 * @brief Helper macro to get ADC channel in literal format ADC_CHANNEL_x 01244 * from number in decimal format. 01245 * @note Example: 01246 * __HAL_ADC_DECIMAL_NB_TO_CHANNEL(4) 01247 * will return a data equivalent to "ADC_CHANNEL_4". 01248 * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 01249 * @retval Returned value can be one of the following values: 01250 * @arg @ref ADC_CHANNEL_0 01251 * @arg @ref ADC_CHANNEL_1 (7) 01252 * @arg @ref ADC_CHANNEL_2 (7) 01253 * @arg @ref ADC_CHANNEL_3 (7) 01254 * @arg @ref ADC_CHANNEL_4 (7) 01255 * @arg @ref ADC_CHANNEL_5 (7) 01256 * @arg @ref ADC_CHANNEL_6 01257 * @arg @ref ADC_CHANNEL_7 01258 * @arg @ref ADC_CHANNEL_8 01259 * @arg @ref ADC_CHANNEL_9 01260 * @arg @ref ADC_CHANNEL_10 01261 * @arg @ref ADC_CHANNEL_11 01262 * @arg @ref ADC_CHANNEL_12 01263 * @arg @ref ADC_CHANNEL_13 01264 * @arg @ref ADC_CHANNEL_14 01265 * @arg @ref ADC_CHANNEL_15 01266 * @arg @ref ADC_CHANNEL_16 01267 * @arg @ref ADC_CHANNEL_17 01268 * @arg @ref ADC_CHANNEL_18 01269 * @arg @ref ADC_CHANNEL_VREFINT (1) 01270 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 01271 * @arg @ref ADC_CHANNEL_VBAT (4) 01272 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 01273 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 01274 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01275 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01276 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01277 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01278 * 01279 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01280 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01281 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01282 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01283 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01284 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01285 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01286 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)).\n 01287 * (1, 2, 3, 4) For ADC channel read back from ADC register, 01288 * comparison with internal channel parameter to be done 01289 * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). 01290 */ 01291 #define __HAL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 01292 __LL_ADC_DECIMAL_NB_TO_CHANNEL((__DECIMAL_NB__)) 01293 01294 /** 01295 * @brief Helper macro to determine whether the selected channel 01296 * corresponds to literal definitions of driver. 01297 * @note The different literal definitions of ADC channels are: 01298 * - ADC internal channel: 01299 * ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ... 01300 * - ADC external channel (channel connected to a GPIO pin): 01301 * ADC_CHANNEL_1, ADC_CHANNEL_2, ... 01302 * @note The channel parameter must be a value defined from literal 01303 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 01304 * ADC_CHANNEL_TEMPSENSOR, ...), 01305 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...), 01306 * must not be a value from functions where a channel number is 01307 * returned from ADC registers, 01308 * because internal and external channels share the same channel 01309 * number in ADC registers. The differentiation is made only with 01310 * parameters definitions of driver. 01311 * @param __CHANNEL__ This parameter can be one of the following values: 01312 * @arg @ref ADC_CHANNEL_0 01313 * @arg @ref ADC_CHANNEL_1 (7) 01314 * @arg @ref ADC_CHANNEL_2 (7) 01315 * @arg @ref ADC_CHANNEL_3 (7) 01316 * @arg @ref ADC_CHANNEL_4 (7) 01317 * @arg @ref ADC_CHANNEL_5 (7) 01318 * @arg @ref ADC_CHANNEL_6 01319 * @arg @ref ADC_CHANNEL_7 01320 * @arg @ref ADC_CHANNEL_8 01321 * @arg @ref ADC_CHANNEL_9 01322 * @arg @ref ADC_CHANNEL_10 01323 * @arg @ref ADC_CHANNEL_11 01324 * @arg @ref ADC_CHANNEL_12 01325 * @arg @ref ADC_CHANNEL_13 01326 * @arg @ref ADC_CHANNEL_14 01327 * @arg @ref ADC_CHANNEL_15 01328 * @arg @ref ADC_CHANNEL_16 01329 * @arg @ref ADC_CHANNEL_17 01330 * @arg @ref ADC_CHANNEL_18 01331 * @arg @ref ADC_CHANNEL_VREFINT (1) 01332 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 01333 * @arg @ref ADC_CHANNEL_VBAT (4) 01334 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 01335 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 01336 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01337 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01338 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01339 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01340 * 01341 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01342 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01343 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01344 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01345 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01346 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01347 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01348 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01349 * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). 01350 * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. 01351 */ 01352 #define __HAL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ 01353 __LL_ADC_IS_CHANNEL_INTERNAL((__CHANNEL__)) 01354 01355 /** 01356 * @brief Helper macro to convert a channel defined from parameter 01357 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 01358 * ADC_CHANNEL_TEMPSENSOR, ...), 01359 * to its equivalent parameter definition of a ADC external channel 01360 * (ADC_CHANNEL_1, ADC_CHANNEL_2, ...). 01361 * @note The channel parameter can be, additionally to a value 01362 * defined from parameter definition of a ADC internal channel 01363 * (ADC_CHANNEL_VREFINT, ADC_CHANNEL_TEMPSENSOR, ...), 01364 * a value defined from parameter definition of 01365 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 01366 * or a value from functions where a channel number is returned 01367 * from ADC registers. 01368 * @param __CHANNEL__ This parameter can be one of the following values: 01369 * @arg @ref ADC_CHANNEL_0 01370 * @arg @ref ADC_CHANNEL_1 (7) 01371 * @arg @ref ADC_CHANNEL_2 (7) 01372 * @arg @ref ADC_CHANNEL_3 (7) 01373 * @arg @ref ADC_CHANNEL_4 (7) 01374 * @arg @ref ADC_CHANNEL_5 (7) 01375 * @arg @ref ADC_CHANNEL_6 01376 * @arg @ref ADC_CHANNEL_7 01377 * @arg @ref ADC_CHANNEL_8 01378 * @arg @ref ADC_CHANNEL_9 01379 * @arg @ref ADC_CHANNEL_10 01380 * @arg @ref ADC_CHANNEL_11 01381 * @arg @ref ADC_CHANNEL_12 01382 * @arg @ref ADC_CHANNEL_13 01383 * @arg @ref ADC_CHANNEL_14 01384 * @arg @ref ADC_CHANNEL_15 01385 * @arg @ref ADC_CHANNEL_16 01386 * @arg @ref ADC_CHANNEL_17 01387 * @arg @ref ADC_CHANNEL_18 01388 * @arg @ref ADC_CHANNEL_VREFINT (1) 01389 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 01390 * @arg @ref ADC_CHANNEL_VBAT (4) 01391 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 01392 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 01393 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01394 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01395 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01396 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01397 * 01398 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01399 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01400 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01401 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01402 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01403 * (6) On STM32L4, parameter available on devices with several ADC instances.\n 01404 * (7) On STM32L4, fast channel (0.188 us for 12-bit resolution (ADC conversion rate up to 5.33 Ms/s)). 01405 * Other channels are slow channels (0.238 us for 12-bit resolution (ADC conversion rate up to 4.21 Ms/s)). 01406 * @retval Returned value can be one of the following values: 01407 * @arg @ref ADC_CHANNEL_0 01408 * @arg @ref ADC_CHANNEL_1 01409 * @arg @ref ADC_CHANNEL_2 01410 * @arg @ref ADC_CHANNEL_3 01411 * @arg @ref ADC_CHANNEL_4 01412 * @arg @ref ADC_CHANNEL_5 01413 * @arg @ref ADC_CHANNEL_6 01414 * @arg @ref ADC_CHANNEL_7 01415 * @arg @ref ADC_CHANNEL_8 01416 * @arg @ref ADC_CHANNEL_9 01417 * @arg @ref ADC_CHANNEL_10 01418 * @arg @ref ADC_CHANNEL_11 01419 * @arg @ref ADC_CHANNEL_12 01420 * @arg @ref ADC_CHANNEL_13 01421 * @arg @ref ADC_CHANNEL_14 01422 * @arg @ref ADC_CHANNEL_15 01423 * @arg @ref ADC_CHANNEL_16 01424 * @arg @ref ADC_CHANNEL_17 01425 * @arg @ref ADC_CHANNEL_18 01426 */ 01427 #define __HAL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ 01428 __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL((__CHANNEL__)) 01429 01430 /** 01431 * @brief Helper macro to determine whether the internal channel 01432 * selected is available on the ADC instance selected. 01433 * @note The channel parameter must be a value defined from parameter 01434 * definition of a ADC internal channel (ADC_CHANNEL_VREFINT, 01435 * ADC_CHANNEL_TEMPSENSOR, ...), 01436 * must not be a value defined from parameter definition of 01437 * ADC external channel (ADC_CHANNEL_1, ADC_CHANNEL_2, ...) 01438 * or a value from functions where a channel number is 01439 * returned from ADC registers, 01440 * because internal and external channels share the same channel 01441 * number in ADC registers. The differentiation is made only with 01442 * parameters definitions of driver. 01443 * @param __ADC_INSTANCE__ ADC instance 01444 * @param __CHANNEL__ This parameter can be one of the following values: 01445 * @arg @ref ADC_CHANNEL_VREFINT (1) 01446 * @arg @ref ADC_CHANNEL_TEMPSENSOR (4) 01447 * @arg @ref ADC_CHANNEL_VBAT (4) 01448 * @arg @ref ADC_CHANNEL_DAC1CH1 (5) 01449 * @arg @ref ADC_CHANNEL_DAC1CH2 (5) 01450 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC2 (2)(6) 01451 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC2 (2)(6) 01452 * @arg @ref ADC_CHANNEL_DAC1CH1_ADC3 (3)(6) 01453 * @arg @ref ADC_CHANNEL_DAC1CH2_ADC3 (3)(6) 01454 * 01455 * (1) On STM32L4, parameter available only on ADC instance: ADC1.\n 01456 * (2) On STM32L4, parameter available only on ADC instance: ADC2.\n 01457 * (3) On STM32L4, parameter available only on ADC instance: ADC3.\n 01458 * (4) On STM32L4, parameter available only on ADC instances: ADC1, ADC3.\n 01459 * (5) On STM32L4, parameter available on devices with only 1 ADC instance.\n 01460 * (6) On STM32L4, parameter available on devices with several ADC instances. 01461 * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. 01462 * Value "1" if the internal channel selected is available on the ADC instance selected. 01463 */ 01464 #define __HAL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ 01465 __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE((__ADC_INSTANCE__), (__CHANNEL__)) 01466 01467 #if defined(ADC_MULTIMODE_SUPPORT) 01468 /** 01469 * @brief Helper macro to get the ADC multimode conversion data of ADC master 01470 * or ADC slave from raw value with both ADC conversion data concatenated. 01471 * @note This macro is intended to be used when multimode transfer by DMA 01472 * is enabled: refer to function @ref LL_ADC_SetMultiDMATransfer(). 01473 * In this case the transferred data need to processed with this macro 01474 * to separate the conversion data of ADC master and ADC slave. 01475 * @param __ADC_MULTI_MASTER_SLAVE__ This parameter can be one of the following values: 01476 * @arg @ref LL_ADC_MULTI_MASTER 01477 * @arg @ref LL_ADC_MULTI_SLAVE 01478 * @param __ADC_MULTI_CONV_DATA__ Value between Min_Data=0x000 and Max_Data=0xFFF 01479 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01480 */ 01481 #define __HAL_ADC_MULTI_CONV_DATA_MASTER_SLAVE(__ADC_MULTI_MASTER_SLAVE__, __ADC_MULTI_CONV_DATA__) \ 01482 __LL_ADC_MULTI_CONV_DATA_MASTER_SLAVE((__ADC_MULTI_MASTER_SLAVE__), (__ADC_MULTI_CONV_DATA__)) 01483 #endif 01484 01485 /** 01486 * @brief Helper macro to select the ADC common instance 01487 * to which is belonging the selected ADC instance. 01488 * @note ADC common register instance can be used for: 01489 * - Set parameters common to several ADC instances 01490 * - Multimode (for devices with several ADC instances) 01491 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01492 * @param __ADCx__ ADC instance 01493 * @retval ADC common register instance 01494 */ 01495 #define __HAL_ADC_COMMON_INSTANCE(__ADCx__) \ 01496 __LL_ADC_COMMON_INSTANCE((__ADCx__)) 01497 01498 /** 01499 * @brief Helper macro to check if all ADC instances sharing the same 01500 * ADC common instance are disabled. 01501 * @note This check is required by functions with setting conditioned to 01502 * ADC state: 01503 * All ADC instances of the ADC common group must be disabled. 01504 * Refer to functions having argument "ADCxy_COMMON" as parameter. 01505 * @note On devices with only 1 ADC common instance, parameter of this macro 01506 * is useless and can be ignored (parameter kept for compatibility 01507 * with devices featuring several ADC common instances). 01508 * @param __ADCXY_COMMON__ ADC common instance 01509 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) 01510 * @retval Value "0" if all ADC instances sharing the same ADC common instance 01511 * are disabled. 01512 * Value "1" if at least one ADC instance sharing the same ADC common instance 01513 * is enabled. 01514 */ 01515 #define __HAL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ 01516 __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE((__ADCXY_COMMON__)) 01517 01518 /** 01519 * @brief Helper macro to define the ADC conversion data full-scale digital 01520 * value corresponding to the selected ADC resolution. 01521 * @note ADC conversion data full-scale corresponds to voltage range 01522 * determined by analog voltage references Vref+ and Vref- 01523 * (refer to reference manual). 01524 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01525 * @arg @ref ADC_RESOLUTION_12B 01526 * @arg @ref ADC_RESOLUTION_10B 01527 * @arg @ref ADC_RESOLUTION_8B 01528 * @arg @ref ADC_RESOLUTION_6B 01529 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 01530 */ 01531 #define __HAL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ 01532 __LL_ADC_DIGITAL_SCALE((__ADC_RESOLUTION__)) 01533 01534 /** 01535 * @brief Helper macro to convert the ADC conversion data from 01536 * a resolution to another resolution. 01537 * @param __DATA__ ADC conversion data to be converted 01538 * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted 01539 * This parameter can be one of the following values: 01540 * @arg @ref ADC_RESOLUTION_12B 01541 * @arg @ref ADC_RESOLUTION_10B 01542 * @arg @ref ADC_RESOLUTION_8B 01543 * @arg @ref ADC_RESOLUTION_6B 01544 * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion 01545 * This parameter can be one of the following values: 01546 * @arg @ref ADC_RESOLUTION_12B 01547 * @arg @ref ADC_RESOLUTION_10B 01548 * @arg @ref ADC_RESOLUTION_8B 01549 * @arg @ref ADC_RESOLUTION_6B 01550 * @retval ADC conversion data to the requested resolution 01551 */ 01552 #define __HAL_ADC_CONVERT_DATA_RESOLUTION(__DATA__,\ 01553 __ADC_RESOLUTION_CURRENT__,\ 01554 __ADC_RESOLUTION_TARGET__) \ 01555 __LL_ADC_CONVERT_DATA_RESOLUTION((__DATA__),\ 01556 (__ADC_RESOLUTION_CURRENT__),\ 01557 (__ADC_RESOLUTION_TARGET__)) 01558 01559 /** 01560 * @brief Helper macro to calculate the voltage (unit: mVolt) 01561 * corresponding to a ADC conversion data (unit: digital value). 01562 * @note Analog reference voltage (Vref+) must be either known from 01563 * user board environment or can be calculated using ADC measurement 01564 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01565 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 01566 * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) 01567 * (unit: digital value). 01568 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01569 * @arg @ref ADC_RESOLUTION_12B 01570 * @arg @ref ADC_RESOLUTION_10B 01571 * @arg @ref ADC_RESOLUTION_8B 01572 * @arg @ref ADC_RESOLUTION_6B 01573 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 01574 */ 01575 #define __HAL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,\ 01576 __ADC_DATA__,\ 01577 __ADC_RESOLUTION__) \ 01578 __LL_ADC_CALC_DATA_TO_VOLTAGE((__VREFANALOG_VOLTAGE__),\ 01579 (__ADC_DATA__),\ 01580 (__ADC_RESOLUTION__)) 01581 01582 /** 01583 * @brief Helper macro to calculate analog reference voltage (Vref+) 01584 * (unit: mVolt) from ADC conversion data of internal voltage 01585 * reference VrefInt. 01586 * @note Computation is using VrefInt calibration value 01587 * stored in system memory for each device during production. 01588 * @note This voltage depends on user board environment: voltage level 01589 * connected to pin Vref+. 01590 * On devices with small package, the pin Vref+ is not present 01591 * and internally bonded to pin Vdda. 01592 * @note On this STM32 serie, calibration data of internal voltage reference 01593 * VrefInt corresponds to a resolution of 12 bits, 01594 * this is the recommended ADC resolution to convert voltage of 01595 * internal voltage reference VrefInt. 01596 * Otherwise, this macro performs the processing to scale 01597 * ADC conversion data to 12 bits. 01598 * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) 01599 * of internal voltage reference VrefInt (unit: digital value). 01600 * @param __ADC_RESOLUTION__ This parameter can be one of the following values: 01601 * @arg @ref ADC_RESOLUTION_12B 01602 * @arg @ref ADC_RESOLUTION_10B 01603 * @arg @ref ADC_RESOLUTION_8B 01604 * @arg @ref ADC_RESOLUTION_6B 01605 * @retval Analog reference voltage (unit: mV) 01606 */ 01607 #define __HAL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,\ 01608 __ADC_RESOLUTION__) \ 01609 __LL_ADC_CALC_VREFANALOG_VOLTAGE((__VREFINT_ADC_DATA__),\ 01610 (__ADC_RESOLUTION__)) 01611 01612 /** 01613 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 01614 * from ADC conversion data of internal temperature sensor. 01615 * @note Computation is using temperature sensor calibration values 01616 * stored in system memory for each device during production. 01617 * @note Calculation formula: 01618 * Temperature = ((TS_ADC_DATA - TS_CAL1) 01619 * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) 01620 * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP 01621 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 01622 * Avg_Slope = (TS_CAL2 - TS_CAL1) 01623 * / (TS_CAL2_TEMP - TS_CAL1_TEMP) 01624 * TS_CAL1 = equivalent TS_ADC_DATA at temperature 01625 * TEMP_DEGC_CAL1 (calibrated in factory) 01626 * TS_CAL2 = equivalent TS_ADC_DATA at temperature 01627 * TEMP_DEGC_CAL2 (calibrated in factory) 01628 * Caution: Calculation relevancy under reserve that calibration 01629 * parameters are correct (address and data). 01630 * To calculate temperature using temperature sensor 01631 * datasheet typical values (generic values less, therefore 01632 * less accurate than calibrated values), 01633 * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). 01634 * @note As calculation input, the analog reference voltage (Vref+) must be 01635 * defined as it impacts the ADC LSB equivalent voltage. 01636 * @note Analog reference voltage (Vref+) must be either known from 01637 * user board environment or can be calculated using ADC measurement 01638 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01639 * @note On this STM32 serie, calibration data of temperature sensor 01640 * corresponds to a resolution of 12 bits, 01641 * this is the recommended ADC resolution to convert voltage of 01642 * temperature sensor. 01643 * Otherwise, this macro performs the processing to scale 01644 * ADC conversion data to 12 bits. 01645 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 01646 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal 01647 * temperature sensor (unit: digital value). 01648 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature 01649 * sensor voltage has been measured. 01650 * This parameter can be one of the following values: 01651 * @arg @ref ADC_RESOLUTION_12B 01652 * @arg @ref ADC_RESOLUTION_10B 01653 * @arg @ref ADC_RESOLUTION_8B 01654 * @arg @ref ADC_RESOLUTION_6B 01655 * @retval Temperature (unit: degree Celsius) 01656 */ 01657 #define __HAL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ 01658 __TEMPSENSOR_ADC_DATA__,\ 01659 __ADC_RESOLUTION__) \ 01660 __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ 01661 (__TEMPSENSOR_ADC_DATA__),\ 01662 (__ADC_RESOLUTION__)) 01663 01664 /** 01665 * @brief Helper macro to calculate the temperature (unit: degree Celsius) 01666 * from ADC conversion data of internal temperature sensor. 01667 * @note Computation is using temperature sensor typical values 01668 * (refer to device datasheet). 01669 * @note Calculation formula: 01670 * Temperature = (TS_TYP_CALx_VOLT(uV) - TS_ADC_DATA * Conversion_uV) 01671 * / Avg_Slope + CALx_TEMP 01672 * with TS_ADC_DATA = temperature sensor raw data measured by ADC 01673 * (unit: digital value) 01674 * Avg_Slope = temperature sensor slope 01675 * (unit: uV/Degree Celsius) 01676 * TS_TYP_CALx_VOLT = temperature sensor digital value at 01677 * temperature CALx_TEMP (unit: mV) 01678 * Caution: Calculation relevancy under reserve the temperature sensor 01679 * of the current device has characteristics in line with 01680 * datasheet typical values. 01681 * If temperature sensor calibration values are available on 01682 * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), 01683 * temperature calculation will be more accurate using 01684 * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). 01685 * @note As calculation input, the analog reference voltage (Vref+) must be 01686 * defined as it impacts the ADC LSB equivalent voltage. 01687 * @note Analog reference voltage (Vref+) must be either known from 01688 * user board environment or can be calculated using ADC measurement 01689 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 01690 * @note ADC measurement data must correspond to a resolution of 12bits 01691 * (full scale digital value 4095). If not the case, the data must be 01692 * preliminarily rescaled to an equivalent resolution of 12 bits. 01693 * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). 01694 * On STM32L4, refer to device datasheet parameter "Avg_Slope". 01695 * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). 01696 * On STM32L4, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). 01697 * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) 01698 * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) 01699 * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). 01700 * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. 01701 * This parameter can be one of the following values: 01702 * @arg @ref ADC_RESOLUTION_12B 01703 * @arg @ref ADC_RESOLUTION_10B 01704 * @arg @ref ADC_RESOLUTION_8B 01705 * @arg @ref ADC_RESOLUTION_6B 01706 * @retval Temperature (unit: degree Celsius) 01707 */ 01708 #define __HAL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ 01709 __TEMPSENSOR_TYP_CALX_V__,\ 01710 __TEMPSENSOR_CALX_TEMP__,\ 01711 __VREFANALOG_VOLTAGE__,\ 01712 __TEMPSENSOR_ADC_DATA__,\ 01713 __ADC_RESOLUTION__) \ 01714 __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS((__TEMPSENSOR_TYP_AVGSLOPE__),\ 01715 (__TEMPSENSOR_TYP_CALX_V__),\ 01716 (__TEMPSENSOR_CALX_TEMP__),\ 01717 (__VREFANALOG_VOLTAGE__),\ 01718 (__TEMPSENSOR_ADC_DATA__),\ 01719 (__ADC_RESOLUTION__)) 01720 01721 /** 01722 * @} 01723 */ 01724 01725 /** 01726 * @} 01727 */ 01728 01729 /* Include ADC HAL Extended module */ 01730 #include "stm32l4xx_hal_adc_ex.h" 01731 01732 /* Exported functions --------------------------------------------------------*/ 01733 /** @addtogroup ADC_Exported_Functions 01734 * @{ 01735 */ 01736 01737 /** @addtogroup ADC_Exported_Functions_Group1 01738 * @brief Initialization and Configuration functions 01739 * @{ 01740 */ 01741 /* Initialization and de-initialization functions ****************************/ 01742 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc); 01743 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc); 01744 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc); 01745 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc); 01746 01747 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 01748 /* Callbacks Register/UnRegister functions ***********************************/ 01749 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback); 01750 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID); 01751 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 01752 /** 01753 * @} 01754 */ 01755 01756 /** @addtogroup ADC_Exported_Functions_Group2 01757 * @brief IO operation functions 01758 * @{ 01759 */ 01760 /* IO operation functions *****************************************************/ 01761 01762 /* Blocking mode: Polling */ 01763 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc); 01764 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc); 01765 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout); 01766 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout); 01767 01768 /* Non-blocking mode: Interruption */ 01769 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc); 01770 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc); 01771 01772 /* Non-blocking mode: DMA */ 01773 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length); 01774 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc); 01775 01776 /* ADC retrieve conversion value intended to be used with polling or interruption */ 01777 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc); 01778 01779 /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ 01780 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc); 01781 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc); 01782 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc); 01783 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc); 01784 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); 01785 /** 01786 * @} 01787 */ 01788 01789 /** @addtogroup ADC_Exported_Functions_Group3 Peripheral Control functions 01790 * @brief Peripheral Control functions 01791 * @{ 01792 */ 01793 /* Peripheral Control functions ***********************************************/ 01794 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig); 01795 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig); 01796 01797 /** 01798 * @} 01799 */ 01800 01801 /* Peripheral State functions *************************************************/ 01802 /** @addtogroup ADC_Exported_Functions_Group4 01803 * @{ 01804 */ 01805 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc); 01806 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); 01807 01808 /** 01809 * @} 01810 */ 01811 01812 /** 01813 * @} 01814 */ 01815 01816 /* Private functions -----------------------------------------------------------*/ 01817 /** @addtogroup ADC_Private_Functions ADC Private Functions 01818 * @{ 01819 */ 01820 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup); 01821 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc); 01822 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc); 01823 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma); 01824 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma); 01825 void ADC_DMAError(DMA_HandleTypeDef *hdma); 01826 01827 /** 01828 * @} 01829 */ 01830 01831 /** 01832 * @} 01833 */ 01834 01835 /** 01836 * @} 01837 */ 01838 01839 #ifdef __cplusplus 01840 } 01841 #endif 01842 01843 01844 #endif /* __STM32L4xx_HAL_ADC_H */ 01845 01846 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1