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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal.h 00004 * @author MCD Application Team 00005 * @brief This file contains all the functions prototypes for the HAL 00006 * module driver. 00007 ****************************************************************************** 00008 * @attention 00009 * 00010 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00011 * 00012 * Redistribution and use in source and binary forms, with or without modification, 00013 * are permitted provided that the following conditions are met: 00014 * 1. Redistributions of source code must retain the above copyright notice, 00015 * this list of conditions and the following disclaimer. 00016 * 2. Redistributions in binary form must reproduce the above copyright notice, 00017 * this list of conditions and the following disclaimer in the documentation 00018 * and/or other materials provided with the distribution. 00019 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00020 * may be used to endorse or promote products derived from this software 00021 * without specific prior written permission. 00022 * 00023 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00024 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00025 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00026 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00027 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00028 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00029 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00030 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00031 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00032 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00033 * 00034 ****************************************************************************** 00035 */ 00036 00037 /* Define to prevent recursive inclusion -------------------------------------*/ 00038 #ifndef __STM32L4xx_HAL_H 00039 #define __STM32L4xx_HAL_H 00040 00041 #ifdef __cplusplus 00042 extern "C" { 00043 #endif 00044 00045 /* Includes ------------------------------------------------------------------*/ 00046 #include "stm32l4xx_hal_conf.h" 00047 00048 /** @addtogroup STM32L4xx_HAL_Driver 00049 * @{ 00050 */ 00051 00052 /** @addtogroup HAL 00053 * @{ 00054 */ 00055 00056 /* Exported types ------------------------------------------------------------*/ 00057 /* Exported constants --------------------------------------------------------*/ 00058 /** @defgroup SYSCFG_Exported_Constants SYSCFG Exported Constants 00059 * @{ 00060 */ 00061 00062 /** @defgroup SYSCFG_BootMode Boot Mode 00063 * @{ 00064 */ 00065 #define SYSCFG_BOOT_MAINFLASH ((uint32_t)0x00000000) 00066 #define SYSCFG_BOOT_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 00067 00068 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00069 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00070 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00071 #define SYSCFG_BOOT_FMC SYSCFG_MEMRMP_MEM_MODE_1 00072 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 00073 /* STM32L496xx || STM32L4A6xx || */ 00074 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00075 00076 #define SYSCFG_BOOT_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) 00077 00078 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00079 #define SYSCFG_BOOT_OCTOPSPI1 (SYSCFG_MEMRMP_MEM_MODE_2) 00080 #define SYSCFG_BOOT_OCTOPSPI2 (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_0) 00081 #else 00082 #define SYSCFG_BOOT_QUADSPI (SYSCFG_MEMRMP_MEM_MODE_2 | SYSCFG_MEMRMP_MEM_MODE_1) 00083 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00084 00085 /** 00086 * @} 00087 */ 00088 00089 /** @defgroup SYSCFG_FPU_Interrupts FPU Interrupts 00090 * @{ 00091 */ 00092 #define SYSCFG_IT_FPU_IOC SYSCFG_CFGR1_FPU_IE_0 /*!< Floating Point Unit Invalid operation Interrupt */ 00093 #define SYSCFG_IT_FPU_DZC SYSCFG_CFGR1_FPU_IE_1 /*!< Floating Point Unit Divide-by-zero Interrupt */ 00094 #define SYSCFG_IT_FPU_UFC SYSCFG_CFGR1_FPU_IE_2 /*!< Floating Point Unit Underflow Interrupt */ 00095 #define SYSCFG_IT_FPU_OFC SYSCFG_CFGR1_FPU_IE_3 /*!< Floating Point Unit Overflow Interrupt */ 00096 #define SYSCFG_IT_FPU_IDC SYSCFG_CFGR1_FPU_IE_4 /*!< Floating Point Unit Input denormal Interrupt */ 00097 #define SYSCFG_IT_FPU_IXC SYSCFG_CFGR1_FPU_IE_5 /*!< Floating Point Unit Inexact Interrupt */ 00098 00099 /** 00100 * @} 00101 */ 00102 00103 /** @defgroup SYSCFG_SRAM2WRP SRAM2 Page Write protection (0 to 31) 00104 * @{ 00105 */ 00106 #define SYSCFG_SRAM2WRP_PAGE0 SYSCFG_SWPR_PAGE0 /*!< SRAM2 Write protection page 0 */ 00107 #define SYSCFG_SRAM2WRP_PAGE1 SYSCFG_SWPR_PAGE1 /*!< SRAM2 Write protection page 1 */ 00108 #define SYSCFG_SRAM2WRP_PAGE2 SYSCFG_SWPR_PAGE2 /*!< SRAM2 Write protection page 2 */ 00109 #define SYSCFG_SRAM2WRP_PAGE3 SYSCFG_SWPR_PAGE3 /*!< SRAM2 Write protection page 3 */ 00110 #define SYSCFG_SRAM2WRP_PAGE4 SYSCFG_SWPR_PAGE4 /*!< SRAM2 Write protection page 4 */ 00111 #define SYSCFG_SRAM2WRP_PAGE5 SYSCFG_SWPR_PAGE5 /*!< SRAM2 Write protection page 5 */ 00112 #define SYSCFG_SRAM2WRP_PAGE6 SYSCFG_SWPR_PAGE6 /*!< SRAM2 Write protection page 6 */ 00113 #define SYSCFG_SRAM2WRP_PAGE7 SYSCFG_SWPR_PAGE7 /*!< SRAM2 Write protection page 7 */ 00114 #define SYSCFG_SRAM2WRP_PAGE8 SYSCFG_SWPR_PAGE8 /*!< SRAM2 Write protection page 8 */ 00115 #define SYSCFG_SRAM2WRP_PAGE9 SYSCFG_SWPR_PAGE9 /*!< SRAM2 Write protection page 9 */ 00116 #define SYSCFG_SRAM2WRP_PAGE10 SYSCFG_SWPR_PAGE10 /*!< SRAM2 Write protection page 10 */ 00117 #define SYSCFG_SRAM2WRP_PAGE11 SYSCFG_SWPR_PAGE11 /*!< SRAM2 Write protection page 11 */ 00118 #define SYSCFG_SRAM2WRP_PAGE12 SYSCFG_SWPR_PAGE12 /*!< SRAM2 Write protection page 12 */ 00119 #define SYSCFG_SRAM2WRP_PAGE13 SYSCFG_SWPR_PAGE13 /*!< SRAM2 Write protection page 13 */ 00120 #define SYSCFG_SRAM2WRP_PAGE14 SYSCFG_SWPR_PAGE14 /*!< SRAM2 Write protection page 14 */ 00121 #define SYSCFG_SRAM2WRP_PAGE15 SYSCFG_SWPR_PAGE15 /*!< SRAM2 Write protection page 15 */ 00122 #if defined(SYSCFG_SWPR_PAGE31) 00123 #define SYSCFG_SRAM2WRP_PAGE16 SYSCFG_SWPR_PAGE16 /*!< SRAM2 Write protection page 16 */ 00124 #define SYSCFG_SRAM2WRP_PAGE17 SYSCFG_SWPR_PAGE17 /*!< SRAM2 Write protection page 17 */ 00125 #define SYSCFG_SRAM2WRP_PAGE18 SYSCFG_SWPR_PAGE18 /*!< SRAM2 Write protection page 18 */ 00126 #define SYSCFG_SRAM2WRP_PAGE19 SYSCFG_SWPR_PAGE19 /*!< SRAM2 Write protection page 19 */ 00127 #define SYSCFG_SRAM2WRP_PAGE20 SYSCFG_SWPR_PAGE20 /*!< SRAM2 Write protection page 20 */ 00128 #define SYSCFG_SRAM2WRP_PAGE21 SYSCFG_SWPR_PAGE21 /*!< SRAM2 Write protection page 21 */ 00129 #define SYSCFG_SRAM2WRP_PAGE22 SYSCFG_SWPR_PAGE22 /*!< SRAM2 Write protection page 22 */ 00130 #define SYSCFG_SRAM2WRP_PAGE23 SYSCFG_SWPR_PAGE23 /*!< SRAM2 Write protection page 23 */ 00131 #define SYSCFG_SRAM2WRP_PAGE24 SYSCFG_SWPR_PAGE24 /*!< SRAM2 Write protection page 24 */ 00132 #define SYSCFG_SRAM2WRP_PAGE25 SYSCFG_SWPR_PAGE25 /*!< SRAM2 Write protection page 25 */ 00133 #define SYSCFG_SRAM2WRP_PAGE26 SYSCFG_SWPR_PAGE26 /*!< SRAM2 Write protection page 26 */ 00134 #define SYSCFG_SRAM2WRP_PAGE27 SYSCFG_SWPR_PAGE27 /*!< SRAM2 Write protection page 27 */ 00135 #define SYSCFG_SRAM2WRP_PAGE28 SYSCFG_SWPR_PAGE28 /*!< SRAM2 Write protection page 28 */ 00136 #define SYSCFG_SRAM2WRP_PAGE29 SYSCFG_SWPR_PAGE29 /*!< SRAM2 Write protection page 29 */ 00137 #define SYSCFG_SRAM2WRP_PAGE30 SYSCFG_SWPR_PAGE30 /*!< SRAM2 Write protection page 30 */ 00138 #define SYSCFG_SRAM2WRP_PAGE31 SYSCFG_SWPR_PAGE31 /*!< SRAM2 Write protection page 31 */ 00139 #endif /* SYSCFG_SWPR_PAGE31 */ 00140 00141 /** 00142 * @} 00143 */ 00144 00145 #if defined(SYSCFG_SWPR2_PAGE63) 00146 /** @defgroup SYSCFG_SRAM2WRP_32_63 SRAM2 Page Write protection (32 to 63) 00147 * @{ 00148 */ 00149 #define SYSCFG_SRAM2WRP_PAGE32 SYSCFG_SWPR2_PAGE32 /*!< SRAM2 Write protection page 32 */ 00150 #define SYSCFG_SRAM2WRP_PAGE33 SYSCFG_SWPR2_PAGE33 /*!< SRAM2 Write protection page 33 */ 00151 #define SYSCFG_SRAM2WRP_PAGE34 SYSCFG_SWPR2_PAGE34 /*!< SRAM2 Write protection page 34 */ 00152 #define SYSCFG_SRAM2WRP_PAGE35 SYSCFG_SWPR2_PAGE35 /*!< SRAM2 Write protection page 35 */ 00153 #define SYSCFG_SRAM2WRP_PAGE36 SYSCFG_SWPR2_PAGE36 /*!< SRAM2 Write protection page 36 */ 00154 #define SYSCFG_SRAM2WRP_PAGE37 SYSCFG_SWPR2_PAGE37 /*!< SRAM2 Write protection page 37 */ 00155 #define SYSCFG_SRAM2WRP_PAGE38 SYSCFG_SWPR2_PAGE38 /*!< SRAM2 Write protection page 38 */ 00156 #define SYSCFG_SRAM2WRP_PAGE39 SYSCFG_SWPR2_PAGE39 /*!< SRAM2 Write protection page 39 */ 00157 #define SYSCFG_SRAM2WRP_PAGE40 SYSCFG_SWPR2_PAGE40 /*!< SRAM2 Write protection page 40 */ 00158 #define SYSCFG_SRAM2WRP_PAGE41 SYSCFG_SWPR2_PAGE41 /*!< SRAM2 Write protection page 41 */ 00159 #define SYSCFG_SRAM2WRP_PAGE42 SYSCFG_SWPR2_PAGE42 /*!< SRAM2 Write protection page 42 */ 00160 #define SYSCFG_SRAM2WRP_PAGE43 SYSCFG_SWPR2_PAGE43 /*!< SRAM2 Write protection page 43 */ 00161 #define SYSCFG_SRAM2WRP_PAGE44 SYSCFG_SWPR2_PAGE44 /*!< SRAM2 Write protection page 44 */ 00162 #define SYSCFG_SRAM2WRP_PAGE45 SYSCFG_SWPR2_PAGE45 /*!< SRAM2 Write protection page 45 */ 00163 #define SYSCFG_SRAM2WRP_PAGE46 SYSCFG_SWPR2_PAGE46 /*!< SRAM2 Write protection page 46 */ 00164 #define SYSCFG_SRAM2WRP_PAGE47 SYSCFG_SWPR2_PAGE47 /*!< SRAM2 Write protection page 47 */ 00165 #define SYSCFG_SRAM2WRP_PAGE48 SYSCFG_SWPR2_PAGE48 /*!< SRAM2 Write protection page 48 */ 00166 #define SYSCFG_SRAM2WRP_PAGE49 SYSCFG_SWPR2_PAGE49 /*!< SRAM2 Write protection page 49 */ 00167 #define SYSCFG_SRAM2WRP_PAGE50 SYSCFG_SWPR2_PAGE50 /*!< SRAM2 Write protection page 50 */ 00168 #define SYSCFG_SRAM2WRP_PAGE51 SYSCFG_SWPR2_PAGE51 /*!< SRAM2 Write protection page 51 */ 00169 #define SYSCFG_SRAM2WRP_PAGE52 SYSCFG_SWPR2_PAGE52 /*!< SRAM2 Write protection page 52 */ 00170 #define SYSCFG_SRAM2WRP_PAGE53 SYSCFG_SWPR2_PAGE53 /*!< SRAM2 Write protection page 53 */ 00171 #define SYSCFG_SRAM2WRP_PAGE54 SYSCFG_SWPR2_PAGE54 /*!< SRAM2 Write protection page 54 */ 00172 #define SYSCFG_SRAM2WRP_PAGE55 SYSCFG_SWPR2_PAGE55 /*!< SRAM2 Write protection page 55 */ 00173 #define SYSCFG_SRAM2WRP_PAGE56 SYSCFG_SWPR2_PAGE56 /*!< SRAM2 Write protection page 56 */ 00174 #define SYSCFG_SRAM2WRP_PAGE57 SYSCFG_SWPR2_PAGE57 /*!< SRAM2 Write protection page 57 */ 00175 #define SYSCFG_SRAM2WRP_PAGE58 SYSCFG_SWPR2_PAGE58 /*!< SRAM2 Write protection page 58 */ 00176 #define SYSCFG_SRAM2WRP_PAGE59 SYSCFG_SWPR2_PAGE59 /*!< SRAM2 Write protection page 59 */ 00177 #define SYSCFG_SRAM2WRP_PAGE60 SYSCFG_SWPR2_PAGE60 /*!< SRAM2 Write protection page 60 */ 00178 #define SYSCFG_SRAM2WRP_PAGE61 SYSCFG_SWPR2_PAGE61 /*!< SRAM2 Write protection page 61 */ 00179 #define SYSCFG_SRAM2WRP_PAGE62 SYSCFG_SWPR2_PAGE62 /*!< SRAM2 Write protection page 62 */ 00180 #define SYSCFG_SRAM2WRP_PAGE63 SYSCFG_SWPR2_PAGE63 /*!< SRAM2 Write protection page 63 */ 00181 00182 /** 00183 * @} 00184 */ 00185 #endif /* SYSCFG_SWPR2_PAGE63 */ 00186 00187 #if defined(VREFBUF) 00188 /** @defgroup SYSCFG_VREFBUF_VoltageScale VREFBUF Voltage Scale 00189 * @{ 00190 */ 00191 #define SYSCFG_VREFBUF_VOLTAGE_SCALE0 ((uint32_t)0x00000000) /*!< Voltage reference scale 0 (VREF_OUT1) */ 00192 #define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_CSR_VRS /*!< Voltage reference scale 1 (VREF_OUT2) */ 00193 00194 /** 00195 * @} 00196 */ 00197 00198 /** @defgroup SYSCFG_VREFBUF_HighImpedance VREFBUF High Impedance 00199 * @{ 00200 */ 00201 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE ((uint32_t)0x00000000) /*!< VREF_plus pin is internally connected to Voltage reference buffer output */ 00202 #define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_CSR_HIZ /*!< VREF_plus pin is high impedance */ 00203 00204 /** 00205 * @} 00206 */ 00207 #endif /* VREFBUF */ 00208 00209 /** @defgroup SYSCFG_flags_definition Flags 00210 * @{ 00211 */ 00212 00213 #define SYSCFG_FLAG_SRAM2_PE SYSCFG_CFGR2_SPF /*!< SRAM2 parity error */ 00214 #define SYSCFG_FLAG_SRAM2_BUSY SYSCFG_SCSR_SRAM2BSY /*!< SRAM2 busy by erase operation */ 00215 00216 /** 00217 * @} 00218 */ 00219 00220 /** @defgroup SYSCFG_FastModePlus_GPIO Fast-mode Plus on GPIO 00221 * @{ 00222 */ 00223 00224 /** @brief Fast-mode Plus driving capability on a specific GPIO 00225 */ 00226 #define SYSCFG_FASTMODEPLUS_PB6 SYSCFG_CFGR1_I2C_PB6_FMP /*!< Enable Fast-mode Plus on PB6 */ 00227 #define SYSCFG_FASTMODEPLUS_PB7 SYSCFG_CFGR1_I2C_PB7_FMP /*!< Enable Fast-mode Plus on PB7 */ 00228 #if defined(SYSCFG_CFGR1_I2C_PB8_FMP) 00229 #define SYSCFG_FASTMODEPLUS_PB8 SYSCFG_CFGR1_I2C_PB8_FMP /*!< Enable Fast-mode Plus on PB8 */ 00230 #endif /* SYSCFG_CFGR1_I2C_PB8_FMP */ 00231 #if defined(SYSCFG_CFGR1_I2C_PB9_FMP) 00232 #define SYSCFG_FASTMODEPLUS_PB9 SYSCFG_CFGR1_I2C_PB9_FMP /*!< Enable Fast-mode Plus on PB9 */ 00233 #endif /* SYSCFG_CFGR1_I2C_PB9_FMP */ 00234 00235 /** 00236 * @} 00237 */ 00238 00239 /** 00240 * @} 00241 */ 00242 00243 /* Exported macros -----------------------------------------------------------*/ 00244 00245 /** @defgroup DBGMCU_Exported_Macros DBGMCU Exported Macros 00246 * @{ 00247 */ 00248 00249 /** @brief Freeze/Unfreeze Peripherals in Debug mode 00250 */ 00251 #if defined(DBGMCU_APB1FZR1_DBG_TIM2_STOP) 00252 #define __HAL_DBGMCU_FREEZE_TIM2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 00253 #define __HAL_DBGMCU_UNFREEZE_TIM2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM2_STOP) 00254 #endif 00255 00256 #if defined(DBGMCU_APB1FZR1_DBG_TIM3_STOP) 00257 #define __HAL_DBGMCU_FREEZE_TIM3() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 00258 #define __HAL_DBGMCU_UNFREEZE_TIM3() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM3_STOP) 00259 #endif 00260 00261 #if defined(DBGMCU_APB1FZR1_DBG_TIM4_STOP) 00262 #define __HAL_DBGMCU_FREEZE_TIM4() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 00263 #define __HAL_DBGMCU_UNFREEZE_TIM4() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM4_STOP) 00264 #endif 00265 00266 #if defined(DBGMCU_APB1FZR1_DBG_TIM5_STOP) 00267 #define __HAL_DBGMCU_FREEZE_TIM5() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 00268 #define __HAL_DBGMCU_UNFREEZE_TIM5() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM5_STOP) 00269 #endif 00270 00271 #if defined(DBGMCU_APB1FZR1_DBG_TIM6_STOP) 00272 #define __HAL_DBGMCU_FREEZE_TIM6() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 00273 #define __HAL_DBGMCU_UNFREEZE_TIM6() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM6_STOP) 00274 #endif 00275 00276 #if defined(DBGMCU_APB1FZR1_DBG_TIM7_STOP) 00277 #define __HAL_DBGMCU_FREEZE_TIM7() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 00278 #define __HAL_DBGMCU_UNFREEZE_TIM7() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_TIM7_STOP) 00279 #endif 00280 00281 #if defined(DBGMCU_APB1FZR1_DBG_RTC_STOP) 00282 #define __HAL_DBGMCU_FREEZE_RTC() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 00283 #define __HAL_DBGMCU_UNFREEZE_RTC() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_RTC_STOP) 00284 #endif 00285 00286 #if defined(DBGMCU_APB1FZR1_DBG_WWDG_STOP) 00287 #define __HAL_DBGMCU_FREEZE_WWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 00288 #define __HAL_DBGMCU_UNFREEZE_WWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_WWDG_STOP) 00289 #endif 00290 00291 #if defined(DBGMCU_APB1FZR1_DBG_IWDG_STOP) 00292 #define __HAL_DBGMCU_FREEZE_IWDG() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 00293 #define __HAL_DBGMCU_UNFREEZE_IWDG() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_IWDG_STOP) 00294 #endif 00295 00296 #if defined(DBGMCU_APB1FZR1_DBG_I2C1_STOP) 00297 #define __HAL_DBGMCU_FREEZE_I2C1_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 00298 #define __HAL_DBGMCU_UNFREEZE_I2C1_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C1_STOP) 00299 #endif 00300 00301 #if defined(DBGMCU_APB1FZR1_DBG_I2C2_STOP) 00302 #define __HAL_DBGMCU_FREEZE_I2C2_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 00303 #define __HAL_DBGMCU_UNFREEZE_I2C2_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C2_STOP) 00304 #endif 00305 00306 #if defined(DBGMCU_APB1FZR1_DBG_I2C3_STOP) 00307 #define __HAL_DBGMCU_FREEZE_I2C3_TIMEOUT() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 00308 #define __HAL_DBGMCU_UNFREEZE_I2C3_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_I2C3_STOP) 00309 #endif 00310 00311 #if defined(DBGMCU_APB1FZR2_DBG_I2C4_STOP) 00312 #define __HAL_DBGMCU_FREEZE_I2C4_TIMEOUT() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 00313 #define __HAL_DBGMCU_UNFREEZE_I2C4_TIMEOUT() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_I2C4_STOP) 00314 #endif 00315 00316 #if defined(DBGMCU_APB1FZR1_DBG_CAN_STOP) 00317 #define __HAL_DBGMCU_FREEZE_CAN1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 00318 #define __HAL_DBGMCU_UNFREEZE_CAN1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN_STOP) 00319 #endif 00320 00321 #if defined(DBGMCU_APB1FZR1_DBG_CAN2_STOP) 00322 #define __HAL_DBGMCU_FREEZE_CAN2() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 00323 #define __HAL_DBGMCU_UNFREEZE_CAN2() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_CAN2_STOP) 00324 #endif 00325 00326 #if defined(DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 00327 #define __HAL_DBGMCU_FREEZE_LPTIM1() SET_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 00328 #define __HAL_DBGMCU_UNFREEZE_LPTIM1() CLEAR_BIT(DBGMCU->APB1FZR1, DBGMCU_APB1FZR1_DBG_LPTIM1_STOP) 00329 #endif 00330 00331 #if defined(DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 00332 #define __HAL_DBGMCU_FREEZE_LPTIM2() SET_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 00333 #define __HAL_DBGMCU_UNFREEZE_LPTIM2() CLEAR_BIT(DBGMCU->APB1FZR2, DBGMCU_APB1FZR2_DBG_LPTIM2_STOP) 00334 #endif 00335 00336 #if defined(DBGMCU_APB2FZ_DBG_TIM1_STOP) 00337 #define __HAL_DBGMCU_FREEZE_TIM1() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 00338 #define __HAL_DBGMCU_UNFREEZE_TIM1() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM1_STOP) 00339 #endif 00340 00341 #if defined(DBGMCU_APB2FZ_DBG_TIM8_STOP) 00342 #define __HAL_DBGMCU_FREEZE_TIM8() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 00343 #define __HAL_DBGMCU_UNFREEZE_TIM8() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM8_STOP) 00344 #endif 00345 00346 #if defined(DBGMCU_APB2FZ_DBG_TIM15_STOP) 00347 #define __HAL_DBGMCU_FREEZE_TIM15() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 00348 #define __HAL_DBGMCU_UNFREEZE_TIM15() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM15_STOP) 00349 #endif 00350 00351 #if defined(DBGMCU_APB2FZ_DBG_TIM16_STOP) 00352 #define __HAL_DBGMCU_FREEZE_TIM16() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 00353 #define __HAL_DBGMCU_UNFREEZE_TIM16() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM16_STOP) 00354 #endif 00355 00356 #if defined(DBGMCU_APB2FZ_DBG_TIM17_STOP) 00357 #define __HAL_DBGMCU_FREEZE_TIM17() SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 00358 #define __HAL_DBGMCU_UNFREEZE_TIM17() CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2FZ_DBG_TIM17_STOP) 00359 #endif 00360 00361 /** 00362 * @} 00363 */ 00364 00365 /** @defgroup SYSCFG_Exported_Macros SYSCFG Exported Macros 00366 * @{ 00367 */ 00368 00369 /** @brief Main Flash memory mapped at 0x00000000. 00370 */ 00371 #define __HAL_SYSCFG_REMAPMEMORY_FLASH() CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 00372 00373 /** @brief System Flash memory mapped at 0x00000000. 00374 */ 00375 #define __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0) 00376 00377 /** @brief Embedded SRAM mapped at 0x00000000. 00378 */ 00379 #define __HAL_SYSCFG_REMAPMEMORY_SRAM() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_1|SYSCFG_MEMRMP_MEM_MODE_0)) 00380 00381 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || \ 00382 defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00383 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00384 00385 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000. 00386 */ 00387 #define __HAL_SYSCFG_REMAPMEMORY_FMC() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1) 00388 00389 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 00390 /* STM32L496xx || STM32L4A6xx || */ 00391 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00392 00393 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00394 00395 /** @brief OCTOSPI mapped at 0x00000000. 00396 */ 00397 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI1() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2)) 00398 #define __HAL_SYSCFG_REMAPMEMORY_OCTOSPI2() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_0)) 00399 00400 #else 00401 00402 /** @brief QUADSPI mapped at 0x00000000. 00403 */ 00404 #define __HAL_SYSCFG_REMAPMEMORY_QUADSPI() MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, (SYSCFG_MEMRMP_MEM_MODE_2|SYSCFG_MEMRMP_MEM_MODE_1)) 00405 00406 #endif /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 00407 00408 /** 00409 * @brief Return the boot mode as configured by user. 00410 * @retval The boot mode as configured by user. The returned value can be one 00411 * of the following values: 00412 * @arg @ref SYSCFG_BOOT_MAINFLASH 00413 * @arg @ref SYSCFG_BOOT_SYSTEMFLASH 00414 @if STM32L486xx 00415 * @arg @ref SYSCFG_BOOT_FMC 00416 @endif 00417 * @arg @ref SYSCFG_BOOT_SRAM 00418 * @arg @ref SYSCFG_BOOT_QUADSPI 00419 */ 00420 #define __HAL_SYSCFG_GET_BOOT_MODE() READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE) 00421 00422 /** @brief SRAM2 page 0 to 31 write protection enable macro 00423 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP 00424 * @note Write protection can only be disabled by a system reset 00425 */ 00426 #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 00427 SET_BIT(SYSCFG->SWPR, (__SRAM2WRP__));\ 00428 }while(0) 00429 00430 #if defined(SYSCFG_SWPR2_PAGE63) 00431 /** @brief SRAM2 page 32 to 63 write protection enable macro 00432 * @param __SRAM2WRP__ This parameter can be a combination of values of @ref SYSCFG_SRAM2WRP_32_63 00433 * @note Write protection can only be disabled by a system reset 00434 */ 00435 #define __HAL_SYSCFG_SRAM2_WRP_32_63_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ 00436 SET_BIT(SYSCFG->SWPR2, (__SRAM2WRP__));\ 00437 }while(0) 00438 #endif /* SYSCFG_SWPR2_PAGE63 */ 00439 00440 /** @brief SRAM2 page write protection unlock prior to erase 00441 * @note Writing a wrong key reactivates the write protection 00442 */ 00443 #define __HAL_SYSCFG_SRAM2_WRP_UNLOCK() do {SYSCFG->SKR = 0xCA;\ 00444 SYSCFG->SKR = 0x53;\ 00445 }while(0) 00446 00447 /** @brief SRAM2 erase 00448 * @note __SYSCFG_GET_FLAG(SYSCFG_FLAG_SRAM2_BUSY) may be used to check end of erase 00449 */ 00450 #define __HAL_SYSCFG_SRAM2_ERASE() SET_BIT(SYSCFG->SCSR, SYSCFG_SCSR_SRAM2ER) 00451 00452 /** @brief Floating Point Unit interrupt enable/disable macros 00453 * @param __INTERRUPT__ This parameter can be a value of @ref SYSCFG_FPU_Interrupts 00454 */ 00455 #define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 00456 SET_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 00457 }while(0) 00458 00459 #define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE(__INTERRUPT__) do {assert_param(IS_SYSCFG_FPU_INTERRUPT((__INTERRUPT__)));\ 00460 CLEAR_BIT(SYSCFG->CFGR1, (__INTERRUPT__));\ 00461 }while(0) 00462 00463 /** @brief SYSCFG Break ECC lock. 00464 * Enable and lock the connection of Flash ECC error connection to TIM1/8/15/16/17 Break input. 00465 * @note The selected configuration is locked and can be unlocked only by system reset. 00466 */ 00467 #define __HAL_SYSCFG_BREAK_ECC_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ECCL) 00468 00469 /** @brief SYSCFG Break Cortex-M4 Lockup lock. 00470 * Enable and lock the connection of Cortex-M4 LOCKUP (Hardfault) output to TIM1/8/15/16/17 Break input. 00471 * @note The selected configuration is locked and can be unlocked only by system reset. 00472 */ 00473 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_CLL) 00474 00475 /** @brief SYSCFG Break PVD lock. 00476 * Enable and lock the PVD connection to Timer1/8/15/16/17 Break input, as well as the PVDE and PLS[2:0] in the PWR_CR2 register. 00477 * @note The selected configuration is locked and can be unlocked only by system reset. 00478 */ 00479 #define __HAL_SYSCFG_BREAK_PVD_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_PVDL) 00480 00481 /** @brief SYSCFG Break SRAM2 parity lock. 00482 * Enable and lock the SRAM2 parity error signal connection to TIM1/8/15/16/17 Break input. 00483 * @note The selected configuration is locked and can be unlocked by system reset. 00484 */ 00485 #define __HAL_SYSCFG_BREAK_SRAM2PARITY_LOCK() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPL) 00486 00487 /** @brief Check SYSCFG flag is set or not. 00488 * @param __FLAG__ specifies the flag to check. 00489 * This parameter can be one of the following values: 00490 * @arg @ref SYSCFG_FLAG_SRAM2_PE SRAM2 Parity Error Flag 00491 * @arg @ref SYSCFG_FLAG_SRAM2_BUSY SRAM2 Erase Ongoing 00492 * @retval The new state of __FLAG__ (TRUE or FALSE). 00493 */ 00494 #define __HAL_SYSCFG_GET_FLAG(__FLAG__) ((((((__FLAG__) == SYSCFG_SCSR_SRAM2BSY)? SYSCFG->SCSR : SYSCFG->CFGR2) & (__FLAG__))!= 0) ? 1 : 0) 00495 00496 /** @brief Set the SPF bit to clear the SRAM Parity Error Flag. 00497 */ 00498 #define __HAL_SYSCFG_CLEAR_FLAG() SET_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_SPF) 00499 00500 /** @brief Fast-mode Plus driving capability enable/disable macros 00501 * @param __FASTMODEPLUS__ This parameter can be a value of : 00502 * @arg @ref SYSCFG_FASTMODEPLUS_PB6 Fast-mode Plus driving capability activation on PB6 00503 * @arg @ref SYSCFG_FASTMODEPLUS_PB7 Fast-mode Plus driving capability activation on PB7 00504 * @arg @ref SYSCFG_FASTMODEPLUS_PB8 Fast-mode Plus driving capability activation on PB8 00505 * @arg @ref SYSCFG_FASTMODEPLUS_PB9 Fast-mode Plus driving capability activation on PB9 00506 */ 00507 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 00508 SET_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 00509 }while(0) 00510 00511 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\ 00512 CLEAR_BIT(SYSCFG->CFGR1, (__FASTMODEPLUS__));\ 00513 }while(0) 00514 00515 /** 00516 * @} 00517 */ 00518 00519 /* Private macros ------------------------------------------------------------*/ 00520 /** @defgroup SYSCFG_Private_Macros SYSCFG Private Macros 00521 * @{ 00522 */ 00523 00524 #define IS_SYSCFG_FPU_INTERRUPT(__INTERRUPT__) ((((__INTERRUPT__) & SYSCFG_IT_FPU_IOC) == SYSCFG_IT_FPU_IOC) || \ 00525 (((__INTERRUPT__) & SYSCFG_IT_FPU_DZC) == SYSCFG_IT_FPU_DZC) || \ 00526 (((__INTERRUPT__) & SYSCFG_IT_FPU_UFC) == SYSCFG_IT_FPU_UFC) || \ 00527 (((__INTERRUPT__) & SYSCFG_IT_FPU_OFC) == SYSCFG_IT_FPU_OFC) || \ 00528 (((__INTERRUPT__) & SYSCFG_IT_FPU_IDC) == SYSCFG_IT_FPU_IDC) || \ 00529 (((__INTERRUPT__) & SYSCFG_IT_FPU_IXC) == SYSCFG_IT_FPU_IXC)) 00530 00531 #define IS_SYSCFG_BREAK_CONFIG(__CONFIG__) (((__CONFIG__) == SYSCFG_BREAK_ECC) || \ 00532 ((__CONFIG__) == SYSCFG_BREAK_PVD) || \ 00533 ((__CONFIG__) == SYSCFG_BREAK_SRAM2_PARITY) || \ 00534 ((__CONFIG__) == SYSCFG_BREAK_LOCKUP)) 00535 00536 #define IS_SYSCFG_SRAM2WRP_PAGE(__PAGE__) (((__PAGE__) > 0) && ((__PAGE__) <= 0xFFFFFFFF)) 00537 00538 #if defined(VREFBUF) 00539 #define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE(__SCALE__) (((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE0) || \ 00540 ((__SCALE__) == SYSCFG_VREFBUF_VOLTAGE_SCALE1)) 00541 00542 #define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE(__VALUE__) (((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE) || \ 00543 ((__VALUE__) == SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE)) 00544 00545 #define IS_SYSCFG_VREFBUF_TRIMMING(__VALUE__) (((__VALUE__) > 0) && ((__VALUE__) <= VREFBUF_CCR_TRIM)) 00546 #endif /* VREFBUF */ 00547 00548 #if defined(SYSCFG_FASTMODEPLUS_PB8) && defined(SYSCFG_FASTMODEPLUS_PB9) 00549 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 00550 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 00551 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8) || \ 00552 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 00553 #elif defined(SYSCFG_FASTMODEPLUS_PB8) 00554 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 00555 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 00556 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB8) == SYSCFG_FASTMODEPLUS_PB8)) 00557 #elif defined(SYSCFG_FASTMODEPLUS_PB9) 00558 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 00559 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7) || \ 00560 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB9) == SYSCFG_FASTMODEPLUS_PB9)) 00561 #else 00562 #define IS_SYSCFG_FASTMODEPLUS(__PIN__) ((((__PIN__) & SYSCFG_FASTMODEPLUS_PB6) == SYSCFG_FASTMODEPLUS_PB6) || \ 00563 (((__PIN__) & SYSCFG_FASTMODEPLUS_PB7) == SYSCFG_FASTMODEPLUS_PB7)) 00564 #endif 00565 /** 00566 * @} 00567 */ 00568 00569 /* Exported functions --------------------------------------------------------*/ 00570 00571 /** @addtogroup HAL_Exported_Functions 00572 * @{ 00573 */ 00574 00575 /** @addtogroup HAL_Exported_Functions_Group1 00576 * @{ 00577 */ 00578 00579 /* Initialization and de-initialization functions ******************************/ 00580 HAL_StatusTypeDef HAL_Init(void); 00581 HAL_StatusTypeDef HAL_DeInit(void); 00582 void HAL_MspInit(void); 00583 void HAL_MspDeInit(void); 00584 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); 00585 00586 /** 00587 * @} 00588 */ 00589 00590 /** @addtogroup HAL_Exported_Functions_Group2 00591 * @{ 00592 */ 00593 00594 /* Peripheral Control functions ************************************************/ 00595 void HAL_IncTick(void); 00596 void HAL_Delay(uint32_t Delay); 00597 uint32_t HAL_GetTick(void); 00598 void HAL_SuspendTick(void); 00599 void HAL_ResumeTick(void); 00600 uint32_t HAL_GetHalVersion(void); 00601 uint32_t HAL_GetREVID(void); 00602 uint32_t HAL_GetDEVID(void); 00603 uint32_t HAL_GetUIDw0(void); 00604 uint32_t HAL_GetUIDw1(void); 00605 uint32_t HAL_GetUIDw2(void); 00606 00607 /** 00608 * @} 00609 */ 00610 00611 /** @addtogroup HAL_Exported_Functions_Group3 00612 * @{ 00613 */ 00614 00615 /* DBGMCU Peripheral Control functions *****************************************/ 00616 void HAL_DBGMCU_EnableDBGSleepMode(void); 00617 void HAL_DBGMCU_DisableDBGSleepMode(void); 00618 void HAL_DBGMCU_EnableDBGStopMode(void); 00619 void HAL_DBGMCU_DisableDBGStopMode(void); 00620 void HAL_DBGMCU_EnableDBGStandbyMode(void); 00621 void HAL_DBGMCU_DisableDBGStandbyMode(void); 00622 00623 /** 00624 * @} 00625 */ 00626 00627 /** @addtogroup HAL_Exported_Functions_Group4 00628 * @{ 00629 */ 00630 00631 /* SYSCFG Control functions ****************************************************/ 00632 void HAL_SYSCFG_SRAM2Erase(void); 00633 void HAL_SYSCFG_EnableMemorySwappingBank(void); 00634 void HAL_SYSCFG_DisableMemorySwappingBank(void); 00635 00636 #if defined(VREFBUF) 00637 void HAL_SYSCFG_VREFBUF_VoltageScalingConfig(uint32_t VoltageScaling); 00638 void HAL_SYSCFG_VREFBUF_HighImpedanceConfig(uint32_t Mode); 00639 void HAL_SYSCFG_VREFBUF_TrimmingConfig(uint32_t TrimmingValue); 00640 HAL_StatusTypeDef HAL_SYSCFG_EnableVREFBUF(void); 00641 void HAL_SYSCFG_DisableVREFBUF(void); 00642 #endif /* VREFBUF */ 00643 00644 void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); 00645 void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); 00646 00647 /** 00648 * @} 00649 */ 00650 00651 /** 00652 * @} 00653 */ 00654 00655 /** 00656 * @} 00657 */ 00658 00659 /** 00660 * @} 00661 */ 00662 00663 #ifdef __cplusplus 00664 } 00665 #endif 00666 00667 #endif /* __STM32L4xx_HAL_H */ 00668 00669 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1