|
STM32F439xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_tim.h 00004 * @author MCD Application Team 00005 * @brief Header file of TIM LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_LL_TIM_H 00038 #define __STM32F4xx_LL_TIM_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx.h" 00046 00047 /** @addtogroup STM32F4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) 00052 00053 /** @defgroup TIM_LL TIM 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /** @defgroup TIM_LL_Private_Variables TIM Private Variables 00060 * @{ 00061 */ 00062 static const uint8_t OFFSET_TAB_CCMRx[] = 00063 { 00064 0x00U, /* 0: TIMx_CH1 */ 00065 0x00U, /* 1: TIMx_CH1N */ 00066 0x00U, /* 2: TIMx_CH2 */ 00067 0x00U, /* 3: TIMx_CH2N */ 00068 0x04U, /* 4: TIMx_CH3 */ 00069 0x04U, /* 5: TIMx_CH3N */ 00070 0x04U /* 6: TIMx_CH4 */ 00071 }; 00072 00073 static const uint8_t SHIFT_TAB_OCxx[] = 00074 { 00075 0U, /* 0: OC1M, OC1FE, OC1PE */ 00076 0U, /* 1: - NA */ 00077 8U, /* 2: OC2M, OC2FE, OC2PE */ 00078 0U, /* 3: - NA */ 00079 0U, /* 4: OC3M, OC3FE, OC3PE */ 00080 0U, /* 5: - NA */ 00081 8U /* 6: OC4M, OC4FE, OC4PE */ 00082 }; 00083 00084 static const uint8_t SHIFT_TAB_ICxx[] = 00085 { 00086 0U, /* 0: CC1S, IC1PSC, IC1F */ 00087 0U, /* 1: - NA */ 00088 8U, /* 2: CC2S, IC2PSC, IC2F */ 00089 0U, /* 3: - NA */ 00090 0U, /* 4: CC3S, IC3PSC, IC3F */ 00091 0U, /* 5: - NA */ 00092 8U /* 6: CC4S, IC4PSC, IC4F */ 00093 }; 00094 00095 static const uint8_t SHIFT_TAB_CCxP[] = 00096 { 00097 0U, /* 0: CC1P */ 00098 2U, /* 1: CC1NP */ 00099 4U, /* 2: CC2P */ 00100 6U, /* 3: CC2NP */ 00101 8U, /* 4: CC3P */ 00102 10U, /* 5: CC3NP */ 00103 12U /* 6: CC4P */ 00104 }; 00105 00106 static const uint8_t SHIFT_TAB_OISx[] = 00107 { 00108 0U, /* 0: OIS1 */ 00109 1U, /* 1: OIS1N */ 00110 2U, /* 2: OIS2 */ 00111 3U, /* 3: OIS2N */ 00112 4U, /* 4: OIS3 */ 00113 5U, /* 5: OIS3N */ 00114 6U /* 6: OIS4 */ 00115 }; 00116 /** 00117 * @} 00118 */ 00119 00120 00121 /* Private constants ---------------------------------------------------------*/ 00122 /** @defgroup TIM_LL_Private_Constants TIM Private Constants 00123 * @{ 00124 */ 00125 00126 00127 /* Remap mask definitions */ 00128 #define TIMx_OR_RMP_SHIFT 16U 00129 #define TIMx_OR_RMP_MASK 0x0000FFFFU 00130 #define TIM2_OR_RMP_MASK (TIM_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT) 00131 #define TIM5_OR_RMP_MASK (TIM_OR_TI4_RMP << TIMx_OR_RMP_SHIFT) 00132 #define TIM11_OR_RMP_MASK (TIM_OR_TI1_RMP << TIMx_OR_RMP_SHIFT) 00133 00134 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ 00135 #define DT_DELAY_1 ((uint8_t)0x7FU) 00136 #define DT_DELAY_2 ((uint8_t)0x3FU) 00137 #define DT_DELAY_3 ((uint8_t)0x1FU) 00138 #define DT_DELAY_4 ((uint8_t)0x1FU) 00139 00140 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ 00141 #define DT_RANGE_1 ((uint8_t)0x00U) 00142 #define DT_RANGE_2 ((uint8_t)0x80U) 00143 #define DT_RANGE_3 ((uint8_t)0xC0U) 00144 #define DT_RANGE_4 ((uint8_t)0xE0U) 00145 00146 00147 /** 00148 * @} 00149 */ 00150 00151 /* Private macros ------------------------------------------------------------*/ 00152 /** @defgroup TIM_LL_Private_Macros TIM Private Macros 00153 * @{ 00154 */ 00155 /** @brief Convert channel id into channel index. 00156 * @param __CHANNEL__ This parameter can be one of the following values: 00157 * @arg @ref LL_TIM_CHANNEL_CH1 00158 * @arg @ref LL_TIM_CHANNEL_CH1N 00159 * @arg @ref LL_TIM_CHANNEL_CH2 00160 * @arg @ref LL_TIM_CHANNEL_CH2N 00161 * @arg @ref LL_TIM_CHANNEL_CH3 00162 * @arg @ref LL_TIM_CHANNEL_CH3N 00163 * @arg @ref LL_TIM_CHANNEL_CH4 00164 * @retval none 00165 */ 00166 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ 00167 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ 00168 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ 00169 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ 00170 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ 00171 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ 00172 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) 00173 00174 /** @brief Calculate the deadtime sampling period(in ps). 00175 * @param __TIMCLK__ timer input clock frequency (in Hz). 00176 * @param __CKD__ This parameter can be one of the following values: 00177 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 00178 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 00179 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 00180 * @retval none 00181 */ 00182 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ 00183 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ 00184 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ 00185 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) 00186 /** 00187 * @} 00188 */ 00189 00190 00191 /* Exported types ------------------------------------------------------------*/ 00192 #if defined(USE_FULL_LL_DRIVER) 00193 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure 00194 * @{ 00195 */ 00196 00197 /** 00198 * @brief TIM Time Base configuration structure definition. 00199 */ 00200 typedef struct 00201 { 00202 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00203 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00204 00205 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ 00206 00207 uint32_t CounterMode; /*!< Specifies the counter mode. 00208 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. 00209 00210 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ 00211 00212 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active 00213 Auto-Reload Register at the next update event. 00214 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00215 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. 00216 00217 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ 00218 00219 uint32_t ClockDivision; /*!< Specifies the clock division. 00220 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. 00221 00222 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ 00223 00224 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00225 reaches zero, an update event is generated and counting restarts 00226 from the RCR value (N). 00227 This means in PWM mode that (N+1) corresponds to: 00228 - the number of PWM periods in edge-aligned mode 00229 - the number of half PWM period in center-aligned mode 00230 This parameter must be a number between 0x00 and 0xFF. 00231 00232 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ 00233 } LL_TIM_InitTypeDef; 00234 00235 /** 00236 * @brief TIM Output Compare configuration structure definition. 00237 */ 00238 typedef struct 00239 { 00240 uint32_t OCMode; /*!< Specifies the output mode. 00241 This parameter can be a value of @ref TIM_LL_EC_OCMODE. 00242 00243 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ 00244 00245 uint32_t OCState; /*!< Specifies the TIM Output Compare state. 00246 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 00247 00248 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 00249 00250 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. 00251 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 00252 00253 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 00254 00255 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. 00256 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00257 00258 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ 00259 00260 uint32_t OCPolarity; /*!< Specifies the output polarity. 00261 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 00262 00263 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ 00264 00265 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00266 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 00267 00268 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ 00269 00270 00271 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00272 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 00273 00274 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ 00275 00276 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00277 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 00278 00279 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ 00280 } LL_TIM_OC_InitTypeDef; 00281 00282 /** 00283 * @brief TIM Input Capture configuration structure definition. 00284 */ 00285 00286 typedef struct 00287 { 00288 00289 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00290 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00291 00292 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00293 00294 uint32_t ICActiveInput; /*!< Specifies the input. 00295 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00296 00297 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ 00298 00299 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00300 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00301 00302 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00303 00304 uint32_t ICFilter; /*!< Specifies the input capture filter. 00305 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00306 00307 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00308 } LL_TIM_IC_InitTypeDef; 00309 00310 00311 /** 00312 * @brief TIM Encoder interface configuration structure definition. 00313 */ 00314 typedef struct 00315 { 00316 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). 00317 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. 00318 00319 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ 00320 00321 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 00322 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00323 00324 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00325 00326 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source 00327 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00328 00329 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ 00330 00331 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 00332 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00333 00334 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00335 00336 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 00337 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00338 00339 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00340 00341 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. 00342 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00343 00344 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00345 00346 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source 00347 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00348 00349 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ 00350 00351 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. 00352 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00353 00354 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00355 00356 uint32_t IC2Filter; /*!< Specifies the TI2 input filter. 00357 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00358 00359 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00360 00361 } LL_TIM_ENCODER_InitTypeDef; 00362 00363 /** 00364 * @brief TIM Hall sensor interface configuration structure definition. 00365 */ 00366 typedef struct 00367 { 00368 00369 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 00370 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00371 00372 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00373 00374 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 00375 Prescaler must be set to get a maximum counter period longer than the 00376 time interval between 2 consecutive changes on the Hall inputs. 00377 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00378 00379 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00380 00381 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 00382 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00383 00384 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00385 00386 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. 00387 A positive pulse (TRGO event) is generated with a programmable delay every time 00388 a change occurs on the Hall inputs. 00389 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. 00390 00391 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ 00392 } LL_TIM_HALLSENSOR_InitTypeDef; 00393 00394 /** 00395 * @brief BDTR (Break and Dead Time) structure definition 00396 */ 00397 typedef struct 00398 { 00399 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. 00400 This parameter can be a value of @ref TIM_LL_EC_OSSR 00401 00402 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() 00403 00404 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ 00405 00406 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. 00407 This parameter can be a value of @ref TIM_LL_EC_OSSI 00408 00409 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() 00410 00411 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ 00412 00413 uint32_t LockLevel; /*!< Specifies the LOCK level parameters. 00414 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL 00415 00416 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register 00417 has been written, their content is frozen until the next reset.*/ 00418 00419 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the 00420 switching-on of the outputs. 00421 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00422 00423 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() 00424 00425 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ 00426 00427 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. 00428 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE 00429 00430 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() 00431 00432 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ 00433 00434 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 00435 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY 00436 00437 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() 00438 00439 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ 00440 00441 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 00442 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE 00443 00444 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() 00445 00446 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ 00447 } LL_TIM_BDTR_InitTypeDef; 00448 00449 /** 00450 * @} 00451 */ 00452 #endif /* USE_FULL_LL_DRIVER */ 00453 00454 /* Exported constants --------------------------------------------------------*/ 00455 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants 00456 * @{ 00457 */ 00458 00459 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines 00460 * @brief Flags defines which can be used with LL_TIM_ReadReg function. 00461 * @{ 00462 */ 00463 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ 00464 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ 00465 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ 00466 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ 00467 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ 00468 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ 00469 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ 00470 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ 00471 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ 00472 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ 00473 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ 00474 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ 00475 /** 00476 * @} 00477 */ 00478 00479 #if defined(USE_FULL_LL_DRIVER) 00480 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable 00481 * @{ 00482 */ 00483 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ 00484 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ 00485 /** 00486 * @} 00487 */ 00488 00489 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable 00490 * @{ 00491 */ 00492 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 00493 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ 00494 /** 00495 * @} 00496 */ 00497 #endif /* USE_FULL_LL_DRIVER */ 00498 00499 /** @defgroup TIM_LL_EC_IT IT Defines 00500 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. 00501 * @{ 00502 */ 00503 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ 00504 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ 00505 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ 00506 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ 00507 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ 00508 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ 00509 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ 00510 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ 00511 /** 00512 * @} 00513 */ 00514 00515 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source 00516 * @{ 00517 */ 00518 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ 00519 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ 00520 /** 00521 * @} 00522 */ 00523 00524 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode 00525 * @{ 00526 */ 00527 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ 00528 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ 00529 /** 00530 * @} 00531 */ 00532 00533 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode 00534 * @{ 00535 */ 00536 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ 00537 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ 00538 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ 00539 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ 00540 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ 00541 /** 00542 * @} 00543 */ 00544 00545 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division 00546 * @{ 00547 */ 00548 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ 00549 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ 00550 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ 00551 /** 00552 * @} 00553 */ 00554 00555 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction 00556 * @{ 00557 */ 00558 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ 00559 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ 00560 /** 00561 * @} 00562 */ 00563 00564 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source 00565 * @{ 00566 */ 00567 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ 00568 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ 00569 /** 00570 * @} 00571 */ 00572 00573 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request 00574 * @{ 00575 */ 00576 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ 00577 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 00578 /** 00579 * @} 00580 */ 00581 00582 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level 00583 * @{ 00584 */ 00585 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ 00586 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 00587 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 00588 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 00589 /** 00590 * @} 00591 */ 00592 00593 /** @defgroup TIM_LL_EC_CHANNEL Channel 00594 * @{ 00595 */ 00596 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ 00597 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ 00598 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ 00599 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ 00600 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ 00601 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ 00602 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ 00603 /** 00604 * @} 00605 */ 00606 00607 #if defined(USE_FULL_LL_DRIVER) 00608 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State 00609 * @{ 00610 */ 00611 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ 00612 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ 00613 /** 00614 * @} 00615 */ 00616 #endif /* USE_FULL_LL_DRIVER */ 00617 00618 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode 00619 * @{ 00620 */ 00621 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ 00622 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ 00623 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ 00624 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ 00625 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ 00626 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ 00627 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ 00628 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ 00629 /** 00630 * @} 00631 */ 00632 00633 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity 00634 * @{ 00635 */ 00636 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ 00637 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ 00638 /** 00639 * @} 00640 */ 00641 00642 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State 00643 * @{ 00644 */ 00645 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ 00646 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ 00647 /** 00648 * @} 00649 */ 00650 00651 00652 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection 00653 * @{ 00654 */ 00655 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ 00656 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ 00657 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ 00658 /** 00659 * @} 00660 */ 00661 00662 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler 00663 * @{ 00664 */ 00665 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ 00666 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ 00667 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ 00668 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ 00669 /** 00670 * @} 00671 */ 00672 00673 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter 00674 * @{ 00675 */ 00676 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ 00677 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ 00678 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ 00679 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ 00680 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ 00681 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ 00682 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ 00683 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ 00684 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ 00685 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ 00686 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ 00687 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ 00688 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ 00689 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ 00690 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ 00691 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ 00692 /** 00693 * @} 00694 */ 00695 00696 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity 00697 * @{ 00698 */ 00699 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ 00700 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ 00701 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ 00702 /** 00703 * @} 00704 */ 00705 00706 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source 00707 * @{ 00708 */ 00709 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ 00710 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/ 00711 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ 00712 /** 00713 * @} 00714 */ 00715 00716 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode 00717 * @{ 00718 */ 00719 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ 00720 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ 00721 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */ 00722 /** 00723 * @} 00724 */ 00725 00726 /** @defgroup TIM_LL_EC_TRGO Trigger Output 00727 * @{ 00728 */ 00729 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ 00730 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ 00731 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ 00732 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ 00733 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ 00734 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ 00735 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ 00736 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ 00737 /** 00738 * @} 00739 */ 00740 00741 00742 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode 00743 * @{ 00744 */ 00745 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ 00746 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ 00747 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ 00748 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ 00749 /** 00750 * @} 00751 */ 00752 00753 /** @defgroup TIM_LL_EC_TS Trigger Selection 00754 * @{ 00755 */ 00756 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ 00757 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ 00758 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ 00759 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ 00760 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ 00761 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ 00762 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ 00763 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ 00764 /** 00765 * @} 00766 */ 00767 00768 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity 00769 * @{ 00770 */ 00771 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ 00772 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ 00773 /** 00774 * @} 00775 */ 00776 00777 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler 00778 * @{ 00779 */ 00780 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ 00781 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ 00782 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ 00783 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ 00784 /** 00785 * @} 00786 */ 00787 00788 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter 00789 * @{ 00790 */ 00791 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ 00792 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ 00793 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ 00794 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ 00795 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ 00796 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ 00797 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ 00798 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ 00799 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ 00800 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ 00801 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ 00802 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ 00803 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ 00804 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ 00805 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ 00806 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ 00807 /** 00808 * @} 00809 */ 00810 00811 00812 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity 00813 * @{ 00814 */ 00815 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 00816 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 00817 /** 00818 * @} 00819 */ 00820 00821 00822 00823 00824 /** @defgroup TIM_LL_EC_OSSI OSSI 00825 * @{ 00826 */ 00827 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ 00828 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ 00829 /** 00830 * @} 00831 */ 00832 00833 /** @defgroup TIM_LL_EC_OSSR OSSR 00834 * @{ 00835 */ 00836 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ 00837 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ 00838 /** 00839 * @} 00840 */ 00841 00842 00843 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address 00844 * @{ 00845 */ 00846 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ 00847 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ 00848 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ 00849 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ 00850 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ 00851 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ 00852 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ 00853 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ 00854 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ 00855 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ 00856 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ 00857 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ 00858 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ 00859 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ 00860 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ 00861 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ 00862 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ 00863 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ 00864 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) 00865 /** 00866 * @} 00867 */ 00868 00869 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length 00870 * @{ 00871 */ 00872 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ 00873 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ 00874 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ 00875 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ 00876 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ 00877 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ 00878 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ 00879 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ 00880 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ 00881 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ 00882 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ 00883 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ 00884 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ 00885 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ 00886 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ 00887 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ 00888 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ 00889 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ 00890 /** 00891 * @} 00892 */ 00893 00894 00895 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8 00896 * @{ 00897 */ 00898 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */ 00899 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */ 00900 #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */ 00901 /** 00902 * @} 00903 */ 00904 00905 /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap 00906 * @{ 00907 */ 00908 #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */ 00909 #define LL_TIM_TIM5_TI4_RMP_LSI (TIM_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */ 00910 #define LL_TIM_TIM5_TI4_RMP_LSE (TIM_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */ 00911 #define LL_TIM_TIM5_TI4_RMP_RTC (TIM_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */ 00912 /** 00913 * @} 00914 */ 00915 00916 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap 00917 * @{ 00918 */ 00919 #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */ 00920 #define LL_TIM_TIM11_TI1_RMP_GPIO1 (TIM_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */ 00921 #define LL_TIM_TIM11_TI1_RMP_GPIO2 (TIM_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to GPIO */ 00922 #define LL_TIM_TIM11_TI1_RMP_HSE_RTC (TIM_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE_RTC */ 00923 /** 00924 * @} 00925 */ 00926 00927 00928 /** 00929 * @} 00930 */ 00931 00932 /* Exported macro ------------------------------------------------------------*/ 00933 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros 00934 * @{ 00935 */ 00936 00937 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros 00938 * @{ 00939 */ 00940 /** 00941 * @brief Write a value in TIM register. 00942 * @param __INSTANCE__ TIM Instance 00943 * @param __REG__ Register to be written 00944 * @param __VALUE__ Value to be written in the register 00945 * @retval None 00946 */ 00947 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00948 00949 /** 00950 * @brief Read a value in TIM register. 00951 * @param __INSTANCE__ TIM Instance 00952 * @param __REG__ Register to be read 00953 * @retval Register value 00954 */ 00955 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00956 /** 00957 * @} 00958 */ 00959 00960 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros 00961 * @{ 00962 */ 00963 00964 /** 00965 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. 00966 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); 00967 * @param __TIMCLK__ timer input clock frequency (in Hz) 00968 * @param __CKD__ This parameter can be one of the following values: 00969 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 00970 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 00971 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 00972 * @param __DT__ deadtime duration (in ns) 00973 * @retval DTG[0:7] 00974 */ 00975 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ 00976 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ 00977 (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\ 00978 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\ 00979 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\ 00980 0U) 00981 00982 /** 00983 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. 00984 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); 00985 * @param __TIMCLK__ timer input clock frequency (in Hz) 00986 * @param __CNTCLK__ counter clock frequency (in Hz) 00987 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) 00988 */ 00989 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 00990 ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U 00991 00992 /** 00993 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. 00994 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); 00995 * @param __TIMCLK__ timer input clock frequency (in Hz) 00996 * @param __PSC__ prescaler 00997 * @param __FREQ__ output signal frequency (in Hz) 00998 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 00999 */ 01000 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ 01001 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U 01002 01003 /** 01004 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. 01005 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); 01006 * @param __TIMCLK__ timer input clock frequency (in Hz) 01007 * @param __PSC__ prescaler 01008 * @param __DELAY__ timer output compare active/inactive delay (in us) 01009 * @retval Compare value (between Min_Data=0 and Max_Data=65535) 01010 */ 01011 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ 01012 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 01013 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 01014 01015 /** 01016 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). 01017 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); 01018 * @param __TIMCLK__ timer input clock frequency (in Hz) 01019 * @param __PSC__ prescaler 01020 * @param __DELAY__ timer output compare active/inactive delay (in us) 01021 * @param __PULSE__ pulse duration (in us) 01022 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 01023 */ 01024 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 01025 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ 01026 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) 01027 01028 /** 01029 * @brief HELPER macro retrieving the ratio of the input capture prescaler 01030 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); 01031 * @param __ICPSC__ This parameter can be one of the following values: 01032 * @arg @ref LL_TIM_ICPSC_DIV1 01033 * @arg @ref LL_TIM_ICPSC_DIV2 01034 * @arg @ref LL_TIM_ICPSC_DIV4 01035 * @arg @ref LL_TIM_ICPSC_DIV8 01036 * @retval Input capture prescaler ratio (1, 2, 4 or 8) 01037 */ 01038 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ 01039 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) 01040 01041 01042 /** 01043 * @} 01044 */ 01045 01046 01047 /** 01048 * @} 01049 */ 01050 01051 /* Exported functions --------------------------------------------------------*/ 01052 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions 01053 * @{ 01054 */ 01055 01056 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration 01057 * @{ 01058 */ 01059 /** 01060 * @brief Enable timer counter. 01061 * @rmtoll CR1 CEN LL_TIM_EnableCounter 01062 * @param TIMx Timer instance 01063 * @retval None 01064 */ 01065 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) 01066 { 01067 SET_BIT(TIMx->CR1, TIM_CR1_CEN); 01068 } 01069 01070 /** 01071 * @brief Disable timer counter. 01072 * @rmtoll CR1 CEN LL_TIM_DisableCounter 01073 * @param TIMx Timer instance 01074 * @retval None 01075 */ 01076 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) 01077 { 01078 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); 01079 } 01080 01081 /** 01082 * @brief Indicates whether the timer counter is enabled. 01083 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter 01084 * @param TIMx Timer instance 01085 * @retval State of bit (1 or 0). 01086 */ 01087 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) 01088 { 01089 return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)); 01090 } 01091 01092 /** 01093 * @brief Enable update event generation. 01094 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent 01095 * @param TIMx Timer instance 01096 * @retval None 01097 */ 01098 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) 01099 { 01100 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); 01101 } 01102 01103 /** 01104 * @brief Disable update event generation. 01105 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent 01106 * @param TIMx Timer instance 01107 * @retval None 01108 */ 01109 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) 01110 { 01111 SET_BIT(TIMx->CR1, TIM_CR1_UDIS); 01112 } 01113 01114 /** 01115 * @brief Indicates whether update event generation is enabled. 01116 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent 01117 * @param TIMx Timer instance 01118 * @retval Inverted state of bit (0 or 1). 01119 */ 01120 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) 01121 { 01122 return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET); 01123 } 01124 01125 /** 01126 * @brief Set update event source 01127 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 01128 * generate an update interrupt or DMA request if enabled: 01129 * - Counter overflow/underflow 01130 * - Setting the UG bit 01131 * - Update generation through the slave mode controller 01132 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 01133 * overflow/underflow generates an update interrupt or DMA request if enabled. 01134 * @rmtoll CR1 URS LL_TIM_SetUpdateSource 01135 * @param TIMx Timer instance 01136 * @param UpdateSource This parameter can be one of the following values: 01137 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 01138 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 01139 * @retval None 01140 */ 01141 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) 01142 { 01143 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); 01144 } 01145 01146 /** 01147 * @brief Get actual event update source 01148 * @rmtoll CR1 URS LL_TIM_GetUpdateSource 01149 * @param TIMx Timer instance 01150 * @retval Returned value can be one of the following values: 01151 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 01152 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 01153 */ 01154 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) 01155 { 01156 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); 01157 } 01158 01159 /** 01160 * @brief Set one pulse mode (one shot v.s. repetitive). 01161 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode 01162 * @param TIMx Timer instance 01163 * @param OnePulseMode This parameter can be one of the following values: 01164 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 01165 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 01166 * @retval None 01167 */ 01168 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) 01169 { 01170 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); 01171 } 01172 01173 /** 01174 * @brief Get actual one pulse mode. 01175 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode 01176 * @param TIMx Timer instance 01177 * @retval Returned value can be one of the following values: 01178 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 01179 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 01180 */ 01181 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) 01182 { 01183 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); 01184 } 01185 01186 /** 01187 * @brief Set the timer counter counting mode. 01188 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 01189 * check whether or not the counter mode selection feature is supported 01190 * by a timer instance. 01191 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n 01192 * CR1 CMS LL_TIM_SetCounterMode 01193 * @param TIMx Timer instance 01194 * @param CounterMode This parameter can be one of the following values: 01195 * @arg @ref LL_TIM_COUNTERMODE_UP 01196 * @arg @ref LL_TIM_COUNTERMODE_DOWN 01197 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 01198 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 01199 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 01200 * @retval None 01201 */ 01202 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) 01203 { 01204 MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode); 01205 } 01206 01207 /** 01208 * @brief Get actual counter mode. 01209 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 01210 * check whether or not the counter mode selection feature is supported 01211 * by a timer instance. 01212 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n 01213 * CR1 CMS LL_TIM_GetCounterMode 01214 * @param TIMx Timer instance 01215 * @retval Returned value can be one of the following values: 01216 * @arg @ref LL_TIM_COUNTERMODE_UP 01217 * @arg @ref LL_TIM_COUNTERMODE_DOWN 01218 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 01219 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 01220 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 01221 */ 01222 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) 01223 { 01224 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); 01225 } 01226 01227 /** 01228 * @brief Enable auto-reload (ARR) preload. 01229 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload 01230 * @param TIMx Timer instance 01231 * @retval None 01232 */ 01233 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) 01234 { 01235 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 01236 } 01237 01238 /** 01239 * @brief Disable auto-reload (ARR) preload. 01240 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload 01241 * @param TIMx Timer instance 01242 * @retval None 01243 */ 01244 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) 01245 { 01246 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); 01247 } 01248 01249 /** 01250 * @brief Indicates whether auto-reload (ARR) preload is enabled. 01251 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload 01252 * @param TIMx Timer instance 01253 * @retval State of bit (1 or 0). 01254 */ 01255 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) 01256 { 01257 return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)); 01258 } 01259 01260 /** 01261 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. 01262 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 01263 * whether or not the clock division feature is supported by the timer 01264 * instance. 01265 * @rmtoll CR1 CKD LL_TIM_SetClockDivision 01266 * @param TIMx Timer instance 01267 * @param ClockDivision This parameter can be one of the following values: 01268 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01269 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01270 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01271 * @retval None 01272 */ 01273 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) 01274 { 01275 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); 01276 } 01277 01278 /** 01279 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. 01280 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 01281 * whether or not the clock division feature is supported by the timer 01282 * instance. 01283 * @rmtoll CR1 CKD LL_TIM_GetClockDivision 01284 * @param TIMx Timer instance 01285 * @retval Returned value can be one of the following values: 01286 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01287 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01288 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01289 */ 01290 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) 01291 { 01292 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); 01293 } 01294 01295 /** 01296 * @brief Set the counter value. 01297 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01298 * whether or not a timer instance supports a 32 bits counter. 01299 * @rmtoll CNT CNT LL_TIM_SetCounter 01300 * @param TIMx Timer instance 01301 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 01302 * @retval None 01303 */ 01304 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) 01305 { 01306 WRITE_REG(TIMx->CNT, Counter); 01307 } 01308 01309 /** 01310 * @brief Get the counter value. 01311 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01312 * whether or not a timer instance supports a 32 bits counter. 01313 * @rmtoll CNT CNT LL_TIM_GetCounter 01314 * @param TIMx Timer instance 01315 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 01316 */ 01317 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) 01318 { 01319 return (uint32_t)(READ_REG(TIMx->CNT)); 01320 } 01321 01322 /** 01323 * @brief Get the current direction of the counter 01324 * @rmtoll CR1 DIR LL_TIM_GetDirection 01325 * @param TIMx Timer instance 01326 * @retval Returned value can be one of the following values: 01327 * @arg @ref LL_TIM_COUNTERDIRECTION_UP 01328 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN 01329 */ 01330 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) 01331 { 01332 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 01333 } 01334 01335 /** 01336 * @brief Set the prescaler value. 01337 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 01338 * @note The prescaler can be changed on the fly as this control register is buffered. The new 01339 * prescaler ratio is taken into account at the next update event. 01340 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter 01341 * @rmtoll PSC PSC LL_TIM_SetPrescaler 01342 * @param TIMx Timer instance 01343 * @param Prescaler between Min_Data=0 and Max_Data=65535 01344 * @retval None 01345 */ 01346 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) 01347 { 01348 WRITE_REG(TIMx->PSC, Prescaler); 01349 } 01350 01351 /** 01352 * @brief Get the prescaler value. 01353 * @rmtoll PSC PSC LL_TIM_GetPrescaler 01354 * @param TIMx Timer instance 01355 * @retval Prescaler value between Min_Data=0 and Max_Data=65535 01356 */ 01357 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) 01358 { 01359 return (uint32_t)(READ_REG(TIMx->PSC)); 01360 } 01361 01362 /** 01363 * @brief Set the auto-reload value. 01364 * @note The counter is blocked while the auto-reload value is null. 01365 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01366 * whether or not a timer instance supports a 32 bits counter. 01367 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter 01368 * @rmtoll ARR ARR LL_TIM_SetAutoReload 01369 * @param TIMx Timer instance 01370 * @param AutoReload between Min_Data=0 and Max_Data=65535 01371 * @retval None 01372 */ 01373 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) 01374 { 01375 WRITE_REG(TIMx->ARR, AutoReload); 01376 } 01377 01378 /** 01379 * @brief Get the auto-reload value. 01380 * @rmtoll ARR ARR LL_TIM_GetAutoReload 01381 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01382 * whether or not a timer instance supports a 32 bits counter. 01383 * @param TIMx Timer instance 01384 * @retval Auto-reload value 01385 */ 01386 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) 01387 { 01388 return (uint32_t)(READ_REG(TIMx->ARR)); 01389 } 01390 01391 /** 01392 * @brief Set the repetition counter value. 01393 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 01394 * whether or not a timer instance supports a repetition counter. 01395 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter 01396 * @param TIMx Timer instance 01397 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 01398 * @retval None 01399 */ 01400 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) 01401 { 01402 WRITE_REG(TIMx->RCR, RepetitionCounter); 01403 } 01404 01405 /** 01406 * @brief Get the repetition counter value. 01407 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 01408 * whether or not a timer instance supports a repetition counter. 01409 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter 01410 * @param TIMx Timer instance 01411 * @retval Repetition counter value 01412 */ 01413 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) 01414 { 01415 return (uint32_t)(READ_REG(TIMx->RCR)); 01416 } 01417 01418 /** 01419 * @} 01420 */ 01421 01422 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration 01423 * @{ 01424 */ 01425 /** 01426 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 01427 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, 01428 * they are updated only when a commutation event (COM) occurs. 01429 * @note Only on channels that have a complementary output. 01430 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01431 * whether or not a timer instance is able to generate a commutation event. 01432 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload 01433 * @param TIMx Timer instance 01434 * @retval None 01435 */ 01436 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) 01437 { 01438 SET_BIT(TIMx->CR2, TIM_CR2_CCPC); 01439 } 01440 01441 /** 01442 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 01443 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01444 * whether or not a timer instance is able to generate a commutation event. 01445 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload 01446 * @param TIMx Timer instance 01447 * @retval None 01448 */ 01449 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) 01450 { 01451 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); 01452 } 01453 01454 /** 01455 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). 01456 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01457 * whether or not a timer instance is able to generate a commutation event. 01458 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate 01459 * @param TIMx Timer instance 01460 * @param CCUpdateSource This parameter can be one of the following values: 01461 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY 01462 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI 01463 * @retval None 01464 */ 01465 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) 01466 { 01467 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); 01468 } 01469 01470 /** 01471 * @brief Set the trigger of the capture/compare DMA request. 01472 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger 01473 * @param TIMx Timer instance 01474 * @param DMAReqTrigger This parameter can be one of the following values: 01475 * @arg @ref LL_TIM_CCDMAREQUEST_CC 01476 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 01477 * @retval None 01478 */ 01479 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) 01480 { 01481 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); 01482 } 01483 01484 /** 01485 * @brief Get actual trigger of the capture/compare DMA request. 01486 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger 01487 * @param TIMx Timer instance 01488 * @retval Returned value can be one of the following values: 01489 * @arg @ref LL_TIM_CCDMAREQUEST_CC 01490 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 01491 */ 01492 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) 01493 { 01494 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); 01495 } 01496 01497 /** 01498 * @brief Set the lock level to freeze the 01499 * configuration of several capture/compare parameters. 01500 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 01501 * the lock mechanism is supported by a timer instance. 01502 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel 01503 * @param TIMx Timer instance 01504 * @param LockLevel This parameter can be one of the following values: 01505 * @arg @ref LL_TIM_LOCKLEVEL_OFF 01506 * @arg @ref LL_TIM_LOCKLEVEL_1 01507 * @arg @ref LL_TIM_LOCKLEVEL_2 01508 * @arg @ref LL_TIM_LOCKLEVEL_3 01509 * @retval None 01510 */ 01511 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) 01512 { 01513 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); 01514 } 01515 01516 /** 01517 * @brief Enable capture/compare channels. 01518 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n 01519 * CCER CC1NE LL_TIM_CC_EnableChannel\n 01520 * CCER CC2E LL_TIM_CC_EnableChannel\n 01521 * CCER CC2NE LL_TIM_CC_EnableChannel\n 01522 * CCER CC3E LL_TIM_CC_EnableChannel\n 01523 * CCER CC3NE LL_TIM_CC_EnableChannel\n 01524 * CCER CC4E LL_TIM_CC_EnableChannel 01525 * @param TIMx Timer instance 01526 * @param Channels This parameter can be a combination of the following values: 01527 * @arg @ref LL_TIM_CHANNEL_CH1 01528 * @arg @ref LL_TIM_CHANNEL_CH1N 01529 * @arg @ref LL_TIM_CHANNEL_CH2 01530 * @arg @ref LL_TIM_CHANNEL_CH2N 01531 * @arg @ref LL_TIM_CHANNEL_CH3 01532 * @arg @ref LL_TIM_CHANNEL_CH3N 01533 * @arg @ref LL_TIM_CHANNEL_CH4 01534 * @retval None 01535 */ 01536 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 01537 { 01538 SET_BIT(TIMx->CCER, Channels); 01539 } 01540 01541 /** 01542 * @brief Disable capture/compare channels. 01543 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n 01544 * CCER CC1NE LL_TIM_CC_DisableChannel\n 01545 * CCER CC2E LL_TIM_CC_DisableChannel\n 01546 * CCER CC2NE LL_TIM_CC_DisableChannel\n 01547 * CCER CC3E LL_TIM_CC_DisableChannel\n 01548 * CCER CC3NE LL_TIM_CC_DisableChannel\n 01549 * CCER CC4E LL_TIM_CC_DisableChannel 01550 * @param TIMx Timer instance 01551 * @param Channels This parameter can be a combination of the following values: 01552 * @arg @ref LL_TIM_CHANNEL_CH1 01553 * @arg @ref LL_TIM_CHANNEL_CH1N 01554 * @arg @ref LL_TIM_CHANNEL_CH2 01555 * @arg @ref LL_TIM_CHANNEL_CH2N 01556 * @arg @ref LL_TIM_CHANNEL_CH3 01557 * @arg @ref LL_TIM_CHANNEL_CH3N 01558 * @arg @ref LL_TIM_CHANNEL_CH4 01559 * @retval None 01560 */ 01561 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 01562 { 01563 CLEAR_BIT(TIMx->CCER, Channels); 01564 } 01565 01566 /** 01567 * @brief Indicate whether channel(s) is(are) enabled. 01568 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n 01569 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n 01570 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n 01571 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n 01572 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n 01573 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n 01574 * CCER CC4E LL_TIM_CC_IsEnabledChannel 01575 * @param TIMx Timer instance 01576 * @param Channels This parameter can be a combination of the following values: 01577 * @arg @ref LL_TIM_CHANNEL_CH1 01578 * @arg @ref LL_TIM_CHANNEL_CH1N 01579 * @arg @ref LL_TIM_CHANNEL_CH2 01580 * @arg @ref LL_TIM_CHANNEL_CH2N 01581 * @arg @ref LL_TIM_CHANNEL_CH3 01582 * @arg @ref LL_TIM_CHANNEL_CH3N 01583 * @arg @ref LL_TIM_CHANNEL_CH4 01584 * @retval State of bit (1 or 0). 01585 */ 01586 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) 01587 { 01588 return (READ_BIT(TIMx->CCER, Channels) == (Channels)); 01589 } 01590 01591 /** 01592 * @} 01593 */ 01594 01595 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration 01596 * @{ 01597 */ 01598 /** 01599 * @brief Configure an output channel. 01600 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n 01601 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n 01602 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n 01603 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n 01604 * CCER CC1P LL_TIM_OC_ConfigOutput\n 01605 * CCER CC2P LL_TIM_OC_ConfigOutput\n 01606 * CCER CC3P LL_TIM_OC_ConfigOutput\n 01607 * CCER CC4P LL_TIM_OC_ConfigOutput\n 01608 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n 01609 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n 01610 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n 01611 * CR2 OIS4 LL_TIM_OC_ConfigOutput 01612 * @param TIMx Timer instance 01613 * @param Channel This parameter can be one of the following values: 01614 * @arg @ref LL_TIM_CHANNEL_CH1 01615 * @arg @ref LL_TIM_CHANNEL_CH2 01616 * @arg @ref LL_TIM_CHANNEL_CH3 01617 * @arg @ref LL_TIM_CHANNEL_CH4 01618 * @param Configuration This parameter must be a combination of all the following values: 01619 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW 01620 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH 01621 * @retval None 01622 */ 01623 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 01624 { 01625 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01626 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01627 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); 01628 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), 01629 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); 01630 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), 01631 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); 01632 } 01633 01634 /** 01635 * @brief Define the behavior of the output reference signal OCxREF from which 01636 * OCx and OCxN (when relevant) are derived. 01637 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n 01638 * CCMR1 OC2M LL_TIM_OC_SetMode\n 01639 * CCMR2 OC3M LL_TIM_OC_SetMode\n 01640 * CCMR2 OC4M LL_TIM_OC_SetMode 01641 * @param TIMx Timer instance 01642 * @param Channel This parameter can be one of the following values: 01643 * @arg @ref LL_TIM_CHANNEL_CH1 01644 * @arg @ref LL_TIM_CHANNEL_CH2 01645 * @arg @ref LL_TIM_CHANNEL_CH3 01646 * @arg @ref LL_TIM_CHANNEL_CH4 01647 * @param Mode This parameter can be one of the following values: 01648 * @arg @ref LL_TIM_OCMODE_FROZEN 01649 * @arg @ref LL_TIM_OCMODE_ACTIVE 01650 * @arg @ref LL_TIM_OCMODE_INACTIVE 01651 * @arg @ref LL_TIM_OCMODE_TOGGLE 01652 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 01653 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 01654 * @arg @ref LL_TIM_OCMODE_PWM1 01655 * @arg @ref LL_TIM_OCMODE_PWM2 01656 * @retval None 01657 */ 01658 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) 01659 { 01660 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01661 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01662 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); 01663 } 01664 01665 /** 01666 * @brief Get the output compare mode of an output channel. 01667 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n 01668 * CCMR1 OC2M LL_TIM_OC_GetMode\n 01669 * CCMR2 OC3M LL_TIM_OC_GetMode\n 01670 * CCMR2 OC4M LL_TIM_OC_GetMode 01671 * @param TIMx Timer instance 01672 * @param Channel This parameter can be one of the following values: 01673 * @arg @ref LL_TIM_CHANNEL_CH1 01674 * @arg @ref LL_TIM_CHANNEL_CH2 01675 * @arg @ref LL_TIM_CHANNEL_CH3 01676 * @arg @ref LL_TIM_CHANNEL_CH4 01677 * @retval Returned value can be one of the following values: 01678 * @arg @ref LL_TIM_OCMODE_FROZEN 01679 * @arg @ref LL_TIM_OCMODE_ACTIVE 01680 * @arg @ref LL_TIM_OCMODE_INACTIVE 01681 * @arg @ref LL_TIM_OCMODE_TOGGLE 01682 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 01683 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 01684 * @arg @ref LL_TIM_OCMODE_PWM1 01685 * @arg @ref LL_TIM_OCMODE_PWM2 01686 */ 01687 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) 01688 { 01689 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01690 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01691 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); 01692 } 01693 01694 /** 01695 * @brief Set the polarity of an output channel. 01696 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n 01697 * CCER CC1NP LL_TIM_OC_SetPolarity\n 01698 * CCER CC2P LL_TIM_OC_SetPolarity\n 01699 * CCER CC2NP LL_TIM_OC_SetPolarity\n 01700 * CCER CC3P LL_TIM_OC_SetPolarity\n 01701 * CCER CC3NP LL_TIM_OC_SetPolarity\n 01702 * CCER CC4P LL_TIM_OC_SetPolarity 01703 * @param TIMx Timer instance 01704 * @param Channel This parameter can be one of the following values: 01705 * @arg @ref LL_TIM_CHANNEL_CH1 01706 * @arg @ref LL_TIM_CHANNEL_CH1N 01707 * @arg @ref LL_TIM_CHANNEL_CH2 01708 * @arg @ref LL_TIM_CHANNEL_CH2N 01709 * @arg @ref LL_TIM_CHANNEL_CH3 01710 * @arg @ref LL_TIM_CHANNEL_CH3N 01711 * @arg @ref LL_TIM_CHANNEL_CH4 01712 * @param Polarity This parameter can be one of the following values: 01713 * @arg @ref LL_TIM_OCPOLARITY_HIGH 01714 * @arg @ref LL_TIM_OCPOLARITY_LOW 01715 * @retval None 01716 */ 01717 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) 01718 { 01719 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01720 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); 01721 } 01722 01723 /** 01724 * @brief Get the polarity of an output channel. 01725 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n 01726 * CCER CC1NP LL_TIM_OC_GetPolarity\n 01727 * CCER CC2P LL_TIM_OC_GetPolarity\n 01728 * CCER CC2NP LL_TIM_OC_GetPolarity\n 01729 * CCER CC3P LL_TIM_OC_GetPolarity\n 01730 * CCER CC3NP LL_TIM_OC_GetPolarity\n 01731 * CCER CC4P LL_TIM_OC_GetPolarity 01732 * @param TIMx Timer instance 01733 * @param Channel This parameter can be one of the following values: 01734 * @arg @ref LL_TIM_CHANNEL_CH1 01735 * @arg @ref LL_TIM_CHANNEL_CH1N 01736 * @arg @ref LL_TIM_CHANNEL_CH2 01737 * @arg @ref LL_TIM_CHANNEL_CH2N 01738 * @arg @ref LL_TIM_CHANNEL_CH3 01739 * @arg @ref LL_TIM_CHANNEL_CH3N 01740 * @arg @ref LL_TIM_CHANNEL_CH4 01741 * @retval Returned value can be one of the following values: 01742 * @arg @ref LL_TIM_OCPOLARITY_HIGH 01743 * @arg @ref LL_TIM_OCPOLARITY_LOW 01744 */ 01745 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) 01746 { 01747 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01748 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); 01749 } 01750 01751 /** 01752 * @brief Set the IDLE state of an output channel 01753 * @note This function is significant only for the timer instances 01754 * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) 01755 * can be used to check whether or not a timer instance provides 01756 * a break input. 01757 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n 01758 * CR2 OIS1N LL_TIM_OC_SetIdleState\n 01759 * CR2 OIS2 LL_TIM_OC_SetIdleState\n 01760 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 01761 * CR2 OIS3 LL_TIM_OC_SetIdleState\n 01762 * CR2 OIS3N LL_TIM_OC_SetIdleState\n 01763 * CR2 OIS4 LL_TIM_OC_SetIdleState 01764 * @param TIMx Timer instance 01765 * @param Channel This parameter can be one of the following values: 01766 * @arg @ref LL_TIM_CHANNEL_CH1 01767 * @arg @ref LL_TIM_CHANNEL_CH1N 01768 * @arg @ref LL_TIM_CHANNEL_CH2 01769 * @arg @ref LL_TIM_CHANNEL_CH2N 01770 * @arg @ref LL_TIM_CHANNEL_CH3 01771 * @arg @ref LL_TIM_CHANNEL_CH3N 01772 * @arg @ref LL_TIM_CHANNEL_CH4 01773 * @param IdleState This parameter can be one of the following values: 01774 * @arg @ref LL_TIM_OCIDLESTATE_LOW 01775 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 01776 * @retval None 01777 */ 01778 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) 01779 { 01780 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01781 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); 01782 } 01783 01784 /** 01785 * @brief Get the IDLE state of an output channel 01786 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n 01787 * CR2 OIS1N LL_TIM_OC_GetIdleState\n 01788 * CR2 OIS2 LL_TIM_OC_GetIdleState\n 01789 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 01790 * CR2 OIS3 LL_TIM_OC_GetIdleState\n 01791 * CR2 OIS3N LL_TIM_OC_GetIdleState\n 01792 * CR2 OIS4 LL_TIM_OC_GetIdleState 01793 * @param TIMx Timer instance 01794 * @param Channel This parameter can be one of the following values: 01795 * @arg @ref LL_TIM_CHANNEL_CH1 01796 * @arg @ref LL_TIM_CHANNEL_CH1N 01797 * @arg @ref LL_TIM_CHANNEL_CH2 01798 * @arg @ref LL_TIM_CHANNEL_CH2N 01799 * @arg @ref LL_TIM_CHANNEL_CH3 01800 * @arg @ref LL_TIM_CHANNEL_CH3N 01801 * @arg @ref LL_TIM_CHANNEL_CH4 01802 * @retval Returned value can be one of the following values: 01803 * @arg @ref LL_TIM_OCIDLESTATE_LOW 01804 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 01805 */ 01806 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) 01807 { 01808 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01809 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); 01810 } 01811 01812 /** 01813 * @brief Enable fast mode for the output channel. 01814 * @note Acts only if the channel is configured in PWM1 or PWM2 mode. 01815 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n 01816 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n 01817 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n 01818 * CCMR2 OC4FE LL_TIM_OC_EnableFast 01819 * @param TIMx Timer instance 01820 * @param Channel This parameter can be one of the following values: 01821 * @arg @ref LL_TIM_CHANNEL_CH1 01822 * @arg @ref LL_TIM_CHANNEL_CH2 01823 * @arg @ref LL_TIM_CHANNEL_CH3 01824 * @arg @ref LL_TIM_CHANNEL_CH4 01825 * @retval None 01826 */ 01827 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) 01828 { 01829 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01830 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01831 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 01832 01833 } 01834 01835 /** 01836 * @brief Disable fast mode for the output channel. 01837 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n 01838 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n 01839 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n 01840 * CCMR2 OC4FE LL_TIM_OC_DisableFast 01841 * @param TIMx Timer instance 01842 * @param Channel This parameter can be one of the following values: 01843 * @arg @ref LL_TIM_CHANNEL_CH1 01844 * @arg @ref LL_TIM_CHANNEL_CH2 01845 * @arg @ref LL_TIM_CHANNEL_CH3 01846 * @arg @ref LL_TIM_CHANNEL_CH4 01847 * @retval None 01848 */ 01849 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) 01850 { 01851 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01852 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01853 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 01854 01855 } 01856 01857 /** 01858 * @brief Indicates whether fast mode is enabled for the output channel. 01859 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n 01860 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n 01861 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n 01862 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n 01863 * @param TIMx Timer instance 01864 * @param Channel This parameter can be one of the following values: 01865 * @arg @ref LL_TIM_CHANNEL_CH1 01866 * @arg @ref LL_TIM_CHANNEL_CH2 01867 * @arg @ref LL_TIM_CHANNEL_CH3 01868 * @arg @ref LL_TIM_CHANNEL_CH4 01869 * @retval State of bit (1 or 0). 01870 */ 01871 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) 01872 { 01873 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01874 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01875 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; 01876 return (READ_BIT(*pReg, bitfield) == bitfield); 01877 } 01878 01879 /** 01880 * @brief Enable compare register (TIMx_CCRx) preload for the output channel. 01881 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n 01882 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n 01883 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n 01884 * CCMR2 OC4PE LL_TIM_OC_EnablePreload 01885 * @param TIMx Timer instance 01886 * @param Channel This parameter can be one of the following values: 01887 * @arg @ref LL_TIM_CHANNEL_CH1 01888 * @arg @ref LL_TIM_CHANNEL_CH2 01889 * @arg @ref LL_TIM_CHANNEL_CH3 01890 * @arg @ref LL_TIM_CHANNEL_CH4 01891 * @retval None 01892 */ 01893 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 01894 { 01895 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01896 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01897 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 01898 } 01899 01900 /** 01901 * @brief Disable compare register (TIMx_CCRx) preload for the output channel. 01902 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n 01903 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n 01904 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n 01905 * CCMR2 OC4PE LL_TIM_OC_DisablePreload 01906 * @param TIMx Timer instance 01907 * @param Channel This parameter can be one of the following values: 01908 * @arg @ref LL_TIM_CHANNEL_CH1 01909 * @arg @ref LL_TIM_CHANNEL_CH2 01910 * @arg @ref LL_TIM_CHANNEL_CH3 01911 * @arg @ref LL_TIM_CHANNEL_CH4 01912 * @retval None 01913 */ 01914 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 01915 { 01916 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01917 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01918 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 01919 } 01920 01921 /** 01922 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. 01923 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n 01924 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n 01925 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n 01926 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n 01927 * @param TIMx Timer instance 01928 * @param Channel This parameter can be one of the following values: 01929 * @arg @ref LL_TIM_CHANNEL_CH1 01930 * @arg @ref LL_TIM_CHANNEL_CH2 01931 * @arg @ref LL_TIM_CHANNEL_CH3 01932 * @arg @ref LL_TIM_CHANNEL_CH4 01933 * @retval State of bit (1 or 0). 01934 */ 01935 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) 01936 { 01937 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01938 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01939 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; 01940 return (READ_BIT(*pReg, bitfield) == bitfield); 01941 } 01942 01943 /** 01944 * @brief Enable clearing the output channel on an external event. 01945 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 01946 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 01947 * or not a timer instance can clear the OCxREF signal on an external event. 01948 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n 01949 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n 01950 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n 01951 * CCMR2 OC4CE LL_TIM_OC_EnableClear 01952 * @param TIMx Timer instance 01953 * @param Channel This parameter can be one of the following values: 01954 * @arg @ref LL_TIM_CHANNEL_CH1 01955 * @arg @ref LL_TIM_CHANNEL_CH2 01956 * @arg @ref LL_TIM_CHANNEL_CH3 01957 * @arg @ref LL_TIM_CHANNEL_CH4 01958 * @retval None 01959 */ 01960 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) 01961 { 01962 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01963 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01964 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 01965 } 01966 01967 /** 01968 * @brief Disable clearing the output channel on an external event. 01969 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 01970 * or not a timer instance can clear the OCxREF signal on an external event. 01971 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n 01972 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n 01973 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n 01974 * CCMR2 OC4CE LL_TIM_OC_DisableClear 01975 * @param TIMx Timer instance 01976 * @param Channel This parameter can be one of the following values: 01977 * @arg @ref LL_TIM_CHANNEL_CH1 01978 * @arg @ref LL_TIM_CHANNEL_CH2 01979 * @arg @ref LL_TIM_CHANNEL_CH3 01980 * @arg @ref LL_TIM_CHANNEL_CH4 01981 * @retval None 01982 */ 01983 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) 01984 { 01985 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 01986 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 01987 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 01988 } 01989 01990 /** 01991 * @brief Indicates clearing the output channel on an external event is enabled for the output channel. 01992 * @note This function enables clearing the output channel on an external event. 01993 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 01994 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 01995 * or not a timer instance can clear the OCxREF signal on an external event. 01996 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n 01997 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n 01998 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n 01999 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n 02000 * @param TIMx Timer instance 02001 * @param Channel This parameter can be one of the following values: 02002 * @arg @ref LL_TIM_CHANNEL_CH1 02003 * @arg @ref LL_TIM_CHANNEL_CH2 02004 * @arg @ref LL_TIM_CHANNEL_CH3 02005 * @arg @ref LL_TIM_CHANNEL_CH4 02006 * @retval State of bit (1 or 0). 02007 */ 02008 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) 02009 { 02010 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02011 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02012 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; 02013 return (READ_BIT(*pReg, bitfield) == bitfield); 02014 } 02015 02016 /** 02017 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals). 02018 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02019 * dead-time insertion feature is supported by a timer instance. 02020 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter 02021 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime 02022 * @param TIMx Timer instance 02023 * @param DeadTime between Min_Data=0 and Max_Data=255 02024 * @retval None 02025 */ 02026 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) 02027 { 02028 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); 02029 } 02030 02031 /** 02032 * @brief Set compare value for output channel 1 (TIMx_CCR1). 02033 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02034 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02035 * whether or not a timer instance supports a 32 bits counter. 02036 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02037 * output channel 1 is supported by a timer instance. 02038 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 02039 * @param TIMx Timer instance 02040 * @param CompareValue between Min_Data=0 and Max_Data=65535 02041 * @retval None 02042 */ 02043 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) 02044 { 02045 WRITE_REG(TIMx->CCR1, CompareValue); 02046 } 02047 02048 /** 02049 * @brief Set compare value for output channel 2 (TIMx_CCR2). 02050 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02051 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02052 * whether or not a timer instance supports a 32 bits counter. 02053 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02054 * output channel 2 is supported by a timer instance. 02055 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 02056 * @param TIMx Timer instance 02057 * @param CompareValue between Min_Data=0 and Max_Data=65535 02058 * @retval None 02059 */ 02060 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) 02061 { 02062 WRITE_REG(TIMx->CCR2, CompareValue); 02063 } 02064 02065 /** 02066 * @brief Set compare value for output channel 3 (TIMx_CCR3). 02067 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02068 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02069 * whether or not a timer instance supports a 32 bits counter. 02070 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02071 * output channel is supported by a timer instance. 02072 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 02073 * @param TIMx Timer instance 02074 * @param CompareValue between Min_Data=0 and Max_Data=65535 02075 * @retval None 02076 */ 02077 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) 02078 { 02079 WRITE_REG(TIMx->CCR3, CompareValue); 02080 } 02081 02082 /** 02083 * @brief Set compare value for output channel 4 (TIMx_CCR4). 02084 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02085 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02086 * whether or not a timer instance supports a 32 bits counter. 02087 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02088 * output channel 4 is supported by a timer instance. 02089 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 02090 * @param TIMx Timer instance 02091 * @param CompareValue between Min_Data=0 and Max_Data=65535 02092 * @retval None 02093 */ 02094 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) 02095 { 02096 WRITE_REG(TIMx->CCR4, CompareValue); 02097 } 02098 02099 /** 02100 * @brief Get compare value (TIMx_CCR1) set for output channel 1. 02101 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02102 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02103 * whether or not a timer instance supports a 32 bits counter. 02104 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02105 * output channel 1 is supported by a timer instance. 02106 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 02107 * @param TIMx Timer instance 02108 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02109 */ 02110 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) 02111 { 02112 return (uint32_t)(READ_REG(TIMx->CCR1)); 02113 } 02114 02115 /** 02116 * @brief Get compare value (TIMx_CCR2) set for output channel 2. 02117 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02118 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02119 * whether or not a timer instance supports a 32 bits counter. 02120 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02121 * output channel 2 is supported by a timer instance. 02122 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 02123 * @param TIMx Timer instance 02124 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02125 */ 02126 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) 02127 { 02128 return (uint32_t)(READ_REG(TIMx->CCR2)); 02129 } 02130 02131 /** 02132 * @brief Get compare value (TIMx_CCR3) set for output channel 3. 02133 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02134 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02135 * whether or not a timer instance supports a 32 bits counter. 02136 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02137 * output channel 3 is supported by a timer instance. 02138 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 02139 * @param TIMx Timer instance 02140 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02141 */ 02142 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) 02143 { 02144 return (uint32_t)(READ_REG(TIMx->CCR3)); 02145 } 02146 02147 /** 02148 * @brief Get compare value (TIMx_CCR4) set for output channel 4. 02149 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02150 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02151 * whether or not a timer instance supports a 32 bits counter. 02152 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02153 * output channel 4 is supported by a timer instance. 02154 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 02155 * @param TIMx Timer instance 02156 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02157 */ 02158 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) 02159 { 02160 return (uint32_t)(READ_REG(TIMx->CCR4)); 02161 } 02162 02163 /** 02164 * @} 02165 */ 02166 02167 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration 02168 * @{ 02169 */ 02170 /** 02171 * @brief Configure input channel. 02172 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n 02173 * CCMR1 IC1PSC LL_TIM_IC_Config\n 02174 * CCMR1 IC1F LL_TIM_IC_Config\n 02175 * CCMR1 CC2S LL_TIM_IC_Config\n 02176 * CCMR1 IC2PSC LL_TIM_IC_Config\n 02177 * CCMR1 IC2F LL_TIM_IC_Config\n 02178 * CCMR2 CC3S LL_TIM_IC_Config\n 02179 * CCMR2 IC3PSC LL_TIM_IC_Config\n 02180 * CCMR2 IC3F LL_TIM_IC_Config\n 02181 * CCMR2 CC4S LL_TIM_IC_Config\n 02182 * CCMR2 IC4PSC LL_TIM_IC_Config\n 02183 * CCMR2 IC4F LL_TIM_IC_Config\n 02184 * CCER CC1P LL_TIM_IC_Config\n 02185 * CCER CC1NP LL_TIM_IC_Config\n 02186 * CCER CC2P LL_TIM_IC_Config\n 02187 * CCER CC2NP LL_TIM_IC_Config\n 02188 * CCER CC3P LL_TIM_IC_Config\n 02189 * CCER CC3NP LL_TIM_IC_Config\n 02190 * CCER CC4P LL_TIM_IC_Config\n 02191 * CCER CC4NP LL_TIM_IC_Config 02192 * @param TIMx Timer instance 02193 * @param Channel This parameter can be one of the following values: 02194 * @arg @ref LL_TIM_CHANNEL_CH1 02195 * @arg @ref LL_TIM_CHANNEL_CH2 02196 * @arg @ref LL_TIM_CHANNEL_CH3 02197 * @arg @ref LL_TIM_CHANNEL_CH4 02198 * @param Configuration This parameter must be a combination of all the following values: 02199 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC 02200 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 02201 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 02202 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE 02203 * @retval None 02204 */ 02205 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 02206 { 02207 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02208 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02209 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), 02210 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); 02211 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 02212 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); 02213 } 02214 02215 /** 02216 * @brief Set the active input. 02217 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n 02218 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n 02219 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n 02220 * CCMR2 CC4S LL_TIM_IC_SetActiveInput 02221 * @param TIMx Timer instance 02222 * @param Channel This parameter can be one of the following values: 02223 * @arg @ref LL_TIM_CHANNEL_CH1 02224 * @arg @ref LL_TIM_CHANNEL_CH2 02225 * @arg @ref LL_TIM_CHANNEL_CH3 02226 * @arg @ref LL_TIM_CHANNEL_CH4 02227 * @param ICActiveInput This parameter can be one of the following values: 02228 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 02229 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 02230 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 02231 * @retval None 02232 */ 02233 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) 02234 { 02235 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02236 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02237 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02238 } 02239 02240 /** 02241 * @brief Get the current active input. 02242 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n 02243 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n 02244 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n 02245 * CCMR2 CC4S LL_TIM_IC_GetActiveInput 02246 * @param TIMx Timer instance 02247 * @param Channel This parameter can be one of the following values: 02248 * @arg @ref LL_TIM_CHANNEL_CH1 02249 * @arg @ref LL_TIM_CHANNEL_CH2 02250 * @arg @ref LL_TIM_CHANNEL_CH3 02251 * @arg @ref LL_TIM_CHANNEL_CH4 02252 * @retval Returned value can be one of the following values: 02253 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 02254 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 02255 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 02256 */ 02257 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) 02258 { 02259 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02260 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02261 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02262 } 02263 02264 /** 02265 * @brief Set the prescaler of input channel. 02266 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n 02267 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n 02268 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n 02269 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler 02270 * @param TIMx Timer instance 02271 * @param Channel This parameter can be one of the following values: 02272 * @arg @ref LL_TIM_CHANNEL_CH1 02273 * @arg @ref LL_TIM_CHANNEL_CH2 02274 * @arg @ref LL_TIM_CHANNEL_CH3 02275 * @arg @ref LL_TIM_CHANNEL_CH4 02276 * @param ICPrescaler This parameter can be one of the following values: 02277 * @arg @ref LL_TIM_ICPSC_DIV1 02278 * @arg @ref LL_TIM_ICPSC_DIV2 02279 * @arg @ref LL_TIM_ICPSC_DIV4 02280 * @arg @ref LL_TIM_ICPSC_DIV8 02281 * @retval None 02282 */ 02283 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) 02284 { 02285 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02286 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02287 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02288 } 02289 02290 /** 02291 * @brief Get the current prescaler value acting on an input channel. 02292 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n 02293 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n 02294 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n 02295 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler 02296 * @param TIMx Timer instance 02297 * @param Channel This parameter can be one of the following values: 02298 * @arg @ref LL_TIM_CHANNEL_CH1 02299 * @arg @ref LL_TIM_CHANNEL_CH2 02300 * @arg @ref LL_TIM_CHANNEL_CH3 02301 * @arg @ref LL_TIM_CHANNEL_CH4 02302 * @retval Returned value can be one of the following values: 02303 * @arg @ref LL_TIM_ICPSC_DIV1 02304 * @arg @ref LL_TIM_ICPSC_DIV2 02305 * @arg @ref LL_TIM_ICPSC_DIV4 02306 * @arg @ref LL_TIM_ICPSC_DIV8 02307 */ 02308 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) 02309 { 02310 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02311 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02312 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02313 } 02314 02315 /** 02316 * @brief Set the input filter duration. 02317 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n 02318 * CCMR1 IC2F LL_TIM_IC_SetFilter\n 02319 * CCMR2 IC3F LL_TIM_IC_SetFilter\n 02320 * CCMR2 IC4F LL_TIM_IC_SetFilter 02321 * @param TIMx Timer instance 02322 * @param Channel This parameter can be one of the following values: 02323 * @arg @ref LL_TIM_CHANNEL_CH1 02324 * @arg @ref LL_TIM_CHANNEL_CH2 02325 * @arg @ref LL_TIM_CHANNEL_CH3 02326 * @arg @ref LL_TIM_CHANNEL_CH4 02327 * @param ICFilter This parameter can be one of the following values: 02328 * @arg @ref LL_TIM_IC_FILTER_FDIV1 02329 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 02330 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 02331 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 02332 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 02333 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 02334 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 02335 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 02336 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 02337 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 02338 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 02339 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 02340 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 02341 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 02342 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 02343 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 02344 * @retval None 02345 */ 02346 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) 02347 { 02348 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02349 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02350 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02351 } 02352 02353 /** 02354 * @brief Get the input filter duration. 02355 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n 02356 * CCMR1 IC2F LL_TIM_IC_GetFilter\n 02357 * CCMR2 IC3F LL_TIM_IC_GetFilter\n 02358 * CCMR2 IC4F LL_TIM_IC_GetFilter 02359 * @param TIMx Timer instance 02360 * @param Channel This parameter can be one of the following values: 02361 * @arg @ref LL_TIM_CHANNEL_CH1 02362 * @arg @ref LL_TIM_CHANNEL_CH2 02363 * @arg @ref LL_TIM_CHANNEL_CH3 02364 * @arg @ref LL_TIM_CHANNEL_CH4 02365 * @retval Returned value can be one of the following values: 02366 * @arg @ref LL_TIM_IC_FILTER_FDIV1 02367 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 02368 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 02369 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 02370 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 02371 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 02372 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 02373 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 02374 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 02375 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 02376 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 02377 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 02378 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 02379 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 02380 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 02381 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 02382 */ 02383 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) 02384 { 02385 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02386 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02387 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02388 } 02389 02390 /** 02391 * @brief Set the input channel polarity. 02392 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n 02393 * CCER CC1NP LL_TIM_IC_SetPolarity\n 02394 * CCER CC2P LL_TIM_IC_SetPolarity\n 02395 * CCER CC2NP LL_TIM_IC_SetPolarity\n 02396 * CCER CC3P LL_TIM_IC_SetPolarity\n 02397 * CCER CC3NP LL_TIM_IC_SetPolarity\n 02398 * CCER CC4P LL_TIM_IC_SetPolarity\n 02399 * CCER CC4NP LL_TIM_IC_SetPolarity 02400 * @param TIMx Timer instance 02401 * @param Channel This parameter can be one of the following values: 02402 * @arg @ref LL_TIM_CHANNEL_CH1 02403 * @arg @ref LL_TIM_CHANNEL_CH2 02404 * @arg @ref LL_TIM_CHANNEL_CH3 02405 * @arg @ref LL_TIM_CHANNEL_CH4 02406 * @param ICPolarity This parameter can be one of the following values: 02407 * @arg @ref LL_TIM_IC_POLARITY_RISING 02408 * @arg @ref LL_TIM_IC_POLARITY_FALLING 02409 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 02410 * @retval None 02411 */ 02412 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) 02413 { 02414 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02415 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 02416 ICPolarity << SHIFT_TAB_CCxP[iChannel]); 02417 } 02418 02419 /** 02420 * @brief Get the current input channel polarity. 02421 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n 02422 * CCER CC1NP LL_TIM_IC_GetPolarity\n 02423 * CCER CC2P LL_TIM_IC_GetPolarity\n 02424 * CCER CC2NP LL_TIM_IC_GetPolarity\n 02425 * CCER CC3P LL_TIM_IC_GetPolarity\n 02426 * CCER CC3NP LL_TIM_IC_GetPolarity\n 02427 * CCER CC4P LL_TIM_IC_GetPolarity\n 02428 * CCER CC4NP LL_TIM_IC_GetPolarity 02429 * @param TIMx Timer instance 02430 * @param Channel This parameter can be one of the following values: 02431 * @arg @ref LL_TIM_CHANNEL_CH1 02432 * @arg @ref LL_TIM_CHANNEL_CH2 02433 * @arg @ref LL_TIM_CHANNEL_CH3 02434 * @arg @ref LL_TIM_CHANNEL_CH4 02435 * @retval Returned value can be one of the following values: 02436 * @arg @ref LL_TIM_IC_POLARITY_RISING 02437 * @arg @ref LL_TIM_IC_POLARITY_FALLING 02438 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 02439 */ 02440 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) 02441 { 02442 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02443 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> 02444 SHIFT_TAB_CCxP[iChannel]); 02445 } 02446 02447 /** 02448 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). 02449 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 02450 * a timer instance provides an XOR input. 02451 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination 02452 * @param TIMx Timer instance 02453 * @retval None 02454 */ 02455 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) 02456 { 02457 SET_BIT(TIMx->CR2, TIM_CR2_TI1S); 02458 } 02459 02460 /** 02461 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. 02462 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 02463 * a timer instance provides an XOR input. 02464 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination 02465 * @param TIMx Timer instance 02466 * @retval None 02467 */ 02468 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) 02469 { 02470 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); 02471 } 02472 02473 /** 02474 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. 02475 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 02476 * a timer instance provides an XOR input. 02477 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination 02478 * @param TIMx Timer instance 02479 * @retval State of bit (1 or 0). 02480 */ 02481 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) 02482 { 02483 return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)); 02484 } 02485 02486 /** 02487 * @brief Get captured value for input channel 1. 02488 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 02489 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02490 * whether or not a timer instance supports a 32 bits counter. 02491 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02492 * input channel 1 is supported by a timer instance. 02493 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 02494 * @param TIMx Timer instance 02495 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 02496 */ 02497 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) 02498 { 02499 return (uint32_t)(READ_REG(TIMx->CCR1)); 02500 } 02501 02502 /** 02503 * @brief Get captured value for input channel 2. 02504 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 02505 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02506 * whether or not a timer instance supports a 32 bits counter. 02507 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02508 * input channel 2 is supported by a timer instance. 02509 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 02510 * @param TIMx Timer instance 02511 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 02512 */ 02513 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) 02514 { 02515 return (uint32_t)(READ_REG(TIMx->CCR2)); 02516 } 02517 02518 /** 02519 * @brief Get captured value for input channel 3. 02520 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 02521 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02522 * whether or not a timer instance supports a 32 bits counter. 02523 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02524 * input channel 3 is supported by a timer instance. 02525 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 02526 * @param TIMx Timer instance 02527 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 02528 */ 02529 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) 02530 { 02531 return (uint32_t)(READ_REG(TIMx->CCR3)); 02532 } 02533 02534 /** 02535 * @brief Get captured value for input channel 4. 02536 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 02537 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02538 * whether or not a timer instance supports a 32 bits counter. 02539 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02540 * input channel 4 is supported by a timer instance. 02541 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 02542 * @param TIMx Timer instance 02543 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 02544 */ 02545 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) 02546 { 02547 return (uint32_t)(READ_REG(TIMx->CCR4)); 02548 } 02549 02550 /** 02551 * @} 02552 */ 02553 02554 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection 02555 * @{ 02556 */ 02557 /** 02558 * @brief Enable external clock mode 2. 02559 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. 02560 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 02561 * whether or not a timer instance supports external clock mode2. 02562 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock 02563 * @param TIMx Timer instance 02564 * @retval None 02565 */ 02566 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) 02567 { 02568 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); 02569 } 02570 02571 /** 02572 * @brief Disable external clock mode 2. 02573 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 02574 * whether or not a timer instance supports external clock mode2. 02575 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock 02576 * @param TIMx Timer instance 02577 * @retval None 02578 */ 02579 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) 02580 { 02581 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); 02582 } 02583 02584 /** 02585 * @brief Indicate whether external clock mode 2 is enabled. 02586 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 02587 * whether or not a timer instance supports external clock mode2. 02588 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock 02589 * @param TIMx Timer instance 02590 * @retval State of bit (1 or 0). 02591 */ 02592 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) 02593 { 02594 return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)); 02595 } 02596 02597 /** 02598 * @brief Set the clock source of the counter clock. 02599 * @note when selected clock source is external clock mode 1, the timer input 02600 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() 02601 * function. This timer input must be configured by calling 02602 * the @ref LL_TIM_IC_Config() function. 02603 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 02604 * whether or not a timer instance supports external clock mode1. 02605 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 02606 * whether or not a timer instance supports external clock mode2. 02607 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n 02608 * SMCR ECE LL_TIM_SetClockSource 02609 * @param TIMx Timer instance 02610 * @param ClockSource This parameter can be one of the following values: 02611 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL 02612 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 02613 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 02614 * @retval None 02615 */ 02616 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) 02617 { 02618 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 02619 } 02620 02621 /** 02622 * @brief Set the encoder interface mode. 02623 * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 02624 * whether or not a timer instance supports the encoder mode. 02625 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode 02626 * @param TIMx Timer instance 02627 * @param EncoderMode This parameter can be one of the following values: 02628 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 02629 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 02630 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 02631 * @retval None 02632 */ 02633 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) 02634 { 02635 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); 02636 } 02637 02638 /** 02639 * @} 02640 */ 02641 02642 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration 02643 * @{ 02644 */ 02645 /** 02646 * @brief Set the trigger output (TRGO) used for timer synchronization . 02647 * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 02648 * whether or not a timer instance can operate as a master timer. 02649 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput 02650 * @param TIMx Timer instance 02651 * @param TimerSynchronization This parameter can be one of the following values: 02652 * @arg @ref LL_TIM_TRGO_RESET 02653 * @arg @ref LL_TIM_TRGO_ENABLE 02654 * @arg @ref LL_TIM_TRGO_UPDATE 02655 * @arg @ref LL_TIM_TRGO_CC1IF 02656 * @arg @ref LL_TIM_TRGO_OC1REF 02657 * @arg @ref LL_TIM_TRGO_OC2REF 02658 * @arg @ref LL_TIM_TRGO_OC3REF 02659 * @arg @ref LL_TIM_TRGO_OC4REF 02660 * @retval None 02661 */ 02662 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) 02663 { 02664 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 02665 } 02666 02667 /** 02668 * @brief Set the synchronization mode of a slave timer. 02669 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 02670 * a timer instance can operate as a slave timer. 02671 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode 02672 * @param TIMx Timer instance 02673 * @param SlaveMode This parameter can be one of the following values: 02674 * @arg @ref LL_TIM_SLAVEMODE_DISABLED 02675 * @arg @ref LL_TIM_SLAVEMODE_RESET 02676 * @arg @ref LL_TIM_SLAVEMODE_GATED 02677 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER 02678 * @retval None 02679 */ 02680 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) 02681 { 02682 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); 02683 } 02684 02685 /** 02686 * @brief Set the selects the trigger input to be used to synchronize the counter. 02687 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 02688 * a timer instance can operate as a slave timer. 02689 * @rmtoll SMCR TS LL_TIM_SetTriggerInput 02690 * @param TIMx Timer instance 02691 * @param TriggerInput This parameter can be one of the following values: 02692 * @arg @ref LL_TIM_TS_ITR0 02693 * @arg @ref LL_TIM_TS_ITR1 02694 * @arg @ref LL_TIM_TS_ITR2 02695 * @arg @ref LL_TIM_TS_ITR3 02696 * @arg @ref LL_TIM_TS_TI1F_ED 02697 * @arg @ref LL_TIM_TS_TI1FP1 02698 * @arg @ref LL_TIM_TS_TI2FP2 02699 * @arg @ref LL_TIM_TS_ETRF 02700 * @retval None 02701 */ 02702 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) 02703 { 02704 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); 02705 } 02706 02707 /** 02708 * @brief Enable the Master/Slave mode. 02709 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 02710 * a timer instance can operate as a slave timer. 02711 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode 02712 * @param TIMx Timer instance 02713 * @retval None 02714 */ 02715 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) 02716 { 02717 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); 02718 } 02719 02720 /** 02721 * @brief Disable the Master/Slave mode. 02722 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 02723 * a timer instance can operate as a slave timer. 02724 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode 02725 * @param TIMx Timer instance 02726 * @retval None 02727 */ 02728 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) 02729 { 02730 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 02731 } 02732 02733 /** 02734 * @brief Indicates whether the Master/Slave mode is enabled. 02735 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 02736 * a timer instance can operate as a slave timer. 02737 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode 02738 * @param TIMx Timer instance 02739 * @retval State of bit (1 or 0). 02740 */ 02741 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) 02742 { 02743 return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)); 02744 } 02745 02746 /** 02747 * @brief Configure the external trigger (ETR) input. 02748 * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 02749 * a timer instance provides an external trigger input. 02750 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n 02751 * SMCR ETPS LL_TIM_ConfigETR\n 02752 * SMCR ETF LL_TIM_ConfigETR 02753 * @param TIMx Timer instance 02754 * @param ETRPolarity This parameter can be one of the following values: 02755 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED 02756 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED 02757 * @param ETRPrescaler This parameter can be one of the following values: 02758 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 02759 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 02760 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 02761 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 02762 * @param ETRFilter This parameter can be one of the following values: 02763 * @arg @ref LL_TIM_ETR_FILTER_FDIV1 02764 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 02765 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 02766 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 02767 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 02768 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 02769 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 02770 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 02771 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 02772 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 02773 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 02774 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 02775 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 02776 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 02777 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 02778 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 02779 * @retval None 02780 */ 02781 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, 02782 uint32_t ETRFilter) 02783 { 02784 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); 02785 } 02786 02787 /** 02788 * @} 02789 */ 02790 02791 /** @defgroup TIM_LL_EF_Break_Function Break function configuration 02792 * @{ 02793 */ 02794 /** 02795 * @brief Enable the break function. 02796 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02797 * a timer instance provides a break input. 02798 * @rmtoll BDTR BKE LL_TIM_EnableBRK 02799 * @param TIMx Timer instance 02800 * @retval None 02801 */ 02802 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) 02803 { 02804 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); 02805 } 02806 02807 /** 02808 * @brief Disable the break function. 02809 * @rmtoll BDTR BKE LL_TIM_DisableBRK 02810 * @param TIMx Timer instance 02811 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02812 * a timer instance provides a break input. 02813 * @retval None 02814 */ 02815 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) 02816 { 02817 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); 02818 } 02819 02820 /** 02821 * @brief Configure the break input. 02822 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02823 * a timer instance provides a break input. 02824 * @rmtoll BDTR BKP LL_TIM_ConfigBRK 02825 * @param TIMx Timer instance 02826 * @param BreakPolarity This parameter can be one of the following values: 02827 * @arg @ref LL_TIM_BREAK_POLARITY_LOW 02828 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 02829 * @retval None 02830 */ 02831 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) 02832 { 02833 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); 02834 } 02835 02836 /** 02837 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. 02838 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02839 * a timer instance provides a break input. 02840 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n 02841 * BDTR OSSR LL_TIM_SetOffStates 02842 * @param TIMx Timer instance 02843 * @param OffStateIdle This parameter can be one of the following values: 02844 * @arg @ref LL_TIM_OSSI_DISABLE 02845 * @arg @ref LL_TIM_OSSI_ENABLE 02846 * @param OffStateRun This parameter can be one of the following values: 02847 * @arg @ref LL_TIM_OSSR_DISABLE 02848 * @arg @ref LL_TIM_OSSR_ENABLE 02849 * @retval None 02850 */ 02851 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) 02852 { 02853 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); 02854 } 02855 02856 /** 02857 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). 02858 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02859 * a timer instance provides a break input. 02860 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput 02861 * @param TIMx Timer instance 02862 * @retval None 02863 */ 02864 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) 02865 { 02866 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); 02867 } 02868 02869 /** 02870 * @brief Disable automatic output (MOE can be set only by software). 02871 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02872 * a timer instance provides a break input. 02873 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput 02874 * @param TIMx Timer instance 02875 * @retval None 02876 */ 02877 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) 02878 { 02879 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); 02880 } 02881 02882 /** 02883 * @brief Indicate whether automatic output is enabled. 02884 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02885 * a timer instance provides a break input. 02886 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput 02887 * @param TIMx Timer instance 02888 * @retval State of bit (1 or 0). 02889 */ 02890 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) 02891 { 02892 return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)); 02893 } 02894 02895 /** 02896 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). 02897 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 02898 * software and is reset in case of break or break2 event 02899 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02900 * a timer instance provides a break input. 02901 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs 02902 * @param TIMx Timer instance 02903 * @retval None 02904 */ 02905 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) 02906 { 02907 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); 02908 } 02909 02910 /** 02911 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). 02912 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 02913 * software and is reset in case of break or break2 event. 02914 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02915 * a timer instance provides a break input. 02916 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs 02917 * @param TIMx Timer instance 02918 * @retval None 02919 */ 02920 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) 02921 { 02922 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); 02923 } 02924 02925 /** 02926 * @brief Indicates whether outputs are enabled. 02927 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02928 * a timer instance provides a break input. 02929 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs 02930 * @param TIMx Timer instance 02931 * @retval State of bit (1 or 0). 02932 */ 02933 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) 02934 { 02935 return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)); 02936 } 02937 02938 /** 02939 * @} 02940 */ 02941 02942 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration 02943 * @{ 02944 */ 02945 /** 02946 * @brief Configures the timer DMA burst feature. 02947 * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or 02948 * not a timer instance supports the DMA burst mode. 02949 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n 02950 * DCR DBA LL_TIM_ConfigDMABurst 02951 * @param TIMx Timer instance 02952 * @param DMABurstBaseAddress This parameter can be one of the following values: 02953 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 02954 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 02955 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR 02956 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER 02957 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR 02958 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR 02959 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 02960 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 02961 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER 02962 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT 02963 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC 02964 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR 02965 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR 02966 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 02967 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 02968 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 02969 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 02970 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR 02971 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR 02972 * @param DMABurstLength This parameter can be one of the following values: 02973 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER 02974 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS 02975 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS 02976 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS 02977 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS 02978 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS 02979 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS 02980 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS 02981 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS 02982 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS 02983 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS 02984 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS 02985 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS 02986 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS 02987 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS 02988 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS 02989 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS 02990 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS 02991 * @retval None 02992 */ 02993 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) 02994 { 02995 MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength); 02996 } 02997 02998 /** 02999 * @} 03000 */ 03001 03002 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping 03003 * @{ 03004 */ 03005 /** 03006 * @brief Remap TIM inputs (input channel, internal/external triggers). 03007 * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not 03008 * a some timer inputs can be remapped. 03009 * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n 03010 * TIM5_OR TI4_RMP LL_TIM_SetRemap\n 03011 * TIM11_OR TI1_RMP LL_TIM_SetRemap 03012 * @param TIMx Timer instance 03013 * @param Remap Remap param depends on the TIMx. Description available only 03014 * in CHM version of the User Manual (not in .pdf). 03015 * Otherwise see Reference Manual description of OR registers. 03016 * 03017 * Below description summarizes "Timer Instance" and "Remap" param combinations: 03018 * 03019 * TIM2: one of the following values 03020 * 03021 * ITR1_RMP can be one of the following values 03022 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO 03023 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF 03024 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF 03025 * 03026 * TIM5: one of the following values 03027 * 03028 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO 03029 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI 03030 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE 03031 * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC 03032 * 03033 * TIM11: one of the following values 03034 * 03035 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO 03036 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO1 03037 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE_RTC 03038 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO2 03039 * 03040 * @retval None 03041 */ 03042 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) 03043 { 03044 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK)); 03045 } 03046 03047 /** 03048 * @} 03049 */ 03050 03051 03052 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management 03053 * @{ 03054 */ 03055 /** 03056 * @brief Clear the update interrupt flag (UIF). 03057 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE 03058 * @param TIMx Timer instance 03059 * @retval None 03060 */ 03061 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) 03062 { 03063 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 03064 } 03065 03066 /** 03067 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). 03068 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE 03069 * @param TIMx Timer instance 03070 * @retval State of bit (1 or 0). 03071 */ 03072 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) 03073 { 03074 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)); 03075 } 03076 03077 /** 03078 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). 03079 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 03080 * @param TIMx Timer instance 03081 * @retval None 03082 */ 03083 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) 03084 { 03085 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); 03086 } 03087 03088 /** 03089 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). 03090 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 03091 * @param TIMx Timer instance 03092 * @retval State of bit (1 or 0). 03093 */ 03094 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) 03095 { 03096 return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)); 03097 } 03098 03099 /** 03100 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). 03101 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 03102 * @param TIMx Timer instance 03103 * @retval None 03104 */ 03105 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) 03106 { 03107 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); 03108 } 03109 03110 /** 03111 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). 03112 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 03113 * @param TIMx Timer instance 03114 * @retval State of bit (1 or 0). 03115 */ 03116 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) 03117 { 03118 return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)); 03119 } 03120 03121 /** 03122 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). 03123 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 03124 * @param TIMx Timer instance 03125 * @retval None 03126 */ 03127 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) 03128 { 03129 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); 03130 } 03131 03132 /** 03133 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). 03134 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 03135 * @param TIMx Timer instance 03136 * @retval State of bit (1 or 0). 03137 */ 03138 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) 03139 { 03140 return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)); 03141 } 03142 03143 /** 03144 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). 03145 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 03146 * @param TIMx Timer instance 03147 * @retval None 03148 */ 03149 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) 03150 { 03151 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); 03152 } 03153 03154 /** 03155 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). 03156 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 03157 * @param TIMx Timer instance 03158 * @retval State of bit (1 or 0). 03159 */ 03160 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) 03161 { 03162 return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)); 03163 } 03164 03165 /** 03166 * @brief Clear the commutation interrupt flag (COMIF). 03167 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM 03168 * @param TIMx Timer instance 03169 * @retval None 03170 */ 03171 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) 03172 { 03173 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); 03174 } 03175 03176 /** 03177 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). 03178 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM 03179 * @param TIMx Timer instance 03180 * @retval State of bit (1 or 0). 03181 */ 03182 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) 03183 { 03184 return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)); 03185 } 03186 03187 /** 03188 * @brief Clear the trigger interrupt flag (TIF). 03189 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG 03190 * @param TIMx Timer instance 03191 * @retval None 03192 */ 03193 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) 03194 { 03195 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); 03196 } 03197 03198 /** 03199 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). 03200 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG 03201 * @param TIMx Timer instance 03202 * @retval State of bit (1 or 0). 03203 */ 03204 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) 03205 { 03206 return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)); 03207 } 03208 03209 /** 03210 * @brief Clear the break interrupt flag (BIF). 03211 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK 03212 * @param TIMx Timer instance 03213 * @retval None 03214 */ 03215 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) 03216 { 03217 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); 03218 } 03219 03220 /** 03221 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). 03222 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK 03223 * @param TIMx Timer instance 03224 * @retval State of bit (1 or 0). 03225 */ 03226 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) 03227 { 03228 return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)); 03229 } 03230 03231 /** 03232 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). 03233 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR 03234 * @param TIMx Timer instance 03235 * @retval None 03236 */ 03237 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) 03238 { 03239 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); 03240 } 03241 03242 /** 03243 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). 03244 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR 03245 * @param TIMx Timer instance 03246 * @retval State of bit (1 or 0). 03247 */ 03248 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) 03249 { 03250 return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)); 03251 } 03252 03253 /** 03254 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). 03255 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR 03256 * @param TIMx Timer instance 03257 * @retval None 03258 */ 03259 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) 03260 { 03261 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); 03262 } 03263 03264 /** 03265 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). 03266 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR 03267 * @param TIMx Timer instance 03268 * @retval State of bit (1 or 0). 03269 */ 03270 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) 03271 { 03272 return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)); 03273 } 03274 03275 /** 03276 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). 03277 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR 03278 * @param TIMx Timer instance 03279 * @retval None 03280 */ 03281 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) 03282 { 03283 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); 03284 } 03285 03286 /** 03287 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). 03288 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR 03289 * @param TIMx Timer instance 03290 * @retval State of bit (1 or 0). 03291 */ 03292 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) 03293 { 03294 return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)); 03295 } 03296 03297 /** 03298 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). 03299 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR 03300 * @param TIMx Timer instance 03301 * @retval None 03302 */ 03303 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) 03304 { 03305 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); 03306 } 03307 03308 /** 03309 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). 03310 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR 03311 * @param TIMx Timer instance 03312 * @retval State of bit (1 or 0). 03313 */ 03314 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) 03315 { 03316 return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)); 03317 } 03318 03319 /** 03320 * @} 03321 */ 03322 03323 /** @defgroup TIM_LL_EF_IT_Management IT-Management 03324 * @{ 03325 */ 03326 /** 03327 * @brief Enable update interrupt (UIE). 03328 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE 03329 * @param TIMx Timer instance 03330 * @retval None 03331 */ 03332 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) 03333 { 03334 SET_BIT(TIMx->DIER, TIM_DIER_UIE); 03335 } 03336 03337 /** 03338 * @brief Disable update interrupt (UIE). 03339 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE 03340 * @param TIMx Timer instance 03341 * @retval None 03342 */ 03343 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) 03344 { 03345 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); 03346 } 03347 03348 /** 03349 * @brief Indicates whether the update interrupt (UIE) is enabled. 03350 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE 03351 * @param TIMx Timer instance 03352 * @retval State of bit (1 or 0). 03353 */ 03354 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) 03355 { 03356 return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)); 03357 } 03358 03359 /** 03360 * @brief Enable capture/compare 1 interrupt (CC1IE). 03361 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 03362 * @param TIMx Timer instance 03363 * @retval None 03364 */ 03365 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) 03366 { 03367 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); 03368 } 03369 03370 /** 03371 * @brief Disable capture/compare 1 interrupt (CC1IE). 03372 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 03373 * @param TIMx Timer instance 03374 * @retval None 03375 */ 03376 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) 03377 { 03378 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); 03379 } 03380 03381 /** 03382 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. 03383 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 03384 * @param TIMx Timer instance 03385 * @retval State of bit (1 or 0). 03386 */ 03387 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) 03388 { 03389 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)); 03390 } 03391 03392 /** 03393 * @brief Enable capture/compare 2 interrupt (CC2IE). 03394 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 03395 * @param TIMx Timer instance 03396 * @retval None 03397 */ 03398 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) 03399 { 03400 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); 03401 } 03402 03403 /** 03404 * @brief Disable capture/compare 2 interrupt (CC2IE). 03405 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 03406 * @param TIMx Timer instance 03407 * @retval None 03408 */ 03409 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) 03410 { 03411 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); 03412 } 03413 03414 /** 03415 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. 03416 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 03417 * @param TIMx Timer instance 03418 * @retval State of bit (1 or 0). 03419 */ 03420 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) 03421 { 03422 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)); 03423 } 03424 03425 /** 03426 * @brief Enable capture/compare 3 interrupt (CC3IE). 03427 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 03428 * @param TIMx Timer instance 03429 * @retval None 03430 */ 03431 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) 03432 { 03433 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); 03434 } 03435 03436 /** 03437 * @brief Disable capture/compare 3 interrupt (CC3IE). 03438 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 03439 * @param TIMx Timer instance 03440 * @retval None 03441 */ 03442 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) 03443 { 03444 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); 03445 } 03446 03447 /** 03448 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. 03449 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 03450 * @param TIMx Timer instance 03451 * @retval State of bit (1 or 0). 03452 */ 03453 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) 03454 { 03455 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)); 03456 } 03457 03458 /** 03459 * @brief Enable capture/compare 4 interrupt (CC4IE). 03460 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 03461 * @param TIMx Timer instance 03462 * @retval None 03463 */ 03464 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) 03465 { 03466 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); 03467 } 03468 03469 /** 03470 * @brief Disable capture/compare 4 interrupt (CC4IE). 03471 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 03472 * @param TIMx Timer instance 03473 * @retval None 03474 */ 03475 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) 03476 { 03477 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); 03478 } 03479 03480 /** 03481 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. 03482 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 03483 * @param TIMx Timer instance 03484 * @retval State of bit (1 or 0). 03485 */ 03486 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) 03487 { 03488 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)); 03489 } 03490 03491 /** 03492 * @brief Enable commutation interrupt (COMIE). 03493 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM 03494 * @param TIMx Timer instance 03495 * @retval None 03496 */ 03497 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) 03498 { 03499 SET_BIT(TIMx->DIER, TIM_DIER_COMIE); 03500 } 03501 03502 /** 03503 * @brief Disable commutation interrupt (COMIE). 03504 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM 03505 * @param TIMx Timer instance 03506 * @retval None 03507 */ 03508 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) 03509 { 03510 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); 03511 } 03512 03513 /** 03514 * @brief Indicates whether the commutation interrupt (COMIE) is enabled. 03515 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM 03516 * @param TIMx Timer instance 03517 * @retval State of bit (1 or 0). 03518 */ 03519 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) 03520 { 03521 return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)); 03522 } 03523 03524 /** 03525 * @brief Enable trigger interrupt (TIE). 03526 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG 03527 * @param TIMx Timer instance 03528 * @retval None 03529 */ 03530 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) 03531 { 03532 SET_BIT(TIMx->DIER, TIM_DIER_TIE); 03533 } 03534 03535 /** 03536 * @brief Disable trigger interrupt (TIE). 03537 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG 03538 * @param TIMx Timer instance 03539 * @retval None 03540 */ 03541 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) 03542 { 03543 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); 03544 } 03545 03546 /** 03547 * @brief Indicates whether the trigger interrupt (TIE) is enabled. 03548 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG 03549 * @param TIMx Timer instance 03550 * @retval State of bit (1 or 0). 03551 */ 03552 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) 03553 { 03554 return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)); 03555 } 03556 03557 /** 03558 * @brief Enable break interrupt (BIE). 03559 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK 03560 * @param TIMx Timer instance 03561 * @retval None 03562 */ 03563 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) 03564 { 03565 SET_BIT(TIMx->DIER, TIM_DIER_BIE); 03566 } 03567 03568 /** 03569 * @brief Disable break interrupt (BIE). 03570 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK 03571 * @param TIMx Timer instance 03572 * @retval None 03573 */ 03574 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) 03575 { 03576 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); 03577 } 03578 03579 /** 03580 * @brief Indicates whether the break interrupt (BIE) is enabled. 03581 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK 03582 * @param TIMx Timer instance 03583 * @retval State of bit (1 or 0). 03584 */ 03585 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) 03586 { 03587 return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)); 03588 } 03589 03590 /** 03591 * @} 03592 */ 03593 03594 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management 03595 * @{ 03596 */ 03597 /** 03598 * @brief Enable update DMA request (UDE). 03599 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE 03600 * @param TIMx Timer instance 03601 * @retval None 03602 */ 03603 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) 03604 { 03605 SET_BIT(TIMx->DIER, TIM_DIER_UDE); 03606 } 03607 03608 /** 03609 * @brief Disable update DMA request (UDE). 03610 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE 03611 * @param TIMx Timer instance 03612 * @retval None 03613 */ 03614 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) 03615 { 03616 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); 03617 } 03618 03619 /** 03620 * @brief Indicates whether the update DMA request (UDE) is enabled. 03621 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE 03622 * @param TIMx Timer instance 03623 * @retval State of bit (1 or 0). 03624 */ 03625 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) 03626 { 03627 return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)); 03628 } 03629 03630 /** 03631 * @brief Enable capture/compare 1 DMA request (CC1DE). 03632 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 03633 * @param TIMx Timer instance 03634 * @retval None 03635 */ 03636 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) 03637 { 03638 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); 03639 } 03640 03641 /** 03642 * @brief Disable capture/compare 1 DMA request (CC1DE). 03643 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 03644 * @param TIMx Timer instance 03645 * @retval None 03646 */ 03647 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) 03648 { 03649 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); 03650 } 03651 03652 /** 03653 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. 03654 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 03655 * @param TIMx Timer instance 03656 * @retval State of bit (1 or 0). 03657 */ 03658 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) 03659 { 03660 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)); 03661 } 03662 03663 /** 03664 * @brief Enable capture/compare 2 DMA request (CC2DE). 03665 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 03666 * @param TIMx Timer instance 03667 * @retval None 03668 */ 03669 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) 03670 { 03671 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); 03672 } 03673 03674 /** 03675 * @brief Disable capture/compare 2 DMA request (CC2DE). 03676 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 03677 * @param TIMx Timer instance 03678 * @retval None 03679 */ 03680 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) 03681 { 03682 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); 03683 } 03684 03685 /** 03686 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. 03687 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 03688 * @param TIMx Timer instance 03689 * @retval State of bit (1 or 0). 03690 */ 03691 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) 03692 { 03693 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)); 03694 } 03695 03696 /** 03697 * @brief Enable capture/compare 3 DMA request (CC3DE). 03698 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 03699 * @param TIMx Timer instance 03700 * @retval None 03701 */ 03702 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) 03703 { 03704 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); 03705 } 03706 03707 /** 03708 * @brief Disable capture/compare 3 DMA request (CC3DE). 03709 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 03710 * @param TIMx Timer instance 03711 * @retval None 03712 */ 03713 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) 03714 { 03715 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); 03716 } 03717 03718 /** 03719 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. 03720 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 03721 * @param TIMx Timer instance 03722 * @retval State of bit (1 or 0). 03723 */ 03724 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) 03725 { 03726 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)); 03727 } 03728 03729 /** 03730 * @brief Enable capture/compare 4 DMA request (CC4DE). 03731 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 03732 * @param TIMx Timer instance 03733 * @retval None 03734 */ 03735 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) 03736 { 03737 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); 03738 } 03739 03740 /** 03741 * @brief Disable capture/compare 4 DMA request (CC4DE). 03742 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 03743 * @param TIMx Timer instance 03744 * @retval None 03745 */ 03746 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) 03747 { 03748 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); 03749 } 03750 03751 /** 03752 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. 03753 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 03754 * @param TIMx Timer instance 03755 * @retval State of bit (1 or 0). 03756 */ 03757 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) 03758 { 03759 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)); 03760 } 03761 03762 /** 03763 * @brief Enable commutation DMA request (COMDE). 03764 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM 03765 * @param TIMx Timer instance 03766 * @retval None 03767 */ 03768 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) 03769 { 03770 SET_BIT(TIMx->DIER, TIM_DIER_COMDE); 03771 } 03772 03773 /** 03774 * @brief Disable commutation DMA request (COMDE). 03775 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM 03776 * @param TIMx Timer instance 03777 * @retval None 03778 */ 03779 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) 03780 { 03781 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); 03782 } 03783 03784 /** 03785 * @brief Indicates whether the commutation DMA request (COMDE) is enabled. 03786 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM 03787 * @param TIMx Timer instance 03788 * @retval State of bit (1 or 0). 03789 */ 03790 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) 03791 { 03792 return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)); 03793 } 03794 03795 /** 03796 * @brief Enable trigger interrupt (TDE). 03797 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG 03798 * @param TIMx Timer instance 03799 * @retval None 03800 */ 03801 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) 03802 { 03803 SET_BIT(TIMx->DIER, TIM_DIER_TDE); 03804 } 03805 03806 /** 03807 * @brief Disable trigger interrupt (TDE). 03808 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG 03809 * @param TIMx Timer instance 03810 * @retval None 03811 */ 03812 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) 03813 { 03814 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); 03815 } 03816 03817 /** 03818 * @brief Indicates whether the trigger interrupt (TDE) is enabled. 03819 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG 03820 * @param TIMx Timer instance 03821 * @retval State of bit (1 or 0). 03822 */ 03823 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) 03824 { 03825 return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)); 03826 } 03827 03828 /** 03829 * @} 03830 */ 03831 03832 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management 03833 * @{ 03834 */ 03835 /** 03836 * @brief Generate an update event. 03837 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE 03838 * @param TIMx Timer instance 03839 * @retval None 03840 */ 03841 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) 03842 { 03843 SET_BIT(TIMx->EGR, TIM_EGR_UG); 03844 } 03845 03846 /** 03847 * @brief Generate Capture/Compare 1 event. 03848 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 03849 * @param TIMx Timer instance 03850 * @retval None 03851 */ 03852 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) 03853 { 03854 SET_BIT(TIMx->EGR, TIM_EGR_CC1G); 03855 } 03856 03857 /** 03858 * @brief Generate Capture/Compare 2 event. 03859 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 03860 * @param TIMx Timer instance 03861 * @retval None 03862 */ 03863 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) 03864 { 03865 SET_BIT(TIMx->EGR, TIM_EGR_CC2G); 03866 } 03867 03868 /** 03869 * @brief Generate Capture/Compare 3 event. 03870 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 03871 * @param TIMx Timer instance 03872 * @retval None 03873 */ 03874 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) 03875 { 03876 SET_BIT(TIMx->EGR, TIM_EGR_CC3G); 03877 } 03878 03879 /** 03880 * @brief Generate Capture/Compare 4 event. 03881 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 03882 * @param TIMx Timer instance 03883 * @retval None 03884 */ 03885 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) 03886 { 03887 SET_BIT(TIMx->EGR, TIM_EGR_CC4G); 03888 } 03889 03890 /** 03891 * @brief Generate commutation event. 03892 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM 03893 * @param TIMx Timer instance 03894 * @retval None 03895 */ 03896 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) 03897 { 03898 SET_BIT(TIMx->EGR, TIM_EGR_COMG); 03899 } 03900 03901 /** 03902 * @brief Generate trigger event. 03903 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG 03904 * @param TIMx Timer instance 03905 * @retval None 03906 */ 03907 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) 03908 { 03909 SET_BIT(TIMx->EGR, TIM_EGR_TG); 03910 } 03911 03912 /** 03913 * @brief Generate break event. 03914 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK 03915 * @param TIMx Timer instance 03916 * @retval None 03917 */ 03918 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) 03919 { 03920 SET_BIT(TIMx->EGR, TIM_EGR_BG); 03921 } 03922 03923 /** 03924 * @} 03925 */ 03926 03927 #if defined(USE_FULL_LL_DRIVER) 03928 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions 03929 * @{ 03930 */ 03931 03932 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); 03933 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); 03934 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); 03935 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); 03936 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); 03937 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 03938 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); 03939 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); 03940 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); 03941 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); 03942 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); 03943 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); 03944 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); 03945 /** 03946 * @} 03947 */ 03948 #endif /* USE_FULL_LL_DRIVER */ 03949 03950 /** 03951 * @} 03952 */ 03953 03954 /** 03955 * @} 03956 */ 03957 03958 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */ 03959 03960 /** 03961 * @} 03962 */ 03963 03964 #ifdef __cplusplus 03965 } 03966 #endif 03967 03968 #endif /* __STM32F4xx_LL_TIM_H */ 03969 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1