|
STM32F439xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_dac.h 00004 * @author MCD Application Team 00005 * @brief Header file of DAC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_LL_DAC_H 00038 #define __STM32F4xx_LL_DAC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx.h" 00046 00047 /** @addtogroup STM32F4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined(DAC) 00052 00053 /** @defgroup DAC_LL DAC 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 00060 /* Private constants ---------------------------------------------------------*/ 00061 /** @defgroup DAC_LL_Private_Constants DAC Private Constants 00062 * @{ 00063 */ 00064 00065 /* Internal masks for DAC channels definition */ 00066 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ 00067 /* - channel bits position into register CR */ 00068 /* - channel bits position into register SWTRIG */ 00069 /* - channel register offset of data holding register DHRx */ 00070 /* - channel register offset of data output register DORx */ 00071 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ 00072 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ 00073 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) 00074 00075 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ 00076 #if defined(DAC_CHANNEL2_SUPPORT) 00077 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ 00078 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) 00079 #else 00080 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) 00081 #endif /* DAC_CHANNEL2_SUPPORT */ 00082 00083 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ 00084 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ 00085 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ 00086 #if defined(DAC_CHANNEL2_SUPPORT) 00087 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ 00088 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ 00089 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ 00090 #endif /* DAC_CHANNEL2_SUPPORT */ 00091 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U 00092 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U 00093 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U 00094 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) 00095 00096 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ 00097 #if defined(DAC_CHANNEL2_SUPPORT) 00098 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ 00099 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) 00100 #else 00101 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) 00102 #endif /* DAC_CHANNEL2_SUPPORT */ 00103 00104 /* DAC registers bits positions */ 00105 #if defined(DAC_CHANNEL2_SUPPORT) 00106 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ 00107 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ 00108 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ 00109 #endif /* DAC_CHANNEL2_SUPPORT */ 00110 00111 /* Miscellaneous data */ 00112 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ 00113 00114 /** 00115 * @} 00116 */ 00117 00118 00119 /* Private macros ------------------------------------------------------------*/ 00120 /** @defgroup DAC_LL_Private_Macros DAC Private Macros 00121 * @{ 00122 */ 00123 00124 /** 00125 * @brief Driver macro reserved for internal use: isolate bits with the 00126 * selected mask and shift them to the register LSB 00127 * (shift mask on register position bit 0). 00128 * @param __BITS__ Bits in register 32 bits 00129 * @param __MASK__ Mask in register 32 bits 00130 * @retval Bits in register 32 bits 00131 */ 00132 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \ 00133 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) 00134 00135 /** 00136 * @brief Driver macro reserved for internal use: set a pointer to 00137 * a register from a register basis from which an offset 00138 * is applied. 00139 * @param __REG__ Register basis from which the offset is applied. 00140 * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). 00141 * @retval Pointer to register address 00142 */ 00143 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00144 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) 00145 00146 /** 00147 * @} 00148 */ 00149 00150 00151 /* Exported types ------------------------------------------------------------*/ 00152 #if defined(USE_FULL_LL_DRIVER) 00153 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure 00154 * @{ 00155 */ 00156 00157 /** 00158 * @brief Structure definition of some features of DAC instance. 00159 */ 00160 typedef struct 00161 { 00162 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). 00163 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE 00164 00165 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ 00166 00167 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00168 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE 00169 00170 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ 00171 00172 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00173 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS 00174 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE 00175 @note If waveform automatic generation mode is disabled, this parameter is discarded. 00176 00177 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ 00178 00179 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. 00180 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER 00181 00182 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ 00183 00184 } LL_DAC_InitTypeDef; 00185 00186 /** 00187 * @} 00188 */ 00189 #endif /* USE_FULL_LL_DRIVER */ 00190 00191 /* Exported constants --------------------------------------------------------*/ 00192 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants 00193 * @{ 00194 */ 00195 00196 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags 00197 * @brief Flags defines which can be used with LL_DAC_ReadReg function 00198 * @{ 00199 */ 00200 /* DAC channel 1 flags */ 00201 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ 00202 00203 #if defined(DAC_CHANNEL2_SUPPORT) 00204 /* DAC channel 2 flags */ 00205 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ 00206 #endif /* DAC_CHANNEL2_SUPPORT */ 00207 /** 00208 * @} 00209 */ 00210 00211 /** @defgroup DAC_LL_EC_IT DAC interruptions 00212 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions 00213 * @{ 00214 */ 00215 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ 00216 #if defined(DAC_CHANNEL2_SUPPORT) 00217 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ 00218 #endif /* DAC_CHANNEL2_SUPPORT */ 00219 /** 00220 * @} 00221 */ 00222 00223 /** @defgroup DAC_LL_EC_CHANNEL DAC channels 00224 * @{ 00225 */ 00226 #define LL_DAC_CHANNEL_1 (DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ 00227 #if defined(DAC_CHANNEL2_SUPPORT) 00228 #define LL_DAC_CHANNEL_2 (DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ 00229 #endif /* DAC_CHANNEL2_SUPPORT */ 00230 /** 00231 * @} 00232 */ 00233 00234 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source 00235 * @{ 00236 */ 00237 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ 00238 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ 00239 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ 00240 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ 00241 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ 00242 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ 00243 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ 00244 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ 00245 /** 00246 * @} 00247 */ 00248 00249 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode 00250 * @{ 00251 */ 00252 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ 00253 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ 00254 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ 00255 /** 00256 * @} 00257 */ 00258 00259 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits 00260 * @{ 00261 */ 00262 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ 00263 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ 00264 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ 00265 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ 00266 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ 00267 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ 00268 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ 00269 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ 00270 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ 00271 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ 00272 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ 00273 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ 00274 /** 00275 * @} 00276 */ 00277 00278 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude 00279 * @{ 00280 */ 00281 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ 00282 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ 00283 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ 00284 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ 00285 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ 00286 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ 00287 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ 00288 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ 00289 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ 00290 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ 00291 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ 00292 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ 00293 /** 00294 * @} 00295 */ 00296 00297 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer 00298 * @{ 00299 */ 00300 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ 00301 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_CR_BOFF1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ 00302 /** 00303 * @} 00304 */ 00305 00306 00307 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution 00308 * @{ 00309 */ 00310 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ 00311 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ 00312 /** 00313 * @} 00314 */ 00315 00316 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose 00317 * @{ 00318 */ 00319 /* List of DAC registers intended to be used (most commonly) with */ 00320 /* DMA transfer. */ 00321 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ 00322 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */ 00323 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */ 00324 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */ 00325 /** 00326 * @} 00327 */ 00328 00329 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays 00330 * @note Only DAC IP HW delays are defined in DAC LL driver driver, 00331 * not timeout values. 00332 * For details on delays values, refer to descriptions in source code 00333 * above each literal definition. 00334 * @{ 00335 */ 00336 00337 /* Delay for DAC channel voltage settling time from DAC channel startup */ 00338 /* (transition from disable to enable). */ 00339 /* Note: DAC channel startup time depends on board application environment: */ 00340 /* impedance connected to DAC channel output. */ 00341 /* The delay below is specified under conditions: */ 00342 /* - voltage maximum transition (lowest to highest value) */ 00343 /* - until voltage reaches final value +-1LSB */ 00344 /* - DAC channel output buffer enabled */ 00345 /* - load impedance of 5kOhm (min), 50pF (max) */ 00346 /* Literal set to maximum value (refer to device datasheet, */ 00347 /* parameter "tWAKEUP"). */ 00348 /* Unit: us */ 00349 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 15U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ 00350 00351 /* Delay for DAC channel voltage settling time. */ 00352 /* Note: DAC channel startup time depends on board application environment: */ 00353 /* impedance connected to DAC channel output. */ 00354 /* The delay below is specified under conditions: */ 00355 /* - voltage maximum transition (lowest to highest value) */ 00356 /* - until voltage reaches final value +-1LSB */ 00357 /* - DAC channel output buffer enabled */ 00358 /* - load impedance of 5kOhm min, 50pF max */ 00359 /* Literal set to maximum value (refer to device datasheet, */ 00360 /* parameter "tSETTLING"). */ 00361 /* Unit: us */ 00362 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 12U /*!< Delay for DAC channel voltage settling time */ 00363 /** 00364 * @} 00365 */ 00366 00367 /** 00368 * @} 00369 */ 00370 00371 /* Exported macro ------------------------------------------------------------*/ 00372 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros 00373 * @{ 00374 */ 00375 00376 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros 00377 * @{ 00378 */ 00379 00380 /** 00381 * @brief Write a value in DAC register 00382 * @param __INSTANCE__ DAC Instance 00383 * @param __REG__ Register to be written 00384 * @param __VALUE__ Value to be written in the register 00385 * @retval None 00386 */ 00387 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00388 00389 /** 00390 * @brief Read a value in DAC register 00391 * @param __INSTANCE__ DAC Instance 00392 * @param __REG__ Register to be read 00393 * @retval Register value 00394 */ 00395 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00396 00397 /** 00398 * @} 00399 */ 00400 00401 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro 00402 * @{ 00403 */ 00404 00405 /** 00406 * @brief Helper macro to get DAC channel number in decimal format 00407 * from literals LL_DAC_CHANNEL_x. 00408 * Example: 00409 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) 00410 * will return decimal number "1". 00411 * @note The input can be a value from functions where a channel 00412 * number is returned. 00413 * @param __CHANNEL__ This parameter can be one of the following values: 00414 * @arg @ref LL_DAC_CHANNEL_1 00415 * @arg @ref LL_DAC_CHANNEL_2 (1) 00416 * 00417 * (1) On this STM32 serie, parameter not available on all devices. 00418 * Refer to device datasheet for channels availability. 00419 * @retval 1...2 (value "2" depending on DAC channel 2 availability) 00420 */ 00421 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 00422 ((__CHANNEL__) & DAC_SWTR_CHX_MASK) 00423 00424 /** 00425 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x 00426 * from number in decimal format. 00427 * Example: 00428 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) 00429 * will return a data equivalent to "LL_DAC_CHANNEL_1". 00430 * @note If the input parameter does not correspond to a DAC channel, 00431 * this macro returns value '0'. 00432 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) 00433 * @retval Returned value can be one of the following values: 00434 * @arg @ref LL_DAC_CHANNEL_1 00435 * @arg @ref LL_DAC_CHANNEL_2 (1) 00436 * 00437 * (1) On this STM32 serie, parameter not available on all devices. 00438 * Refer to device datasheet for channels availability. 00439 */ 00440 #if defined(DAC_CHANNEL2_SUPPORT) 00441 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 00442 (((__DECIMAL_NB__) == 1U) \ 00443 ? ( \ 00444 LL_DAC_CHANNEL_1 \ 00445 ) \ 00446 : \ 00447 (((__DECIMAL_NB__) == 2U) \ 00448 ? ( \ 00449 LL_DAC_CHANNEL_2 \ 00450 ) \ 00451 : \ 00452 ( \ 00453 0 \ 00454 ) \ 00455 ) \ 00456 ) 00457 #else 00458 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 00459 (((__DECIMAL_NB__) == 1U) \ 00460 ? ( \ 00461 LL_DAC_CHANNEL_1 \ 00462 ) \ 00463 : \ 00464 ( \ 00465 0 \ 00466 ) \ 00467 ) 00468 #endif /* DAC_CHANNEL2_SUPPORT */ 00469 00470 /** 00471 * @brief Helper macro to define the DAC conversion data full-scale digital 00472 * value corresponding to the selected DAC resolution. 00473 * @note DAC conversion data full-scale corresponds to voltage range 00474 * determined by analog voltage references Vref+ and Vref- 00475 * (refer to reference manual). 00476 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00477 * @arg @ref LL_DAC_RESOLUTION_12B 00478 * @arg @ref LL_DAC_RESOLUTION_8B 00479 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 00480 */ 00481 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00482 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) 00483 00484 /** 00485 * @brief Helper macro to calculate the DAC conversion data (unit: digital 00486 * value) corresponding to a voltage (unit: mVolt). 00487 * @note This helper macro is intended to provide input data in voltage 00488 * rather than digital value, 00489 * to be used with LL DAC functions such as 00490 * @ref LL_DAC_ConvertData12RightAligned(). 00491 * @note Analog reference voltage (Vref+) must be either known from 00492 * user board environment or can be calculated using ADC measurement 00493 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 00494 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) 00495 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel 00496 * (unit: mVolt). 00497 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00498 * @arg @ref LL_DAC_RESOLUTION_12B 00499 * @arg @ref LL_DAC_RESOLUTION_8B 00500 * @retval DAC conversion data (unit: digital value) 00501 */ 00502 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ 00503 __DAC_VOLTAGE__,\ 00504 __DAC_RESOLUTION__) \ 00505 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00506 / (__VREFANALOG_VOLTAGE__) \ 00507 ) 00508 00509 /** 00510 * @} 00511 */ 00512 00513 /** 00514 * @} 00515 */ 00516 00517 00518 /* Exported functions --------------------------------------------------------*/ 00519 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions 00520 * @{ 00521 */ 00522 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels 00523 * @{ 00524 */ 00525 00526 /** 00527 * @brief Set the conversion trigger source for the selected DAC channel. 00528 * @note For conversion trigger source to be effective, DAC trigger 00529 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00530 * @note To set conversion trigger source, DAC channel must be disabled. 00531 * Otherwise, the setting is discarded. 00532 * @note Availability of parameters of trigger sources from timer 00533 * depends on timers availability on the selected device. 00534 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n 00535 * CR TSEL2 LL_DAC_SetTriggerSource 00536 * @param DACx DAC instance 00537 * @param DAC_Channel This parameter can be one of the following values: 00538 * @arg @ref LL_DAC_CHANNEL_1 00539 * @arg @ref LL_DAC_CHANNEL_2 (1) 00540 * 00541 * (1) On this STM32 serie, parameter not available on all devices. 00542 * Refer to device datasheet for channels availability. 00543 * @param TriggerSource This parameter can be one of the following values: 00544 * @arg @ref LL_DAC_TRIG_SOFTWARE 00545 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 00546 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00547 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00548 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00549 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00550 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00551 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00552 * @retval None 00553 */ 00554 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) 00555 { 00556 MODIFY_REG(DACx->CR, 00557 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00558 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00559 } 00560 00561 /** 00562 * @brief Get the conversion trigger source for the selected DAC channel. 00563 * @note For conversion trigger source to be effective, DAC trigger 00564 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00565 * @note Availability of parameters of trigger sources from timer 00566 * depends on timers availability on the selected device. 00567 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n 00568 * CR TSEL2 LL_DAC_GetTriggerSource 00569 * @param DACx DAC instance 00570 * @param DAC_Channel This parameter can be one of the following values: 00571 * @arg @ref LL_DAC_CHANNEL_1 00572 * @arg @ref LL_DAC_CHANNEL_2 (1) 00573 * 00574 * (1) On this STM32 serie, parameter not available on all devices. 00575 * Refer to device datasheet for channels availability. 00576 * @retval Returned value can be one of the following values: 00577 * @arg @ref LL_DAC_TRIG_SOFTWARE 00578 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 00579 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00580 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00581 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00582 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00583 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00584 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00585 */ 00586 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00587 { 00588 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00589 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00590 ); 00591 } 00592 00593 /** 00594 * @brief Set the waveform automatic generation mode 00595 * for the selected DAC channel. 00596 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n 00597 * CR WAVE2 LL_DAC_SetWaveAutoGeneration 00598 * @param DACx DAC instance 00599 * @param DAC_Channel This parameter can be one of the following values: 00600 * @arg @ref LL_DAC_CHANNEL_1 00601 * @arg @ref LL_DAC_CHANNEL_2 (1) 00602 * 00603 * (1) On this STM32 serie, parameter not available on all devices. 00604 * Refer to device datasheet for channels availability. 00605 * @param WaveAutoGeneration This parameter can be one of the following values: 00606 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00607 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00608 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00609 * @retval None 00610 */ 00611 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) 00612 { 00613 MODIFY_REG(DACx->CR, 00614 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00615 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00616 } 00617 00618 /** 00619 * @brief Get the waveform automatic generation mode 00620 * for the selected DAC channel. 00621 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n 00622 * CR WAVE2 LL_DAC_GetWaveAutoGeneration 00623 * @param DACx DAC instance 00624 * @param DAC_Channel This parameter can be one of the following values: 00625 * @arg @ref LL_DAC_CHANNEL_1 00626 * @arg @ref LL_DAC_CHANNEL_2 (1) 00627 * 00628 * (1) On this STM32 serie, parameter not available on all devices. 00629 * Refer to device datasheet for channels availability. 00630 * @retval Returned value can be one of the following values: 00631 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00632 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00633 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00634 */ 00635 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00636 { 00637 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00638 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00639 ); 00640 } 00641 00642 /** 00643 * @brief Set the noise waveform generation for the selected DAC channel: 00644 * Noise mode and parameters LFSR (linear feedback shift register). 00645 * @note For wave generation to be effective, DAC channel 00646 * wave generation mode must be enabled using 00647 * function @ref LL_DAC_SetWaveAutoGeneration(). 00648 * @note This setting can be set when the selected DAC channel is disabled 00649 * (otherwise, the setting operation is ignored). 00650 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n 00651 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR 00652 * @param DACx DAC instance 00653 * @param DAC_Channel This parameter can be one of the following values: 00654 * @arg @ref LL_DAC_CHANNEL_1 00655 * @arg @ref LL_DAC_CHANNEL_2 (1) 00656 * 00657 * (1) On this STM32 serie, parameter not available on all devices. 00658 * Refer to device datasheet for channels availability. 00659 * @param NoiseLFSRMask This parameter can be one of the following values: 00660 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00661 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00662 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00663 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00664 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00665 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00666 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00667 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00668 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00669 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00670 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00671 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00672 * @retval None 00673 */ 00674 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) 00675 { 00676 MODIFY_REG(DACx->CR, 00677 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00678 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00679 } 00680 00681 /** 00682 * @brief Set the noise waveform generation for the selected DAC channel: 00683 * Noise mode and parameters LFSR (linear feedback shift register). 00684 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n 00685 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR 00686 * @param DACx DAC instance 00687 * @param DAC_Channel This parameter can be one of the following values: 00688 * @arg @ref LL_DAC_CHANNEL_1 00689 * @arg @ref LL_DAC_CHANNEL_2 (1) 00690 * 00691 * (1) On this STM32 serie, parameter not available on all devices. 00692 * Refer to device datasheet for channels availability. 00693 * @retval Returned value can be one of the following values: 00694 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00695 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00696 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00697 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00698 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00699 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00700 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00701 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00702 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00703 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00704 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00705 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00706 */ 00707 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00708 { 00709 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00710 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00711 ); 00712 } 00713 00714 /** 00715 * @brief Set the triangle waveform generation for the selected DAC channel: 00716 * triangle mode and amplitude. 00717 * @note For wave generation to be effective, DAC channel 00718 * wave generation mode must be enabled using 00719 * function @ref LL_DAC_SetWaveAutoGeneration(). 00720 * @note This setting can be set when the selected DAC channel is disabled 00721 * (otherwise, the setting operation is ignored). 00722 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n 00723 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude 00724 * @param DACx DAC instance 00725 * @param DAC_Channel This parameter can be one of the following values: 00726 * @arg @ref LL_DAC_CHANNEL_1 00727 * @arg @ref LL_DAC_CHANNEL_2 (1) 00728 * 00729 * (1) On this STM32 serie, parameter not available on all devices. 00730 * Refer to device datasheet for channels availability. 00731 * @param TriangleAmplitude This parameter can be one of the following values: 00732 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00733 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00734 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00735 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00736 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00737 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00738 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00739 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00740 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00741 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00742 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00743 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00744 * @retval None 00745 */ 00746 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) 00747 { 00748 MODIFY_REG(DACx->CR, 00749 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00750 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00751 } 00752 00753 /** 00754 * @brief Set the triangle waveform generation for the selected DAC channel: 00755 * triangle mode and amplitude. 00756 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n 00757 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude 00758 * @param DACx DAC instance 00759 * @param DAC_Channel This parameter can be one of the following values: 00760 * @arg @ref LL_DAC_CHANNEL_1 00761 * @arg @ref LL_DAC_CHANNEL_2 (1) 00762 * 00763 * (1) On this STM32 serie, parameter not available on all devices. 00764 * Refer to device datasheet for channels availability. 00765 * @retval Returned value can be one of the following values: 00766 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00767 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00768 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00769 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00770 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00771 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00772 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00773 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00774 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00775 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00776 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00777 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00778 */ 00779 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00780 { 00781 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00782 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00783 ); 00784 } 00785 00786 /** 00787 * @brief Set the output buffer for the selected DAC channel. 00788 * @rmtoll CR BOFF1 LL_DAC_SetOutputBuffer\n 00789 * CR BOFF2 LL_DAC_SetOutputBuffer 00790 * @param DACx DAC instance 00791 * @param DAC_Channel This parameter can be one of the following values: 00792 * @arg @ref LL_DAC_CHANNEL_1 00793 * @arg @ref LL_DAC_CHANNEL_2 (1) 00794 * 00795 * (1) On this STM32 serie, parameter not available on all devices. 00796 * Refer to device datasheet for channels availability. 00797 * @param OutputBuffer This parameter can be one of the following values: 00798 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 00799 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 00800 * @retval None 00801 */ 00802 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) 00803 { 00804 MODIFY_REG(DACx->CR, 00805 DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00806 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00807 } 00808 00809 /** 00810 * @brief Get the output buffer state for the selected DAC channel. 00811 * @rmtoll CR BOFF1 LL_DAC_GetOutputBuffer\n 00812 * CR BOFF2 LL_DAC_GetOutputBuffer 00813 * @param DACx DAC instance 00814 * @param DAC_Channel This parameter can be one of the following values: 00815 * @arg @ref LL_DAC_CHANNEL_1 00816 * @arg @ref LL_DAC_CHANNEL_2 (1) 00817 * 00818 * (1) On this STM32 serie, parameter not available on all devices. 00819 * Refer to device datasheet for channels availability. 00820 * @retval Returned value can be one of the following values: 00821 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 00822 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 00823 */ 00824 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00825 { 00826 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_BOFF1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00827 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00828 ); 00829 } 00830 00831 /** 00832 * @} 00833 */ 00834 00835 /** @defgroup DAC_LL_EF_DMA_Management DMA Management 00836 * @{ 00837 */ 00838 00839 /** 00840 * @brief Enable DAC DMA transfer request of the selected channel. 00841 * @note To configure DMA source address (peripheral address), 00842 * use function @ref LL_DAC_DMA_GetRegAddr(). 00843 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n 00844 * CR DMAEN2 LL_DAC_EnableDMAReq 00845 * @param DACx DAC instance 00846 * @param DAC_Channel This parameter can be one of the following values: 00847 * @arg @ref LL_DAC_CHANNEL_1 00848 * @arg @ref LL_DAC_CHANNEL_2 (1) 00849 * 00850 * (1) On this STM32 serie, parameter not available on all devices. 00851 * Refer to device datasheet for channels availability. 00852 * @retval None 00853 */ 00854 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00855 { 00856 SET_BIT(DACx->CR, 00857 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00858 } 00859 00860 /** 00861 * @brief Disable DAC DMA transfer request of the selected channel. 00862 * @note To configure DMA source address (peripheral address), 00863 * use function @ref LL_DAC_DMA_GetRegAddr(). 00864 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n 00865 * CR DMAEN2 LL_DAC_DisableDMAReq 00866 * @param DACx DAC instance 00867 * @param DAC_Channel This parameter can be one of the following values: 00868 * @arg @ref LL_DAC_CHANNEL_1 00869 * @arg @ref LL_DAC_CHANNEL_2 (1) 00870 * 00871 * (1) On this STM32 serie, parameter not available on all devices. 00872 * Refer to device datasheet for channels availability. 00873 * @retval None 00874 */ 00875 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00876 { 00877 CLEAR_BIT(DACx->CR, 00878 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00879 } 00880 00881 /** 00882 * @brief Get DAC DMA transfer request state of the selected channel. 00883 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) 00884 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n 00885 * CR DMAEN2 LL_DAC_IsDMAReqEnabled 00886 * @param DACx DAC instance 00887 * @param DAC_Channel This parameter can be one of the following values: 00888 * @arg @ref LL_DAC_CHANNEL_1 00889 * @arg @ref LL_DAC_CHANNEL_2 (1) 00890 * 00891 * (1) On this STM32 serie, parameter not available on all devices. 00892 * Refer to device datasheet for channels availability. 00893 * @retval State of bit (1 or 0). 00894 */ 00895 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00896 { 00897 return (READ_BIT(DACx->CR, 00898 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00899 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); 00900 } 00901 00902 /** 00903 * @brief Function to help to configure DMA transfer to DAC: retrieve the 00904 * DAC register address from DAC instance and a list of DAC registers 00905 * intended to be used (most commonly) with DMA transfer. 00906 * @note These DAC registers are data holding registers: 00907 * when DAC conversion is requested, DAC generates a DMA transfer 00908 * request to have data available in DAC data holding registers. 00909 * @note This macro is intended to be used with LL DMA driver, refer to 00910 * function "LL_DMA_ConfigAddresses()". 00911 * Example: 00912 * LL_DMA_ConfigAddresses(DMA1, 00913 * LL_DMA_CHANNEL_1, 00914 * (uint32_t)&< array or variable >, 00915 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), 00916 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 00917 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 00918 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 00919 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 00920 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 00921 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 00922 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr 00923 * @param DACx DAC instance 00924 * @param DAC_Channel This parameter can be one of the following values: 00925 * @arg @ref LL_DAC_CHANNEL_1 00926 * @arg @ref LL_DAC_CHANNEL_2 (1) 00927 * 00928 * (1) On this STM32 serie, parameter not available on all devices. 00929 * Refer to device datasheet for channels availability. 00930 * @param Register This parameter can be one of the following values: 00931 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED 00932 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED 00933 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED 00934 * @retval DAC register address 00935 */ 00936 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) 00937 { 00938 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ 00939 /* DAC channel selected. */ 00940 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register)))); 00941 } 00942 /** 00943 * @} 00944 */ 00945 00946 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels 00947 * @{ 00948 */ 00949 00950 /** 00951 * @brief Enable DAC selected channel. 00952 * @rmtoll CR EN1 LL_DAC_Enable\n 00953 * CR EN2 LL_DAC_Enable 00954 * @note After enable from off state, DAC channel requires a delay 00955 * for output voltage to reach accuracy +/- 1 LSB. 00956 * Refer to device datasheet, parameter "tWAKEUP". 00957 * @param DACx DAC instance 00958 * @param DAC_Channel This parameter can be one of the following values: 00959 * @arg @ref LL_DAC_CHANNEL_1 00960 * @arg @ref LL_DAC_CHANNEL_2 (1) 00961 * 00962 * (1) On this STM32 serie, parameter not available on all devices. 00963 * Refer to device datasheet for channels availability. 00964 * @retval None 00965 */ 00966 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00967 { 00968 SET_BIT(DACx->CR, 00969 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00970 } 00971 00972 /** 00973 * @brief Disable DAC selected channel. 00974 * @rmtoll CR EN1 LL_DAC_Disable\n 00975 * CR EN2 LL_DAC_Disable 00976 * @param DACx DAC instance 00977 * @param DAC_Channel This parameter can be one of the following values: 00978 * @arg @ref LL_DAC_CHANNEL_1 00979 * @arg @ref LL_DAC_CHANNEL_2 (1) 00980 * 00981 * (1) On this STM32 serie, parameter not available on all devices. 00982 * Refer to device datasheet for channels availability. 00983 * @retval None 00984 */ 00985 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00986 { 00987 CLEAR_BIT(DACx->CR, 00988 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00989 } 00990 00991 /** 00992 * @brief Get DAC enable state of the selected channel. 00993 * (0: DAC channel is disabled, 1: DAC channel is enabled) 00994 * @rmtoll CR EN1 LL_DAC_IsEnabled\n 00995 * CR EN2 LL_DAC_IsEnabled 00996 * @param DACx DAC instance 00997 * @param DAC_Channel This parameter can be one of the following values: 00998 * @arg @ref LL_DAC_CHANNEL_1 00999 * @arg @ref LL_DAC_CHANNEL_2 (1) 01000 * 01001 * (1) On this STM32 serie, parameter not available on all devices. 01002 * Refer to device datasheet for channels availability. 01003 * @retval State of bit (1 or 0). 01004 */ 01005 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01006 { 01007 return (READ_BIT(DACx->CR, 01008 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01009 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); 01010 } 01011 01012 /** 01013 * @brief Enable DAC trigger of the selected channel. 01014 * @note - If DAC trigger is disabled, DAC conversion is performed 01015 * automatically once the data holding register is updated, 01016 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01017 * @ref LL_DAC_ConvertData12RightAligned(), ... 01018 * - If DAC trigger is enabled, DAC conversion is performed 01019 * only when a hardware of software trigger event is occurring. 01020 * Select trigger source using 01021 * function @ref LL_DAC_SetTriggerSource(). 01022 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n 01023 * CR TEN2 LL_DAC_EnableTrigger 01024 * @param DACx DAC instance 01025 * @param DAC_Channel This parameter can be one of the following values: 01026 * @arg @ref LL_DAC_CHANNEL_1 01027 * @arg @ref LL_DAC_CHANNEL_2 (1) 01028 * 01029 * (1) On this STM32 serie, parameter not available on all devices. 01030 * Refer to device datasheet for channels availability. 01031 * @retval None 01032 */ 01033 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01034 { 01035 SET_BIT(DACx->CR, 01036 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01037 } 01038 01039 /** 01040 * @brief Disable DAC trigger of the selected channel. 01041 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n 01042 * CR TEN2 LL_DAC_DisableTrigger 01043 * @param DACx DAC instance 01044 * @param DAC_Channel This parameter can be one of the following values: 01045 * @arg @ref LL_DAC_CHANNEL_1 01046 * @arg @ref LL_DAC_CHANNEL_2 (1) 01047 * 01048 * (1) On this STM32 serie, parameter not available on all devices. 01049 * Refer to device datasheet for channels availability. 01050 * @retval None 01051 */ 01052 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01053 { 01054 CLEAR_BIT(DACx->CR, 01055 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01056 } 01057 01058 /** 01059 * @brief Get DAC trigger state of the selected channel. 01060 * (0: DAC trigger is disabled, 1: DAC trigger is enabled) 01061 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n 01062 * CR TEN2 LL_DAC_IsTriggerEnabled 01063 * @param DACx DAC instance 01064 * @param DAC_Channel This parameter can be one of the following values: 01065 * @arg @ref LL_DAC_CHANNEL_1 01066 * @arg @ref LL_DAC_CHANNEL_2 (1) 01067 * 01068 * (1) On this STM32 serie, parameter not available on all devices. 01069 * Refer to device datasheet for channels availability. 01070 * @retval State of bit (1 or 0). 01071 */ 01072 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01073 { 01074 return (READ_BIT(DACx->CR, 01075 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01076 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); 01077 } 01078 01079 /** 01080 * @brief Trig DAC conversion by software for the selected DAC channel. 01081 * @note Preliminarily, DAC trigger must be set to software trigger 01082 * using function @ref LL_DAC_SetTriggerSource() 01083 * with parameter "LL_DAC_TRIGGER_SOFTWARE". 01084 * and DAC trigger must be enabled using 01085 * function @ref LL_DAC_EnableTrigger(). 01086 * @note For devices featuring DAC with 2 channels: this function 01087 * can perform a SW start of both DAC channels simultaneously. 01088 * Two channels can be selected as parameter. 01089 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) 01090 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n 01091 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion 01092 * @param DACx DAC instance 01093 * @param DAC_Channel This parameter can a combination of the following values: 01094 * @arg @ref LL_DAC_CHANNEL_1 01095 * @arg @ref LL_DAC_CHANNEL_2 (1) 01096 * 01097 * (1) On this STM32 serie, parameter not available on all devices. 01098 * Refer to device datasheet for channels availability. 01099 * @retval None 01100 */ 01101 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01102 { 01103 SET_BIT(DACx->SWTRIGR, 01104 (DAC_Channel & DAC_SWTR_CHX_MASK)); 01105 } 01106 01107 /** 01108 * @brief Set the data to be loaded in the data holding register 01109 * in format 12 bits left alignment (LSB aligned on bit 0), 01110 * for the selected DAC channel. 01111 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n 01112 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned 01113 * @param DACx DAC instance 01114 * @param DAC_Channel This parameter can be one of the following values: 01115 * @arg @ref LL_DAC_CHANNEL_1 01116 * @arg @ref LL_DAC_CHANNEL_2 (1) 01117 * 01118 * (1) On this STM32 serie, parameter not available on all devices. 01119 * Refer to device datasheet for channels availability. 01120 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01121 * @retval None 01122 */ 01123 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01124 { 01125 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); 01126 01127 MODIFY_REG(*preg, 01128 DAC_DHR12R1_DACC1DHR, 01129 Data); 01130 } 01131 01132 /** 01133 * @brief Set the data to be loaded in the data holding register 01134 * in format 12 bits left alignment (MSB aligned on bit 15), 01135 * for the selected DAC channel. 01136 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n 01137 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned 01138 * @param DACx DAC instance 01139 * @param DAC_Channel This parameter can be one of the following values: 01140 * @arg @ref LL_DAC_CHANNEL_1 01141 * @arg @ref LL_DAC_CHANNEL_2 (1) 01142 * 01143 * (1) On this STM32 serie, parameter not available on all devices. 01144 * Refer to device datasheet for channels availability. 01145 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01146 * @retval None 01147 */ 01148 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01149 { 01150 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); 01151 01152 MODIFY_REG(*preg, 01153 DAC_DHR12L1_DACC1DHR, 01154 Data); 01155 } 01156 01157 /** 01158 * @brief Set the data to be loaded in the data holding register 01159 * in format 8 bits left alignment (LSB aligned on bit 0), 01160 * for the selected DAC channel. 01161 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n 01162 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned 01163 * @param DACx DAC instance 01164 * @param DAC_Channel This parameter can be one of the following values: 01165 * @arg @ref LL_DAC_CHANNEL_1 01166 * @arg @ref LL_DAC_CHANNEL_2 (1) 01167 * 01168 * (1) On this STM32 serie, parameter not available on all devices. 01169 * Refer to device datasheet for channels availability. 01170 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF 01171 * @retval None 01172 */ 01173 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01174 { 01175 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); 01176 01177 MODIFY_REG(*preg, 01178 DAC_DHR8R1_DACC1DHR, 01179 Data); 01180 } 01181 01182 #if defined(DAC_CHANNEL2_SUPPORT) 01183 /** 01184 * @brief Set the data to be loaded in the data holding register 01185 * in format 12 bits left alignment (LSB aligned on bit 0), 01186 * for both DAC channels. 01187 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n 01188 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned 01189 * @param DACx DAC instance 01190 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01191 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01192 * @retval None 01193 */ 01194 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) 01195 { 01196 MODIFY_REG(DACx->DHR12RD, 01197 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), 01198 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01199 } 01200 01201 /** 01202 * @brief Set the data to be loaded in the data holding register 01203 * in format 12 bits left alignment (MSB aligned on bit 15), 01204 * for both DAC channels. 01205 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n 01206 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned 01207 * @param DACx DAC instance 01208 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01209 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01210 * @retval None 01211 */ 01212 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) 01213 { 01214 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ 01215 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ 01216 /* the 4 LSB must be taken into account for the shift value. */ 01217 MODIFY_REG(DACx->DHR12LD, 01218 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), 01219 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); 01220 } 01221 01222 /** 01223 * @brief Set the data to be loaded in the data holding register 01224 * in format 8 bits left alignment (LSB aligned on bit 0), 01225 * for both DAC channels. 01226 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n 01227 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned 01228 * @param DACx DAC instance 01229 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF 01230 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF 01231 * @retval None 01232 */ 01233 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) 01234 { 01235 MODIFY_REG(DACx->DHR8RD, 01236 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), 01237 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01238 } 01239 01240 #endif /* DAC_CHANNEL2_SUPPORT */ 01241 /** 01242 * @brief Retrieve output data currently generated for the selected DAC channel. 01243 * @note Whatever alignment and resolution settings 01244 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01245 * @ref LL_DAC_ConvertData12RightAligned(), ...), 01246 * output data format is 12 bits right aligned (LSB aligned on bit 0). 01247 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n 01248 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData 01249 * @param DACx DAC instance 01250 * @param DAC_Channel This parameter can be one of the following values: 01251 * @arg @ref LL_DAC_CHANNEL_1 01252 * @arg @ref LL_DAC_CHANNEL_2 (1) 01253 * 01254 * (1) On this STM32 serie, parameter not available on all devices. 01255 * Refer to device datasheet for channels availability. 01256 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01257 */ 01258 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01259 { 01260 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); 01261 01262 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); 01263 } 01264 01265 /** 01266 * @} 01267 */ 01268 01269 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management 01270 * @{ 01271 */ 01272 /** 01273 * @brief Get DAC underrun flag for DAC channel 1 01274 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 01275 * @param DACx DAC instance 01276 * @retval State of bit (1 or 0). 01277 */ 01278 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) 01279 { 01280 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); 01281 } 01282 01283 #if defined(DAC_CHANNEL2_SUPPORT) 01284 /** 01285 * @brief Get DAC underrun flag for DAC channel 2 01286 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 01287 * @param DACx DAC instance 01288 * @retval State of bit (1 or 0). 01289 */ 01290 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) 01291 { 01292 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); 01293 } 01294 #endif /* DAC_CHANNEL2_SUPPORT */ 01295 01296 /** 01297 * @brief Clear DAC underrun flag for DAC channel 1 01298 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 01299 * @param DACx DAC instance 01300 * @retval None 01301 */ 01302 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) 01303 { 01304 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); 01305 } 01306 01307 #if defined(DAC_CHANNEL2_SUPPORT) 01308 /** 01309 * @brief Clear DAC underrun flag for DAC channel 2 01310 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 01311 * @param DACx DAC instance 01312 * @retval None 01313 */ 01314 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) 01315 { 01316 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); 01317 } 01318 #endif /* DAC_CHANNEL2_SUPPORT */ 01319 01320 /** 01321 * @} 01322 */ 01323 01324 /** @defgroup DAC_LL_EF_IT_Management IT management 01325 * @{ 01326 */ 01327 01328 /** 01329 * @brief Enable DMA underrun interrupt for DAC channel 1 01330 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 01331 * @param DACx DAC instance 01332 * @retval None 01333 */ 01334 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) 01335 { 01336 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01337 } 01338 01339 #if defined(DAC_CHANNEL2_SUPPORT) 01340 /** 01341 * @brief Enable DMA underrun interrupt for DAC channel 2 01342 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 01343 * @param DACx DAC instance 01344 * @retval None 01345 */ 01346 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) 01347 { 01348 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01349 } 01350 #endif /* DAC_CHANNEL2_SUPPORT */ 01351 01352 /** 01353 * @brief Disable DMA underrun interrupt for DAC channel 1 01354 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 01355 * @param DACx DAC instance 01356 * @retval None 01357 */ 01358 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) 01359 { 01360 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01361 } 01362 01363 #if defined(DAC_CHANNEL2_SUPPORT) 01364 /** 01365 * @brief Disable DMA underrun interrupt for DAC channel 2 01366 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 01367 * @param DACx DAC instance 01368 * @retval None 01369 */ 01370 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) 01371 { 01372 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01373 } 01374 #endif /* DAC_CHANNEL2_SUPPORT */ 01375 01376 /** 01377 * @brief Get DMA underrun interrupt for DAC channel 1 01378 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 01379 * @param DACx DAC instance 01380 * @retval State of bit (1 or 0). 01381 */ 01382 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) 01383 { 01384 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); 01385 } 01386 01387 #if defined(DAC_CHANNEL2_SUPPORT) 01388 /** 01389 * @brief Get DMA underrun interrupt for DAC channel 2 01390 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 01391 * @param DACx DAC instance 01392 * @retval State of bit (1 or 0). 01393 */ 01394 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) 01395 { 01396 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); 01397 } 01398 #endif /* DAC_CHANNEL2_SUPPORT */ 01399 01400 /** 01401 * @} 01402 */ 01403 01404 #if defined(USE_FULL_LL_DRIVER) 01405 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions 01406 * @{ 01407 */ 01408 01409 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); 01410 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); 01411 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); 01412 01413 /** 01414 * @} 01415 */ 01416 #endif /* USE_FULL_LL_DRIVER */ 01417 01418 /** 01419 * @} 01420 */ 01421 01422 /** 01423 * @} 01424 */ 01425 01426 #endif /* DAC */ 01427 01428 /** 01429 * @} 01430 */ 01431 01432 #ifdef __cplusplus 01433 } 01434 #endif 01435 01436 #endif /* __STM32F4xx_LL_DAC_H */ 01437 01438 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1