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STM32F439xx HAL User Manual
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Defines | |
| #define | DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
| #define | DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
| #define | DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) |
| #define | DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
| #define | DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
| #define | DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
| #define | DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ |
| #define | DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
| #define | DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
| #define | DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ |
| #define | DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
| #define | DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
| #define | DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U |
| #define | DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U |
| #define | DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U |
| #define | DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
| #define | DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ |
| #define | DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ |
| #define | DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) |
| #define | DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ |
| #define | DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ |
| #define | DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ |
| #define | DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ |
| #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ |
Definition at line 71 of file stm32f4xx_ll_dac.h.
| #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ |
Definition at line 72 of file stm32f4xx_ll_dac.h.
Definition at line 73 of file stm32f4xx_ll_dac.h.
Referenced by LL_DAC_Disable(), LL_DAC_DisableDMAReq(), LL_DAC_DisableTrigger(), LL_DAC_Enable(), LL_DAC_EnableDMAReq(), LL_DAC_EnableTrigger(), LL_DAC_GetOutputBuffer(), LL_DAC_GetTriggerSource(), LL_DAC_GetWaveAutoGeneration(), LL_DAC_GetWaveNoiseLFSR(), LL_DAC_GetWaveTriangleAmplitude(), LL_DAC_Init(), LL_DAC_IsDMAReqEnabled(), LL_DAC_IsEnabled(), LL_DAC_IsTriggerEnabled(), LL_DAC_SetOutputBuffer(), LL_DAC_SetTriggerSource(), LL_DAC_SetWaveAutoGeneration(), LL_DAC_SetWaveNoiseLFSR(), and LL_DAC_SetWaveTriangleAmplitude().
| #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ |
Definition at line 107 of file stm32f4xx_ll_dac.h.
Referenced by LL_DAC_ConvertDualData12LeftAligned().
| #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ |
Definition at line 106 of file stm32f4xx_ll_dac.h.
Referenced by LL_DAC_ConvertDualData12RightAligned().
| #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ |
Definition at line 108 of file stm32f4xx_ll_dac.h.
Referenced by LL_DAC_ConvertDualData8RightAligned().
| #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ |
Definition at line 112 of file stm32f4xx_ll_dac.h.
| #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
Definition at line 84 of file stm32f4xx_ll_dac.h.
| #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ |
Definition at line 88 of file stm32f4xx_ll_dac.h.
| #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U |
Definition at line 92 of file stm32f4xx_ll_dac.h.
Referenced by LL_DAC_ConvertData12LeftAligned().
| #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ |
Definition at line 83 of file stm32f4xx_ll_dac.h.
| #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ |
Definition at line 87 of file stm32f4xx_ll_dac.h.
| #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U |
Definition at line 91 of file stm32f4xx_ll_dac.h.
Referenced by LL_DAC_ConvertData12RightAligned().
| #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
Definition at line 85 of file stm32f4xx_ll_dac.h.
| #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ |
Definition at line 89 of file stm32f4xx_ll_dac.h.
| #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U |
Definition at line 93 of file stm32f4xx_ll_dac.h.
Referenced by LL_DAC_ConvertData8RightAligned().
| #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) |
Definition at line 94 of file stm32f4xx_ll_dac.h.
| #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ |
Definition at line 96 of file stm32f4xx_ll_dac.h.
| #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ |
Definition at line 98 of file stm32f4xx_ll_dac.h.
Definition at line 99 of file stm32f4xx_ll_dac.h.
Referenced by LL_DAC_RetrieveOutputData().
| #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
Definition at line 75 of file stm32f4xx_ll_dac.h.
| #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ |
Definition at line 77 of file stm32f4xx_ll_dac.h.
| #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) |
Definition at line 78 of file stm32f4xx_ll_dac.h.
Referenced by LL_DAC_TrigSWConversion().
1.7.6.1