STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_sdram.c 00004 * @author MCD Application Team 00005 * @brief SDRAM HAL module driver. 00006 * This file provides a generic firmware to drive SDRAM memories mounted 00007 * as external device. 00008 * 00009 @verbatim 00010 ============================================================================== 00011 ##### How to use this driver ##### 00012 ============================================================================== 00013 [..] 00014 This driver is a generic layered driver which contains a set of APIs used to 00015 control SDRAM memories. It uses the FMC layer functions to interface 00016 with SDRAM devices. 00017 The following sequence should be followed to configure the FMC to interface 00018 with SDRAM memories: 00019 00020 (#) Declare a SDRAM_HandleTypeDef handle structure, for example: 00021 SDRAM_HandleTypeDef hdsram 00022 00023 (++) Fill the SDRAM_HandleTypeDef handle "Init" field with the allowed 00024 values of the structure member. 00025 00026 (++) Fill the SDRAM_HandleTypeDef handle "Instance" field with a predefined 00027 base register instance for NOR or SDRAM device 00028 00029 (#) Declare a FMC_SDRAM_TimingTypeDef structure; for example: 00030 FMC_SDRAM_TimingTypeDef Timing; 00031 and fill its fields with the allowed values of the structure member. 00032 00033 (#) Initialize the SDRAM Controller by calling the function HAL_SDRAM_Init(). This function 00034 performs the following sequence: 00035 00036 (##) MSP hardware layer configuration using the function HAL_SDRAM_MspInit() 00037 (##) Control register configuration using the FMC SDRAM interface function 00038 FMC_SDRAM_Init() 00039 (##) Timing register configuration using the FMC SDRAM interface function 00040 FMC_SDRAM_Timing_Init() 00041 (##) Program the SDRAM external device by applying its initialization sequence 00042 according to the device plugged in your hardware. This step is mandatory 00043 for accessing the SDRAM device. 00044 00045 (#) At this stage you can perform read/write accesses from/to the memory connected 00046 to the SDRAM Bank. You can perform either polling or DMA transfer using the 00047 following APIs: 00048 (++) HAL_SDRAM_Read()/HAL_SDRAM_Write() for polling read/write access 00049 (++) HAL_SDRAM_Read_DMA()/HAL_SDRAM_Write_DMA() for DMA read/write transfer 00050 00051 (#) You can also control the SDRAM device by calling the control APIs HAL_SDRAM_WriteOperation_Enable()/ 00052 HAL_SDRAM_WriteOperation_Disable() to respectively enable/disable the SDRAM write operation or 00053 the function HAL_SDRAM_SendCommand() to send a specified command to the SDRAM 00054 device. The command to be sent must be configured with the FMC_SDRAM_CommandTypeDef 00055 structure. 00056 00057 (#) You can continuously monitor the SDRAM device HAL state by calling the function 00058 HAL_SDRAM_GetState() 00059 00060 @endverbatim 00061 ****************************************************************************** 00062 * @attention 00063 * 00064 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00065 * 00066 * Redistribution and use in source and binary forms, with or without modification, 00067 * are permitted provided that the following conditions are met: 00068 * 1. Redistributions of source code must retain the above copyright notice, 00069 * this list of conditions and the following disclaimer. 00070 * 2. Redistributions in binary form must reproduce the above copyright notice, 00071 * this list of conditions and the following disclaimer in the documentation 00072 * and/or other materials provided with the distribution. 00073 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00074 * may be used to endorse or promote products derived from this software 00075 * without specific prior written permission. 00076 * 00077 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00078 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00079 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00080 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00081 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00082 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00083 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00084 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00085 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00086 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00087 * 00088 ****************************************************************************** 00089 */ 00090 00091 /* Includes ------------------------------------------------------------------*/ 00092 #include "stm32f4xx_hal.h" 00093 00094 /** @addtogroup STM32F4xx_HAL_Driver 00095 * @{ 00096 */ 00097 00098 /** @defgroup SDRAM SDRAM 00099 * @brief SDRAM driver modules 00100 * @{ 00101 */ 00102 #ifdef HAL_SDRAM_MODULE_ENABLED 00103 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 00104 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 00105 00106 /* Private typedef -----------------------------------------------------------*/ 00107 /* Private define ------------------------------------------------------------*/ 00108 /* Private macro -------------------------------------------------------------*/ 00109 /* Private variables ---------------------------------------------------------*/ 00110 /* Private functions ---------------------------------------------------------*/ 00111 /* Exported functions --------------------------------------------------------*/ 00112 /** @defgroup SDRAM_Exported_Functions SDRAM Exported Functions 00113 * @{ 00114 */ 00115 00116 /** @defgroup SDRAM_Exported_Functions_Group1 Initialization and de-initialization functions 00117 * @brief Initialization and Configuration functions 00118 * 00119 @verbatim 00120 ============================================================================== 00121 ##### SDRAM Initialization and de_initialization functions ##### 00122 ============================================================================== 00123 [..] 00124 This section provides functions allowing to initialize/de-initialize 00125 the SDRAM memory 00126 00127 @endverbatim 00128 * @{ 00129 */ 00130 00131 /** 00132 * @brief Performs the SDRAM device initialization sequence. 00133 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00134 * the configuration information for SDRAM module. 00135 * @param Timing Pointer to SDRAM control timing structure 00136 * @retval HAL status 00137 */ 00138 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing) 00139 { 00140 /* Check the SDRAM handle parameter */ 00141 if(hsdram == NULL) 00142 { 00143 return HAL_ERROR; 00144 } 00145 00146 if(hsdram->State == HAL_SDRAM_STATE_RESET) 00147 { 00148 /* Allocate lock resource and initialize it */ 00149 hsdram->Lock = HAL_UNLOCKED; 00150 /* Initialize the low level hardware (MSP) */ 00151 HAL_SDRAM_MspInit(hsdram); 00152 } 00153 00154 /* Initialize the SDRAM controller state */ 00155 hsdram->State = HAL_SDRAM_STATE_BUSY; 00156 00157 /* Initialize SDRAM control Interface */ 00158 FMC_SDRAM_Init(hsdram->Instance, &(hsdram->Init)); 00159 00160 /* Initialize SDRAM timing Interface */ 00161 FMC_SDRAM_Timing_Init(hsdram->Instance, Timing, hsdram->Init.SDBank); 00162 00163 /* Update the SDRAM controller state */ 00164 hsdram->State = HAL_SDRAM_STATE_READY; 00165 00166 return HAL_OK; 00167 } 00168 00169 /** 00170 * @brief Perform the SDRAM device initialization sequence. 00171 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00172 * the configuration information for SDRAM module. 00173 * @retval HAL status 00174 */ 00175 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram) 00176 { 00177 /* Initialize the low level hardware (MSP) */ 00178 HAL_SDRAM_MspDeInit(hsdram); 00179 00180 /* Configure the SDRAM registers with their reset values */ 00181 FMC_SDRAM_DeInit(hsdram->Instance, hsdram->Init.SDBank); 00182 00183 /* Reset the SDRAM controller state */ 00184 hsdram->State = HAL_SDRAM_STATE_RESET; 00185 00186 /* Release Lock */ 00187 __HAL_UNLOCK(hsdram); 00188 00189 return HAL_OK; 00190 } 00191 00192 /** 00193 * @brief SDRAM MSP Init. 00194 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00195 * the configuration information for SDRAM module. 00196 * @retval None 00197 */ 00198 __weak void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram) 00199 { 00200 /* Prevent unused argument(s) compilation warning */ 00201 UNUSED(hsdram); 00202 /* NOTE: This function Should not be modified, when the callback is needed, 00203 the HAL_SDRAM_MspInit could be implemented in the user file 00204 */ 00205 } 00206 00207 /** 00208 * @brief SDRAM MSP DeInit. 00209 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00210 * the configuration information for SDRAM module. 00211 * @retval None 00212 */ 00213 __weak void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram) 00214 { 00215 /* Prevent unused argument(s) compilation warning */ 00216 UNUSED(hsdram); 00217 /* NOTE: This function Should not be modified, when the callback is needed, 00218 the HAL_SDRAM_MspDeInit could be implemented in the user file 00219 */ 00220 } 00221 00222 /** 00223 * @brief This function handles SDRAM refresh error interrupt request. 00224 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00225 * the configuration information for SDRAM module. 00226 * @retval HAL status 00227 */ 00228 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram) 00229 { 00230 /* Check SDRAM interrupt Rising edge flag */ 00231 if(__FMC_SDRAM_GET_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_IT)) 00232 { 00233 /* SDRAM refresh error interrupt callback */ 00234 HAL_SDRAM_RefreshErrorCallback(hsdram); 00235 00236 /* Clear SDRAM refresh error interrupt pending bit */ 00237 __FMC_SDRAM_CLEAR_FLAG(hsdram->Instance, FMC_SDRAM_FLAG_REFRESH_ERROR); 00238 } 00239 } 00240 00241 /** 00242 * @brief SDRAM Refresh error callback. 00243 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00244 * the configuration information for SDRAM module. 00245 * @retval None 00246 */ 00247 __weak void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram) 00248 { 00249 /* Prevent unused argument(s) compilation warning */ 00250 UNUSED(hsdram); 00251 /* NOTE: This function Should not be modified, when the callback is needed, 00252 the HAL_SDRAM_RefreshErrorCallback could be implemented in the user file 00253 */ 00254 } 00255 00256 /** 00257 * @brief DMA transfer complete callback. 00258 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00259 * the configuration information for the specified DMA module. 00260 * @retval None 00261 */ 00262 __weak void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) 00263 { 00264 /* Prevent unused argument(s) compilation warning */ 00265 UNUSED(hdma); 00266 /* NOTE: This function Should not be modified, when the callback is needed, 00267 the HAL_SDRAM_DMA_XferCpltCallback could be implemented in the user file 00268 */ 00269 } 00270 00271 /** 00272 * @brief DMA transfer complete error callback. 00273 * @param hdma DMA handle 00274 * @retval None 00275 */ 00276 __weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) 00277 { 00278 /* Prevent unused argument(s) compilation warning */ 00279 UNUSED(hdma); 00280 /* NOTE: This function Should not be modified, when the callback is needed, 00281 the HAL_SDRAM_DMA_XferErrorCallback could be implemented in the user file 00282 */ 00283 } 00284 /** 00285 * @} 00286 */ 00287 00288 /** @defgroup SDRAM_Exported_Functions_Group2 Input and Output functions 00289 * @brief Input Output and memory control functions 00290 * 00291 @verbatim 00292 ============================================================================== 00293 ##### SDRAM Input and Output functions ##### 00294 ============================================================================== 00295 [..] 00296 This section provides functions allowing to use and control the SDRAM memory 00297 00298 @endverbatim 00299 * @{ 00300 */ 00301 00302 /** 00303 * @brief Reads 8-bit data buffer from the SDRAM memory. 00304 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00305 * the configuration information for SDRAM module. 00306 * @param pAddress Pointer to read start address 00307 * @param pDstBuffer Pointer to destination buffer 00308 * @param BufferSize Size of the buffer to read from memory 00309 * @retval HAL status 00310 */ 00311 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) 00312 { 00313 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; 00314 00315 /* Process Locked */ 00316 __HAL_LOCK(hsdram); 00317 00318 /* Check the SDRAM controller state */ 00319 if(hsdram->State == HAL_SDRAM_STATE_BUSY) 00320 { 00321 return HAL_BUSY; 00322 } 00323 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) 00324 { 00325 return HAL_ERROR; 00326 } 00327 00328 /* Read data from source */ 00329 for(; BufferSize != 0U; BufferSize--) 00330 { 00331 *pDstBuffer = *(__IO uint8_t *)pSdramAddress; 00332 pDstBuffer++; 00333 pSdramAddress++; 00334 } 00335 00336 /* Process Unlocked */ 00337 __HAL_UNLOCK(hsdram); 00338 00339 return HAL_OK; 00340 } 00341 00342 /** 00343 * @brief Writes 8-bit data buffer to SDRAM memory. 00344 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00345 * the configuration information for SDRAM module. 00346 * @param pAddress Pointer to write start address 00347 * @param pSrcBuffer Pointer to source buffer to write 00348 * @param BufferSize Size of the buffer to write to memory 00349 * @retval HAL status 00350 */ 00351 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) 00352 { 00353 __IO uint8_t *pSdramAddress = (uint8_t *)pAddress; 00354 uint32_t tmp = 0U; 00355 00356 /* Process Locked */ 00357 __HAL_LOCK(hsdram); 00358 00359 /* Check the SDRAM controller state */ 00360 tmp = hsdram->State; 00361 00362 if(tmp == HAL_SDRAM_STATE_BUSY) 00363 { 00364 return HAL_BUSY; 00365 } 00366 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00367 { 00368 return HAL_ERROR; 00369 } 00370 00371 /* Write data to memory */ 00372 for(; BufferSize != 0U; BufferSize--) 00373 { 00374 *(__IO uint8_t *)pSdramAddress = *pSrcBuffer; 00375 pSrcBuffer++; 00376 pSdramAddress++; 00377 } 00378 00379 /* Process Unlocked */ 00380 __HAL_UNLOCK(hsdram); 00381 00382 return HAL_OK; 00383 } 00384 00385 /** 00386 * @brief Reads 16-bit data buffer from the SDRAM memory. 00387 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00388 * the configuration information for SDRAM module. 00389 * @param pAddress Pointer to read start address 00390 * @param pDstBuffer Pointer to destination buffer 00391 * @param BufferSize Size of the buffer to read from memory 00392 * @retval HAL status 00393 */ 00394 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) 00395 { 00396 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; 00397 00398 /* Process Locked */ 00399 __HAL_LOCK(hsdram); 00400 00401 /* Check the SDRAM controller state */ 00402 if(hsdram->State == HAL_SDRAM_STATE_BUSY) 00403 { 00404 return HAL_BUSY; 00405 } 00406 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) 00407 { 00408 return HAL_ERROR; 00409 } 00410 00411 /* Read data from source */ 00412 for(; BufferSize != 0U; BufferSize--) 00413 { 00414 *pDstBuffer = *(__IO uint16_t *)pSdramAddress; 00415 pDstBuffer++; 00416 pSdramAddress++; 00417 } 00418 00419 /* Process Unlocked */ 00420 __HAL_UNLOCK(hsdram); 00421 00422 return HAL_OK; 00423 } 00424 00425 /** 00426 * @brief Writes 16-bit data buffer to SDRAM memory. 00427 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00428 * the configuration information for SDRAM module. 00429 * @param pAddress Pointer to write start address 00430 * @param pSrcBuffer Pointer to source buffer to write 00431 * @param BufferSize Size of the buffer to write to memory 00432 * @retval HAL status 00433 */ 00434 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) 00435 { 00436 __IO uint16_t *pSdramAddress = (uint16_t *)pAddress; 00437 uint32_t tmp = 0U; 00438 00439 /* Process Locked */ 00440 __HAL_LOCK(hsdram); 00441 00442 /* Check the SDRAM controller state */ 00443 tmp = hsdram->State; 00444 00445 if(tmp == HAL_SDRAM_STATE_BUSY) 00446 { 00447 return HAL_BUSY; 00448 } 00449 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00450 { 00451 return HAL_ERROR; 00452 } 00453 00454 /* Write data to memory */ 00455 for(; BufferSize != 0U; BufferSize--) 00456 { 00457 *(__IO uint16_t *)pSdramAddress = *pSrcBuffer; 00458 pSrcBuffer++; 00459 pSdramAddress++; 00460 } 00461 00462 /* Process Unlocked */ 00463 __HAL_UNLOCK(hsdram); 00464 00465 return HAL_OK; 00466 } 00467 00468 /** 00469 * @brief Reads 32-bit data buffer from the SDRAM memory. 00470 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00471 * the configuration information for SDRAM module. 00472 * @param pAddress Pointer to read start address 00473 * @param pDstBuffer Pointer to destination buffer 00474 * @param BufferSize Size of the buffer to read from memory 00475 * @retval HAL status 00476 */ 00477 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) 00478 { 00479 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; 00480 00481 /* Process Locked */ 00482 __HAL_LOCK(hsdram); 00483 00484 /* Check the SDRAM controller state */ 00485 if(hsdram->State == HAL_SDRAM_STATE_BUSY) 00486 { 00487 return HAL_BUSY; 00488 } 00489 else if(hsdram->State == HAL_SDRAM_STATE_PRECHARGED) 00490 { 00491 return HAL_ERROR; 00492 } 00493 00494 /* Read data from source */ 00495 for(; BufferSize != 0U; BufferSize--) 00496 { 00497 *pDstBuffer = *(__IO uint32_t *)pSdramAddress; 00498 pDstBuffer++; 00499 pSdramAddress++; 00500 } 00501 00502 /* Process Unlocked */ 00503 __HAL_UNLOCK(hsdram); 00504 00505 return HAL_OK; 00506 } 00507 00508 /** 00509 * @brief Writes 32-bit data buffer to SDRAM memory. 00510 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00511 * the configuration information for SDRAM module. 00512 * @param pAddress Pointer to write start address 00513 * @param pSrcBuffer Pointer to source buffer to write 00514 * @param BufferSize Size of the buffer to write to memory 00515 * @retval HAL status 00516 */ 00517 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) 00518 { 00519 __IO uint32_t *pSdramAddress = (uint32_t *)pAddress; 00520 uint32_t tmp = 0U; 00521 00522 /* Process Locked */ 00523 __HAL_LOCK(hsdram); 00524 00525 /* Check the SDRAM controller state */ 00526 tmp = hsdram->State; 00527 00528 if(tmp == HAL_SDRAM_STATE_BUSY) 00529 { 00530 return HAL_BUSY; 00531 } 00532 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00533 { 00534 return HAL_ERROR; 00535 } 00536 00537 /* Write data to memory */ 00538 for(; BufferSize != 0U; BufferSize--) 00539 { 00540 *(__IO uint32_t *)pSdramAddress = *pSrcBuffer; 00541 pSrcBuffer++; 00542 pSdramAddress++; 00543 } 00544 00545 /* Process Unlocked */ 00546 __HAL_UNLOCK(hsdram); 00547 00548 return HAL_OK; 00549 } 00550 00551 /** 00552 * @brief Reads a Words data from the SDRAM memory using DMA transfer. 00553 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00554 * the configuration information for SDRAM module. 00555 * @param pAddress Pointer to read start address 00556 * @param pDstBuffer Pointer to destination buffer 00557 * @param BufferSize Size of the buffer to read from memory 00558 * @retval HAL status 00559 */ 00560 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) 00561 { 00562 uint32_t tmp = 0U; 00563 00564 /* Process Locked */ 00565 __HAL_LOCK(hsdram); 00566 00567 /* Check the SDRAM controller state */ 00568 tmp = hsdram->State; 00569 00570 if(tmp == HAL_SDRAM_STATE_BUSY) 00571 { 00572 return HAL_BUSY; 00573 } 00574 else if(tmp == HAL_SDRAM_STATE_PRECHARGED) 00575 { 00576 return HAL_ERROR; 00577 } 00578 00579 /* Configure DMA user callbacks */ 00580 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; 00581 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; 00582 00583 /* Enable the DMA Stream */ 00584 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); 00585 00586 /* Process Unlocked */ 00587 __HAL_UNLOCK(hsdram); 00588 00589 return HAL_OK; 00590 } 00591 00592 /** 00593 * @brief Writes a Words data buffer to SDRAM memory using DMA transfer. 00594 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00595 * the configuration information for SDRAM module. 00596 * @param pAddress Pointer to write start address 00597 * @param pSrcBuffer Pointer to source buffer to write 00598 * @param BufferSize Size of the buffer to write to memory 00599 * @retval HAL status 00600 */ 00601 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) 00602 { 00603 uint32_t tmp = 0U; 00604 00605 /* Process Locked */ 00606 __HAL_LOCK(hsdram); 00607 00608 /* Check the SDRAM controller state */ 00609 tmp = hsdram->State; 00610 00611 if(tmp == HAL_SDRAM_STATE_BUSY) 00612 { 00613 return HAL_BUSY; 00614 } 00615 else if((tmp == HAL_SDRAM_STATE_PRECHARGED) || (tmp == HAL_SDRAM_STATE_WRITE_PROTECTED)) 00616 { 00617 return HAL_ERROR; 00618 } 00619 00620 /* Configure DMA user callbacks */ 00621 hsdram->hdma->XferCpltCallback = HAL_SDRAM_DMA_XferCpltCallback; 00622 hsdram->hdma->XferErrorCallback = HAL_SDRAM_DMA_XferErrorCallback; 00623 00624 /* Enable the DMA Stream */ 00625 HAL_DMA_Start_IT(hsdram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); 00626 00627 /* Process Unlocked */ 00628 __HAL_UNLOCK(hsdram); 00629 00630 return HAL_OK; 00631 } 00632 /** 00633 * @} 00634 */ 00635 00636 /** @defgroup SDRAM_Exported_Functions_Group3 Control functions 00637 * @brief management functions 00638 * 00639 @verbatim 00640 ============================================================================== 00641 ##### SDRAM Control functions ##### 00642 ============================================================================== 00643 [..] 00644 This subsection provides a set of functions allowing to control dynamically 00645 the SDRAM interface. 00646 00647 @endverbatim 00648 * @{ 00649 */ 00650 00651 /** 00652 * @brief Enables dynamically SDRAM write protection. 00653 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00654 * the configuration information for SDRAM module. 00655 * @retval HAL status 00656 */ 00657 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram) 00658 { 00659 /* Check the SDRAM controller state */ 00660 if(hsdram->State == HAL_SDRAM_STATE_BUSY) 00661 { 00662 return HAL_BUSY; 00663 } 00664 00665 /* Update the SDRAM state */ 00666 hsdram->State = HAL_SDRAM_STATE_BUSY; 00667 00668 /* Enable write protection */ 00669 FMC_SDRAM_WriteProtection_Enable(hsdram->Instance, hsdram->Init.SDBank); 00670 00671 /* Update the SDRAM state */ 00672 hsdram->State = HAL_SDRAM_STATE_WRITE_PROTECTED; 00673 00674 return HAL_OK; 00675 } 00676 00677 /** 00678 * @brief Disables dynamically SDRAM write protection. 00679 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00680 * the configuration information for SDRAM module. 00681 * @retval HAL status 00682 */ 00683 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram) 00684 { 00685 /* Check the SDRAM controller state */ 00686 if(hsdram->State == HAL_SDRAM_STATE_BUSY) 00687 { 00688 return HAL_BUSY; 00689 } 00690 00691 /* Update the SDRAM state */ 00692 hsdram->State = HAL_SDRAM_STATE_BUSY; 00693 00694 /* Disable write protection */ 00695 FMC_SDRAM_WriteProtection_Disable(hsdram->Instance, hsdram->Init.SDBank); 00696 00697 /* Update the SDRAM state */ 00698 hsdram->State = HAL_SDRAM_STATE_READY; 00699 00700 return HAL_OK; 00701 } 00702 00703 /** 00704 * @brief Sends Command to the SDRAM bank. 00705 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00706 * the configuration information for SDRAM module. 00707 * @param Command SDRAM command structure 00708 * @param Timeout Timeout duration 00709 * @retval HAL status 00710 */ 00711 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout) 00712 { 00713 /* Check the SDRAM controller state */ 00714 if(hsdram->State == HAL_SDRAM_STATE_BUSY) 00715 { 00716 return HAL_BUSY; 00717 } 00718 00719 /* Update the SDRAM state */ 00720 hsdram->State = HAL_SDRAM_STATE_BUSY; 00721 00722 /* Send SDRAM command */ 00723 FMC_SDRAM_SendCommand(hsdram->Instance, Command, Timeout); 00724 00725 /* Update the SDRAM controller state */ 00726 if(Command->CommandMode == FMC_SDRAM_CMD_PALL) 00727 { 00728 hsdram->State = HAL_SDRAM_STATE_PRECHARGED; 00729 } 00730 else 00731 { 00732 hsdram->State = HAL_SDRAM_STATE_READY; 00733 } 00734 00735 return HAL_OK; 00736 } 00737 00738 /** 00739 * @brief Programs the SDRAM Memory Refresh rate. 00740 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00741 * the configuration information for SDRAM module. 00742 * @param RefreshRate The SDRAM refresh rate value 00743 * @retval HAL status 00744 */ 00745 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate) 00746 { 00747 /* Check the SDRAM controller state */ 00748 if(hsdram->State == HAL_SDRAM_STATE_BUSY) 00749 { 00750 return HAL_BUSY; 00751 } 00752 00753 /* Update the SDRAM state */ 00754 hsdram->State = HAL_SDRAM_STATE_BUSY; 00755 00756 /* Program the refresh rate */ 00757 FMC_SDRAM_ProgramRefreshRate(hsdram->Instance ,RefreshRate); 00758 00759 /* Update the SDRAM state */ 00760 hsdram->State = HAL_SDRAM_STATE_READY; 00761 00762 return HAL_OK; 00763 } 00764 00765 /** 00766 * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands. 00767 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00768 * the configuration information for SDRAM module. 00769 * @param AutoRefreshNumber The SDRAM auto Refresh number 00770 * @retval HAL status 00771 */ 00772 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber) 00773 { 00774 /* Check the SDRAM controller state */ 00775 if(hsdram->State == HAL_SDRAM_STATE_BUSY) 00776 { 00777 return HAL_BUSY; 00778 } 00779 00780 /* Update the SDRAM state */ 00781 hsdram->State = HAL_SDRAM_STATE_BUSY; 00782 00783 /* Set the Auto-Refresh number */ 00784 FMC_SDRAM_SetAutoRefreshNumber(hsdram->Instance ,AutoRefreshNumber); 00785 00786 /* Update the SDRAM state */ 00787 hsdram->State = HAL_SDRAM_STATE_READY; 00788 00789 return HAL_OK; 00790 } 00791 00792 /** 00793 * @brief Returns the SDRAM memory current mode. 00794 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00795 * the configuration information for SDRAM module. 00796 * @retval The SDRAM memory mode. 00797 */ 00798 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram) 00799 { 00800 /* Return the SDRAM memory current mode */ 00801 return(FMC_SDRAM_GetModeStatus(hsdram->Instance, hsdram->Init.SDBank)); 00802 } 00803 00804 /** 00805 * @} 00806 */ 00807 00808 /** @defgroup SDRAM_Exported_Functions_Group4 State functions 00809 * @brief Peripheral State functions 00810 * 00811 @verbatim 00812 ============================================================================== 00813 ##### SDRAM State functions ##### 00814 ============================================================================== 00815 [..] 00816 This subsection permits to get in run-time the status of the SDRAM controller 00817 and the data flow. 00818 00819 @endverbatim 00820 * @{ 00821 */ 00822 00823 /** 00824 * @brief Returns the SDRAM state. 00825 * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains 00826 * the configuration information for SDRAM module. 00827 * @retval HAL state 00828 */ 00829 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram) 00830 { 00831 return hsdram->State; 00832 } 00833 00834 /** 00835 * @} 00836 */ 00837 00838 /** 00839 * @} 00840 */ 00841 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 00842 #endif /* HAL_SDRAM_MODULE_ENABLED */ 00843 /** 00844 * @} 00845 */ 00846 00847 /** 00848 * @} 00849 */ 00850 00851 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/