STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_pwr_ex.c 00004 * @author MCD Application Team 00005 * @brief Extended PWR HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of PWR extension peripheral: 00008 * + Peripheral Extended features functions 00009 * 00010 ****************************************************************************** 00011 * @attention 00012 * 00013 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00014 * 00015 * Redistribution and use in source and binary forms, with or without modification, 00016 * are permitted provided that the following conditions are met: 00017 * 1. Redistributions of source code must retain the above copyright notice, 00018 * this list of conditions and the following disclaimer. 00019 * 2. Redistributions in binary form must reproduce the above copyright notice, 00020 * this list of conditions and the following disclaimer in the documentation 00021 * and/or other materials provided with the distribution. 00022 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00023 * may be used to endorse or promote products derived from this software 00024 * without specific prior written permission. 00025 * 00026 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00027 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00028 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00029 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00030 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00031 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00032 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00033 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00034 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00035 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00036 * 00037 ****************************************************************************** 00038 */ 00039 00040 /* Includes ------------------------------------------------------------------*/ 00041 #include "stm32f4xx_hal.h" 00042 00043 /** @addtogroup STM32F4xx_HAL_Driver 00044 * @{ 00045 */ 00046 00047 /** @defgroup PWREx PWREx 00048 * @brief PWR HAL module driver 00049 * @{ 00050 */ 00051 00052 #ifdef HAL_PWR_MODULE_ENABLED 00053 00054 /* Private typedef -----------------------------------------------------------*/ 00055 /* Private define ------------------------------------------------------------*/ 00056 /** @addtogroup PWREx_Private_Constants 00057 * @{ 00058 */ 00059 #define PWR_OVERDRIVE_TIMEOUT_VALUE 1000U 00060 #define PWR_UDERDRIVE_TIMEOUT_VALUE 1000U 00061 #define PWR_BKPREG_TIMEOUT_VALUE 1000U 00062 #define PWR_VOSRDY_TIMEOUT_VALUE 1000U 00063 /** 00064 * @} 00065 */ 00066 00067 00068 /* Private macro -------------------------------------------------------------*/ 00069 /* Private variables ---------------------------------------------------------*/ 00070 /* Private function prototypes -----------------------------------------------*/ 00071 /* Private functions ---------------------------------------------------------*/ 00072 /** @defgroup PWREx_Exported_Functions PWREx Exported Functions 00073 * @{ 00074 */ 00075 00076 /** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended features functions 00077 * @brief Peripheral Extended features functions 00078 * 00079 @verbatim 00080 00081 =============================================================================== 00082 ##### Peripheral extended features functions ##### 00083 =============================================================================== 00084 00085 *** Main and Backup Regulators configuration *** 00086 ================================================ 00087 [..] 00088 (+) The backup domain includes 4 Kbytes of backup SRAM accessible only from 00089 the CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is 00090 retained even in Standby or VBAT mode when the low power backup regulator 00091 is enabled. It can be considered as an internal EEPROM when VBAT is 00092 always present. You can use the HAL_PWREx_EnableBkUpReg() function to 00093 enable the low power backup regulator. 00094 00095 (+) When the backup domain is supplied by VDD (analog switch connected to VDD) 00096 the backup SRAM is powered from VDD which replaces the VBAT power supply to 00097 save battery life. 00098 00099 (+) The backup SRAM is not mass erased by a tamper event. It is read 00100 protected to prevent confidential data, such as cryptographic private 00101 key, from being accessed. The backup SRAM can be erased only through 00102 the Flash interface when a protection level change from level 1 to 00103 level 0 is requested. 00104 -@- Refer to the description of Read protection (RDP) in the Flash 00105 programming manual. 00106 00107 (+) The main internal regulator can be configured to have a tradeoff between 00108 performance and power consumption when the device does not operate at 00109 the maximum frequency. This is done through __HAL_PWR_MAINREGULATORMODE_CONFIG() 00110 macro which configure VOS bit in PWR_CR register 00111 00112 Refer to the product datasheets for more details. 00113 00114 *** FLASH Power Down configuration **** 00115 ======================================= 00116 [..] 00117 (+) By setting the FPDS bit in the PWR_CR register by using the 00118 HAL_PWREx_EnableFlashPowerDown() function, the Flash memory also enters power 00119 down mode when the device enters Stop mode. When the Flash memory 00120 is in power down mode, an additional startup delay is incurred when 00121 waking up from Stop mode. 00122 00123 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, the scale can be modified only when the PLL 00124 is OFF and the HSI or HSE clock source is selected as system clock. 00125 The new value programmed is active only when the PLL is ON. 00126 When the PLL is OFF, the voltage scale 3 is automatically selected. 00127 Refer to the datasheets for more details. 00128 00129 *** Over-Drive and Under-Drive configuration **** 00130 ================================================= 00131 [..] 00132 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Run mode: the main regulator has 00133 2 operating modes available: 00134 (++) Normal mode: The CPU and core logic operate at maximum frequency at a given 00135 voltage scaling (scale 1, scale 2 or scale 3) 00136 (++) Over-drive mode: This mode allows the CPU and the core logic to operate at a 00137 higher frequency than the normal mode for a given voltage scaling (scale 1, 00138 scale 2 or scale 3). This mode is enabled through HAL_PWREx_EnableOverDrive() function and 00139 disabled by HAL_PWREx_DisableOverDrive() function, to enter or exit from Over-drive mode please follow 00140 the sequence described in Reference manual. 00141 00142 (+) For STM32F42xxx/43xxx/446xx/469xx/479xx Devices, in Stop mode: the main regulator or low power regulator 00143 supplies a low power voltage to the 1.2V domain, thus preserving the content of registers 00144 and internal SRAM. 2 operating modes are available: 00145 (++) Normal mode: the 1.2V domain is preserved in nominal leakage mode. This mode is only 00146 available when the main regulator or the low power regulator is used in Scale 3 or 00147 low voltage mode. 00148 (++) Under-drive mode: the 1.2V domain is preserved in reduced leakage mode. This mode is only 00149 available when the main regulator or the low power regulator is in low voltage mode. 00150 00151 @endverbatim 00152 * @{ 00153 */ 00154 00155 /** 00156 * @brief Enables the Backup Regulator. 00157 * @retval HAL status 00158 */ 00159 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void) 00160 { 00161 uint32_t tickstart = 0U; 00162 00163 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)ENABLE; 00164 00165 /* Get tick */ 00166 tickstart = HAL_GetTick(); 00167 00168 /* Wait till Backup regulator ready flag is set */ 00169 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) == RESET) 00170 { 00171 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) 00172 { 00173 return HAL_TIMEOUT; 00174 } 00175 } 00176 return HAL_OK; 00177 } 00178 00179 /** 00180 * @brief Disables the Backup Regulator. 00181 * @retval HAL status 00182 */ 00183 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void) 00184 { 00185 uint32_t tickstart = 0U; 00186 00187 *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)DISABLE; 00188 00189 /* Get tick */ 00190 tickstart = HAL_GetTick(); 00191 00192 /* Wait till Backup regulator ready flag is set */ 00193 while(__HAL_PWR_GET_FLAG(PWR_FLAG_BRR) != RESET) 00194 { 00195 if((HAL_GetTick() - tickstart ) > PWR_BKPREG_TIMEOUT_VALUE) 00196 { 00197 return HAL_TIMEOUT; 00198 } 00199 } 00200 return HAL_OK; 00201 } 00202 00203 /** 00204 * @brief Enables the Flash Power Down in Stop mode. 00205 * @retval None 00206 */ 00207 void HAL_PWREx_EnableFlashPowerDown(void) 00208 { 00209 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)ENABLE; 00210 } 00211 00212 /** 00213 * @brief Disables the Flash Power Down in Stop mode. 00214 * @retval None 00215 */ 00216 void HAL_PWREx_DisableFlashPowerDown(void) 00217 { 00218 *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)DISABLE; 00219 } 00220 00221 /** 00222 * @brief Return Voltage Scaling Range. 00223 * @retval The configured scale for the regulator voltage(VOS bit field). 00224 * The returned value can be one of the following: 00225 * - @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode 00226 * - @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode 00227 * - @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode 00228 */ 00229 uint32_t HAL_PWREx_GetVoltageRange(void) 00230 { 00231 return (PWR->CR & PWR_CR_VOS); 00232 } 00233 00234 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) 00235 /** 00236 * @brief Configures the main internal regulator output voltage. 00237 * @param VoltageScaling specifies the regulator output voltage to achieve 00238 * a tradeoff between performance and power consumption. 00239 * This parameter can be one of the following values: 00240 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, 00241 * the maximum value of fHCLK = 168 MHz. 00242 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, 00243 * the maximum value of fHCLK = 144 MHz. 00244 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to 00245 * a value below 144 MHz before calling HAL_PWREx_ConfigVoltageScaling() API. 00246 * When moving from Range 2 to Range 1, the system frequency can be increased to 00247 * a value up to 168 MHz after calling HAL_PWREx_ConfigVoltageScaling() API. 00248 * @retval HAL Status 00249 */ 00250 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) 00251 { 00252 uint32_t tickstart = 0U; 00253 00254 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); 00255 00256 /* Enable PWR RCC Clock Peripheral */ 00257 __HAL_RCC_PWR_CLK_ENABLE(); 00258 00259 /* Set Range */ 00260 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); 00261 00262 /* Get Start Tick*/ 00263 tickstart = HAL_GetTick(); 00264 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) 00265 { 00266 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) 00267 { 00268 return HAL_TIMEOUT; 00269 } 00270 } 00271 00272 return HAL_OK; 00273 } 00274 00275 #elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \ 00276 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \ 00277 defined(STM32F410Rx) || defined(STM32F411xE) || defined(STM32F446xx) || defined(STM32F469xx) || \ 00278 defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \ 00279 defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx) 00280 /** 00281 * @brief Configures the main internal regulator output voltage. 00282 * @param VoltageScaling specifies the regulator output voltage to achieve 00283 * a tradeoff between performance and power consumption. 00284 * This parameter can be one of the following values: 00285 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode, 00286 * the maximum value of fHCLK is 168 MHz. It can be extended to 00287 * 180 MHz by activating the over-drive mode. 00288 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output range 2 mode, 00289 * the maximum value of fHCLK is 144 MHz. It can be extended to, 00290 * 168 MHz by activating the over-drive mode. 00291 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output range 3 mode, 00292 * the maximum value of fHCLK is 120 MHz. 00293 * @note To update the system clock frequency(SYSCLK): 00294 * - Set the HSI or HSE as system clock frequency using the HAL_RCC_ClockConfig(). 00295 * - Call the HAL_RCC_OscConfig() to configure the PLL. 00296 * - Call HAL_PWREx_ConfigVoltageScaling() API to adjust the voltage scale. 00297 * - Set the new system clock frequency using the HAL_RCC_ClockConfig(). 00298 * @note The scale can be modified only when the HSI or HSE clock source is selected 00299 * as system clock source, otherwise the API returns HAL_ERROR. 00300 * @note When the PLL is OFF, the voltage scale 3 is automatically selected and the VOS bits 00301 * value in the PWR_CR1 register are not taken in account. 00302 * @note This API forces the PLL state ON to allow the possibility to configure the voltage scale 1 or 2. 00303 * @note The new voltage scale is active only when the PLL is ON. 00304 * @retval HAL Status 00305 */ 00306 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) 00307 { 00308 uint32_t tickstart = 0U; 00309 00310 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); 00311 00312 /* Enable PWR RCC Clock Peripheral */ 00313 __HAL_RCC_PWR_CLK_ENABLE(); 00314 00315 /* Check if the PLL is used as system clock or not */ 00316 if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL) 00317 { 00318 /* Disable the main PLL */ 00319 __HAL_RCC_PLL_DISABLE(); 00320 00321 /* Get Start Tick */ 00322 tickstart = HAL_GetTick(); 00323 /* Wait till PLL is disabled */ 00324 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET) 00325 { 00326 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 00327 { 00328 return HAL_TIMEOUT; 00329 } 00330 } 00331 00332 /* Set Range */ 00333 __HAL_PWR_VOLTAGESCALING_CONFIG(VoltageScaling); 00334 00335 /* Enable the main PLL */ 00336 __HAL_RCC_PLL_ENABLE(); 00337 00338 /* Get Start Tick */ 00339 tickstart = HAL_GetTick(); 00340 /* Wait till PLL is ready */ 00341 while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET) 00342 { 00343 if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE) 00344 { 00345 return HAL_TIMEOUT; 00346 } 00347 } 00348 00349 /* Get Start Tick */ 00350 tickstart = HAL_GetTick(); 00351 while((__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY) == RESET)) 00352 { 00353 if((HAL_GetTick() - tickstart ) > PWR_VOSRDY_TIMEOUT_VALUE) 00354 { 00355 return HAL_TIMEOUT; 00356 } 00357 } 00358 } 00359 else 00360 { 00361 return HAL_ERROR; 00362 } 00363 00364 return HAL_OK; 00365 } 00366 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */ 00367 00368 #if defined(STM32F469xx) || defined(STM32F479xx) 00369 /** 00370 * @brief Enables Wakeup Pin Detection on high level (rising edge). 00371 * @retval None 00372 */ 00373 void HAL_PWREx_EnableWakeUpPinPolarityRisingEdge(void) 00374 { 00375 *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)DISABLE; 00376 } 00377 00378 /** 00379 * @brief Enables Wakeup Pin Detection on low level (falling edge). 00380 * @retval None 00381 */ 00382 void HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(void) 00383 { 00384 *(__IO uint32_t *) CSR_WUPP_BB = (uint32_t)ENABLE; 00385 } 00386 #endif /* STM32F469xx || STM32F479xx */ 00387 00388 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) ||\ 00389 defined(STM32F411xE) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\ 00390 defined(STM32F413xx) || defined(STM32F423xx) 00391 /** 00392 * @brief Enables Main Regulator low voltage mode. 00393 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ 00394 * STM32F413xx/STM32F423xx devices. 00395 * @retval None 00396 */ 00397 void HAL_PWREx_EnableMainRegulatorLowVoltage(void) 00398 { 00399 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)ENABLE; 00400 } 00401 00402 /** 00403 * @brief Disables Main Regulator low voltage mode. 00404 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ 00405 * STM32F413xx/STM32F423xxdevices. 00406 * @retval None 00407 */ 00408 void HAL_PWREx_DisableMainRegulatorLowVoltage(void) 00409 { 00410 *(__IO uint32_t *) CR_MRLVDS_BB = (uint32_t)DISABLE; 00411 } 00412 00413 /** 00414 * @brief Enables Low Power Regulator low voltage mode. 00415 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ 00416 * STM32F413xx/STM32F423xx devices. 00417 * @retval None 00418 */ 00419 void HAL_PWREx_EnableLowRegulatorLowVoltage(void) 00420 { 00421 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)ENABLE; 00422 } 00423 00424 /** 00425 * @brief Disables Low Power Regulator low voltage mode. 00426 * @note This mode is only available for STM32F401xx/STM32F410xx/STM32F411xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx/ 00427 * STM32F413xx/STM32F423xx devices. 00428 * @retval None 00429 */ 00430 void HAL_PWREx_DisableLowRegulatorLowVoltage(void) 00431 { 00432 *(__IO uint32_t *) CR_LPLVDS_BB = (uint32_t)DISABLE; 00433 } 00434 00435 #endif /* STM32F401xC || STM32F401xE || STM32F410xx || STM32F411xE || STM32F412Zx || STM32F412Rx || STM32F412Vx || STM32F412Cx || 00436 STM32F413xx || STM32F423xx */ 00437 00438 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\ 00439 defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) 00440 /** 00441 * @brief Activates the Over-Drive mode. 00442 * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. 00443 * This mode allows the CPU and the core logic to operate at a higher frequency 00444 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). 00445 * @note It is recommended to enter or exit Over-drive mode when the application is not running 00446 * critical tasks and when the system clock source is either HSI or HSE. 00447 * During the Over-drive switch activation, no peripheral clocks should be enabled. 00448 * The peripheral clocks must be enabled once the Over-drive mode is activated. 00449 * @retval HAL status 00450 */ 00451 HAL_StatusTypeDef HAL_PWREx_EnableOverDrive(void) 00452 { 00453 uint32_t tickstart = 0U; 00454 00455 __HAL_RCC_PWR_CLK_ENABLE(); 00456 00457 /* Enable the Over-drive to extend the clock frequency to 180 Mhz */ 00458 __HAL_PWR_OVERDRIVE_ENABLE(); 00459 00460 /* Get tick */ 00461 tickstart = HAL_GetTick(); 00462 00463 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) 00464 { 00465 if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) 00466 { 00467 return HAL_TIMEOUT; 00468 } 00469 } 00470 00471 /* Enable the Over-drive switch */ 00472 __HAL_PWR_OVERDRIVESWITCHING_ENABLE(); 00473 00474 /* Get tick */ 00475 tickstart = HAL_GetTick(); 00476 00477 while(!__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) 00478 { 00479 if((HAL_GetTick() - tickstart ) > PWR_OVERDRIVE_TIMEOUT_VALUE) 00480 { 00481 return HAL_TIMEOUT; 00482 } 00483 } 00484 return HAL_OK; 00485 } 00486 00487 /** 00488 * @brief Deactivates the Over-Drive mode. 00489 * @note This function can be used only for STM32F42xx/STM32F43xx/STM32F446xx/STM32F469xx/STM32F479xx devices. 00490 * This mode allows the CPU and the core logic to operate at a higher frequency 00491 * than the normal mode for a given voltage scaling (scale 1, scale 2 or scale 3). 00492 * @note It is recommended to enter or exit Over-drive mode when the application is not running 00493 * critical tasks and when the system clock source is either HSI or HSE. 00494 * During the Over-drive switch activation, no peripheral clocks should be enabled. 00495 * The peripheral clocks must be enabled once the Over-drive mode is activated. 00496 * @retval HAL status 00497 */ 00498 HAL_StatusTypeDef HAL_PWREx_DisableOverDrive(void) 00499 { 00500 uint32_t tickstart = 0U; 00501 00502 __HAL_RCC_PWR_CLK_ENABLE(); 00503 00504 /* Disable the Over-drive switch */ 00505 __HAL_PWR_OVERDRIVESWITCHING_DISABLE(); 00506 00507 /* Get tick */ 00508 tickstart = HAL_GetTick(); 00509 00510 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODSWRDY)) 00511 { 00512 if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) 00513 { 00514 return HAL_TIMEOUT; 00515 } 00516 } 00517 00518 /* Disable the Over-drive */ 00519 __HAL_PWR_OVERDRIVE_DISABLE(); 00520 00521 /* Get tick */ 00522 tickstart = HAL_GetTick(); 00523 00524 while(__HAL_PWR_GET_FLAG(PWR_FLAG_ODRDY)) 00525 { 00526 if((HAL_GetTick() - tickstart) > PWR_OVERDRIVE_TIMEOUT_VALUE) 00527 { 00528 return HAL_TIMEOUT; 00529 } 00530 } 00531 00532 return HAL_OK; 00533 } 00534 00535 /** 00536 * @brief Enters in Under-Drive STOP mode. 00537 * 00538 * @note This mode is only available for STM32F42xxx/STM32F43xxx/STM32F446xx/STM32F469xx/STM32F479xx devices. 00539 * 00540 * @note This mode can be selected only when the Under-Drive is already active 00541 * 00542 * @note This mode is enabled only with STOP low power mode. 00543 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This 00544 * mode is only available when the main regulator or the low power regulator 00545 * is in low voltage mode 00546 * 00547 * @note If the Under-drive mode was enabled, it is automatically disabled after 00548 * exiting Stop mode. 00549 * When the voltage regulator operates in Under-drive mode, an additional 00550 * startup delay is induced when waking up from Stop mode. 00551 * 00552 * @note In Stop mode, all I/O pins keep the same state as in Run mode. 00553 * 00554 * @note When exiting Stop mode by issuing an interrupt or a wake-up event, 00555 * the HSI RC oscillator is selected as system clock. 00556 * 00557 * @note When the voltage regulator operates in low power mode, an additional 00558 * startup delay is incurred when waking up from Stop mode. 00559 * By keeping the internal regulator ON during Stop mode, the consumption 00560 * is higher although the startup time is reduced. 00561 * 00562 * @param Regulator specifies the regulator state in STOP mode. 00563 * This parameter can be one of the following values: 00564 * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode 00565 * and Flash memory in power-down when the device is in Stop under-drive mode 00566 * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode 00567 * and Flash memory in power-down when the device is in Stop under-drive mode 00568 * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. 00569 * This parameter can be one of the following values: 00570 * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction 00571 * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction 00572 * @retval None 00573 */ 00574 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry) 00575 { 00576 uint32_t tmpreg1 = 0U; 00577 00578 /* Check the parameters */ 00579 assert_param(IS_PWR_REGULATOR_UNDERDRIVE(Regulator)); 00580 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 00581 00582 /* Enable Power ctrl clock */ 00583 __HAL_RCC_PWR_CLK_ENABLE(); 00584 /* Enable the Under-drive Mode ---------------------------------------------*/ 00585 /* Clear Under-drive flag */ 00586 __HAL_PWR_CLEAR_ODRUDR_FLAG(); 00587 00588 /* Enable the Under-drive */ 00589 __HAL_PWR_UNDERDRIVE_ENABLE(); 00590 00591 /* Select the regulator state in STOP mode ---------------------------------*/ 00592 tmpreg1 = PWR->CR; 00593 /* Clear PDDS, LPDS, MRLUDS and LPLUDS bits */ 00594 tmpreg1 &= (uint32_t)~(PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_LPUDS | PWR_CR_MRUDS); 00595 00596 /* Set LPDS, MRLUDS and LPLUDS bits according to PWR_Regulator value */ 00597 tmpreg1 |= Regulator; 00598 00599 /* Store the new value */ 00600 PWR->CR = tmpreg1; 00601 00602 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00603 SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; 00604 00605 /* Select STOP mode entry --------------------------------------------------*/ 00606 if(STOPEntry == PWR_SLEEPENTRY_WFI) 00607 { 00608 /* Request Wait For Interrupt */ 00609 __WFI(); 00610 } 00611 else 00612 { 00613 /* Request Wait For Event */ 00614 __WFE(); 00615 } 00616 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 00617 SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk); 00618 00619 return HAL_OK; 00620 } 00621 00622 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ 00623 /** 00624 * @} 00625 */ 00626 00627 /** 00628 * @} 00629 */ 00630 00631 #endif /* HAL_PWR_MODULE_ENABLED */ 00632 /** 00633 * @} 00634 */ 00635 00636 /** 00637 * @} 00638 */ 00639 00640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/