STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_i2s.c 00004 * @author MCD Application Team 00005 * @brief I2S HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the Integrated Interchip Sound (I2S) peripheral: 00008 * + Initialization and de-initialization functions 00009 * + IO operation functions 00010 * + Peripheral State and Errors functions 00011 @verbatim 00012 =============================================================================== 00013 ##### How to use this driver ##### 00014 =============================================================================== 00015 [..] 00016 The I2S HAL driver can be used as follow: 00017 00018 (#) Declare a I2S_HandleTypeDef handle structure. 00019 (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API: 00020 (##) Enable the SPIx interface clock. 00021 (##) I2S pins configuration: 00022 (+++) Enable the clock for the I2S GPIOs. 00023 (+++) Configure these I2S pins as alternate function pull-up. 00024 (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT() 00025 and HAL_I2S_Receive_IT() APIs). 00026 (+++) Configure the I2Sx interrupt priority. 00027 (+++) Enable the NVIC I2S IRQ handle. 00028 (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA() 00029 and HAL_I2S_Receive_DMA() APIs: 00030 (+++) Declare a DMA handle structure for the Tx/Rx stream. 00031 (+++) Enable the DMAx interface clock. 00032 (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters. 00033 (+++) Configure the DMA Tx/Rx Stream. 00034 (+++) Associate the initialized DMA handle to the I2S DMA Tx/Rx handle. 00035 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the 00036 DMA Tx/Rx Stream. 00037 00038 (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity 00039 using HAL_I2S_Init() function. 00040 00041 -@- The specific I2S interrupts (Transmission complete interrupt, 00042 RXNE interrupt and Error Interrupts) will be managed using the macros 00043 __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process. 00044 -@- Make sure that either: 00045 (+@) I2S PLL is configured or 00046 (+@) External clock source is configured after setting correctly 00047 the define constant EXTERNAL_CLOCK_VALUE in the stm32f4xx_hal_conf.h file. 00048 00049 (#) Three operation modes are available within this driver : 00050 00051 *** Polling mode IO operation *** 00052 ================================= 00053 [..] 00054 (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() 00055 (+) Receive an amount of data in blocking mode using HAL_I2S_Receive() 00056 00057 *** Interrupt mode IO operation *** 00058 =================================== 00059 [..] 00060 (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() 00061 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 00062 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 00063 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 00064 add his own code by customization of function pointer HAL_I2S_TxCpltCallback 00065 (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() 00066 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 00067 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 00068 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 00069 add his own code by customization of function pointer HAL_I2S_RxCpltCallback 00070 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 00071 add his own code by customization of function pointer HAL_I2S_ErrorCallback 00072 00073 *** DMA mode IO operation *** 00074 ============================== 00075 [..] 00076 (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() 00077 (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 00078 add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 00079 (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 00080 add his own code by customization of function pointer HAL_I2S_TxCpltCallback 00081 (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() 00082 (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 00083 add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 00084 (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 00085 add his own code by customization of function pointer HAL_I2S_RxCpltCallback 00086 (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 00087 add his own code by customization of function pointer HAL_I2S_ErrorCallback 00088 (+) Pause the DMA Transfer using HAL_I2S_DMAPause() 00089 (+) Resume the DMA Transfer using HAL_I2S_DMAResume() 00090 (+) Stop the DMA Transfer using HAL_I2S_DMAStop() 00091 00092 *** I2S HAL driver macros list *** 00093 ============================================= 00094 [..] 00095 Below the list of most used macros in I2S HAL driver. 00096 00097 (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) 00098 (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode) 00099 (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts 00100 (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts 00101 (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not 00102 00103 [..] 00104 (@) You can refer to the I2S HAL driver header file for more useful macros 00105 00106 @endverbatim 00107 ****************************************************************************** 00108 * @attention 00109 * 00110 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00111 * 00112 * Redistribution and use in source and binary forms, with or without modification, 00113 * are permitted provided that the following conditions are met: 00114 * 1. Redistributions of source code must retain the above copyright notice, 00115 * this list of conditions and the following disclaimer. 00116 * 2. Redistributions in binary form must reproduce the above copyright notice, 00117 * this list of conditions and the following disclaimer in the documentation 00118 * and/or other materials provided with the distribution. 00119 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00120 * may be used to endorse or promote products derived from this software 00121 * without specific prior written permission. 00122 * 00123 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00124 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00125 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00126 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00127 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00128 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00129 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00130 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00131 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00132 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00133 * 00134 ****************************************************************************** 00135 */ 00136 00137 /* Includes ------------------------------------------------------------------*/ 00138 #include "stm32f4xx_hal.h" 00139 00140 /** @addtogroup STM32F4xx_HAL_Driver 00141 * @{ 00142 */ 00143 00144 #ifdef HAL_I2S_MODULE_ENABLED 00145 00146 /** @defgroup I2S I2S 00147 * @brief I2S HAL module driver 00148 * @{ 00149 */ 00150 00151 /* Private typedef -----------------------------------------------------------*/ 00152 /* Private define ------------------------------------------------------------*/ 00153 /* Private macro -------------------------------------------------------------*/ 00154 /* Private variables ---------------------------------------------------------*/ 00155 /* Private function prototypes -----------------------------------------------*/ 00156 00157 /** @addtogroup I2S_Private_Functions 00158 * @{ 00159 */ 00160 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma); 00161 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); 00162 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma); 00163 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma); 00164 static void I2S_DMAError(DMA_HandleTypeDef *hdma); 00165 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s); 00166 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s); 00167 static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s); 00168 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, 00169 uint32_t Timeout); 00170 /** 00171 * @} 00172 */ 00173 00174 /* Exported functions --------------------------------------------------------*/ 00175 /** @addtogroup I2S_Exported_Functions I2S Exported Functions 00176 * @{ 00177 */ 00178 00179 /** @addtogroup I2S_Exported_Functions_Group1 00180 * @brief Initialization and Configuration functions 00181 * 00182 @verbatim 00183 =============================================================================== 00184 ##### Initialization and de-initialization functions ##### 00185 =============================================================================== 00186 [..] This subsection provides a set of functions allowing to initialize and 00187 de-initialize the I2Sx peripheral in simplex mode: 00188 00189 (+) User must Implement HAL_I2S_MspInit() function in which he configures 00190 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ). 00191 00192 (+) Call the function HAL_I2S_Init() to configure the selected device with 00193 the selected configuration: 00194 (++) Mode 00195 (++) Standard 00196 (++) Data Format 00197 (++) MCLK Output 00198 (++) Audio frequency 00199 (++) Polarity 00200 (++) Full duplex mode 00201 00202 (+) Call the function HAL_I2S_DeInit() to restore the default configuration 00203 of the selected I2Sx peripheral. 00204 @endverbatim 00205 * @{ 00206 */ 00207 00208 /** 00209 * @brief Initializes the I2S according to the specified parameters 00210 * in the I2S_InitTypeDef and create the associated handle. 00211 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 00212 * the configuration information for I2S module 00213 * @retval HAL status 00214 */ 00215 HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s) 00216 { 00217 uint32_t tmpreg = 0U, i2sdiv = 2U, i2sodd = 0U, packetlength = 16U; 00218 uint32_t tmp = 0U, i2sclk = 0U; 00219 00220 /* Check the I2S handle allocation */ 00221 if(hi2s == NULL) 00222 { 00223 return HAL_ERROR; 00224 } 00225 00226 /* Check the I2S parameters */ 00227 assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance)); 00228 assert_param(IS_I2S_MODE(hi2s->Init.Mode)); 00229 assert_param(IS_I2S_STANDARD(hi2s->Init.Standard)); 00230 assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat)); 00231 assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput)); 00232 assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq)); 00233 assert_param(IS_I2S_CPOL(hi2s->Init.CPOL)); 00234 assert_param(IS_I2S_CLOCKSOURCE(hi2s->Init.ClockSource)); 00235 00236 hi2s->State = HAL_I2S_STATE_BUSY; 00237 00238 /* Initialize Default I2S IrqHandler ISR */ 00239 hi2s->IrqHandlerISR = I2S_IRQHandler; 00240 00241 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */ 00242 HAL_I2S_MspInit(hi2s); 00243 00244 /*----------------------- SPIx I2SCFGR & I2SPR Configuration ---------------*/ 00245 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ 00246 CLEAR_BIT(hi2s->Instance->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ 00247 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ 00248 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); 00249 hi2s->Instance->I2SPR = 0x0002U; 00250 00251 /* Get the I2SCFGR register value */ 00252 tmpreg = hi2s->Instance->I2SCFGR; 00253 00254 /* If the default frequency value has to be written, reinitialize i2sdiv and i2sodd */ 00255 /* If the requested audio frequency is not the default, compute the prescaler */ 00256 if(hi2s->Init.AudioFreq != I2S_AUDIOFREQ_DEFAULT) 00257 { 00258 /* Check the frame length (For the Prescaler computing) *******************/ 00259 /* Set I2S Packet Length value*/ 00260 if(hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) 00261 { 00262 /* Packet length is 32 bits */ 00263 packetlength = 32U; 00264 } 00265 else 00266 { 00267 /* Packet length is 16 bits */ 00268 packetlength = 16U; 00269 } 00270 00271 /* I2S standard */ 00272 if(hi2s->Init.Standard <= I2S_STANDARD_LSB) 00273 { 00274 /* In I2S standard packet lenght is multiplied by 2 */ 00275 packetlength = packetlength * 2U; 00276 } 00277 00278 /* Get I2S source Clock frequency from RCC ********************************/ 00279 #if defined(I2S_APB1_APB2_FEATURE) 00280 if(IS_I2S_APB1_INSTANCE(hi2s->Instance)) 00281 { 00282 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB1); 00283 } 00284 else 00285 { 00286 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S_APB2); 00287 } 00288 #else 00289 i2sclk = HAL_RCCEx_GetPeriphCLKFreq(RCC_PERIPHCLK_I2S); 00290 #endif 00291 00292 /* Compute the Real divider depending on the MCLK output state, with a floating point */ 00293 if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE) 00294 { 00295 /* MCLK output is enabled */ 00296 if (hi2s->Init.DataFormat != I2S_DATAFORMAT_16B) 00297 { 00298 tmp = (uint32_t)(((((i2sclk / (packetlength*4)) * 10) / hi2s->Init.AudioFreq)) + 5); 00299 } 00300 else 00301 { 00302 tmp = (uint32_t)(((((i2sclk / (packetlength*8)) * 10) / hi2s->Init.AudioFreq)) + 5); 00303 } 00304 } 00305 else 00306 { 00307 /* MCLK output is disabled */ 00308 tmp = (uint32_t)(((((i2sclk / packetlength) *10 ) / hi2s->Init.AudioFreq)) + 5); 00309 } 00310 00311 /* Remove the flatting point */ 00312 tmp = tmp / 10U; 00313 00314 /* Check the parity of the divider */ 00315 i2sodd = (uint16_t)(tmp & (uint16_t)1U); 00316 00317 /* Compute the i2sdiv prescaler */ 00318 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); 00319 00320 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ 00321 i2sodd = (uint32_t) (i2sodd << 8U); 00322 } 00323 00324 /* Test if the divider is 1 or 0 or greater than 0xFF */ 00325 if((i2sdiv < 2U) || (i2sdiv > 0xFFU)) 00326 { 00327 /* Set the default values */ 00328 i2sdiv = 2U; 00329 i2sodd = 0U; 00330 00331 /* Set the error code and execute error callback*/ 00332 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_PRESCALER); 00333 HAL_I2S_ErrorCallback(hi2s); 00334 return HAL_ERROR; 00335 } 00336 00337 /* Write to SPIx I2SPR register the computed value */ 00338 hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput)); 00339 00340 /* Configure the I2S with the I2S_InitStruct values */ 00341 tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(hi2s->Init.Mode | \ 00342 (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ 00343 (uint16_t)hi2s->Init.CPOL)))); 00344 00345 #if defined(SPI_I2SCFGR_ASTRTEN) 00346 if ((hi2s->Init.Standard == I2S_STANDARD_PCM_SHORT) ||(hi2s->Init.Standard == I2S_STANDARD_PCM_LONG)) 00347 { 00348 /* Write to SPIx I2SCFGR */ 00349 WRITE_REG(hi2s->Instance->I2SCFGR,(tmpreg | SPI_I2SCFGR_ASTRTEN)); 00350 } 00351 else 00352 { 00353 /* Write to SPIx I2SCFGR */ 00354 WRITE_REG(hi2s->Instance->I2SCFGR,tmpreg); 00355 } 00356 #else 00357 /* Write to SPIx I2SCFGR */ 00358 WRITE_REG(hi2s->Instance->I2SCFGR, tmpreg); 00359 #endif 00360 00361 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) 00362 00363 /* Configure the I2S extended if the full duplex mode is enabled */ 00364 assert_param(IS_I2S_FULLDUPLEX_MODE(hi2s->Init.FullDuplexMode)); 00365 00366 if(hi2s->Init.FullDuplexMode == I2S_FULLDUPLEXMODE_ENABLE) 00367 { 00368 /* Set FullDuplex I2S IrqHandler ISR if FULLDUPLEXMODE is enabled */ 00369 hi2s->IrqHandlerISR = HAL_I2SEx_FullDuplex_IRQHandler; 00370 00371 /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */ 00372 CLEAR_BIT(I2SxEXT(hi2s->Instance)->I2SCFGR,(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CKPOL | \ 00373 SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG | \ 00374 SPI_I2SCFGR_I2SE | SPI_I2SCFGR_I2SMOD)); 00375 I2SxEXT(hi2s->Instance)->I2SPR = 2U; 00376 00377 /* Get the I2SCFGR register value */ 00378 tmpreg = I2SxEXT(hi2s->Instance)->I2SCFGR; 00379 00380 /* Get the mode to be configured for the extended I2S */ 00381 if((hi2s->Init.Mode == I2S_MODE_MASTER_TX) || (hi2s->Init.Mode == I2S_MODE_SLAVE_TX)) 00382 { 00383 tmp = I2S_MODE_SLAVE_RX; 00384 } 00385 else /* I2S_MODE_MASTER_RX || I2S_MODE_SLAVE_RX */ 00386 { 00387 tmp = I2S_MODE_SLAVE_TX; 00388 } 00389 00390 /* Configure the I2S Slave with the I2S Master parameter values */ 00391 tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \ 00392 (uint16_t)(hi2s->Init.Standard | (uint16_t)(hi2s->Init.DataFormat | \ 00393 (uint16_t)hi2s->Init.CPOL)))); 00394 00395 /* Write to SPIx I2SCFGR */ 00396 WRITE_REG(I2SxEXT(hi2s->Instance)->I2SCFGR,tmpreg); 00397 } 00398 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ 00399 00400 hi2s->ErrorCode = HAL_I2S_ERROR_NONE; 00401 hi2s->State = HAL_I2S_STATE_READY; 00402 00403 return HAL_OK; 00404 } 00405 00406 /** 00407 * @brief DeInitializes the I2S peripheral 00408 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 00409 * the configuration information for I2S module 00410 * @retval HAL status 00411 */ 00412 HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s) 00413 { 00414 /* Check the I2S handle allocation */ 00415 if(hi2s == NULL) 00416 { 00417 return HAL_ERROR; 00418 } 00419 00420 hi2s->State = HAL_I2S_STATE_BUSY; 00421 00422 /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */ 00423 HAL_I2S_MspDeInit(hi2s); 00424 00425 hi2s->ErrorCode = HAL_I2S_ERROR_NONE; 00426 hi2s->State = HAL_I2S_STATE_RESET; 00427 00428 /* Release Lock */ 00429 __HAL_UNLOCK(hi2s); 00430 00431 return HAL_OK; 00432 } 00433 00434 /** 00435 * @brief I2S MSP Init 00436 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 00437 * the configuration information for I2S module 00438 * @retval None 00439 */ 00440 __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s) 00441 { 00442 /* Prevent unused argument(s) compilation warning */ 00443 UNUSED(hi2s); 00444 /* NOTE : This function Should not be modified, when the callback is needed, 00445 the HAL_I2S_MspInit could be implemented in the user file 00446 */ 00447 } 00448 00449 /** 00450 * @brief I2S MSP DeInit 00451 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 00452 * the configuration information for I2S module 00453 * @retval None 00454 */ 00455 __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s) 00456 { 00457 /* Prevent unused argument(s) compilation warning */ 00458 UNUSED(hi2s); 00459 /* NOTE : This function Should not be modified, when the callback is needed, 00460 the HAL_I2S_MspDeInit could be implemented in the user file 00461 */ 00462 } 00463 /** 00464 * @} 00465 */ 00466 00467 /** @addtogroup I2S_Exported_Functions_Group2 00468 * @brief Data transfers functions 00469 * 00470 @verbatim 00471 =============================================================================== 00472 ##### IO operation functions ##### 00473 =============================================================================== 00474 [..] 00475 This subsection provides a set of functions allowing to manage the I2S data 00476 transfers. 00477 00478 (#) There are two modes of transfer: 00479 (++) Blocking mode : The communication is performed in the polling mode. 00480 The status of all data processing is returned by the same function 00481 after finishing transfer. 00482 (++) No-Blocking mode : The communication is performed using Interrupts 00483 or DMA. These functions return the status of the transfer startup. 00484 The end of the data processing will be indicated through the 00485 dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when 00486 using DMA mode. 00487 00488 (#) Blocking mode functions are : 00489 (++) HAL_I2S_Transmit() 00490 (++) HAL_I2S_Receive() 00491 00492 (#) No-Blocking mode functions with Interrupt are : 00493 (++) HAL_I2S_Transmit_IT() 00494 (++) HAL_I2S_Receive_IT() 00495 00496 (#) No-Blocking mode functions with DMA are : 00497 (++) HAL_I2S_Transmit_DMA() 00498 (++) HAL_I2S_Receive_DMA() 00499 00500 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode: 00501 (++) HAL_I2S_TxCpltCallback() 00502 (++) HAL_I2S_RxCpltCallback() 00503 (++) HAL_I2S_ErrorCallback() 00504 00505 @endverbatim 00506 * @{ 00507 */ 00508 00509 /** 00510 * @brief Transmit an amount of data in blocking mode 00511 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 00512 * the configuration information for I2S module 00513 * @param pData a 16-bit pointer to data buffer. 00514 * @param Size number of data sample to be sent: 00515 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S 00516 * configuration phase, the Size parameter means the number of 16-bit data length 00517 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 00518 * the Size parameter means the number of 16-bit data length. 00519 * @param Timeout Timeout duration 00520 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 00521 * between Master and Slave(example: audio streaming). 00522 * @retval HAL status 00523 */ 00524 HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) 00525 { 00526 uint32_t tmp1 = 0U; 00527 00528 if((pData == NULL ) || (Size == 0U)) 00529 { 00530 return HAL_ERROR; 00531 } 00532 00533 if(hi2s->State == HAL_I2S_STATE_READY) 00534 { 00535 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); 00536 00537 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) 00538 { 00539 hi2s->TxXferSize = (Size << 1U); 00540 hi2s->TxXferCount = (Size << 1U); 00541 } 00542 else 00543 { 00544 hi2s->TxXferSize = Size; 00545 hi2s->TxXferCount = Size; 00546 } 00547 00548 /* Process Locked */ 00549 __HAL_LOCK(hi2s); 00550 00551 hi2s->ErrorCode = HAL_I2S_ERROR_NONE; 00552 hi2s->State = HAL_I2S_STATE_BUSY_TX; 00553 00554 /* Check if the I2S is already enabled */ 00555 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) 00556 { 00557 /* Enable I2S peripheral */ 00558 __HAL_I2S_ENABLE(hi2s); 00559 } 00560 00561 while(hi2s->TxXferCount > 0U) 00562 { 00563 hi2s->Instance->DR = (*pData++); 00564 hi2s->TxXferCount--; 00565 00566 /* Wait until TXE flag is set */ 00567 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, SET, Timeout) != HAL_OK) 00568 { 00569 /* Set the error code and execute error callback*/ 00570 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_TIMEOUT); 00571 HAL_I2S_ErrorCallback(hi2s); 00572 return HAL_TIMEOUT; 00573 } 00574 00575 /* Check if an underrun occurs */ 00576 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_UDR) == SET) 00577 { 00578 /* Clear underrun flag */ 00579 __HAL_I2S_CLEAR_UDRFLAG(hi2s); 00580 /* Set the I2S State ready */ 00581 hi2s->State = HAL_I2S_STATE_READY; 00582 00583 /* Process Unlocked */ 00584 __HAL_UNLOCK(hi2s); 00585 00586 /* Set the error code and execute error callback*/ 00587 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); 00588 HAL_I2S_ErrorCallback(hi2s); 00589 00590 return HAL_ERROR; 00591 } 00592 } 00593 hi2s->State = HAL_I2S_STATE_READY; 00594 00595 /* Process Unlocked */ 00596 __HAL_UNLOCK(hi2s); 00597 00598 return HAL_OK; 00599 } 00600 else 00601 { 00602 return HAL_BUSY; 00603 } 00604 } 00605 00606 /** 00607 * @brief Receive an amount of data in blocking mode 00608 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 00609 * the configuration information for I2S module 00610 * @param pData a 16-bit pointer to data buffer 00611 * @param Size number of data sample to be sent: 00612 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S 00613 * configuration phase, the Size parameter means the number of 16-bit data length 00614 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 00615 * the Size parameter means the number of 16-bit data length. 00616 * @param Timeout Timeout duration 00617 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 00618 * between Master and Slave(example: audio streaming) 00619 * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate 00620 * in continuous way and as the I2S is not disabled at the end of the I2S transaction 00621 * @retval HAL status 00622 */ 00623 HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout) 00624 { 00625 uint32_t tmp1 = 0U; 00626 00627 if((pData == NULL ) || (Size == 0U)) 00628 { 00629 return HAL_ERROR; 00630 } 00631 00632 if(hi2s->State == HAL_I2S_STATE_READY) 00633 { 00634 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); 00635 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) 00636 { 00637 hi2s->RxXferSize = (Size << 1U); 00638 hi2s->RxXferCount = (Size << 1U); 00639 } 00640 else 00641 { 00642 hi2s->RxXferSize = Size; 00643 hi2s->RxXferCount = Size; 00644 } 00645 /* Process Locked */ 00646 __HAL_LOCK(hi2s); 00647 00648 hi2s->ErrorCode = HAL_I2S_ERROR_NONE; 00649 hi2s->State = HAL_I2S_STATE_BUSY_RX; 00650 00651 /* Check if the I2S is already enabled */ 00652 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) 00653 { 00654 /* Enable I2S peripheral */ 00655 __HAL_I2S_ENABLE(hi2s); 00656 } 00657 00658 /* Check if Master Receiver mode is selected */ 00659 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) 00660 { 00661 /* Clear the Overrun Flag by a read operation on the SPI_DR register followed by a read 00662 access to the SPI_SR register. */ 00663 __HAL_I2S_CLEAR_OVRFLAG(hi2s); 00664 } 00665 00666 /* Receive data */ 00667 while(hi2s->RxXferCount > 0U) 00668 { 00669 /* Wait until RXNE flag is set */ 00670 if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, SET, Timeout) != HAL_OK) 00671 { 00672 /* Set the error code and execute error callback*/ 00673 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_TIMEOUT); 00674 HAL_I2S_ErrorCallback(hi2s); 00675 return HAL_TIMEOUT; 00676 } 00677 00678 /* Check if an overrun occurs */ 00679 if(__HAL_I2S_GET_FLAG(hi2s, I2S_FLAG_OVR) == SET) 00680 { 00681 /* Clear overrun flag */ 00682 __HAL_I2S_CLEAR_OVRFLAG(hi2s); 00683 00684 /* Set the I2S State ready */ 00685 hi2s->State = HAL_I2S_STATE_READY; 00686 00687 /* Process Unlocked */ 00688 __HAL_UNLOCK(hi2s); 00689 00690 /* Set the error code and execute error callback*/ 00691 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR); 00692 HAL_I2S_ErrorCallback(hi2s); 00693 00694 return HAL_ERROR; 00695 } 00696 00697 (*pData++) = hi2s->Instance->DR; 00698 hi2s->RxXferCount--; 00699 } 00700 00701 hi2s->State = HAL_I2S_STATE_READY; 00702 00703 /* Process Unlocked */ 00704 __HAL_UNLOCK(hi2s); 00705 00706 return HAL_OK; 00707 } 00708 else 00709 { 00710 return HAL_BUSY; 00711 } 00712 } 00713 00714 /** 00715 * @brief Transmit an amount of data in non-blocking mode with Interrupt 00716 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 00717 * the configuration information for I2S module 00718 * @param pData a 16-bit pointer to data buffer. 00719 * @param Size number of data sample to be sent: 00720 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S 00721 * configuration phase, the Size parameter means the number of 16-bit data length 00722 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 00723 * the Size parameter means the number of 16-bit data length. 00724 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 00725 * between Master and Slave(example: audio streaming). 00726 * @retval HAL status 00727 */ 00728 HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) 00729 { 00730 uint32_t tmp1 = 0U; 00731 00732 if(hi2s->State == HAL_I2S_STATE_READY) 00733 { 00734 if((pData == NULL) || (Size == 0U)) 00735 { 00736 return HAL_ERROR; 00737 } 00738 00739 hi2s->pTxBuffPtr = pData; 00740 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); 00741 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) 00742 { 00743 hi2s->TxXferSize = (Size << 1U); 00744 hi2s->TxXferCount = (Size << 1U); 00745 } 00746 else 00747 { 00748 hi2s->TxXferSize = Size; 00749 hi2s->TxXferCount = Size; 00750 } 00751 00752 /* Process Locked */ 00753 __HAL_LOCK(hi2s); 00754 00755 hi2s->State = HAL_I2S_STATE_BUSY_TX; 00756 hi2s->ErrorCode = HAL_I2S_ERROR_NONE; 00757 00758 /* Enable TXE and ERR interrupt */ 00759 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); 00760 00761 /* Check if the I2S is already enabled */ 00762 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) 00763 { 00764 /* Enable I2S peripheral */ 00765 __HAL_I2S_ENABLE(hi2s); 00766 } 00767 00768 /* Process Unlocked */ 00769 __HAL_UNLOCK(hi2s); 00770 00771 return HAL_OK; 00772 } 00773 else 00774 { 00775 return HAL_BUSY; 00776 } 00777 } 00778 00779 /** 00780 * @brief Receive an amount of data in non-blocking mode with Interrupt 00781 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 00782 * the configuration information for I2S module 00783 * @param pData a 16-bit pointer to the Receive data buffer. 00784 * @param Size number of data sample to be sent: 00785 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S 00786 * configuration phase, the Size parameter means the number of 16-bit data length 00787 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 00788 * the Size parameter means the number of 16-bit data length. 00789 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 00790 * between Master and Slave(example: audio streaming). 00791 * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation 00792 * between Master and Slave otherwise the I2S interrupt should be optimized. 00793 * @retval HAL status 00794 */ 00795 HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) 00796 { 00797 uint32_t tmp1 = 0U; 00798 00799 if(hi2s->State == HAL_I2S_STATE_READY) 00800 { 00801 if((pData == NULL) || (Size == 0U)) 00802 { 00803 return HAL_ERROR; 00804 } 00805 00806 hi2s->pRxBuffPtr = pData; 00807 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); 00808 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) 00809 { 00810 hi2s->RxXferSize = (Size << 1U); 00811 hi2s->RxXferCount = (Size << 1U); 00812 } 00813 else 00814 { 00815 hi2s->RxXferSize = Size; 00816 hi2s->RxXferCount = Size; 00817 } 00818 /* Process Locked */ 00819 __HAL_LOCK(hi2s); 00820 00821 hi2s->State = HAL_I2S_STATE_BUSY_RX; 00822 hi2s->ErrorCode = HAL_I2S_ERROR_NONE; 00823 00824 /* Enable TXE and ERR interrupt */ 00825 __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); 00826 00827 /* Check if the I2S is already enabled */ 00828 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) 00829 { 00830 /* Enable I2S peripheral */ 00831 __HAL_I2S_ENABLE(hi2s); 00832 } 00833 00834 /* Process Unlocked */ 00835 __HAL_UNLOCK(hi2s); 00836 00837 return HAL_OK; 00838 } 00839 00840 else 00841 { 00842 return HAL_BUSY; 00843 } 00844 } 00845 00846 /** 00847 * @brief Transmit an amount of data in non-blocking mode with DMA 00848 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 00849 * the configuration information for I2S module 00850 * @param pData a 16-bit pointer to the Transmit data buffer. 00851 * @param Size number of data sample to be sent: 00852 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S 00853 * configuration phase, the Size parameter means the number of 16-bit data length 00854 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 00855 * the Size parameter means the number of 16-bit data length. 00856 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 00857 * between Master and Slave(example: audio streaming). 00858 * @retval HAL status 00859 */ 00860 HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) 00861 { 00862 uint32_t *tmp = NULL; 00863 uint32_t tmp1 = 0U; 00864 00865 if((pData == NULL) || (Size == 0U)) 00866 { 00867 return HAL_ERROR; 00868 } 00869 00870 if(hi2s->State == HAL_I2S_STATE_READY) 00871 { 00872 hi2s->pTxBuffPtr = pData; 00873 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); 00874 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) 00875 { 00876 hi2s->TxXferSize = (Size << 1U); 00877 hi2s->TxXferCount = (Size << 1U); 00878 } 00879 else 00880 { 00881 hi2s->TxXferSize = Size; 00882 hi2s->TxXferCount = Size; 00883 } 00884 00885 /* Process Locked */ 00886 __HAL_LOCK(hi2s); 00887 00888 hi2s->ErrorCode = HAL_I2S_ERROR_NONE; 00889 hi2s->State = HAL_I2S_STATE_BUSY_TX; 00890 00891 /* Set the I2S Tx DMA Half transfer complete callback */ 00892 hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt; 00893 00894 /* Set the I2S Tx DMA transfer complete callback */ 00895 hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt; 00896 00897 /* Set the DMA error callback */ 00898 hi2s->hdmatx->XferErrorCallback = I2S_DMAError; 00899 00900 /* Enable the Tx DMA Stream */ 00901 tmp = (uint32_t*)&pData; 00902 HAL_DMA_Start_IT(hi2s->hdmatx, *(uint32_t*)tmp, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize); 00903 00904 /* Check if the I2S is already enabled */ 00905 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) 00906 { 00907 /* Enable I2S peripheral */ 00908 __HAL_I2S_ENABLE(hi2s); 00909 } 00910 00911 /* Check if the I2S Tx request is already enabled */ 00912 if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN) 00913 { 00914 /* Enable Tx DMA Request */ 00915 SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN); 00916 } 00917 00918 /* Process Unlocked */ 00919 __HAL_UNLOCK(hi2s); 00920 00921 return HAL_OK; 00922 } 00923 else 00924 { 00925 return HAL_BUSY; 00926 } 00927 } 00928 00929 /** 00930 * @brief Receive an amount of data in non-blocking mode with DMA 00931 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 00932 * the configuration information for I2S module 00933 * @param pData a 16-bit pointer to the Receive data buffer. 00934 * @param Size number of data sample to be sent: 00935 * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S 00936 * configuration phase, the Size parameter means the number of 16-bit data length 00937 * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 00938 * the Size parameter means the number of 16-bit data length. 00939 * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 00940 * between Master and Slave(example: audio streaming). 00941 * @retval HAL status 00942 */ 00943 HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size) 00944 { 00945 uint32_t *tmp = NULL; 00946 uint32_t tmp1 = 0U; 00947 00948 if((pData == NULL) || (Size == 0U)) 00949 { 00950 return HAL_ERROR; 00951 } 00952 00953 if(hi2s->State == HAL_I2S_STATE_READY) 00954 { 00955 hi2s->pRxBuffPtr = pData; 00956 tmp1 = hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN); 00957 if((tmp1 == I2S_DATAFORMAT_24B) || (tmp1 == I2S_DATAFORMAT_32B)) 00958 { 00959 hi2s->RxXferSize = (Size << 1U); 00960 hi2s->RxXferCount = (Size << 1U); 00961 } 00962 else 00963 { 00964 hi2s->RxXferSize = Size; 00965 hi2s->RxXferCount = Size; 00966 } 00967 /* Process Locked */ 00968 __HAL_LOCK(hi2s); 00969 00970 hi2s->State = HAL_I2S_STATE_BUSY_RX; 00971 hi2s->ErrorCode = HAL_I2S_ERROR_NONE; 00972 00973 /* Set the I2S Rx DMA Half transfer complete callback */ 00974 hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt; 00975 00976 /* Set the I2S Rx DMA transfer complete callback */ 00977 hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt; 00978 00979 /* Set the DMA error callback */ 00980 hi2s->hdmarx->XferErrorCallback = I2S_DMAError; 00981 00982 /* Check if Master Receiver mode is selected */ 00983 if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX) 00984 { 00985 /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read 00986 access to the SPI_SR register. */ 00987 __HAL_I2S_CLEAR_OVRFLAG(hi2s); 00988 } 00989 00990 /* Enable the Rx DMA Stream */ 00991 tmp = (uint32_t*)&pData; 00992 HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, *(uint32_t*)tmp, hi2s->RxXferSize); 00993 00994 /* Check if the I2S is already enabled */ 00995 if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE) 00996 { 00997 /* Enable I2S peripheral */ 00998 __HAL_I2S_ENABLE(hi2s); 00999 } 01000 01001 /* Check if the I2S Rx request is already enabled */ 01002 if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN) 01003 { 01004 /* Enable Rx DMA Request */ 01005 SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); 01006 } 01007 01008 /* Process Unlocked */ 01009 __HAL_UNLOCK(hi2s); 01010 01011 return HAL_OK; 01012 } 01013 else 01014 { 01015 return HAL_BUSY; 01016 } 01017 } 01018 01019 /** 01020 * @brief Pauses the audio stream playing from the Media. 01021 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01022 * the configuration information for I2S module 01023 * @retval HAL status 01024 */ 01025 HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s) 01026 { 01027 /* Process Locked */ 01028 __HAL_LOCK(hi2s); 01029 01030 if(hi2s->State == HAL_I2S_STATE_BUSY_TX) 01031 { 01032 /* Disable the I2S DMA Tx request */ 01033 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN); 01034 } 01035 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) 01036 { 01037 /* Disable the I2S DMA Rx request */ 01038 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); 01039 } 01040 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) 01041 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) 01042 { 01043 /* Pause the audio file playing by disabling the I2S DMA request */ 01044 CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_TXDMAEN|SPI_CR2_RXDMAEN)); 01045 CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_TXDMAEN|SPI_CR2_RXDMAEN)); 01046 } 01047 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ 01048 01049 /* Process Unlocked */ 01050 __HAL_UNLOCK(hi2s); 01051 01052 return HAL_OK; 01053 } 01054 01055 /** 01056 * @brief Resumes the audio stream playing from the Media. 01057 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01058 * the configuration information for I2S module 01059 * @retval HAL status 01060 */ 01061 HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s) 01062 { 01063 /* Process Locked */ 01064 __HAL_LOCK(hi2s); 01065 01066 if(hi2s->State == HAL_I2S_STATE_BUSY_TX) 01067 { 01068 /* Enable the I2S DMA Tx request */ 01069 SET_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN); 01070 } 01071 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) 01072 { 01073 /* Enable the I2S DMA Rx request */ 01074 SET_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); 01075 } 01076 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) 01077 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) 01078 { 01079 /* Pause the audio file playing by disabling the I2S DMA request */ 01080 SET_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); 01081 SET_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); 01082 01083 /* If the I2Sext peripheral is still not enabled, enable it */ 01084 if ((I2SxEXT(hi2s->Instance)->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U) 01085 { 01086 /* Enable I2Sext peripheral */ 01087 __HAL_I2SEXT_ENABLE(hi2s); 01088 } 01089 } 01090 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ 01091 01092 /* If the I2S peripheral is still not enabled, enable it */ 01093 if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0U) 01094 { 01095 /* Enable I2S peripheral */ 01096 __HAL_I2S_ENABLE(hi2s); 01097 } 01098 01099 /* Process Unlocked */ 01100 __HAL_UNLOCK(hi2s); 01101 01102 return HAL_OK; 01103 } 01104 01105 /** 01106 * @brief Resumes the audio stream playing from the Media. 01107 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01108 * the configuration information for I2S module 01109 * @retval HAL status 01110 */ 01111 HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s) 01112 { 01113 /* Process Locked */ 01114 __HAL_LOCK(hi2s); 01115 01116 if(hi2s->State == HAL_I2S_STATE_BUSY_TX) 01117 { 01118 /* Disable the I2S DMA requests */ 01119 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN); 01120 01121 /* Disable the I2S DMA Channel */ 01122 HAL_DMA_Abort(hi2s->hdmatx); 01123 } 01124 else if(hi2s->State == HAL_I2S_STATE_BUSY_RX) 01125 { 01126 /* Disable the I2S DMA requests */ 01127 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); 01128 01129 /* Disable the I2S DMA Channel */ 01130 HAL_DMA_Abort(hi2s->hdmarx); 01131 } 01132 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) 01133 else if(hi2s->State == HAL_I2S_STATE_BUSY_TX_RX) 01134 { 01135 /* Disable the I2S DMA requests */ 01136 CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); 01137 CLEAR_BIT(I2SxEXT(hi2s->Instance)->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); 01138 01139 /* Disable the I2S DMA Channels */ 01140 HAL_DMA_Abort(hi2s->hdmatx); 01141 HAL_DMA_Abort(hi2s->hdmarx); 01142 01143 /* Disable I2Sext peripheral */ 01144 __HAL_I2SEXT_DISABLE(hi2s); 01145 } 01146 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ 01147 01148 /* Disable I2S peripheral */ 01149 __HAL_I2S_DISABLE(hi2s); 01150 01151 hi2s->State = HAL_I2S_STATE_READY; 01152 01153 /* Process Unlocked */ 01154 __HAL_UNLOCK(hi2s); 01155 01156 return HAL_OK; 01157 } 01158 01159 /** 01160 * @brief This function handles I2S interrupt request. 01161 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01162 * the configuration information for I2S module 01163 * @retval None 01164 */ 01165 void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s) 01166 { 01167 /* Call the IrqHandler ISR set during HAL_I2S_INIT */ 01168 hi2s->IrqHandlerISR(hi2s); 01169 } 01170 01171 /** 01172 * @brief Tx Transfer Half completed callbacks 01173 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01174 * the configuration information for I2S module 01175 * @retval None 01176 */ 01177 __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s) 01178 { 01179 /* Prevent unused argument(s) compilation warning */ 01180 UNUSED(hi2s); 01181 /* NOTE : This function Should not be modified, when the callback is needed, 01182 the HAL_I2S_TxHalfCpltCallback could be implemented in the user file 01183 */ 01184 } 01185 01186 /** 01187 * @brief Tx Transfer completed callbacks 01188 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01189 * the configuration information for I2S module 01190 * @retval None 01191 */ 01192 __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s) 01193 { 01194 /* Prevent unused argument(s) compilation warning */ 01195 UNUSED(hi2s); 01196 /* NOTE : This function Should not be modified, when the callback is needed, 01197 the HAL_I2S_TxCpltCallback could be implemented in the user file 01198 */ 01199 } 01200 01201 /** 01202 * @brief Rx Transfer half completed callbacks 01203 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01204 * the configuration information for I2S module 01205 * @retval None 01206 */ 01207 __weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s) 01208 { 01209 /* Prevent unused argument(s) compilation warning */ 01210 UNUSED(hi2s); 01211 /* NOTE : This function Should not be modified, when the callback is needed, 01212 the HAL_I2S_RxCpltCallback could be implemented in the user file 01213 */ 01214 } 01215 01216 /** 01217 * @brief Rx Transfer completed callbacks 01218 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01219 * the configuration information for I2S module 01220 * @retval None 01221 */ 01222 __weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s) 01223 { 01224 /* Prevent unused argument(s) compilation warning */ 01225 UNUSED(hi2s); 01226 /* NOTE : This function Should not be modified, when the callback is needed, 01227 the HAL_I2S_RxCpltCallback could be implemented in the user file 01228 */ 01229 } 01230 01231 /** 01232 * @brief I2S error callbacks 01233 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01234 * the configuration information for I2S module 01235 * @retval None 01236 */ 01237 __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s) 01238 { 01239 /* Prevent unused argument(s) compilation warning */ 01240 UNUSED(hi2s); 01241 /* NOTE : This function Should not be modified, when the callback is needed, 01242 the HAL_I2S_ErrorCallback could be implemented in the user file 01243 */ 01244 } 01245 01246 /** 01247 * @} 01248 */ 01249 01250 /** @addtogroup I2S_Exported_Functions_Group3 01251 * @brief Peripheral State functions 01252 * 01253 @verbatim 01254 =============================================================================== 01255 ##### Peripheral State and Errors functions ##### 01256 =============================================================================== 01257 [..] 01258 This subsection permits to get in run-time the status of the peripheral 01259 and the data flow. 01260 01261 @endverbatim 01262 * @{ 01263 */ 01264 01265 /** 01266 * @brief Return the I2S state 01267 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01268 * the configuration information for I2S module 01269 * @retval HAL state 01270 */ 01271 HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s) 01272 { 01273 return hi2s->State; 01274 } 01275 01276 /** 01277 * @brief Return the I2S error code 01278 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01279 * the configuration information for I2S module 01280 * @retval I2S Error Code 01281 */ 01282 uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s) 01283 { 01284 return hi2s->ErrorCode; 01285 } 01286 /** 01287 * @} 01288 */ 01289 01290 /** 01291 * @} 01292 */ 01293 01294 /** @addtogroup I2S_Private_Functions I2S Private Functions 01295 * @{ 01296 */ 01297 /** 01298 * @brief DMA I2S transmit process complete callback 01299 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01300 * the configuration information for the specified DMA module. 01301 * @retval None 01302 */ 01303 static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma) 01304 { 01305 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01306 01307 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 01308 { 01309 /* Disable Tx DMA Request */ 01310 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_TXDMAEN); 01311 01312 hi2s->TxXferCount = 0U; 01313 hi2s->State = HAL_I2S_STATE_READY; 01314 } 01315 HAL_I2S_TxCpltCallback(hi2s); 01316 } 01317 /** 01318 * @brief DMA I2S transmit process half complete callback 01319 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01320 * the configuration information for the specified DMA module. 01321 * @retval None 01322 */ 01323 static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma) 01324 { 01325 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; 01326 01327 HAL_I2S_TxHalfCpltCallback(hi2s); 01328 } 01329 01330 /** 01331 * @brief DMA I2S receive process complete callback 01332 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01333 * the configuration information for the specified DMA module. 01334 * @retval None 01335 */ 01336 static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma) 01337 { 01338 I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01339 01340 if((hdma->Instance->CR & DMA_SxCR_CIRC) == 0U) 01341 { 01342 /* Disable Rx DMA Request */ 01343 CLEAR_BIT(hi2s->Instance->CR2,SPI_CR2_RXDMAEN); 01344 hi2s->RxXferCount = 0U; 01345 hi2s->State = HAL_I2S_STATE_READY; 01346 } 01347 HAL_I2S_RxCpltCallback(hi2s); 01348 } 01349 01350 /** 01351 * @brief DMA I2S receive process half complete callback 01352 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01353 * the configuration information for the specified DMA module. 01354 * @retval None 01355 */ 01356 static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma) 01357 { 01358 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; 01359 01360 HAL_I2S_RxHalfCpltCallback(hi2s); 01361 } 01362 01363 /** 01364 * @brief DMA I2S communication error callback 01365 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01366 * the configuration information for the specified DMA module. 01367 * @retval None 01368 */ 01369 static void I2S_DMAError(DMA_HandleTypeDef *hdma) 01370 { 01371 I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent; 01372 01373 /* Disable Rx and Tx DMA Request */ 01374 CLEAR_BIT(hi2s->Instance->CR2,(SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN)); 01375 hi2s->TxXferCount = 0U; 01376 hi2s->RxXferCount = 0U; 01377 01378 hi2s->State= HAL_I2S_STATE_READY; 01379 01380 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_DMA); 01381 HAL_I2S_ErrorCallback(hi2s); 01382 } 01383 01384 /** 01385 * @brief Transmit an amount of data in non-blocking mode with Interrupt 01386 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01387 * the configuration information for I2S module 01388 * @retval HAL status 01389 */ 01390 static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s) 01391 { 01392 /* Transmit data */ 01393 hi2s->Instance->DR = (*hi2s->pTxBuffPtr++); 01394 hi2s->TxXferCount--; 01395 01396 if(hi2s->TxXferCount == 0U) 01397 { 01398 /* Disable TXE and ERR interrupt */ 01399 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); 01400 01401 hi2s->State = HAL_I2S_STATE_READY; 01402 HAL_I2S_TxCpltCallback(hi2s); 01403 } 01404 } 01405 01406 /** 01407 * @brief Receive an amount of data in non-blocking mode with Interrupt 01408 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01409 * the configuration information for I2S module 01410 * @retval HAL status 01411 */ 01412 static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s) 01413 { 01414 /* Receive data */ 01415 (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR; 01416 hi2s->RxXferCount--; 01417 01418 if(hi2s->RxXferCount == 0U) 01419 { 01420 /* Disable RXNE and ERR interrupt */ 01421 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); 01422 01423 hi2s->State = HAL_I2S_STATE_READY; 01424 HAL_I2S_RxCpltCallback(hi2s); 01425 } 01426 } 01427 01428 /** 01429 * @brief This function handles I2S interrupt request. 01430 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01431 * the configuration information for I2S module 01432 * @retval None 01433 */ 01434 static void I2S_IRQHandler(I2S_HandleTypeDef *hi2s) 01435 { 01436 __IO uint32_t i2ssr = hi2s->Instance->SR; 01437 01438 if(hi2s->State == HAL_I2S_STATE_BUSY_RX) 01439 { 01440 /* I2S in mode Receiver ------------------------------------------------*/ 01441 if(((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET)) 01442 { 01443 I2S_Receive_IT(hi2s); 01444 } 01445 01446 /* I2S Overrun error interrupt occured -------------------------------------*/ 01447 if(((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) 01448 { 01449 /* Disable RXNE and ERR interrupt */ 01450 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR)); 01451 01452 /* Clear Overrun flag */ 01453 __HAL_I2S_CLEAR_OVRFLAG(hi2s); 01454 01455 /* Set the I2S State ready */ 01456 hi2s->State = HAL_I2S_STATE_READY; 01457 01458 01459 /* Set the error code and execute error callback*/ 01460 SET_BIT(hi2s->ErrorCode,HAL_I2S_ERROR_OVR); 01461 HAL_I2S_ErrorCallback(hi2s); 01462 } 01463 } 01464 01465 if(hi2s->State == HAL_I2S_STATE_BUSY_TX) 01466 { 01467 /* I2S in mode Transmitter -----------------------------------------------*/ 01468 if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET)) 01469 { 01470 I2S_Transmit_IT(hi2s); 01471 } 01472 01473 /* I2S Underrun error interrupt occurred --------------------------------*/ 01474 if(((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)) 01475 { 01476 /* Disable TXE and ERR interrupt */ 01477 __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR)); 01478 01479 /* Clear Underrun flag */ 01480 __HAL_I2S_CLEAR_UDRFLAG(hi2s); 01481 01482 /* Set the I2S State ready */ 01483 hi2s->State = HAL_I2S_STATE_READY; 01484 01485 /* Set the error code and execute error callback*/ 01486 SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR); 01487 HAL_I2S_ErrorCallback(hi2s); 01488 } 01489 } 01490 } 01491 01492 /** 01493 * @brief This function handles I2S Communication Timeout. 01494 * @param hi2s pointer to a I2S_HandleTypeDef structure that contains 01495 * the configuration information for I2S module 01496 * @param Flag Flag checked 01497 * @param State Value of the flag expected 01498 * @param Timeout Duration of the timeout 01499 * @retval HAL status 01500 */ 01501 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, 01502 uint32_t Timeout) 01503 { 01504 uint32_t tickstart = HAL_GetTick(); 01505 01506 /* Wait until flag is set to status*/ 01507 while(((__HAL_I2S_GET_FLAG(hi2s, Flag)) ? SET : RESET) != State) 01508 { 01509 if(Timeout != HAL_MAX_DELAY) 01510 { 01511 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) 01512 { 01513 /* Set the I2S State ready */ 01514 hi2s->State = HAL_I2S_STATE_READY; 01515 01516 /* Process Unlocked */ 01517 __HAL_UNLOCK(hi2s); 01518 01519 return HAL_TIMEOUT; 01520 } 01521 } 01522 } 01523 return HAL_OK; 01524 } 01525 01526 /** 01527 * @} 01528 */ 01529 01530 /** 01531 * @} 01532 */ 01533 01534 #endif /* HAL_I2S_MODULE_ENABLED */ 01535 /** 01536 * @} 01537 */ 01538 01539 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/