00001
00029
00030 #ifndef __STM32F4xx_TIM_H
00031 #define __STM32F4xx_TIM_H
00032
00033 #ifdef __cplusplus
00034 extern "C" {
00035 #endif
00036
00037
00038 #include "stm32f4xx.h"
00039
00048
00049
00055 typedef struct
00056 {
00057 uint16_t TIM_Prescaler;
00060 uint16_t TIM_CounterMode;
00063 uint32_t TIM_Period;
00067 uint16_t TIM_ClockDivision;
00070 uint8_t TIM_RepetitionCounter;
00078 } TIM_TimeBaseInitTypeDef;
00079
00084 typedef struct
00085 {
00086 uint16_t TIM_OCMode;
00089 uint16_t TIM_OutputState;
00092 uint16_t TIM_OutputNState;
00096 uint32_t TIM_Pulse;
00099 uint16_t TIM_OCPolarity;
00102 uint16_t TIM_OCNPolarity;
00106 uint16_t TIM_OCIdleState;
00110 uint16_t TIM_OCNIdleState;
00113 } TIM_OCInitTypeDef;
00114
00119 typedef struct
00120 {
00121
00122 uint16_t TIM_Channel;
00125 uint16_t TIM_ICPolarity;
00128 uint16_t TIM_ICSelection;
00131 uint16_t TIM_ICPrescaler;
00134 uint16_t TIM_ICFilter;
00136 } TIM_ICInitTypeDef;
00137
00143 typedef struct
00144 {
00145
00146 uint16_t TIM_OSSRState;
00149 uint16_t TIM_OSSIState;
00152 uint16_t TIM_LOCKLevel;
00155 uint16_t TIM_DeadTime;
00159 uint16_t TIM_Break;
00162 uint16_t TIM_BreakPolarity;
00165 uint16_t TIM_AutomaticOutput;
00167 } TIM_BDTRInitTypeDef;
00168
00169
00170
00175 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00176 ((PERIPH) == TIM2) || \
00177 ((PERIPH) == TIM3) || \
00178 ((PERIPH) == TIM4) || \
00179 ((PERIPH) == TIM5) || \
00180 ((PERIPH) == TIM6) || \
00181 ((PERIPH) == TIM7) || \
00182 ((PERIPH) == TIM8) || \
00183 ((PERIPH) == TIM9) || \
00184 ((PERIPH) == TIM10) || \
00185 ((PERIPH) == TIM11) || \
00186 ((PERIPH) == TIM12) || \
00187 (((PERIPH) == TIM13) || \
00188 ((PERIPH) == TIM14)))
00189
00190 #define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00191 ((PERIPH) == TIM2) || \
00192 ((PERIPH) == TIM3) || \
00193 ((PERIPH) == TIM4) || \
00194 ((PERIPH) == TIM5) || \
00195 ((PERIPH) == TIM8) || \
00196 ((PERIPH) == TIM9) || \
00197 ((PERIPH) == TIM10) || \
00198 ((PERIPH) == TIM11) || \
00199 ((PERIPH) == TIM12) || \
00200 ((PERIPH) == TIM13) || \
00201 ((PERIPH) == TIM14))
00202
00203
00204 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00205 ((PERIPH) == TIM2) || \
00206 ((PERIPH) == TIM3) || \
00207 ((PERIPH) == TIM4) || \
00208 ((PERIPH) == TIM5) || \
00209 ((PERIPH) == TIM8) || \
00210 ((PERIPH) == TIM9) || \
00211 ((PERIPH) == TIM12))
00212
00213 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00214 ((PERIPH) == TIM2) || \
00215 ((PERIPH) == TIM3) || \
00216 ((PERIPH) == TIM4) || \
00217 ((PERIPH) == TIM5) || \
00218 ((PERIPH) == TIM8))
00219
00220 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00221 ((PERIPH) == TIM8))
00222
00223 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
00224 ((PERIPH) == TIM2) || \
00225 ((PERIPH) == TIM3) || \
00226 ((PERIPH) == TIM4) || \
00227 ((PERIPH) == TIM5) || \
00228 ((PERIPH) == TIM6) || \
00229 ((PERIPH) == TIM7) || \
00230 ((PERIPH) == TIM8))
00231
00232 #define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \
00233 ((TIMx) == TIM5) || \
00234 ((TIMx) == TIM11))
00235
00240 #define TIM_OCMode_Timing ((uint16_t)0x0000)
00241 #define TIM_OCMode_Active ((uint16_t)0x0010)
00242 #define TIM_OCMode_Inactive ((uint16_t)0x0020)
00243 #define TIM_OCMode_Toggle ((uint16_t)0x0030)
00244 #define TIM_OCMode_PWM1 ((uint16_t)0x0060)
00245 #define TIM_OCMode_PWM2 ((uint16_t)0x0070)
00246 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
00247 ((MODE) == TIM_OCMode_Active) || \
00248 ((MODE) == TIM_OCMode_Inactive) || \
00249 ((MODE) == TIM_OCMode_Toggle)|| \
00250 ((MODE) == TIM_OCMode_PWM1) || \
00251 ((MODE) == TIM_OCMode_PWM2))
00252 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
00253 ((MODE) == TIM_OCMode_Active) || \
00254 ((MODE) == TIM_OCMode_Inactive) || \
00255 ((MODE) == TIM_OCMode_Toggle)|| \
00256 ((MODE) == TIM_OCMode_PWM1) || \
00257 ((MODE) == TIM_OCMode_PWM2) || \
00258 ((MODE) == TIM_ForcedAction_Active) || \
00259 ((MODE) == TIM_ForcedAction_InActive))
00260
00268 #define TIM_OPMode_Single ((uint16_t)0x0008)
00269 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
00270 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
00271 ((MODE) == TIM_OPMode_Repetitive))
00272
00280 #define TIM_Channel_1 ((uint16_t)0x0000)
00281 #define TIM_Channel_2 ((uint16_t)0x0004)
00282 #define TIM_Channel_3 ((uint16_t)0x0008)
00283 #define TIM_Channel_4 ((uint16_t)0x000C)
00284
00285 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00286 ((CHANNEL) == TIM_Channel_2) || \
00287 ((CHANNEL) == TIM_Channel_3) || \
00288 ((CHANNEL) == TIM_Channel_4))
00289
00290 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00291 ((CHANNEL) == TIM_Channel_2))
00292 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
00293 ((CHANNEL) == TIM_Channel_2) || \
00294 ((CHANNEL) == TIM_Channel_3))
00295
00303 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
00304 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
00305 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
00306 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
00307 ((DIV) == TIM_CKD_DIV2) || \
00308 ((DIV) == TIM_CKD_DIV4))
00309
00317 #define TIM_CounterMode_Up ((uint16_t)0x0000)
00318 #define TIM_CounterMode_Down ((uint16_t)0x0010)
00319 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
00320 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
00321 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
00322 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
00323 ((MODE) == TIM_CounterMode_Down) || \
00324 ((MODE) == TIM_CounterMode_CenterAligned1) || \
00325 ((MODE) == TIM_CounterMode_CenterAligned2) || \
00326 ((MODE) == TIM_CounterMode_CenterAligned3))
00327
00335 #define TIM_OCPolarity_High ((uint16_t)0x0000)
00336 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
00337 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
00338 ((POLARITY) == TIM_OCPolarity_Low))
00339
00347 #define TIM_OCNPolarity_High ((uint16_t)0x0000)
00348 #define TIM_OCNPolarity_Low ((uint16_t)0x0008)
00349 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
00350 ((POLARITY) == TIM_OCNPolarity_Low))
00351
00359 #define TIM_OutputState_Disable ((uint16_t)0x0000)
00360 #define TIM_OutputState_Enable ((uint16_t)0x0001)
00361 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
00362 ((STATE) == TIM_OutputState_Enable))
00363
00371 #define TIM_OutputNState_Disable ((uint16_t)0x0000)
00372 #define TIM_OutputNState_Enable ((uint16_t)0x0004)
00373 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
00374 ((STATE) == TIM_OutputNState_Enable))
00375
00383 #define TIM_CCx_Enable ((uint16_t)0x0001)
00384 #define TIM_CCx_Disable ((uint16_t)0x0000)
00385 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
00386 ((CCX) == TIM_CCx_Disable))
00387
00395 #define TIM_CCxN_Enable ((uint16_t)0x0004)
00396 #define TIM_CCxN_Disable ((uint16_t)0x0000)
00397 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
00398 ((CCXN) == TIM_CCxN_Disable))
00399
00407 #define TIM_Break_Enable ((uint16_t)0x1000)
00408 #define TIM_Break_Disable ((uint16_t)0x0000)
00409 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
00410 ((STATE) == TIM_Break_Disable))
00411
00419 #define TIM_BreakPolarity_Low ((uint16_t)0x0000)
00420 #define TIM_BreakPolarity_High ((uint16_t)0x2000)
00421 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
00422 ((POLARITY) == TIM_BreakPolarity_High))
00423
00431 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
00432 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
00433 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
00434 ((STATE) == TIM_AutomaticOutput_Disable))
00435
00443 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
00444 #define TIM_LOCKLevel_1 ((uint16_t)0x0100)
00445 #define TIM_LOCKLevel_2 ((uint16_t)0x0200)
00446 #define TIM_LOCKLevel_3 ((uint16_t)0x0300)
00447 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
00448 ((LEVEL) == TIM_LOCKLevel_1) || \
00449 ((LEVEL) == TIM_LOCKLevel_2) || \
00450 ((LEVEL) == TIM_LOCKLevel_3))
00451
00459 #define TIM_OSSIState_Enable ((uint16_t)0x0400)
00460 #define TIM_OSSIState_Disable ((uint16_t)0x0000)
00461 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
00462 ((STATE) == TIM_OSSIState_Disable))
00463
00471 #define TIM_OSSRState_Enable ((uint16_t)0x0800)
00472 #define TIM_OSSRState_Disable ((uint16_t)0x0000)
00473 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
00474 ((STATE) == TIM_OSSRState_Disable))
00475
00483 #define TIM_OCIdleState_Set ((uint16_t)0x0100)
00484 #define TIM_OCIdleState_Reset ((uint16_t)0x0000)
00485 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
00486 ((STATE) == TIM_OCIdleState_Reset))
00487
00495 #define TIM_OCNIdleState_Set ((uint16_t)0x0200)
00496 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
00497 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
00498 ((STATE) == TIM_OCNIdleState_Reset))
00499
00507 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
00508 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
00509 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
00510 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
00511 ((POLARITY) == TIM_ICPolarity_Falling)|| \
00512 ((POLARITY) == TIM_ICPolarity_BothEdge))
00513
00521 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001)
00523 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
00525 #define TIM_ICSelection_TRC ((uint16_t)0x0003)
00526 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
00527 ((SELECTION) == TIM_ICSelection_IndirectTI) || \
00528 ((SELECTION) == TIM_ICSelection_TRC))
00529
00537 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000)
00538 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004)
00539 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008)
00540 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C)
00541 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
00542 ((PRESCALER) == TIM_ICPSC_DIV2) || \
00543 ((PRESCALER) == TIM_ICPSC_DIV4) || \
00544 ((PRESCALER) == TIM_ICPSC_DIV8))
00545
00553 #define TIM_IT_Update ((uint16_t)0x0001)
00554 #define TIM_IT_CC1 ((uint16_t)0x0002)
00555 #define TIM_IT_CC2 ((uint16_t)0x0004)
00556 #define TIM_IT_CC3 ((uint16_t)0x0008)
00557 #define TIM_IT_CC4 ((uint16_t)0x0010)
00558 #define TIM_IT_COM ((uint16_t)0x0020)
00559 #define TIM_IT_Trigger ((uint16_t)0x0040)
00560 #define TIM_IT_Break ((uint16_t)0x0080)
00561 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
00562
00563 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
00564 ((IT) == TIM_IT_CC1) || \
00565 ((IT) == TIM_IT_CC2) || \
00566 ((IT) == TIM_IT_CC3) || \
00567 ((IT) == TIM_IT_CC4) || \
00568 ((IT) == TIM_IT_COM) || \
00569 ((IT) == TIM_IT_Trigger) || \
00570 ((IT) == TIM_IT_Break))
00571
00579 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
00580 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
00581 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
00582 #define TIM_DMABase_DIER ((uint16_t)0x0003)
00583 #define TIM_DMABase_SR ((uint16_t)0x0004)
00584 #define TIM_DMABase_EGR ((uint16_t)0x0005)
00585 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
00586 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
00587 #define TIM_DMABase_CCER ((uint16_t)0x0008)
00588 #define TIM_DMABase_CNT ((uint16_t)0x0009)
00589 #define TIM_DMABase_PSC ((uint16_t)0x000A)
00590 #define TIM_DMABase_ARR ((uint16_t)0x000B)
00591 #define TIM_DMABase_RCR ((uint16_t)0x000C)
00592 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
00593 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
00594 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
00595 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
00596 #define TIM_DMABase_BDTR ((uint16_t)0x0011)
00597 #define TIM_DMABase_DCR ((uint16_t)0x0012)
00598 #define TIM_DMABase_OR ((uint16_t)0x0013)
00599 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
00600 ((BASE) == TIM_DMABase_CR2) || \
00601 ((BASE) == TIM_DMABase_SMCR) || \
00602 ((BASE) == TIM_DMABase_DIER) || \
00603 ((BASE) == TIM_DMABase_SR) || \
00604 ((BASE) == TIM_DMABase_EGR) || \
00605 ((BASE) == TIM_DMABase_CCMR1) || \
00606 ((BASE) == TIM_DMABase_CCMR2) || \
00607 ((BASE) == TIM_DMABase_CCER) || \
00608 ((BASE) == TIM_DMABase_CNT) || \
00609 ((BASE) == TIM_DMABase_PSC) || \
00610 ((BASE) == TIM_DMABase_ARR) || \
00611 ((BASE) == TIM_DMABase_RCR) || \
00612 ((BASE) == TIM_DMABase_CCR1) || \
00613 ((BASE) == TIM_DMABase_CCR2) || \
00614 ((BASE) == TIM_DMABase_CCR3) || \
00615 ((BASE) == TIM_DMABase_CCR4) || \
00616 ((BASE) == TIM_DMABase_BDTR) || \
00617 ((BASE) == TIM_DMABase_DCR) || \
00618 ((BASE) == TIM_DMABase_OR))
00619
00627 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
00628 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
00629 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
00630 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
00631 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
00632 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
00633 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
00634 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
00635 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
00636 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
00637 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
00638 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
00639 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
00640 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
00641 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
00642 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
00643 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
00644 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
00645 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
00646 ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
00647 ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
00648 ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
00649 ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
00650 ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
00651 ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
00652 ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
00653 ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
00654 ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
00655 ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
00656 ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
00657 ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
00658 ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
00659 ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
00660 ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
00661 ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
00662 ((LENGTH) == TIM_DMABurstLength_18Transfers))
00663
00671 #define TIM_DMA_Update ((uint16_t)0x0100)
00672 #define TIM_DMA_CC1 ((uint16_t)0x0200)
00673 #define TIM_DMA_CC2 ((uint16_t)0x0400)
00674 #define TIM_DMA_CC3 ((uint16_t)0x0800)
00675 #define TIM_DMA_CC4 ((uint16_t)0x1000)
00676 #define TIM_DMA_COM ((uint16_t)0x2000)
00677 #define TIM_DMA_Trigger ((uint16_t)0x4000)
00678 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
00679
00688 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
00689 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
00690 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
00691 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
00692 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
00693 ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
00694 ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
00695 ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
00696
00704 #define TIM_TS_ITR0 ((uint16_t)0x0000)
00705 #define TIM_TS_ITR1 ((uint16_t)0x0010)
00706 #define TIM_TS_ITR2 ((uint16_t)0x0020)
00707 #define TIM_TS_ITR3 ((uint16_t)0x0030)
00708 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
00709 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
00710 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
00711 #define TIM_TS_ETRF ((uint16_t)0x0070)
00712 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
00713 ((SELECTION) == TIM_TS_ITR1) || \
00714 ((SELECTION) == TIM_TS_ITR2) || \
00715 ((SELECTION) == TIM_TS_ITR3) || \
00716 ((SELECTION) == TIM_TS_TI1F_ED) || \
00717 ((SELECTION) == TIM_TS_TI1FP1) || \
00718 ((SELECTION) == TIM_TS_TI2FP2) || \
00719 ((SELECTION) == TIM_TS_ETRF))
00720 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
00721 ((SELECTION) == TIM_TS_ITR1) || \
00722 ((SELECTION) == TIM_TS_ITR2) || \
00723 ((SELECTION) == TIM_TS_ITR3))
00724
00732 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
00733 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
00734 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
00735
00743 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
00744 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
00745 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
00746 ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
00747
00755 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
00756 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
00757 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
00758 ((RELOAD) == TIM_PSCReloadMode_Immediate))
00759
00767 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
00768 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
00769 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
00770 ((ACTION) == TIM_ForcedAction_InActive))
00771
00779 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
00780 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
00781 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
00782 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
00783 ((MODE) == TIM_EncoderMode_TI2) || \
00784 ((MODE) == TIM_EncoderMode_TI12))
00785
00794 #define TIM_EventSource_Update ((uint16_t)0x0001)
00795 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
00796 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
00797 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
00798 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
00799 #define TIM_EventSource_COM ((uint16_t)0x0020)
00800 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
00801 #define TIM_EventSource_Break ((uint16_t)0x0080)
00802 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
00803
00812 #define TIM_UpdateSource_Global ((uint16_t)0x0000)
00815 #define TIM_UpdateSource_Regular ((uint16_t)0x0001)
00816 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
00817 ((SOURCE) == TIM_UpdateSource_Regular))
00818
00826 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
00827 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
00828 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
00829 ((STATE) == TIM_OCPreload_Disable))
00830
00838 #define TIM_OCFast_Enable ((uint16_t)0x0004)
00839 #define TIM_OCFast_Disable ((uint16_t)0x0000)
00840 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
00841 ((STATE) == TIM_OCFast_Disable))
00842
00851 #define TIM_OCClear_Enable ((uint16_t)0x0080)
00852 #define TIM_OCClear_Disable ((uint16_t)0x0000)
00853 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
00854 ((STATE) == TIM_OCClear_Disable))
00855
00863 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
00864 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
00865 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
00866 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
00867 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
00868 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
00869 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
00870 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
00871 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
00872 ((SOURCE) == TIM_TRGOSource_Enable) || \
00873 ((SOURCE) == TIM_TRGOSource_Update) || \
00874 ((SOURCE) == TIM_TRGOSource_OC1) || \
00875 ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
00876 ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
00877 ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
00878 ((SOURCE) == TIM_TRGOSource_OC4Ref))
00879
00887 #define TIM_SlaveMode_Reset ((uint16_t)0x0004)
00888 #define TIM_SlaveMode_Gated ((uint16_t)0x0005)
00889 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
00890 #define TIM_SlaveMode_External1 ((uint16_t)0x0007)
00891 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
00892 ((MODE) == TIM_SlaveMode_Gated) || \
00893 ((MODE) == TIM_SlaveMode_Trigger) || \
00894 ((MODE) == TIM_SlaveMode_External1))
00895
00903 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
00904 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
00905 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
00906 ((STATE) == TIM_MasterSlaveMode_Disable))
00907
00914 #define TIM2_TIM8_TRGO ((uint16_t)0x0000)
00915 #define TIM2_ETH_PTP ((uint16_t)0x0400)
00916 #define TIM2_USBFS_SOF ((uint16_t)0x0800)
00917 #define TIM2_USBHS_SOF ((uint16_t)0x0C00)
00918
00919 #define TIM5_GPIO ((uint16_t)0x0000)
00920 #define TIM5_LSI ((uint16_t)0x0040)
00921 #define TIM5_LSE ((uint16_t)0x0080)
00922 #define TIM5_RTC ((uint16_t)0x00C0)
00923
00924 #define TIM11_GPIO ((uint16_t)0x0000)
00925 #define TIM11_HSE ((uint16_t)0x0002)
00926
00927 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
00928 ((TIM_REMAP) == TIM2_ETH_PTP)||\
00929 ((TIM_REMAP) == TIM2_USBFS_SOF)||\
00930 ((TIM_REMAP) == TIM2_USBHS_SOF)||\
00931 ((TIM_REMAP) == TIM5_GPIO)||\
00932 ((TIM_REMAP) == TIM5_LSI)||\
00933 ((TIM_REMAP) == TIM5_LSE)||\
00934 ((TIM_REMAP) == TIM5_RTC)||\
00935 ((TIM_REMAP) == TIM11_GPIO)||\
00936 ((TIM_REMAP) == TIM11_HSE))
00937
00945 #define TIM_FLAG_Update ((uint16_t)0x0001)
00946 #define TIM_FLAG_CC1 ((uint16_t)0x0002)
00947 #define TIM_FLAG_CC2 ((uint16_t)0x0004)
00948 #define TIM_FLAG_CC3 ((uint16_t)0x0008)
00949 #define TIM_FLAG_CC4 ((uint16_t)0x0010)
00950 #define TIM_FLAG_COM ((uint16_t)0x0020)
00951 #define TIM_FLAG_Trigger ((uint16_t)0x0040)
00952 #define TIM_FLAG_Break ((uint16_t)0x0080)
00953 #define TIM_FLAG_CC1OF ((uint16_t)0x0200)
00954 #define TIM_FLAG_CC2OF ((uint16_t)0x0400)
00955 #define TIM_FLAG_CC3OF ((uint16_t)0x0800)
00956 #define TIM_FLAG_CC4OF ((uint16_t)0x1000)
00957 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
00958 ((FLAG) == TIM_FLAG_CC1) || \
00959 ((FLAG) == TIM_FLAG_CC2) || \
00960 ((FLAG) == TIM_FLAG_CC3) || \
00961 ((FLAG) == TIM_FLAG_CC4) || \
00962 ((FLAG) == TIM_FLAG_COM) || \
00963 ((FLAG) == TIM_FLAG_Trigger) || \
00964 ((FLAG) == TIM_FLAG_Break) || \
00965 ((FLAG) == TIM_FLAG_CC1OF) || \
00966 ((FLAG) == TIM_FLAG_CC2OF) || \
00967 ((FLAG) == TIM_FLAG_CC3OF) || \
00968 ((FLAG) == TIM_FLAG_CC4OF))
00969
00978 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
00979
00987 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
00988
00996 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
00997 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
00998 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
00999 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
01000 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
01001 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
01002 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
01003 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
01004 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
01005 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
01006 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
01007 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
01008 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
01009 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
01010 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
01011 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
01012 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
01013 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
01014
01022
01023
01024
01025
01026 void TIM_DeInit(TIM_TypeDef* TIMx);
01027 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
01028 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
01029 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
01030 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
01031 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
01032 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
01033 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
01034 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
01035 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
01036 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
01037 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
01038 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
01039 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
01040 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
01041
01042
01043 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01044 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01045 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01046 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
01047 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
01048 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
01049 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
01050 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
01051 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
01052 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
01053 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01054 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01055 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01056 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
01057 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01058 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01059 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01060 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
01061 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01062 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01063 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01064 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
01065 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01066 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01067 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01068 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
01069 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01070 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
01071 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01072 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
01073 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01074 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
01075 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
01076 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
01077 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
01078
01079
01080 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
01081 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
01082 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
01083 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
01084 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
01085 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
01086 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
01087 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01088 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01089 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01090 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
01091
01092
01093 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
01094 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
01095 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
01096 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
01097 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
01098
01099
01100 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
01101 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
01102 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
01103 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
01104 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
01105 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
01106 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
01107 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
01108 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
01109
01110
01111 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
01112 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
01113 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
01114 uint16_t TIM_ICPolarity, uint16_t ICFilter);
01115 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
01116 uint16_t ExtTRGFilter);
01117 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
01118 uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
01119
01120
01121 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
01122 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
01123 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
01124 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
01125 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
01126 uint16_t ExtTRGFilter);
01127
01128
01129 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
01130 uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
01131 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
01132
01133
01134 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
01135
01136 #ifdef __cplusplus
01137 }
01138 #endif
01139
01140 #endif
01141
01150