Cache Memory

• Francisco Candel, Salvador Petit, Julio Sahuquillo, José Duato : Accurately modeling the GPU memory subsystem. HPCS 2015: 179-186
• Alejandro Valero, Julio Sahuquillo, Salvador Petit, Pedro López, José Duato: Design of Hybrid Second-Level Caches. IEEE Trans. Computers 64(7): 1884-1897 (2015)
• V. Lorente, A. Valero, S. Petit, P. Foglia, J. Sahuquillo: Analyzing the Optimal Voltage/Frequency Pair in Fault-Tolerant Caches. HPCC/CSS/ICESS 2014
• A. Valero, S. Petit, J. Sahuquillo, D.R. Kaeli, José Duato: A reuse-based refresh policy for energy-aware eDRAM caches. Microprocessors and Microsystems - Embedded Hardware Design 39(1): (2015)
• A. Valero, S. Petit, J. Sahuquillo, P. López, J. Duato: Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches. IEEE Trans. Computers 61(9): (2012)
• A. Valero, J. Sahuquillo, V. Lorente, S. Petit, P. López, J. Duato: Impact on Performance and Energy of the Retention Time and Processor Frequency in L1 Macrocell-Based Data Caches. IEEE Trans. VLSI Syst. 20(6): (2012)
• A. Valero, J. Sahuquillo, S. Petit, P. López, J. Duato: Combining recency of information with selective random and a victim cache in last-level caches. TACO 9(3): (2012)
• J. Sahuquillo, S. Petit, A. Pont, V. Milutinovic: Exploring the performance of split data cache schemes on superscalar processors and symmetric multiprocessors. Journal of Systems Architecture 51(8): (2005)
• A. Valero, J. Sahuquillo, S. Petit, V. Lorente, R. Canal, P. López, J. Duato: An hybrid eDRAM/SRAM macrocell to implement first-level data caches. MICRO 2009
• A. Valero, J. Sahuquillo, S. Petit, P. López, J. Duato: Improving Last-Level Cache Performance by Exploiting the Concept of MRU-Tour. PACT 2011
• A. Valero, J. Sahuquillo, S. Petit, J. Duato: Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches. ICS 2013
• A. Valero, J. Sahuquillo, S. Petit, P. López, J. Duato: Analyzing the optimal ratio of SRAM banks in hybrid caches. ICCD 2012
• R. Ubal, J. Sahuquillo, S. Petit, P. López: Applying the zeros switch-off technique to reduce static energy in data caches. SBAC-PAD 2006
• A. Valero, J. Sahuquillo, S. Petit, P. López, J. Duato: MRU-Tour-based Replacement Algorithms for Last-Level Caches. SBAC-PAD 2011
• V. Lorente, A. Valero, J. Sahuquillo, S. Petit, R. Canal, P. López, J. Duato: Combining RAM technologies for hard-error recovery in L1 data caches working at very-low power modes. DATE 2013
• J. Feliu, J. Sahuquillo, S. Petit, J. Duato: Using Huge Pages and Performance Counters to Determine the LLC Architecture. ICCS 2013
• S. Petit, J. Sahuquillo, J.M. Such, D. Kaeli: Exploiting temporal locality in drowsy cache policies. Conf. Computing Frontiers 2005
• R. Ubal, J. Sahuquillo, S. Petit, H. Hassan, P. López: Leakage Current Reduction in Data Caches on Embedded Systems. IPC 2007
• J. Sahuquillo, A. Pont, S. Petit, V. Milutinovic: A Comparison Study of Data Cache Schemes Exploiting Reuse Information in Multiprocessor Systems. WC3 2001
• A. Valero, J. Sahuquillo, S. Petit, P. López, J. Duato: Combining Technologies to Reduce Energy in L1 Data Caches. ACACES 2011
• J. Sahuquillo, S. Petit, A. Pont. V. Milutinovic: Performance Study of the Filter Data Cache on a Superscalar Processor Architecture. IEEE TCCA Newsletter: (2001)

Processor Microarchitecture

• S. Petit, R. Ubal, J. Sahuquillo, P. López: Efficient Register Renaming and Recovery for High-Performance Processors. IEEE Trans. VLSI Syst. 22(7): (2014)
• S. Petit, J. Sahuquillo, P. López, R. Ubal, J. Duato: A Complexity-Effective Out-of-Order Retirement Microarchitecture. IEEE Trans. Computers 58(12): (2009)
• R. Ubal, J. Sahuquillo, S. Petit, P. López, J. Duato: Hardware-Based Generation of Independent Subtraces of Instructions in Clustered Processors. IEEE Trans. Computers 62(5): (2013)
• R. Ubal, J. Sahuquillo, S. Petit, P. López, D. Kaeli: A Sequentially Consistent Multiprocessor Architecture for Out-of-Order Retirement of Instructions. IEEE Trans. Parallel Distrib. Syst. 23(8): (2012)
• R. Ubal, J. Sahuquillo, S. Petit, H. Hassan, P. López: Power Reduction in Advanced Embedded IPC Processors. Intelligent Automation and Soft Computing: (2009)
• R. Ubal, J. Sahuquillo, S. Petit, P. López, J. Duato: VB-MT: Design Issues and Performance of the Validation Buffer Microarchitecture for Multithreaded Processors. PACT 2007
• R. Ubal, J. Sahuquillo, S. Petit, P. López, J. Duato: Exploiting subtrace-level parallelism in clustered processors. PACT 2010
• R. Ubal, J. Sahuquillo, S. Petit, P. López, J. Duato: The impact of out-of-order commit in coarse-grain, fine-grain and simultaneous multithreaded architectures. IPDPS 2008
• S. Petit, R. Ubal, J. Sahuquillo, P. López: A power-aware hybrid RAM-CAM renaming mechanism for fast recovery. ICCD 2009
• R. Ubal, J. Sahuquillo, S. Petit, P. López, D. Kaeli: Out-of-order retirement of instructions in sequentially consistent multiprocessors. ICCD 2010
• R. Ubal, J. Sahuquillo, S. Petit, P. López: Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. SBAC-PAD 2007
• S. Petit, R. Ubal, J. Sahuquillo, P. López, J. Duato: An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. DSD 2009
• R. Ubal, J. Sahuquillo, S. Petit, P. López: Paired ROBs: A Cost-Effective Reorder Buffer Sharing Strategy for SMT Processors. Euro-Par 2009
• N. Tomás, J. Sahuquillo, S. Petit, P. López: Reducing the Number of Bits in the BTB to Attack the Branch Predictor Hot-Spot. Euro-Par 2008
• D. Yuste, J. Sahuquillo, S. Petit, P. López, J. Duato: Evaluating the Performance Potential of Function Level Parallelism. Interact 2008

Scheduling

• Josué Feliu, Julio Sahuquillo, Salvador Petit , José Duato : Addressing Fairness in SMT Multicores with a Progress-Aware Scheduler. IPDPS 2015: 187-196
• J. Feliu, S. Petit, J. Sahuquillo, J. Duato: Cache-hierarchy contention aware scheduling in CMPs. IEEE Trans. Parallel Distrib. Syst. 25(3): (2014)
• J. Feliu, J. Sahuquillo, S. Petit, J. Duato: Addressing bandwidth contention in SMT multicores through scheduling. ICS 2014
• M. Serrano, J. Sahuquillo, S. Petit, H. Hassan, J. Duato: A cost-effective heuristic to schedule local and remote memory in cluster computers. The Journal of Supercomputing 59(3): (2012)
• J. Feliu, S. Petit, J. Sahuquillo, J. Duato: L1-Bandwidth Aware Thread Allocation in Multicore SMT Processors. PACT 2013
• J. Feliu, J. Sahuquillo, S. Petit, J. Duato: Understanding Cache Hierarchy Contention in CMPs to Improve Job Scheduling. IPDPS 2012
• M. Serrano, S. Petit, J. Sahuquillo, R. Ubal, H. Hassan, J. Duato: Page-Based Memory Allocation Policies of Local and Remote Memory in Cluster Computers. ICPADS 2012
• M. Serrano, J. Sahuquillo, H. Hassan, S. Petit, J. Duato: A Cluster Computer Performance Predictor for Memory Scheduling. ICA3PP (2) 2011
• M. Serrano, J. Sahuquillo, H. Hassan, S. Petit, J. Duato: A Scheduling Heuristic to Handle Local and Remote Memory in Cluster Computers. HPCC 2010

Real-Time Systems

• J.L. March, S. Petit, J. Sahuquillo, H. Hassan, J. Duat Dynamic WCET Estimation for Real-Time Multicore Embedded Systems Supporting DVFS. HPCC/CSS/ICESS 2014
• J.L. March, J. Sahuquillo, S. Petit, H. Hassan, J. Duato: Power-aware scheduling with effective task migration for real-time multicore embedded systems. Concurrency and Computation: Practice and Experience 25(14): (2013)
• J.L. March, J. Sahuquillo, H. Hassan, S. Petit, J. Duato: A New Energy-Aware Dynamic Task Set Partitioning Algorithm for Soft and Hard Embedded Real-Time Systems. Comput. J. 54(8): (2011)
• J.L. March, J. Sahuquillo, S. Petit, J. Duato: Power-Aware Scheduling with Effective Task Migration for Real-Time Multicore Embedded Systems. Concurrency and Comp. Practice and Experience: 25(14): (2013)
• D. Bautista, J. Sahuquillo, H. Hassan, S. Petit, J. Duato: Dynamic task set partitioning based on balancing memory requirements to reduce power consumption. ICS 2009
• D. Bautista, J. Sahuquillo, H. Hassan, S. Petit, J. Duato: A simple power-aware scheduling for multicore systems when running real-time applications. IPDPS 2008
• J.L. March, S. Petit, J. Sahuquillo, H. Hassan, J. Duato: Efficiently Handling Memory Accesses to Improve QoS in Multicore Systems under Real-Time Constraints. SBAC-PAD 2012
• J.L. March, J. Sahuquillo, S. Petit, H. Hassan, J. Duato: A Dynamic Power-Aware Partitioner with Task Migration for Multicore Embedded Systems. Euro-Par (1) 2011
• J.L. March, J. Sahuquillo, H. Hassan, S. Petit, J. Duato: Extending a Multicore Multithread Simulator to Model Power-Aware Hard Real-Time Systems. ICA3PP (2) 2010
• D. Bautista, J. Sahuquillo, H. Hassan, S. Petit, J. Duato: Dynamic task set partitioning based on balancing resource requirements and utilization to reduce power consumption. SAC 2010
• D. Bautista, J. Sahuquillo, H. Hassan, S. Petit, J. Duato: Balancing Task Resource Requirements in Embedded Multithreaded Multicore Processors to Reduce Power Consumption. PDP 2010
• J.L. March, J. Sahuquillo, S. Petit, H. Hassan, J. Duato: How to Model Real-Time Task Constraints on a High-Performance Processor Simulator. ACACES 2011

Shared Virtual Memory

• S. Petit, J. Sahuquillo, A. Pont, D. Kaeli: Addressing a workload characterization study to the design of consistency protocols. The Journal of Supercomputing 38(1): (2006)
• S. Petit, J. Sahuquillo, A. Pont: About the sensitivity of the HLRC-DU protocol to the diff and page size. ISPASS 2001
• S. Petit, J. Sahuquillo, A. Pont, D. Kaeli: Characterizing the Dynamic Behavior of Workload Execution in SVM systems. SBAC-PAD 2004
• S. Petit, J. Sahuquillo, A. Pont: A Comparison Study of the HLRC-DU Protocol versus a HLRC Hardware Assisted Protocol. PDP 2005
• S. Petit, J. Sahuquillo, A. Pont: Characterizing Parallel Workloads to Reduce Multiple Writer Overhead in Shared Virtual Memory Systems. PDP 2002
• S. Petit, J. Sahuquillo, J.A. Donet, A. Pont: Detecting Spatial Locality to Improve SVM Consistency Protocols. SSGRR 2001
• S. Petit, J. Sahuquillo, A. Pont: Performance Evaluation of Consistency Models Using a New Simulation Environment for SVMS. WSDSM 2000
• S. Petit, J.A. Gil, J. Sahuquillo, A. Pont: LIDE: a simulation environment for shared virtual memory systems. SIGARCH Computer Architecture News 28(4): (2000)

Computer Architecture Education

• Julio Sahuquillo, Salvador Petit , Vicent Selfa , María Engracia Gómez : A Research-Oriented Course on Advanced Multicore Architecture. IPDPS Workshops 2015: 760-765
• J. Sahuquillo, N. Tomás, S.Petit, A. Pont: Spim-cache: a Pedagogical Tool for Teaching Cache Memories through Code-Based Exercises. IEEE Transactions on Education 50(3): (2007)
• R. Ubal, J.C. Cano, S.Petit, J. Sahuquillo: RACFP: a Training Tool to Work with Floating-Point Representation, Algorithms, and Circuits in Undergraduate Courses. IEEE Transactions on Education 49(3): (2006)
• S. Petit, N. Tomás, J. Sahuquillo, A. Pont: An execution-driven simulation tool for teaching cache memories in introductory computer organization courses. WCAE 2006