src/slave_Silabs_C8051F342/USB_ISR.c
00001 //----------------------------------------------------------------------------- 00002 // USB_ISR.c 00003 //----------------------------------------------------------------------------- 00004 00005 //----------------------------------------------------------------------------- 00006 // Includes 00007 //----------------------------------------------------------------------------- 00008 00009 #include "USB_Type.h" 00010 #include "USB_Configuration.h" 00011 #include "USB_Register.h" 00012 #include "USB_Standard_Requests.h" 00013 #include "USB_Class_Requests.h" 00014 #include "USB_CDC_UART.h" 00015 #include "FIFO_RW.h" 00016 00017 //#define ALLOCATE_VARS 00018 #include "USB_ISR.h" 00019 00020 //----------------------------------------------------------------------------- 00021 // configuration conditions 00022 //----------------------------------------------------------------------------- 00023 00024 #if (defined USE_EP1_OUT) && !(defined ENABLE_EP1_OUT_ISO) 00025 #define USE_EP1_OUT_STATUS 00026 #endif 00027 #if (defined USE_EP2_OUT) && !(defined ENABLE_EP2_OUT_ISO) 00028 #define USE_EP2_OUT_STATUS 00029 #endif 00030 #if (defined USE_EP3_OUT) && !(defined ENABLE_EP3_OUT_ISO) 00031 #define USE_EP3_OUT_STATUS 00032 #endif 00033 #if (defined USE_EP1_IN) && !(defined ENABLE_EP1_IN_ISO) 00034 #define USE_EP1_IN_STATUS 00035 #endif 00036 #if (defined USE_EP2_IN) && !(defined ENABLE_EP2_IN_ISO) 00037 #define USE_EP2_IN_STATUS 00038 #endif 00039 #if (defined USE_EP3_IN) && !(defined ENABLE_EP3_IN_ISO) 00040 #define USE_EP3_IN_STATUS 00041 #endif 00042 00043 00044 #ifdef ENABLE_EP1_OUT_INTERRUPT 00045 #define EP1_OUT_INTEN rbOUT1E 00046 #else 00047 #define EP1_OUT_INTEN 0 00048 #endif 00049 #ifdef ENABLE_EP2_OUT_INTERRUPT 00050 #define EP2_OUT_INTEN rbOUT2E 00051 #else 00052 #define EP2_OUT_INTEN 0 00053 #endif 00054 #ifdef ENABLE_EP3_OUT_INTERRUPT 00055 #define EP3_OUT_INTEN rbOUT3E 00056 #else 00057 #define EP3_OUT_INTEN 0 00058 #endif 00059 00060 #ifdef ENABLE_EP1_IN_INTERRUPT 00061 #define EP1_IN_INTEN rbIN1E 00062 #else 00063 #define EP1_IN_INTEN 0 00064 #endif 00065 #ifdef ENABLE_EP2_IN_INTERRUPT 00066 #define EP2_IN_INTEN rbIN2E 00067 #else 00068 #define EP2_IN_INTEN 0 00069 #endif 00070 #ifdef ENABLE_EP3_IN_INTERRUPT 00071 #define EP3_IN_INTEN rbIN3E 00072 #else 00073 #define EP3_IN_INTEN 0 00074 #endif 00075 00076 #ifdef ENABLE_SOF_INTERRUPT 00077 #define SOF_INTEN rbSOFE 00078 #else 00079 #define SOF_INTEN 0 00080 #endif 00081 00082 #ifdef ENABLE_SUSPEND_RESUME 00083 // #define SUSPEND_RESUME_INTEN (rbSUSINTE | rbRSUINTE) 00084 #define SUSPEND_RESUME_INTEN (rbSUSINTE) 00085 #else 00086 #define SUSPEND_RESUME_INTEN 0 00087 #endif 00088 00089 #define EP_OUT_INTEN (EP1_OUT_INTEN | EP2_OUT_INTEN | EP3_OUT_INTEN) 00090 #define EP_IN_INTEN (EP1_IN_INTEN | EP2_IN_INTEN | EP3_IN_INTEN) 00091 00092 00093 //----------------------------------------------------------------------------- 00094 // Global Variables 00095 //----------------------------------------------------------------------------- 00096 00097 BYTE USB_State; // Hold current usb device state 00098 Tsetup_buffer Setup; // Buffer for current device request 00099 bit setup_handled; // flag that indicates setup stage is handled or not 00100 UINT DataSize; // Size of data to return 00101 BYTE* DataPtr; // Pointer to data to return 00102 00103 // Holds the status for each endpoint 00104 volatile BYTE Ep_Status0 = EP_IDLE; 00105 00106 #ifdef USE_EP1_OUT_STATUS 00107 volatile bit Ep_StatusOUT1 = EP_HALT; 00108 #endif 00109 #ifdef USE_EP2_OUT_STATUS 00110 volatile bit Ep_StatusOUT2 = EP_HALT; 00111 #endif 00112 #ifdef USE_EP3_OUT_STATUS 00113 volatile bit Ep_StatusOUT3 = EP_HALT; 00114 #endif 00115 #ifdef USE_EP1_IN_STATUS 00116 volatile bit Ep_StatusIN1 = EP_HALT; 00117 #endif 00118 #ifdef USE_EP2_IN_STATUS 00119 volatile bit Ep_StatusIN2 = EP_HALT; 00120 #endif 00121 #ifdef USE_EP3_IN_STATUS 00122 volatile bit Ep_StatusIN3 = EP_HALT; 00123 #endif 00124 00125 // FIFO status of endpoints 00126 volatile bit IN1_FIFO_empty = TRUE; 00127 volatile bit IN2_FIFO_empty = TRUE; 00128 volatile bit IN3_FIFO_empty = TRUE; 00129 volatile bit OUT1_FIFO_loaded = FALSE; 00130 volatile bit OUT2_FIFO_loaded = FALSE; 00131 volatile bit OUT3_FIFO_loaded = FALSE; 00132 00133 // function pointer for the request callback function at the end of control OUT transfer 00134 bit (*USB_request_callback)( void ); 00135 00136 //----------------------------------------------------------------------------- 00137 // Static Variables in this file 00138 //----------------------------------------------------------------------------- 00139 00140 //----------------------------------------------------------------------------- 00141 // Local function prototypes 00142 //----------------------------------------------------------------------------- 00143 00144 static void Handle_Setup(void); // Handle setup packet on Endpoint 0 00145 static void Usb_Reset(void); // Called after USB bus reset 00146 static void Handle_SOF(void); 00147 00148 static void Handle_Out1(void); // Handle out packet on Endpoint 1 00149 static void Handle_Out2(void); // Handle out packet on Endpoint 2 00150 static void Handle_Out3(void); // Handle out packet on Endpoint 3 00151 static void Handle_In1(void); // Handle in packet on Endpoint 1 00152 static void Handle_In2(void); // Handle in packet on Endpoint 2 00153 static void Handle_In3(void); // Handle in packet on Endpoint 3 00154 00155 //----------------------------------------------------------------------------- 00156 // Usb0_Init 00157 //----------------------------------------------------------------------------- 00158 // 00159 // - Initialize USB0 00160 // - Enable USB0 interrupts 00161 // - Enable USB0 transceiver 00162 // - Enable USB0 with suspend detection 00163 //----------------------------------------------------------------------------- 00164 void Usb0_Init(void) 00165 { 00166 POLL_WRITE_BYTE(POWER, 0x08); // Force Asynchronous USB Reset 00167 // USB Interrupt enable flags are reset by USB bus reset 00168 POLL_WRITE_BYTE(IN1IE, rbEP0E); // Enable EP 0 interrupt, disable EP1-3 IN interrupt 00169 POLL_WRITE_BYTE(OUT1IE, 0x00); // Disable EP 1-3 OUT interrupts 00170 00171 POLL_WRITE_BYTE(CMIE, rbRSTINTE | SUSPEND_RESUME_INTEN); // Enable Reset and Suspend interrupts 00172 00173 USB0XCN = 0xE0; // Enable transceiver; select full speed 00174 POLL_WRITE_BYTE(CLKREC, 0x80); // Enable clock recovery, single-step mode 00175 // disabled 00176 #ifdef ENABLE_SUSPEND_RESUME 00177 // Enable USB0 by clearing the USB Inhibit bit 00178 POLL_WRITE_BYTE(POWER, 0x01); // and enable suspend detection 00179 #else 00180 // Enable USB0 by clearing the USB Inhibit bit 00181 POLL_WRITE_BYTE(POWER, 0x00); 00182 #endif 00183 00184 } 00185 00186 //----------------------------------------------------------------------------- 00187 // Interrupt Service Routines 00188 //----------------------------------------------------------------------------- 00189 00190 //----------------------------------------------------------------------------- 00191 // Usb_ISR 00192 //----------------------------------------------------------------------------- 00193 // 00194 // Called after any USB type interrupt, this handler determines which type 00195 // of interrupt occurred, and calls the specific routine to handle it. 00196 // 00197 //----------------------------------------------------------------------------- 00198 00199 void Usb_ISR(void) interrupt 8 // Top-level USB ISR 00200 { 00201 BYTE bCommon, bIn; 00202 #if (EP_OUT_INTEN != 0) 00203 BYTE bOut; 00204 #endif 00205 00206 POLL_READ_BYTE(CMINT, bCommon); // Read all interrupt registers 00207 POLL_READ_BYTE(IN1INT, bIn); // this read also clears the register 00208 00209 #if (EP_OUT_INTEN != 0) 00210 POLL_READ_BYTE(OUT1INT, bOut); 00211 #endif 00212 // Handle Reset interrupt 00213 if (bCommon & rbRSTINT) { Usb_Reset(); } 00214 // Handle EP1-3 interrupt 00215 #ifdef ENABLE_EP1_OUT_INTERRUPT 00216 if (bOut & rbOUT1) { Handle_Out1(); } 00217 #endif 00218 #ifdef ENABLE_EP2_OUT_INTERRUPT 00219 // if (bOut & rbOUT2) { Handle_Out2(); } 00220 if (bOut & rbOUT2) { OUT2_FIFO_loaded = TRUE; } 00221 #endif 00222 #ifdef ENABLE_EP3_OUT_INTERRUPT 00223 // if (bOut & rbOUT3) { Handle_Out3(); } 00224 if (bOut & rbOUT3) { OUT3_FIFO_loaded = TRUE; } 00225 #endif 00226 #ifdef ENABLE_EP1_IN_INTERRUPT 00227 // if (bIn & rbIN1) { Handle_In1(); } 00228 if (bIn & rbIN1) { IN1_FIFO_empty = TRUE; } 00229 #endif 00230 #ifdef ENABLE_EP2_IN_INTERRUPT 00231 // if (bIn & rbIN2) { Handle_In2(); } 00232 if (bIn & rbIN2) { IN2_FIFO_empty = TRUE; } 00233 #endif 00234 #ifdef ENABLE_EP3_IN_INTERRUPT 00235 // if (bIn & rbIN3) { Handle_In3(); } 00236 if (bIn & rbIN3) { IN3_FIFO_empty = TRUE; } 00237 #endif 00238 // Handle EP0 interrupt 00239 if (bIn & rbEP0) { Handle_Setup(); } 00240 00241 #ifdef ENABLE_SUSPEND_RESUME 00242 // Handle Suspend interrupt 00243 if (bCommon & rbSUSINT) { Usb_Suspend(); } 00244 // Handle Resume interrupt 00245 // if (bCommon & rbRSUINT) { Usb_Resume(); } 00246 #endif 00247 00248 // SOF interrupt 00249 #ifdef ENABLE_SOF_INTERRUPT 00250 // if (bCommon & rbSOF) { Handle_SOF(); } 00251 if (bCommon & rbSOF) { CDC_Handle_INT_IN(); // Handle Notification endpoint 00252 CDC_Handle_Bulk_IN_ZLP(); } // Send ZLP to bulk IN when required 00253 #endif 00254 00255 } 00256 00257 //----------------------------------------------------------------------------- 00258 // Support Routines for ISR 00259 //----------------------------------------------------------------------------- 00260 00261 //----------------------------------------------------------------------------- 00262 // SDCC suport 00263 //----------------------------------------------------------------------------- 00264 #if defined SDCC 00265 #pragma nooverlay 00266 #endif // SDCC 00267 00268 //----------------------------------------------------------------------------- 00269 // Usb_Reset 00270 //----------------------------------------------------------------------------- 00271 // 00272 // - Set state to default 00273 // - Clear Usb Inhibit bit 00274 // 00275 //----------------------------------------------------------------------------- 00276 00277 static void Usb_Reset(void) 00278 { 00279 POLL_WRITE_BYTE(IN1IE, rbEP0E | EP_IN_INTEN ); // Enable Ep0 and EP1-3 IN 00280 #if (EP_OUT_INTEN != 0) 00281 POLL_WRITE_BYTE(OUT1IE, EP_OUT_INTEN ); // Enable EP1-3 OUT 00282 #endif 00283 POLL_WRITE_BYTE(CMIE, rbRSTINTE | SUSPEND_RESUME_INTEN | SOF_INTEN); // Enable Reset, Suspend interrupts 00284 00285 POLL_WRITE_BYTE(POWER, 0x01); // Clear usb inhibit bit to enable USB 00286 // suspend detection 00287 00288 USB_State = DEV_DEFAULT; // Set device state to default 00289 00290 Ep_Status0 = EP_IDLE; // Set default Endpoint Status 00291 00292 #ifdef USE_EP1_OUT_STATUS 00293 Ep_StatusOUT1 = EP_HALT; 00294 #endif 00295 #ifdef USE_EP2_OUT_STATUS 00296 Ep_StatusOUT2 = EP_HALT; 00297 #endif 00298 #ifdef USE_EP3_OUT_STATUS 00299 Ep_StatusOUT3 = EP_HALT; 00300 #endif 00301 #ifdef USE_EP1_IN_STATUS 00302 Ep_StatusIN1 = EP_HALT; 00303 #endif 00304 #ifdef USE_EP2_IN_STATUS 00305 Ep_StatusIN2 = EP_HALT; 00306 #endif 00307 #ifdef USE_EP3_IN_STATUS 00308 Ep_StatusIN3 = EP_HALT; 00309 #endif 00310 00311 } 00312 00313 //----------------------------------------------------------------------------- 00314 // Handle_Setup 00315 //----------------------------------------------------------------------------- 00316 // 00317 // - Decode Incoming Setup requests 00318 // - Load data packets on fifo while in transmit mode 00319 // 00320 //----------------------------------------------------------------------------- 00321 00322 static bit send_eq_requested = FALSE; // flag that indicates that the data to send on TX 00323 // equals to the requested by Setup wLength 00324 // KEIL doesn't accept static local bit variable 00325 static void Handle_Setup(void) 00326 { 00327 BYTE ControlReg, TempReg; // Temporary storage for EP control register 00328 00329 POLL_WRITE_BYTE(INDEX, 0); // Set Index to Endpoint Zero 00330 POLL_READ_BYTE(E0CSR, ControlReg); // Read control register 00331 00332 if (ControlReg & rbSTSTL) // If last packet was a sent stall, reset 00333 { // STSTL bit and return EP0 to idle state 00334 POLL_WRITE_BYTE(E0CSR, 0); 00335 Ep_Status0 = EP_IDLE; 00336 return; 00337 } 00338 00339 if (ControlReg & rbSUEND) // SUEND bit is asserted after status stage by SIE 00340 { // or when SIE receives early SETUP 00341 POLL_WRITE_BYTE(E0CSR, rbSSUEND); // Serviced Setup End bit and return to EP_IDLE 00342 Ep_Status0 = EP_IDLE; 00343 } 00344 00345 if (Ep_Status0 == EP_IDLE) // If Endpoint 0 is in idle mode 00346 { 00347 if (ControlReg & rbOPRDY) // Make sure that EP 0 has an Out Packet ready from host 00348 { // although if EP0 is idle, this should always be the case 00349 // Fifo_Read(FIFO_EP0, 8, (BYTE *)&Setup); 00350 // FIFO_Read_generic(FIFO_EP0, 8, (BYTE *)&Setup); 00351 FIFO_Read_idata(FIFO_EP0, 8, (BYTE idata *)&Setup); 00352 // FIFO_Read_pdata(FIFO_EP0, 8, (BYTE pdata *)&Setup); 00353 // FIFO_Read_xdata(FIFO_EP0, 8, (BYTE xdata *)&Setup); 00354 // Get Setup Packet off of Fifo 00355 #if defined BIG_ENDIAN 00356 // As the USB custom, multi-byte number is LSB first - little endian 00357 Setup.wValue.i = ((UINT)Setup.wValue.c[1] << 8) | Setup.wValue.c[0]; 00358 Setup.wIndex.i = ((UINT)Setup.wIndex.c[1] << 8) | Setup.wIndex.c[0]; 00359 Setup.wLength.i = ((UINT)Setup.wLength.c[1] << 8) | Setup.wLength.c[0]; 00360 #endif // end of BIG_ENDIAN 00361 00362 setup_handled = FALSE; 00363 USB_request_callback = NULL; 00364 switch ( Setup.bmRequestType & DRT_MASK ) // Device Request Type 00365 { 00366 case DRT_STD: // Standard device request 00367 Standard_Device_Request(); 00368 break; 00369 case DRT_CLASS: // class specific request 00370 Class_Request(); 00371 break; 00372 /* 00373 case DRT_VENDOR: // vendor request 00374 Vendor_Request(); 00375 break; 00376 */ 00377 default: 00378 break; 00379 } 00380 00381 if ( setup_handled ) 00382 TempReg = rbSOPRDY; // Tell to SIE that the setup is handled 00383 else { 00384 TempReg = rbSDSTL; // Return STALL to the host 00385 Ep_Status0 = EP_STALL; // Put the endpoint in stall status 00386 } 00387 00388 send_eq_requested = (DataSize == Setup.wLength.i); // get this flag before DataSize 00389 // is reduced in TX cycle 00390 POLL_WRITE_BYTE(INDEX, 0); // Assure the indexed registers are accessed correctly 00391 POLL_WRITE_BYTE(E0CSR, TempReg); 00392 } 00393 } // end of EP_IDLE 00394 00395 if ( Ep_Status0 == EP_TX ) // See if the endpoint has data to transmit to host 00396 { 00397 if ( !(ControlReg & rbINPRDY) ) // Make sure you don't overwrite last packet 00398 { 00399 POLL_READ_BYTE( E0CSR, ControlReg ); 00400 // Read control register 00401 00402 if ( (!(ControlReg & rbSUEND)) && (!(ControlReg & rbOPRDY)) ) 00403 // Check to see if Setup End or Out Packet received, if so 00404 // do not put any new data on FIFO 00405 { 00406 TempReg = rbINPRDY; // Add In Packet ready flag to E0CSR bitmask 00407 // Break Data into multiple packets if larger than Max Packet 00408 if (DataSize >= EP0_PACKET_SIZE) 00409 { // The data size to send in this cycle is 00410 // just EP0_PACKET_SIZE 00411 // Fifo_Write( FIFO_EP0, EP0_PACKET_SIZE, (BYTE *)DataPtr ); 00412 FIFO_Write_generic( FIFO_EP0, EP0_PACKET_SIZE, (BYTE *)DataPtr ); 00413 DataPtr += EP0_PACKET_SIZE; // Advance data pointer 00414 DataSize -= EP0_PACKET_SIZE; // Decrement data size 00415 if ( send_eq_requested && (DataSize == 0) ) // In this case, no need to send ZLP, 00416 { // finish TX immediately 00417 TempReg |= rbDATAEND; 00418 Ep_Status0 = EP_IDLE; 00419 } 00420 } else { // The data size to send in this cycle is 00421 // smaller than EP0_PACKET_SIZE or zero (ZLP) 00422 // Fifo_Write( FIFO_EP0, (BYTE)DataSize, (BYTE *)DataPtr ); 00423 FIFO_Write_generic( FIFO_EP0, (BYTE)DataSize, (BYTE *)DataPtr ); 00424 TempReg |= rbDATAEND; 00425 Ep_Status0 = EP_IDLE; 00426 } 00427 POLL_WRITE_BYTE(E0CSR, TempReg); // Write mask to E0CSR 00428 } 00429 } 00430 } // end of EP_TX 00431 00432 if (Ep_Status0 == EP_RX) // See if endpoint should receive 00433 { 00434 BYTE dataCount; 00435 00436 POLL_READ_BYTE( E0CSR, ControlReg ); // Read control register 00437 if ( ControlReg & rbOPRDY ) // Verify packet was received 00438 { 00439 TempReg = rbSOPRDY; 00440 00441 POLL_READ_BYTE( E0CNT, dataCount ); // get data bytes on the FIFO 00442 // Fifo_Read( FIFO_EP0, dataCount, (BYTE*)DataPtr ); 00443 FIFO_Read_generic( FIFO_EP0, dataCount, (BYTE*)DataPtr ); 00444 // Empty the FIFO 00445 // FIFO must be read out just the size it has, 00446 // otherwize the FIFO pointer on the SIE goes out of synch. 00447 DataPtr += dataCount; // Advance the pointer 00448 if ( DataSize > dataCount ) // Update the scheduled number to be received 00449 DataSize -= dataCount; 00450 // Meet the end of the data stage 00451 else { 00452 if ( (DataSize == dataCount) 00453 && USB_request_callback 00454 && (*USB_request_callback)() ) 00455 { 00456 TempReg |= rbDATAEND; // Signal end of data stage 00457 Ep_Status0 = EP_IDLE; // Set Endpoint to IDLE 00458 } else { 00459 TempReg = rbSDSTL; // Signal STALL on the data stage 00460 Ep_Status0 = EP_STALL; // Put the endpoint in stall status 00461 } 00462 } 00463 POLL_WRITE_BYTE ( E0CSR, TempReg ); 00464 } 00465 } // end of EP_RX 00466 00467 } 00468 00469 //----------------------------------------------------------------------------- 00470 // Fifo_Read 00471 //----------------------------------------------------------------------------- 00472 // 00473 // Return Value : None 00474 // Parameters : 00475 // 1) BYTE addr : target address 00476 // 2) BYTE uNumBytes : number of bytes to unload 00477 // 3) BYTE * pData : read data destination 00478 // 00479 // Read from the selected endpoint FIFO 00480 // 00481 //----------------------------------------------------------------------------- 00482 /* 00483 void Fifo_Read(BYTE addr, BYTE uNumBytes, BYTE * pData) 00484 { 00485 BYTE idx; 00486 00487 while(USB0ADR & 0x80); // Wait for BUSY->'0' 00488 USB0ADR = addr | 0xC0; // Set address 00489 // Set auto-read and initiate first read 00490 // Read <NumBytes> from the selected FIFO 00491 for ( idx = 0; idx < uNumBytes; idx++ ) { 00492 while(USB0ADR & 0x80); // Wait for BUSY->'0' (read complete) 00493 pData[ idx ] = USB0DAT; 00494 } 00495 USB0ADR = 0; // Clear auto-read 00496 } 00497 */ 00498 //----------------------------------------------------------------------------- 00499 // Fifo_Write 00500 //----------------------------------------------------------------------------- 00501 // 00502 // Return Value : None 00503 // Parameters : 00504 // 1) BYTE addr : target address 00505 // 2) BYTE uNumBytes : number of bytes to unload 00506 // 3) BYTE * pData : location of source data 00507 // 00508 // Write to the selected endpoint FIFO 00509 // 00510 //----------------------------------------------------------------------------- 00511 /* 00512 void Fifo_Write(BYTE addr, BYTE uNumBytes, BYTE * pData) 00513 { 00514 BYTE idx; 00515 00516 while(USB0ADR & 0x80); // Wait for BUSY->'0' 00517 USB0ADR = (addr & 0x3F); // Set address (mask out bits7-6) 00518 00519 // Write <NumBytes> to the selected FIFO 00520 for ( idx = 0; idx < uNumBytes; idx++ ) { 00521 while(USB0ADR & 0x80); // Wait for BUSY->'0' (write complete) 00522 USB0DAT = pData[ idx ]; 00523 } 00524 } 00525 */ 00526 //----------------------------------------------------------------------------- 00527 // POLL_READ_BYTE, POLL_WRITE_BYTE 00528 //----------------------------------------------------------------------------- 00529 // When the macros are not defined, provide them as functions 00530 //----------------------------------------------------------------------------- 00531 00532 #if defined( POLL_READ_BYTE_DEF ) 00533 00534 BYTE POLL_READ_BYTE_FUNC( BYTE addr ) 00535 { 00536 while( USB0ADR & 0x80 ); 00537 USB0ADR = (0x80 | addr); 00538 while( USB0ADR & 0x80 ); 00539 return USB0DAT; 00540 } 00541 00542 #endif 00543 00544 #if !defined( POLL_WRITE_BYTE ) 00545 00546 void POLL_WRITE_BYTE( BYTE addr, BYTE dt ) 00547 { 00548 while(USB0ADR & 0x80); 00549 USB0ADR = addr; 00550 USB0DAT = dt; 00551 } 00552 00553 #endif 00554 00555 //----------------------------------------------------------------------------- 00556 // Handle_Out1 00557 //----------------------------------------------------------------------------- 00558 // Handle out packet on Endpoint 1 00559 //----------------------------------------------------------------------------- 00560 00561 #ifdef ENABLE_EP1_OUT_INTERRUPT 00562 /* 00563 static void Handle_Out1(void) 00564 { 00565 } 00566 */ 00567 #endif 00568 00569 //----------------------------------------------------------------------------- 00570 // Handle_Out2 00571 //----------------------------------------------------------------------------- 00572 // Handle out packet on Endpoint 2 00573 //----------------------------------------------------------------------------- 00574 00575 #ifdef ENABLE_EP2_OUT_INTERRUPT 00576 /* 00577 static void Handle_Out2(void) 00578 { 00579 } 00580 */ 00581 #endif 00582 00583 //----------------------------------------------------------------------------- 00584 // Handle_Out3 00585 //----------------------------------------------------------------------------- 00586 // Handle out packet on Endpoint 3 00587 //----------------------------------------------------------------------------- 00588 00589 #ifdef ENABLE_EP3_OUT_INTERRUPT 00590 /* 00591 static void Handle_Out3(void) 00592 { 00593 } 00594 */ 00595 #endif 00596 00597 //----------------------------------------------------------------------------- 00598 // Handle_In1 00599 //----------------------------------------------------------------------------- 00600 // Handle in packet on Endpoint 1 00601 //----------------------------------------------------------------------------- 00602 00603 #ifdef ENABLE_EP1_IN_INTERRUPT 00604 /* 00605 static void Handle_In1(void) 00606 { 00607 } 00608 */ 00609 #endif 00610 00611 //----------------------------------------------------------------------------- 00612 // Handle_In2 00613 //----------------------------------------------------------------------------- 00614 // Handle in packet on Endpoint 2 00615 //----------------------------------------------------------------------------- 00616 00617 #ifdef ENABLE_EP2_IN_INTERRUPT 00618 /* 00619 static void Handle_In2(void) 00620 { 00621 } 00622 */ 00623 #endif 00624 00625 //----------------------------------------------------------------------------- 00626 // Handle_In3 00627 //----------------------------------------------------------------------------- 00628 // Handle in packet on Endpoint 3 00629 //----------------------------------------------------------------------------- 00630 00631 #ifdef ENABLE_EP3_IN_INTERRUPT 00632 /* 00633 static void Handle_In3(void) 00634 { 00635 } 00636 */ 00637 #endif 00638 00639 //----------------------------------------------------------------------------- 00640 // Handle_SOF 00641 //----------------------------------------------------------------------------- 00642 // Handle SOF interrupt 00643 // SOF interrupt is evoked in 1 ms interval, when enabled 00644 // When the device is connected to USB bus, this interrupt synchronizes to SOF 00645 // When the device is not connected, the USB engine automatically generates the interval 00646 //----------------------------------------------------------------------------- 00647 00648 #ifdef ENABLE_SOF_INTERRUPT 00649 /* 00650 static void Handle_SOF(void) 00651 { 00652 } 00653 */ 00654 #endif 00655 00656 //----------------------------------------------------------------------------- 00657 // End Of File 00658 //-----------------------------------------------------------------------------
