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STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_eth.h 00004 * @author MCD Application Team 00005 * @brief Header file of ETH HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_HAL_ETH_H 00038 #define __STM32F4xx_HAL_ETH_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\ 00045 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx) 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32f4xx_hal_def.h" 00048 00049 /** @addtogroup STM32F4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup ETH 00054 * @{ 00055 */ 00056 00057 /** @addtogroup ETH_Private_Macros 00058 * @{ 00059 */ 00060 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20U) 00061 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \ 00062 ((CMD) == ETH_AUTONEGOTIATION_DISABLE)) 00063 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \ 00064 ((SPEED) == ETH_SPEED_100M)) 00065 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \ 00066 ((MODE) == ETH_MODE_HALFDUPLEX)) 00067 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \ 00068 ((MODE) == ETH_RXINTERRUPT_MODE)) 00069 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \ 00070 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE)) 00071 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \ 00072 ((MODE) == ETH_MEDIA_INTERFACE_RMII)) 00073 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \ 00074 ((CMD) == ETH_WATCHDOG_DISABLE)) 00075 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \ 00076 ((CMD) == ETH_JABBER_DISABLE)) 00077 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \ 00078 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \ 00079 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \ 00080 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \ 00081 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \ 00082 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \ 00083 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \ 00084 ((GAP) == ETH_INTERFRAMEGAP_40BIT)) 00085 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \ 00086 ((CMD) == ETH_CARRIERSENCE_DISABLE)) 00087 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \ 00088 ((CMD) == ETH_RECEIVEOWN_DISABLE)) 00089 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \ 00090 ((CMD) == ETH_LOOPBACKMODE_DISABLE)) 00091 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \ 00092 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE)) 00093 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \ 00094 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE)) 00095 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \ 00096 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE)) 00097 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \ 00098 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \ 00099 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \ 00100 ((LIMIT) == ETH_BACKOFFLIMIT_1)) 00101 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \ 00102 ((CMD) == ETH_DEFFERRALCHECK_DISABLE)) 00103 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \ 00104 ((CMD) == ETH_RECEIVEAll_DISABLE)) 00105 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \ 00106 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \ 00107 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE)) 00108 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \ 00109 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \ 00110 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER)) 00111 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \ 00112 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE)) 00113 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \ 00114 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE)) 00115 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \ 00116 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE)) 00117 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 00118 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \ 00119 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \ 00120 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE)) 00121 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \ 00122 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \ 00123 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT)) 00124 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFFU) 00125 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \ 00126 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE)) 00127 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \ 00128 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \ 00129 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \ 00130 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256)) 00131 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \ 00132 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE)) 00133 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \ 00134 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE)) 00135 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \ 00136 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE)) 00137 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \ 00138 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT)) 00139 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFFU) 00140 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \ 00141 ((ADDRESS) == ETH_MAC_ADDRESS1) || \ 00142 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 00143 ((ADDRESS) == ETH_MAC_ADDRESS3)) 00144 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \ 00145 ((ADDRESS) == ETH_MAC_ADDRESS2) || \ 00146 ((ADDRESS) == ETH_MAC_ADDRESS3)) 00147 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \ 00148 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA)) 00149 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \ 00150 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \ 00151 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \ 00152 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \ 00153 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \ 00154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1)) 00155 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \ 00156 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE)) 00157 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \ 00158 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE)) 00159 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \ 00160 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE)) 00161 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \ 00162 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE)) 00163 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \ 00164 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \ 00165 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \ 00166 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \ 00167 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \ 00168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \ 00169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \ 00170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES)) 00171 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \ 00172 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE)) 00173 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \ 00174 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE)) 00175 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \ 00176 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \ 00177 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \ 00178 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES)) 00179 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \ 00180 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE)) 00181 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \ 00182 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE)) 00183 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \ 00184 ((CMD) == ETH_FIXEDBURST_DISABLE)) 00185 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \ 00186 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \ 00187 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \ 00188 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \ 00189 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \ 00190 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \ 00191 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \ 00192 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \ 00193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \ 00194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \ 00195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \ 00196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT)) 00197 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \ 00198 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \ 00199 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \ 00200 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \ 00201 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \ 00202 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \ 00203 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \ 00204 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \ 00205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \ 00206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \ 00207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \ 00208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT)) 00209 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1FU) 00210 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \ 00211 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \ 00212 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \ 00213 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \ 00214 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX)) 00215 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \ 00216 ((FLAG) == ETH_DMATXDESC_IC) || \ 00217 ((FLAG) == ETH_DMATXDESC_LS) || \ 00218 ((FLAG) == ETH_DMATXDESC_FS) || \ 00219 ((FLAG) == ETH_DMATXDESC_DC) || \ 00220 ((FLAG) == ETH_DMATXDESC_DP) || \ 00221 ((FLAG) == ETH_DMATXDESC_TTSE) || \ 00222 ((FLAG) == ETH_DMATXDESC_TER) || \ 00223 ((FLAG) == ETH_DMATXDESC_TCH) || \ 00224 ((FLAG) == ETH_DMATXDESC_TTSS) || \ 00225 ((FLAG) == ETH_DMATXDESC_IHE) || \ 00226 ((FLAG) == ETH_DMATXDESC_ES) || \ 00227 ((FLAG) == ETH_DMATXDESC_JT) || \ 00228 ((FLAG) == ETH_DMATXDESC_FF) || \ 00229 ((FLAG) == ETH_DMATXDESC_PCE) || \ 00230 ((FLAG) == ETH_DMATXDESC_LCA) || \ 00231 ((FLAG) == ETH_DMATXDESC_NC) || \ 00232 ((FLAG) == ETH_DMATXDESC_LCO) || \ 00233 ((FLAG) == ETH_DMATXDESC_EC) || \ 00234 ((FLAG) == ETH_DMATXDESC_VF) || \ 00235 ((FLAG) == ETH_DMATXDESC_CC) || \ 00236 ((FLAG) == ETH_DMATXDESC_ED) || \ 00237 ((FLAG) == ETH_DMATXDESC_UF) || \ 00238 ((FLAG) == ETH_DMATXDESC_DB)) 00239 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \ 00240 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT)) 00241 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \ 00242 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \ 00243 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \ 00244 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL)) 00245 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFFU) 00246 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \ 00247 ((FLAG) == ETH_DMARXDESC_AFM) || \ 00248 ((FLAG) == ETH_DMARXDESC_ES) || \ 00249 ((FLAG) == ETH_DMARXDESC_DE) || \ 00250 ((FLAG) == ETH_DMARXDESC_SAF) || \ 00251 ((FLAG) == ETH_DMARXDESC_LE) || \ 00252 ((FLAG) == ETH_DMARXDESC_OE) || \ 00253 ((FLAG) == ETH_DMARXDESC_VLAN) || \ 00254 ((FLAG) == ETH_DMARXDESC_FS) || \ 00255 ((FLAG) == ETH_DMARXDESC_LS) || \ 00256 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \ 00257 ((FLAG) == ETH_DMARXDESC_LC) || \ 00258 ((FLAG) == ETH_DMARXDESC_FT) || \ 00259 ((FLAG) == ETH_DMARXDESC_RWT) || \ 00260 ((FLAG) == ETH_DMARXDESC_RE) || \ 00261 ((FLAG) == ETH_DMARXDESC_DBE) || \ 00262 ((FLAG) == ETH_DMARXDESC_CE) || \ 00263 ((FLAG) == ETH_DMARXDESC_MAMPCE)) 00264 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \ 00265 ((BUFFER) == ETH_DMARXDESC_BUFFER2)) 00266 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \ 00267 ((FLAG) == ETH_PMT_FLAG_MPR)) 00268 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & 0xC7FE1800U) == 0x00U) && ((FLAG) != 0x00U)) 00269 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \ 00270 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \ 00271 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \ 00272 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \ 00273 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \ 00274 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \ 00275 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \ 00276 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \ 00277 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \ 00278 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \ 00279 ((FLAG) == ETH_DMA_FLAG_T)) 00280 #define IS_ETH_MAC_IT(IT) ((((IT) & 0xFFFFFDF1U) == 0x00U) && ((IT) != 0x00U)) 00281 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \ 00282 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \ 00283 ((IT) == ETH_MAC_IT_PMT)) 00284 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \ 00285 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \ 00286 ((FLAG) == ETH_MAC_FLAG_PMT)) 00287 #define IS_ETH_DMA_IT(IT) ((((IT) & 0xC7FE1800U) == 0x00U) && ((IT) != 0x00U)) 00288 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \ 00289 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \ 00290 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \ 00291 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \ 00292 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \ 00293 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \ 00294 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \ 00295 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \ 00296 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T)) 00297 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \ 00298 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER)) 00299 #define IS_ETH_MMC_IT(IT) (((((IT) & 0xFFDF3FFFU) == 0x00U) || (((IT) & 0xEFFDFF9FU) == 0x00U)) && \ 00300 ((IT) != 0x00U)) 00301 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \ 00302 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \ 00303 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE)) 00304 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \ 00305 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE)) 00306 00307 /** 00308 * @} 00309 */ 00310 00311 /** @addtogroup ETH_Private_Defines 00312 * @{ 00313 */ 00314 /* Delay to wait when writing to some Ethernet registers */ 00315 #define ETH_REG_WRITE_DELAY 0x00000001U 00316 00317 /* ETHERNET Errors */ 00318 #define ETH_SUCCESS 0U 00319 #define ETH_ERROR 1U 00320 00321 /* ETHERNET DMA Tx descriptors Collision Count Shift */ 00322 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT 3U 00323 00324 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */ 00325 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT 16U 00326 00327 /* ETHERNET DMA Rx descriptors Frame Length Shift */ 00328 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT 16U 00329 00330 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */ 00331 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT 16U 00332 00333 /* ETHERNET DMA Rx descriptors Frame length Shift */ 00334 #define ETH_DMARXDESC_FRAMELENGTHSHIFT 16U 00335 00336 /* ETHERNET MAC address offsets */ 00337 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + 0x40U) /* ETHERNET MAC address high offset */ 00338 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + 0x44U) /* ETHERNET MAC address low offset */ 00339 00340 /* ETHERNET MACMIIAR register Mask */ 00341 #define ETH_MACMIIAR_CR_MASK 0xFFFFFFE3U 00342 00343 /* ETHERNET MACCR register Mask */ 00344 #define ETH_MACCR_CLEAR_MASK 0xFF20810FU 00345 00346 /* ETHERNET MACFCR register Mask */ 00347 #define ETH_MACFCR_CLEAR_MASK 0x0000FF41U 00348 00349 /* ETHERNET DMAOMR register Mask */ 00350 #define ETH_DMAOMR_CLEAR_MASK 0xF8DE3F23U 00351 00352 /* ETHERNET Remote Wake-up frame register length */ 00353 #define ETH_WAKEUP_REGISTER_LENGTH 8U 00354 00355 /* ETHERNET Missed frames counter Shift */ 00356 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17U 00357 /** 00358 * @} 00359 */ 00360 00361 /* Exported types ------------------------------------------------------------*/ 00362 /** @defgroup ETH_Exported_Types ETH Exported Types 00363 * @{ 00364 */ 00365 00366 /** 00367 * @brief HAL State structures definition 00368 */ 00369 typedef enum 00370 { 00371 HAL_ETH_STATE_RESET = 0x00U, /*!< Peripheral not yet Initialized or disabled */ 00372 HAL_ETH_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00373 HAL_ETH_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 00374 HAL_ETH_STATE_BUSY_TX = 0x12U, /*!< Data Transmission process is ongoing */ 00375 HAL_ETH_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */ 00376 HAL_ETH_STATE_BUSY_TX_RX = 0x32U, /*!< Data Transmission and Reception process is ongoing */ 00377 HAL_ETH_STATE_BUSY_WR = 0x42U, /*!< Write process is ongoing */ 00378 HAL_ETH_STATE_BUSY_RD = 0x82U, /*!< Read process is ongoing */ 00379 HAL_ETH_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00380 HAL_ETH_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ 00381 }HAL_ETH_StateTypeDef; 00382 00383 /** 00384 * @brief ETH Init Structure definition 00385 */ 00386 00387 typedef struct 00388 { 00389 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY 00390 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps) 00391 and the mode (half/full-duplex). 00392 This parameter can be a value of @ref ETH_AutoNegotiation */ 00393 00394 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps. 00395 This parameter can be a value of @ref ETH_Speed */ 00396 00397 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode 00398 This parameter can be a value of @ref ETH_Duplex_Mode */ 00399 00400 uint16_t PhyAddress; /*!< Ethernet PHY address. 00401 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 00402 00403 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */ 00404 00405 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode. 00406 This parameter can be a value of @ref ETH_Rx_Mode */ 00407 00408 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software. 00409 This parameter can be a value of @ref ETH_Checksum_Mode */ 00410 00411 uint32_t MediaInterface; /*!< Selects the media-independent interface or the reduced media-independent interface. 00412 This parameter can be a value of @ref ETH_Media_Interface */ 00413 00414 } ETH_InitTypeDef; 00415 00416 00417 /** 00418 * @brief ETH MAC Configuration Structure definition 00419 */ 00420 00421 typedef struct 00422 { 00423 uint32_t Watchdog; /*!< Selects or not the Watchdog timer 00424 When enabled, the MAC allows no more then 2048 bytes to be received. 00425 When disabled, the MAC can receive up to 16384 bytes. 00426 This parameter can be a value of @ref ETH_Watchdog */ 00427 00428 uint32_t Jabber; /*!< Selects or not Jabber timer 00429 When enabled, the MAC allows no more then 2048 bytes to be sent. 00430 When disabled, the MAC can send up to 16384 bytes. 00431 This parameter can be a value of @ref ETH_Jabber */ 00432 00433 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission. 00434 This parameter can be a value of @ref ETH_Inter_Frame_Gap */ 00435 00436 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense. 00437 This parameter can be a value of @ref ETH_Carrier_Sense */ 00438 00439 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn, 00440 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted 00441 in Half-Duplex mode. 00442 This parameter can be a value of @ref ETH_Receive_Own */ 00443 00444 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode. 00445 This parameter can be a value of @ref ETH_Loop_Back_Mode */ 00446 00447 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers. 00448 This parameter can be a value of @ref ETH_Checksum_Offload */ 00449 00450 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL, 00451 when a collision occurs (Half-Duplex mode). 00452 This parameter can be a value of @ref ETH_Retry_Transmission */ 00453 00454 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping. 00455 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */ 00456 00457 uint32_t BackOffLimit; /*!< Selects the BackOff limit value. 00458 This parameter can be a value of @ref ETH_Back_Off_Limit */ 00459 00460 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode). 00461 This parameter can be a value of @ref ETH_Deferral_Check */ 00462 00463 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering). 00464 This parameter can be a value of @ref ETH_Receive_All */ 00465 00466 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode. 00467 This parameter can be a value of @ref ETH_Source_Addr_Filter */ 00468 00469 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames) 00470 This parameter can be a value of @ref ETH_Pass_Control_Frames */ 00471 00472 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames. 00473 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */ 00474 00475 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames. 00476 This parameter can be a value of @ref ETH_Destination_Addr_Filter */ 00477 00478 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode 00479 This parameter can be a value of @ref ETH_Promiscuous_Mode */ 00480 00481 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter. 00482 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */ 00483 00484 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter. 00485 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */ 00486 00487 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table. 00488 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ 00489 00490 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table. 00491 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFFU */ 00492 00493 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame. 00494 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFU */ 00495 00496 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames. 00497 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ 00498 00499 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for 00500 automatic retransmission of PAUSE Frame. 00501 This parameter can be a value of @ref ETH_Pause_Low_Threshold */ 00502 00503 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0 00504 unicast address and unique multicast address). 00505 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ 00506 00507 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and 00508 disable its transmitter for a specified time (Pause Time) 00509 This parameter can be a value of @ref ETH_Receive_Flow_Control */ 00510 00511 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode) 00512 or the MAC back-pressure operation (Half-Duplex mode) 00513 This parameter can be a value of @ref ETH_Transmit_Flow_Control */ 00514 00515 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for 00516 comparison and filtering. 00517 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */ 00518 00519 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */ 00520 00521 } ETH_MACInitTypeDef; 00522 00523 /** 00524 * @brief ETH DMA Configuration Structure definition 00525 */ 00526 00527 typedef struct 00528 { 00529 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames. 00530 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */ 00531 00532 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode. 00533 This parameter can be a value of @ref ETH_Receive_Store_Forward */ 00534 00535 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames. 00536 This parameter can be a value of @ref ETH_Flush_Received_Frame */ 00537 00538 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode. 00539 This parameter can be a value of @ref ETH_Transmit_Store_Forward */ 00540 00541 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control. 00542 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */ 00543 00544 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames. 00545 This parameter can be a value of @ref ETH_Forward_Error_Frames */ 00546 00547 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error 00548 and length less than 64 bytes) including pad-bytes and CRC) 00549 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */ 00550 00551 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO. 00552 This parameter can be a value of @ref ETH_Receive_Threshold_Control */ 00553 00554 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second 00555 frame of Transmit data even before obtaining the status for the first frame. 00556 This parameter can be a value of @ref ETH_Second_Frame_Operate */ 00557 00558 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats. 00559 This parameter can be a value of @ref ETH_Address_Aligned_Beats */ 00560 00561 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers. 00562 This parameter can be a value of @ref ETH_Fixed_Burst */ 00563 00564 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction. 00565 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ 00566 00567 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction. 00568 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ 00569 00570 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format. 00571 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */ 00572 00573 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode) 00574 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */ 00575 00576 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration. 00577 This parameter can be a value of @ref ETH_DMA_Arbitration */ 00578 } ETH_DMAInitTypeDef; 00579 00580 00581 /** 00582 * @brief ETH DMA Descriptors data structure definition 00583 */ 00584 00585 typedef struct 00586 { 00587 __IO uint32_t Status; /*!< Status */ 00588 00589 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ 00590 00591 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */ 00592 00593 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ 00594 00595 /*!< Enhanced ETHERNET DMA PTP Descriptors */ 00596 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */ 00597 00598 uint32_t Reserved1; /*!< Reserved */ 00599 00600 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ 00601 00602 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ 00603 00604 } ETH_DMADescTypeDef; 00605 00606 /** 00607 * @brief Received Frame Informations structure definition 00608 */ 00609 typedef struct 00610 { 00611 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */ 00612 00613 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */ 00614 00615 uint32_t SegCount; /*!< Segment count */ 00616 00617 uint32_t length; /*!< Frame length */ 00618 00619 uint32_t buffer; /*!< Frame buffer */ 00620 00621 } ETH_DMARxFrameInfos; 00622 00623 /** 00624 * @brief ETH Handle Structure definition 00625 */ 00626 00627 typedef struct 00628 { 00629 ETH_TypeDef *Instance; /*!< Register base address */ 00630 00631 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */ 00632 00633 uint32_t LinkStatus; /*!< Ethernet link status */ 00634 00635 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */ 00636 00637 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */ 00638 00639 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */ 00640 00641 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */ 00642 00643 HAL_LockTypeDef Lock; /*!< ETH Lock */ 00644 00645 } ETH_HandleTypeDef; 00646 00647 /** 00648 * @} 00649 */ 00650 00651 /* Exported constants --------------------------------------------------------*/ 00652 /** @defgroup ETH_Exported_Constants ETH Exported Constants 00653 * @{ 00654 */ 00655 00656 /** @defgroup ETH_Buffers_setting ETH Buffers setting 00657 * @{ 00658 */ 00659 #define ETH_MAX_PACKET_SIZE 1524U /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ 00660 #define ETH_HEADER 14U /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ 00661 #define ETH_CRC 4U /*!< Ethernet CRC */ 00662 #define ETH_EXTRA 2U /*!< Extra bytes in some cases */ 00663 #define ETH_VLAN_TAG 4U /*!< optional 802.1q VLAN Tag */ 00664 #define ETH_MIN_ETH_PAYLOAD 46U /*!< Minimum Ethernet payload size */ 00665 #define ETH_MAX_ETH_PAYLOAD 1500U /*!< Maximum Ethernet payload size */ 00666 #define ETH_JUMBO_FRAME_PAYLOAD 9000U /*!< Jumbo frame payload size */ 00667 00668 /* Ethernet driver receive buffers are organized in a chained linked-list, when 00669 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO 00670 to the driver receive buffers memory. 00671 00672 Depending on the size of the received ethernet packet and the size of 00673 each ethernet driver receive buffer, the received packet can take one or more 00674 ethernet driver receive buffer. 00675 00676 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE 00677 and the total count of the driver receive buffers ETH_RXBUFNB. 00678 00679 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as 00680 example, they can be reconfigured in the application layer to fit the application 00681 needs */ 00682 00683 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet 00684 packet */ 00685 #ifndef ETH_RX_BUF_SIZE 00686 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE 00687 #endif 00688 00689 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/ 00690 #ifndef ETH_RXBUFNB 00691 #define ETH_RXBUFNB 5U /* 5 Rx buffers of size ETH_RX_BUF_SIZE */ 00692 #endif 00693 00694 00695 /* Ethernet driver transmit buffers are organized in a chained linked-list, when 00696 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the 00697 driver transmit buffers memory to the TxFIFO. 00698 00699 Depending on the size of the Ethernet packet to be transmitted and the size of 00700 each ethernet driver transmit buffer, the packet to be transmitted can take 00701 one or more ethernet driver transmit buffer. 00702 00703 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE 00704 and the total count of the driver transmit buffers ETH_TXBUFNB. 00705 00706 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as 00707 example, they can be reconfigured in the application layer to fit the application 00708 needs */ 00709 00710 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet 00711 packet */ 00712 #ifndef ETH_TX_BUF_SIZE 00713 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE 00714 #endif 00715 00716 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/ 00717 #ifndef ETH_TXBUFNB 00718 #define ETH_TXBUFNB 5U /* 5 Tx buffers of size ETH_TX_BUF_SIZE */ 00719 #endif 00720 00721 /** 00722 * @} 00723 */ 00724 00725 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor 00726 * @{ 00727 */ 00728 00729 /* 00730 DMA Tx Descriptor 00731 ----------------------------------------------------------------------------------------------- 00732 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] | 00733 ----------------------------------------------------------------------------------------------- 00734 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | 00735 ----------------------------------------------------------------------------------------------- 00736 TDES2 | Buffer1 Address [31:0] | 00737 ----------------------------------------------------------------------------------------------- 00738 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 00739 ----------------------------------------------------------------------------------------------- 00740 */ 00741 00742 /** 00743 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register 00744 */ 00745 #define ETH_DMATXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 00746 #define ETH_DMATXDESC_IC 0x40000000U /*!< Interrupt on Completion */ 00747 #define ETH_DMATXDESC_LS 0x20000000U /*!< Last Segment */ 00748 #define ETH_DMATXDESC_FS 0x10000000U /*!< First Segment */ 00749 #define ETH_DMATXDESC_DC 0x08000000U /*!< Disable CRC */ 00750 #define ETH_DMATXDESC_DP 0x04000000U /*!< Disable Padding */ 00751 #define ETH_DMATXDESC_TTSE 0x02000000U /*!< Transmit Time Stamp Enable */ 00752 #define ETH_DMATXDESC_CIC 0x00C00000U /*!< Checksum Insertion Control: 4 cases */ 00753 #define ETH_DMATXDESC_CIC_BYPASS 0x00000000U /*!< Do Nothing: Checksum Engine is bypassed */ 00754 #define ETH_DMATXDESC_CIC_IPV4HEADER 0x00400000U /*!< IPV4 header Checksum Insertion */ 00755 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT 0x00800000U /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ 00756 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL 0x00C00000U /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ 00757 #define ETH_DMATXDESC_TER 0x00200000U /*!< Transmit End of Ring */ 00758 #define ETH_DMATXDESC_TCH 0x00100000U /*!< Second Address Chained */ 00759 #define ETH_DMATXDESC_TTSS 0x00020000U /*!< Tx Time Stamp Status */ 00760 #define ETH_DMATXDESC_IHE 0x00010000U /*!< IP Header Error */ 00761 #define ETH_DMATXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */ 00762 #define ETH_DMATXDESC_JT 0x00004000U /*!< Jabber Timeout */ 00763 #define ETH_DMATXDESC_FF 0x00002000U /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */ 00764 #define ETH_DMATXDESC_PCE 0x00001000U /*!< Payload Checksum Error */ 00765 #define ETH_DMATXDESC_LCA 0x00000800U /*!< Loss of Carrier: carrier lost during transmission */ 00766 #define ETH_DMATXDESC_NC 0x00000400U /*!< No Carrier: no carrier signal from the transceiver */ 00767 #define ETH_DMATXDESC_LCO 0x00000200U /*!< Late Collision: transmission aborted due to collision */ 00768 #define ETH_DMATXDESC_EC 0x00000100U /*!< Excessive Collision: transmission aborted after 16 collisions */ 00769 #define ETH_DMATXDESC_VF 0x00000080U /*!< VLAN Frame */ 00770 #define ETH_DMATXDESC_CC 0x00000078U /*!< Collision Count */ 00771 #define ETH_DMATXDESC_ED 0x00000004U /*!< Excessive Deferral */ 00772 #define ETH_DMATXDESC_UF 0x00000002U /*!< Underflow Error: late data arrival from the memory */ 00773 #define ETH_DMATXDESC_DB 0x00000001U /*!< Deferred Bit */ 00774 00775 /** 00776 * @brief Bit definition of TDES1 register 00777 */ 00778 #define ETH_DMATXDESC_TBS2 0x1FFF0000U /*!< Transmit Buffer2 Size */ 00779 #define ETH_DMATXDESC_TBS1 0x00001FFFU /*!< Transmit Buffer1 Size */ 00780 00781 /** 00782 * @brief Bit definition of TDES2 register 00783 */ 00784 #define ETH_DMATXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 00785 00786 /** 00787 * @brief Bit definition of TDES3 register 00788 */ 00789 #define ETH_DMATXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 00790 00791 /*--------------------------------------------------------------------------------------------- 00792 TDES6 | Transmit Time Stamp Low [31:0] | 00793 ----------------------------------------------------------------------------------------------- 00794 TDES7 | Transmit Time Stamp High [31:0] | 00795 ----------------------------------------------------------------------------------------------*/ 00796 00797 /* Bit definition of TDES6 register */ 00798 #define ETH_DMAPTPTXDESC_TTSL 0xFFFFFFFFU /* Transmit Time Stamp Low */ 00799 00800 /* Bit definition of TDES7 register */ 00801 #define ETH_DMAPTPTXDESC_TTSH 0xFFFFFFFFU /* Transmit Time Stamp High */ 00802 00803 /** 00804 * @} 00805 */ 00806 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor 00807 * @{ 00808 */ 00809 00810 /* 00811 DMA Rx Descriptor 00812 -------------------------------------------------------------------------------------------------------------------- 00813 RDES0 | OWN(31) | Status [30:0] | 00814 --------------------------------------------------------------------------------------------------------------------- 00815 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | 00816 --------------------------------------------------------------------------------------------------------------------- 00817 RDES2 | Buffer1 Address [31:0] | 00818 --------------------------------------------------------------------------------------------------------------------- 00819 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | 00820 --------------------------------------------------------------------------------------------------------------------- 00821 */ 00822 00823 /** 00824 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register 00825 */ 00826 #define ETH_DMARXDESC_OWN 0x80000000U /*!< OWN bit: descriptor is owned by DMA engine */ 00827 #define ETH_DMARXDESC_AFM 0x40000000U /*!< DA Filter Fail for the rx frame */ 00828 #define ETH_DMARXDESC_FL 0x3FFF0000U /*!< Receive descriptor frame length */ 00829 #define ETH_DMARXDESC_ES 0x00008000U /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */ 00830 #define ETH_DMARXDESC_DE 0x00004000U /*!< Descriptor error: no more descriptors for receive frame */ 00831 #define ETH_DMARXDESC_SAF 0x00002000U /*!< SA Filter Fail for the received frame */ 00832 #define ETH_DMARXDESC_LE 0x00001000U /*!< Frame size not matching with length field */ 00833 #define ETH_DMARXDESC_OE 0x00000800U /*!< Overflow Error: Frame was damaged due to buffer overflow */ 00834 #define ETH_DMARXDESC_VLAN 0x00000400U /*!< VLAN Tag: received frame is a VLAN frame */ 00835 #define ETH_DMARXDESC_FS 0x00000200U /*!< First descriptor of the frame */ 00836 #define ETH_DMARXDESC_LS 0x00000100U /*!< Last descriptor of the frame */ 00837 #define ETH_DMARXDESC_IPV4HCE 0x00000080U /*!< IPC Checksum Error: Rx Ipv4 header checksum error */ 00838 #define ETH_DMARXDESC_LC 0x00000040U /*!< Late collision occurred during reception */ 00839 #define ETH_DMARXDESC_FT 0x00000020U /*!< Frame type - Ethernet, otherwise 802.3 */ 00840 #define ETH_DMARXDESC_RWT 0x00000010U /*!< Receive Watchdog Timeout: watchdog timer expired during reception */ 00841 #define ETH_DMARXDESC_RE 0x00000008U /*!< Receive error: error reported by MII interface */ 00842 #define ETH_DMARXDESC_DBE 0x00000004U /*!< Dribble bit error: frame contains non int multiple of 8 bits */ 00843 #define ETH_DMARXDESC_CE 0x00000002U /*!< CRC error */ 00844 #define ETH_DMARXDESC_MAMPCE 0x00000001U /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */ 00845 00846 /** 00847 * @brief Bit definition of RDES1 register 00848 */ 00849 #define ETH_DMARXDESC_DIC 0x80000000U /*!< Disable Interrupt on Completion */ 00850 #define ETH_DMARXDESC_RBS2 0x1FFF0000U /*!< Receive Buffer2 Size */ 00851 #define ETH_DMARXDESC_RER 0x00008000U /*!< Receive End of Ring */ 00852 #define ETH_DMARXDESC_RCH 0x00004000U /*!< Second Address Chained */ 00853 #define ETH_DMARXDESC_RBS1 0x00001FFFU /*!< Receive Buffer1 Size */ 00854 00855 /** 00856 * @brief Bit definition of RDES2 register 00857 */ 00858 #define ETH_DMARXDESC_B1AP 0xFFFFFFFFU /*!< Buffer1 Address Pointer */ 00859 00860 /** 00861 * @brief Bit definition of RDES3 register 00862 */ 00863 #define ETH_DMARXDESC_B2AP 0xFFFFFFFFU /*!< Buffer2 Address Pointer */ 00864 00865 /*--------------------------------------------------------------------------------------------------------------------- 00866 RDES4 | Reserved[31:15] | Extended Status [14:0] | 00867 --------------------------------------------------------------------------------------------------------------------- 00868 RDES5 | Reserved[31:0] | 00869 --------------------------------------------------------------------------------------------------------------------- 00870 RDES6 | Receive Time Stamp Low [31:0] | 00871 --------------------------------------------------------------------------------------------------------------------- 00872 RDES7 | Receive Time Stamp High [31:0] | 00873 --------------------------------------------------------------------------------------------------------------------*/ 00874 00875 /* Bit definition of RDES4 register */ 00876 #define ETH_DMAPTPRXDESC_PTPV 0x00002000U /* PTP Version */ 00877 #define ETH_DMAPTPRXDESC_PTPFT 0x00001000U /* PTP Frame Type */ 00878 #define ETH_DMAPTPRXDESC_PTPMT 0x00000F00U /* PTP Message Type */ 00879 #define ETH_DMAPTPRXDESC_PTPMT_SYNC 0x00000100U /* SYNC message (all clock types) */ 00880 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP 0x00000200U /* FollowUp message (all clock types) */ 00881 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ 0x00000300U /* DelayReq message (all clock types) */ 00882 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP 0x00000400U /* DelayResp message (all clock types) */ 00883 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE 0x00000500U /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */ 00884 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG 0x00000600U /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */ 00885 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL 0x00000700U /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */ 00886 #define ETH_DMAPTPRXDESC_IPV6PR 0x00000080U /* IPv6 Packet Received */ 00887 #define ETH_DMAPTPRXDESC_IPV4PR 0x00000040U /* IPv4 Packet Received */ 00888 #define ETH_DMAPTPRXDESC_IPCB 0x00000020U /* IP Checksum Bypassed */ 00889 #define ETH_DMAPTPRXDESC_IPPE 0x00000010U /* IP Payload Error */ 00890 #define ETH_DMAPTPRXDESC_IPHE 0x00000008U /* IP Header Error */ 00891 #define ETH_DMAPTPRXDESC_IPPT 0x00000007U /* IP Payload Type */ 00892 #define ETH_DMAPTPRXDESC_IPPT_UDP 0x00000001U /* UDP payload encapsulated in the IP datagram */ 00893 #define ETH_DMAPTPRXDESC_IPPT_TCP 0x00000002U /* TCP payload encapsulated in the IP datagram */ 00894 #define ETH_DMAPTPRXDESC_IPPT_ICMP 0x00000003U /* ICMP payload encapsulated in the IP datagram */ 00895 00896 /* Bit definition of RDES6 register */ 00897 #define ETH_DMAPTPRXDESC_RTSL 0xFFFFFFFFU /* Receive Time Stamp Low */ 00898 00899 /* Bit definition of RDES7 register */ 00900 #define ETH_DMAPTPRXDESC_RTSH 0xFFFFFFFFU /* Receive Time Stamp High */ 00901 /** 00902 * @} 00903 */ 00904 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation 00905 * @{ 00906 */ 00907 #define ETH_AUTONEGOTIATION_ENABLE 0x00000001U 00908 #define ETH_AUTONEGOTIATION_DISABLE 0x00000000U 00909 00910 /** 00911 * @} 00912 */ 00913 /** @defgroup ETH_Speed ETH Speed 00914 * @{ 00915 */ 00916 #define ETH_SPEED_10M 0x00000000U 00917 #define ETH_SPEED_100M 0x00004000U 00918 00919 /** 00920 * @} 00921 */ 00922 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode 00923 * @{ 00924 */ 00925 #define ETH_MODE_FULLDUPLEX 0x00000800U 00926 #define ETH_MODE_HALFDUPLEX 0x00000000U 00927 /** 00928 * @} 00929 */ 00930 /** @defgroup ETH_Rx_Mode ETH Rx Mode 00931 * @{ 00932 */ 00933 #define ETH_RXPOLLING_MODE 0x00000000U 00934 #define ETH_RXINTERRUPT_MODE 0x00000001U 00935 /** 00936 * @} 00937 */ 00938 00939 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode 00940 * @{ 00941 */ 00942 #define ETH_CHECKSUM_BY_HARDWARE 0x00000000U 00943 #define ETH_CHECKSUM_BY_SOFTWARE 0x00000001U 00944 /** 00945 * @} 00946 */ 00947 00948 /** @defgroup ETH_Media_Interface ETH Media Interface 00949 * @{ 00950 */ 00951 #define ETH_MEDIA_INTERFACE_MII 0x00000000U 00952 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL) 00953 /** 00954 * @} 00955 */ 00956 00957 /** @defgroup ETH_Watchdog ETH Watchdog 00958 * @{ 00959 */ 00960 #define ETH_WATCHDOG_ENABLE 0x00000000U 00961 #define ETH_WATCHDOG_DISABLE 0x00800000U 00962 /** 00963 * @} 00964 */ 00965 00966 /** @defgroup ETH_Jabber ETH Jabber 00967 * @{ 00968 */ 00969 #define ETH_JABBER_ENABLE 0x00000000U 00970 #define ETH_JABBER_DISABLE 0x00400000U 00971 /** 00972 * @} 00973 */ 00974 00975 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap 00976 * @{ 00977 */ 00978 #define ETH_INTERFRAMEGAP_96BIT 0x00000000U /*!< minimum IFG between frames during transmission is 96Bit */ 00979 #define ETH_INTERFRAMEGAP_88BIT 0x00020000U /*!< minimum IFG between frames during transmission is 88Bit */ 00980 #define ETH_INTERFRAMEGAP_80BIT 0x00040000U /*!< minimum IFG between frames during transmission is 80Bit */ 00981 #define ETH_INTERFRAMEGAP_72BIT 0x00060000U /*!< minimum IFG between frames during transmission is 72Bit */ 00982 #define ETH_INTERFRAMEGAP_64BIT 0x00080000U /*!< minimum IFG between frames during transmission is 64Bit */ 00983 #define ETH_INTERFRAMEGAP_56BIT 0x000A0000U /*!< minimum IFG between frames during transmission is 56Bit */ 00984 #define ETH_INTERFRAMEGAP_48BIT 0x000C0000U /*!< minimum IFG between frames during transmission is 48Bit */ 00985 #define ETH_INTERFRAMEGAP_40BIT 0x000E0000U /*!< minimum IFG between frames during transmission is 40Bit */ 00986 /** 00987 * @} 00988 */ 00989 00990 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense 00991 * @{ 00992 */ 00993 #define ETH_CARRIERSENCE_ENABLE 0x00000000U 00994 #define ETH_CARRIERSENCE_DISABLE 0x00010000U 00995 /** 00996 * @} 00997 */ 00998 00999 /** @defgroup ETH_Receive_Own ETH Receive Own 01000 * @{ 01001 */ 01002 #define ETH_RECEIVEOWN_ENABLE 0x00000000U 01003 #define ETH_RECEIVEOWN_DISABLE 0x00002000U 01004 /** 01005 * @} 01006 */ 01007 01008 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode 01009 * @{ 01010 */ 01011 #define ETH_LOOPBACKMODE_ENABLE 0x00001000U 01012 #define ETH_LOOPBACKMODE_DISABLE 0x00000000U 01013 /** 01014 * @} 01015 */ 01016 01017 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload 01018 * @{ 01019 */ 01020 #define ETH_CHECKSUMOFFLAOD_ENABLE 0x00000400U 01021 #define ETH_CHECKSUMOFFLAOD_DISABLE 0x00000000U 01022 /** 01023 * @} 01024 */ 01025 01026 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission 01027 * @{ 01028 */ 01029 #define ETH_RETRYTRANSMISSION_ENABLE 0x00000000U 01030 #define ETH_RETRYTRANSMISSION_DISABLE 0x00000200U 01031 /** 01032 * @} 01033 */ 01034 01035 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip 01036 * @{ 01037 */ 01038 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE 0x00000080U 01039 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE 0x00000000U 01040 /** 01041 * @} 01042 */ 01043 01044 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit 01045 * @{ 01046 */ 01047 #define ETH_BACKOFFLIMIT_10 0x00000000U 01048 #define ETH_BACKOFFLIMIT_8 0x00000020U 01049 #define ETH_BACKOFFLIMIT_4 0x00000040U 01050 #define ETH_BACKOFFLIMIT_1 0x00000060U 01051 /** 01052 * @} 01053 */ 01054 01055 /** @defgroup ETH_Deferral_Check ETH Deferral Check 01056 * @{ 01057 */ 01058 #define ETH_DEFFERRALCHECK_ENABLE 0x00000010U 01059 #define ETH_DEFFERRALCHECK_DISABLE 0x00000000U 01060 /** 01061 * @} 01062 */ 01063 01064 /** @defgroup ETH_Receive_All ETH Receive All 01065 * @{ 01066 */ 01067 #define ETH_RECEIVEALL_ENABLE 0x80000000U 01068 #define ETH_RECEIVEAll_DISABLE 0x00000000U 01069 /** 01070 * @} 01071 */ 01072 01073 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter 01074 * @{ 01075 */ 01076 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE 0x00000200U 01077 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE 0x00000300U 01078 #define ETH_SOURCEADDRFILTER_DISABLE 0x00000000U 01079 /** 01080 * @} 01081 */ 01082 01083 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames 01084 * @{ 01085 */ 01086 #define ETH_PASSCONTROLFRAMES_BLOCKALL 0x00000040U /*!< MAC filters all control frames from reaching the application */ 01087 #define ETH_PASSCONTROLFRAMES_FORWARDALL 0x00000080U /*!< MAC forwards all control frames to application even if they fail the Address Filter */ 01088 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER 0x000000C0U /*!< MAC forwards control frames that pass the Address Filter. */ 01089 /** 01090 * @} 01091 */ 01092 01093 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception 01094 * @{ 01095 */ 01096 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE 0x00000000U 01097 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE 0x00000020U 01098 /** 01099 * @} 01100 */ 01101 01102 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter 01103 * @{ 01104 */ 01105 #define ETH_DESTINATIONADDRFILTER_NORMAL 0x00000000U 01106 #define ETH_DESTINATIONADDRFILTER_INVERSE 0x00000008U 01107 /** 01108 * @} 01109 */ 01110 01111 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode 01112 * @{ 01113 */ 01114 #define ETH_PROMISCUOUS_MODE_ENABLE 0x00000001U 01115 #define ETH_PROMISCUOUS_MODE_DISABLE 0x00000000U 01116 /** 01117 * @} 01118 */ 01119 01120 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter 01121 * @{ 01122 */ 01123 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000404U 01124 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE 0x00000004U 01125 #define ETH_MULTICASTFRAMESFILTER_PERFECT 0x00000000U 01126 #define ETH_MULTICASTFRAMESFILTER_NONE 0x00000010U 01127 /** 01128 * @} 01129 */ 01130 01131 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter 01132 * @{ 01133 */ 01134 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE 0x00000402U 01135 #define ETH_UNICASTFRAMESFILTER_HASHTABLE 0x00000002U 01136 #define ETH_UNICASTFRAMESFILTER_PERFECT 0x00000000U 01137 /** 01138 * @} 01139 */ 01140 01141 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause 01142 * @{ 01143 */ 01144 #define ETH_ZEROQUANTAPAUSE_ENABLE 0x00000000U 01145 #define ETH_ZEROQUANTAPAUSE_DISABLE 0x00000080U 01146 /** 01147 * @} 01148 */ 01149 01150 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold 01151 * @{ 01152 */ 01153 #define ETH_PAUSELOWTHRESHOLD_MINUS4 0x00000000U /*!< Pause time minus 4 slot times */ 01154 #define ETH_PAUSELOWTHRESHOLD_MINUS28 0x00000010U /*!< Pause time minus 28 slot times */ 01155 #define ETH_PAUSELOWTHRESHOLD_MINUS144 0x00000020U /*!< Pause time minus 144 slot times */ 01156 #define ETH_PAUSELOWTHRESHOLD_MINUS256 0x00000030U /*!< Pause time minus 256 slot times */ 01157 /** 01158 * @} 01159 */ 01160 01161 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect 01162 * @{ 01163 */ 01164 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE 0x00000008U 01165 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE 0x00000000U 01166 /** 01167 * @} 01168 */ 01169 01170 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control 01171 * @{ 01172 */ 01173 #define ETH_RECEIVEFLOWCONTROL_ENABLE 0x00000004U 01174 #define ETH_RECEIVEFLOWCONTROL_DISABLE 0x00000000U 01175 /** 01176 * @} 01177 */ 01178 01179 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control 01180 * @{ 01181 */ 01182 #define ETH_TRANSMITFLOWCONTROL_ENABLE 0x00000002U 01183 #define ETH_TRANSMITFLOWCONTROL_DISABLE 0x00000000U 01184 /** 01185 * @} 01186 */ 01187 01188 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison 01189 * @{ 01190 */ 01191 #define ETH_VLANTAGCOMPARISON_12BIT 0x00010000U 01192 #define ETH_VLANTAGCOMPARISON_16BIT 0x00000000U 01193 /** 01194 * @} 01195 */ 01196 01197 /** @defgroup ETH_MAC_addresses ETH MAC addresses 01198 * @{ 01199 */ 01200 #define ETH_MAC_ADDRESS0 0x00000000U 01201 #define ETH_MAC_ADDRESS1 0x00000008U 01202 #define ETH_MAC_ADDRESS2 0x00000010U 01203 #define ETH_MAC_ADDRESS3 0x00000018U 01204 /** 01205 * @} 01206 */ 01207 01208 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA 01209 * @{ 01210 */ 01211 #define ETH_MAC_ADDRESSFILTER_SA 0x00000000U 01212 #define ETH_MAC_ADDRESSFILTER_DA 0x00000008U 01213 /** 01214 * @} 01215 */ 01216 01217 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes 01218 * @{ 01219 */ 01220 #define ETH_MAC_ADDRESSMASK_BYTE6 0x20000000U /*!< Mask MAC Address high reg bits [15:8] */ 01221 #define ETH_MAC_ADDRESSMASK_BYTE5 0x10000000U /*!< Mask MAC Address high reg bits [7:0] */ 01222 #define ETH_MAC_ADDRESSMASK_BYTE4 0x08000000U /*!< Mask MAC Address low reg bits [31:24] */ 01223 #define ETH_MAC_ADDRESSMASK_BYTE3 0x04000000U /*!< Mask MAC Address low reg bits [23:16] */ 01224 #define ETH_MAC_ADDRESSMASK_BYTE2 0x02000000U /*!< Mask MAC Address low reg bits [15:8] */ 01225 #define ETH_MAC_ADDRESSMASK_BYTE1 0x01000000U /*!< Mask MAC Address low reg bits [70] */ 01226 /** 01227 * @} 01228 */ 01229 01230 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame 01231 * @{ 01232 */ 01233 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE 0x00000000U 01234 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE 0x04000000U 01235 /** 01236 * @} 01237 */ 01238 01239 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward 01240 * @{ 01241 */ 01242 #define ETH_RECEIVESTOREFORWARD_ENABLE 0x02000000U 01243 #define ETH_RECEIVESTOREFORWARD_DISABLE 0x00000000U 01244 /** 01245 * @} 01246 */ 01247 01248 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame 01249 * @{ 01250 */ 01251 #define ETH_FLUSHRECEIVEDFRAME_ENABLE 0x00000000U 01252 #define ETH_FLUSHRECEIVEDFRAME_DISABLE 0x01000000U 01253 /** 01254 * @} 01255 */ 01256 01257 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward 01258 * @{ 01259 */ 01260 #define ETH_TRANSMITSTOREFORWARD_ENABLE 0x00200000U 01261 #define ETH_TRANSMITSTOREFORWARD_DISABLE 0x00000000U 01262 /** 01263 * @} 01264 */ 01265 01266 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control 01267 * @{ 01268 */ 01269 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */ 01270 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES 0x00004000U /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */ 01271 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES 0x00008000U /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */ 01272 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES 0x0000C000U /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */ 01273 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES 0x00010000U /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */ 01274 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES 0x00014000U /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */ 01275 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES 0x00018000U /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */ 01276 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES 0x0001C000U /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */ 01277 /** 01278 * @} 01279 */ 01280 01281 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames 01282 * @{ 01283 */ 01284 #define ETH_FORWARDERRORFRAMES_ENABLE 0x00000080U 01285 #define ETH_FORWARDERRORFRAMES_DISABLE 0x00000000U 01286 /** 01287 * @} 01288 */ 01289 01290 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames 01291 * @{ 01292 */ 01293 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE 0x00000040U 01294 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE 0x00000000U 01295 /** 01296 * @} 01297 */ 01298 01299 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control 01300 * @{ 01301 */ 01302 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES 0x00000000U /*!< threshold level of the MTL Receive FIFO is 64 Bytes */ 01303 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES 0x00000008U /*!< threshold level of the MTL Receive FIFO is 32 Bytes */ 01304 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES 0x00000010U /*!< threshold level of the MTL Receive FIFO is 96 Bytes */ 01305 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES 0x00000018U /*!< threshold level of the MTL Receive FIFO is 128 Bytes */ 01306 /** 01307 * @} 01308 */ 01309 01310 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate 01311 * @{ 01312 */ 01313 #define ETH_SECONDFRAMEOPERARTE_ENABLE 0x00000004U 01314 #define ETH_SECONDFRAMEOPERARTE_DISABLE 0x00000000U 01315 /** 01316 * @} 01317 */ 01318 01319 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats 01320 * @{ 01321 */ 01322 #define ETH_ADDRESSALIGNEDBEATS_ENABLE 0x02000000U 01323 #define ETH_ADDRESSALIGNEDBEATS_DISABLE 0x00000000U 01324 /** 01325 * @} 01326 */ 01327 01328 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst 01329 * @{ 01330 */ 01331 #define ETH_FIXEDBURST_ENABLE 0x00010000U 01332 #define ETH_FIXEDBURST_DISABLE 0x00000000U 01333 /** 01334 * @} 01335 */ 01336 01337 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length 01338 * @{ 01339 */ 01340 #define ETH_RXDMABURSTLENGTH_1BEAT 0x00020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */ 01341 #define ETH_RXDMABURSTLENGTH_2BEAT 0x00040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */ 01342 #define ETH_RXDMABURSTLENGTH_4BEAT 0x00080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 01343 #define ETH_RXDMABURSTLENGTH_8BEAT 0x00100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 01344 #define ETH_RXDMABURSTLENGTH_16BEAT 0x00200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 01345 #define ETH_RXDMABURSTLENGTH_32BEAT 0x00400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 01346 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT 0x01020000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */ 01347 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT 0x01040000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */ 01348 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT 0x01080000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */ 01349 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT 0x01100000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */ 01350 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT 0x01200000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */ 01351 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT 0x01400000U /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */ 01352 /** 01353 * @} 01354 */ 01355 01356 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length 01357 * @{ 01358 */ 01359 #define ETH_TXDMABURSTLENGTH_1BEAT 0x00000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ 01360 #define ETH_TXDMABURSTLENGTH_2BEAT 0x00000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ 01361 #define ETH_TXDMABURSTLENGTH_4BEAT 0x00000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 01362 #define ETH_TXDMABURSTLENGTH_8BEAT 0x00000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 01363 #define ETH_TXDMABURSTLENGTH_16BEAT 0x00001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 01364 #define ETH_TXDMABURSTLENGTH_32BEAT 0x00002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 01365 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT 0x01000100U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ 01366 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT 0x01000200U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ 01367 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT 0x01000400U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ 01368 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT 0x01000800U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ 01369 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT 0x01001000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ 01370 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT 0x01002000U /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ 01371 /** 01372 * @} 01373 */ 01374 01375 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format 01376 * @{ 01377 */ 01378 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE 0x00000080U 01379 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE 0x00000000U 01380 /** 01381 * @} 01382 */ 01383 01384 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration 01385 * @{ 01386 */ 01387 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 0x00000000U 01388 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 0x00004000U 01389 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 0x00008000U 01390 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 0x0000C000U 01391 #define ETH_DMAARBITRATION_RXPRIORTX 0x00000002U 01392 /** 01393 * @} 01394 */ 01395 01396 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment 01397 * @{ 01398 */ 01399 #define ETH_DMATXDESC_LASTSEGMENTS 0x40000000U /*!< Last Segment */ 01400 #define ETH_DMATXDESC_FIRSTSEGMENT 0x20000000U /*!< First Segment */ 01401 /** 01402 * @} 01403 */ 01404 01405 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control 01406 * @{ 01407 */ 01408 #define ETH_DMATXDESC_CHECKSUMBYPASS 0x00000000U /*!< Checksum engine bypass */ 01409 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER 0x00400000U /*!< IPv4 header checksum insertion */ 01410 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT 0x00800000U /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */ 01411 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL 0x00C00000U /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */ 01412 /** 01413 * @} 01414 */ 01415 01416 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers 01417 * @{ 01418 */ 01419 #define ETH_DMARXDESC_BUFFER1 0x00000000U /*!< DMA Rx Desc Buffer1 */ 01420 #define ETH_DMARXDESC_BUFFER2 0x00000001U /*!< DMA Rx Desc Buffer2 */ 01421 /** 01422 * @} 01423 */ 01424 01425 /** @defgroup ETH_PMT_Flags ETH PMT Flags 01426 * @{ 01427 */ 01428 #define ETH_PMT_FLAG_WUFFRPR 0x80000000U /*!< Wake-Up Frame Filter Register Pointer Reset */ 01429 #define ETH_PMT_FLAG_WUFR 0x00000040U /*!< Wake-Up Frame Received */ 01430 #define ETH_PMT_FLAG_MPR 0x00000020U /*!< Magic Packet Received */ 01431 /** 01432 * @} 01433 */ 01434 01435 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts 01436 * @{ 01437 */ 01438 #define ETH_MMC_IT_TGF 0x00200000U /*!< When Tx good frame counter reaches half the maximum value */ 01439 #define ETH_MMC_IT_TGFMSC 0x00008000U /*!< When Tx good multi col counter reaches half the maximum value */ 01440 #define ETH_MMC_IT_TGFSC 0x00004000U /*!< When Tx good single col counter reaches half the maximum value */ 01441 /** 01442 * @} 01443 */ 01444 01445 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts 01446 * @{ 01447 */ 01448 #define ETH_MMC_IT_RGUF 0x10020000U /*!< When Rx good unicast frames counter reaches half the maximum value */ 01449 #define ETH_MMC_IT_RFAE 0x10000040U /*!< When Rx alignment error counter reaches half the maximum value */ 01450 #define ETH_MMC_IT_RFCE 0x10000020U /*!< When Rx crc error counter reaches half the maximum value */ 01451 /** 01452 * @} 01453 */ 01454 01455 /** @defgroup ETH_MAC_Flags ETH MAC Flags 01456 * @{ 01457 */ 01458 #define ETH_MAC_FLAG_TST 0x00000200U /*!< Time stamp trigger flag (on MAC) */ 01459 #define ETH_MAC_FLAG_MMCT 0x00000040U /*!< MMC transmit flag */ 01460 #define ETH_MAC_FLAG_MMCR 0x00000020U /*!< MMC receive flag */ 01461 #define ETH_MAC_FLAG_MMC 0x00000010U /*!< MMC flag (on MAC) */ 01462 #define ETH_MAC_FLAG_PMT 0x00000008U /*!< PMT flag (on MAC) */ 01463 /** 01464 * @} 01465 */ 01466 01467 /** @defgroup ETH_DMA_Flags ETH DMA Flags 01468 * @{ 01469 */ 01470 #define ETH_DMA_FLAG_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 01471 #define ETH_DMA_FLAG_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 01472 #define ETH_DMA_FLAG_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 01473 #define ETH_DMA_FLAG_DATATRANSFERERROR 0x00800000U /*!< Error bits 0-Rx DMA, 1-Tx DMA */ 01474 #define ETH_DMA_FLAG_READWRITEERROR 0x01000000U /*!< Error bits 0-write transfer, 1-read transfer */ 01475 #define ETH_DMA_FLAG_ACCESSERROR 0x02000000U /*!< Error bits 0-data buffer, 1-desc. access */ 01476 #define ETH_DMA_FLAG_NIS 0x00010000U /*!< Normal interrupt summary flag */ 01477 #define ETH_DMA_FLAG_AIS 0x00008000U /*!< Abnormal interrupt summary flag */ 01478 #define ETH_DMA_FLAG_ER 0x00004000U /*!< Early receive flag */ 01479 #define ETH_DMA_FLAG_FBE 0x00002000U /*!< Fatal bus error flag */ 01480 #define ETH_DMA_FLAG_ET 0x00000400U /*!< Early transmit flag */ 01481 #define ETH_DMA_FLAG_RWT 0x00000200U /*!< Receive watchdog timeout flag */ 01482 #define ETH_DMA_FLAG_RPS 0x00000100U /*!< Receive process stopped flag */ 01483 #define ETH_DMA_FLAG_RBU 0x00000080U /*!< Receive buffer unavailable flag */ 01484 #define ETH_DMA_FLAG_R 0x00000040U /*!< Receive flag */ 01485 #define ETH_DMA_FLAG_TU 0x00000020U /*!< Underflow flag */ 01486 #define ETH_DMA_FLAG_RO 0x00000010U /*!< Overflow flag */ 01487 #define ETH_DMA_FLAG_TJT 0x00000008U /*!< Transmit jabber timeout flag */ 01488 #define ETH_DMA_FLAG_TBU 0x00000004U /*!< Transmit buffer unavailable flag */ 01489 #define ETH_DMA_FLAG_TPS 0x00000002U /*!< Transmit process stopped flag */ 01490 #define ETH_DMA_FLAG_T 0x00000001U /*!< Transmit flag */ 01491 /** 01492 * @} 01493 */ 01494 01495 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts 01496 * @{ 01497 */ 01498 #define ETH_MAC_IT_TST 0x00000200U /*!< Time stamp trigger interrupt (on MAC) */ 01499 #define ETH_MAC_IT_MMCT 0x00000040U /*!< MMC transmit interrupt */ 01500 #define ETH_MAC_IT_MMCR 0x00000020U /*!< MMC receive interrupt */ 01501 #define ETH_MAC_IT_MMC 0x00000010U /*!< MMC interrupt (on MAC) */ 01502 #define ETH_MAC_IT_PMT 0x00000008U /*!< PMT interrupt (on MAC) */ 01503 /** 01504 * @} 01505 */ 01506 01507 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts 01508 * @{ 01509 */ 01510 #define ETH_DMA_IT_TST 0x20000000U /*!< Time-stamp trigger interrupt (on DMA) */ 01511 #define ETH_DMA_IT_PMT 0x10000000U /*!< PMT interrupt (on DMA) */ 01512 #define ETH_DMA_IT_MMC 0x08000000U /*!< MMC interrupt (on DMA) */ 01513 #define ETH_DMA_IT_NIS 0x00010000U /*!< Normal interrupt summary */ 01514 #define ETH_DMA_IT_AIS 0x00008000U /*!< Abnormal interrupt summary */ 01515 #define ETH_DMA_IT_ER 0x00004000U /*!< Early receive interrupt */ 01516 #define ETH_DMA_IT_FBE 0x00002000U /*!< Fatal bus error interrupt */ 01517 #define ETH_DMA_IT_ET 0x00000400U /*!< Early transmit interrupt */ 01518 #define ETH_DMA_IT_RWT 0x00000200U /*!< Receive watchdog timeout interrupt */ 01519 #define ETH_DMA_IT_RPS 0x00000100U /*!< Receive process stopped interrupt */ 01520 #define ETH_DMA_IT_RBU 0x00000080U /*!< Receive buffer unavailable interrupt */ 01521 #define ETH_DMA_IT_R 0x00000040U /*!< Receive interrupt */ 01522 #define ETH_DMA_IT_TU 0x00000020U /*!< Underflow interrupt */ 01523 #define ETH_DMA_IT_RO 0x00000010U /*!< Overflow interrupt */ 01524 #define ETH_DMA_IT_TJT 0x00000008U /*!< Transmit jabber timeout interrupt */ 01525 #define ETH_DMA_IT_TBU 0x00000004U /*!< Transmit buffer unavailable interrupt */ 01526 #define ETH_DMA_IT_TPS 0x00000002U /*!< Transmit process stopped interrupt */ 01527 #define ETH_DMA_IT_T 0x00000001U /*!< Transmit interrupt */ 01528 /** 01529 * @} 01530 */ 01531 01532 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state 01533 * @{ 01534 */ 01535 #define ETH_DMA_TRANSMITPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Tx Command issued */ 01536 #define ETH_DMA_TRANSMITPROCESS_FETCHING 0x00100000U /*!< Running - fetching the Tx descriptor */ 01537 #define ETH_DMA_TRANSMITPROCESS_WAITING 0x00200000U /*!< Running - waiting for status */ 01538 #define ETH_DMA_TRANSMITPROCESS_READING 0x00300000U /*!< Running - reading the data from host memory */ 01539 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED 0x00600000U /*!< Suspended - Tx Descriptor unavailable */ 01540 #define ETH_DMA_TRANSMITPROCESS_CLOSING 0x00700000U /*!< Running - closing Rx descriptor */ 01541 01542 /** 01543 * @} 01544 */ 01545 01546 01547 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state 01548 * @{ 01549 */ 01550 #define ETH_DMA_RECEIVEPROCESS_STOPPED 0x00000000U /*!< Stopped - Reset or Stop Rx Command issued */ 01551 #define ETH_DMA_RECEIVEPROCESS_FETCHING 0x00020000U /*!< Running - fetching the Rx descriptor */ 01552 #define ETH_DMA_RECEIVEPROCESS_WAITING 0x00060000U /*!< Running - waiting for packet */ 01553 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED 0x00080000U /*!< Suspended - Rx Descriptor unavailable */ 01554 #define ETH_DMA_RECEIVEPROCESS_CLOSING 0x000A0000U /*!< Running - closing descriptor */ 01555 #define ETH_DMA_RECEIVEPROCESS_QUEUING 0x000E0000U /*!< Running - queuing the receive frame into host memory */ 01556 01557 /** 01558 * @} 01559 */ 01560 01561 /** @defgroup ETH_DMA_overflow ETH DMA overflow 01562 * @{ 01563 */ 01564 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER 0x10000000U /*!< Overflow bit for FIFO overflow counter */ 01565 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER 0x00010000U /*!< Overflow bit for missed frame counter */ 01566 /** 01567 * @} 01568 */ 01569 01570 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP 01571 * @{ 01572 */ 01573 #define ETH_EXTI_LINE_WAKEUP 0x00080000U /*!< External interrupt line 19 Connected to the ETH EXTI Line */ 01574 01575 /** 01576 * @} 01577 */ 01578 01579 /** 01580 * @} 01581 */ 01582 01583 /* Exported macro ------------------------------------------------------------*/ 01584 /** @defgroup ETH_Exported_Macros ETH Exported Macros 01585 * @brief macros to handle interrupts and specific clock configurations 01586 * @{ 01587 */ 01588 01589 /** @brief Reset ETH handle state 01590 * @param __HANDLE__ specifies the ETH handle. 01591 * @retval None 01592 */ 01593 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET) 01594 01595 /** 01596 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not. 01597 * @param __HANDLE__ ETH Handle 01598 * @param __FLAG__ specifies the flag of TDES0 to check. 01599 * @retval the ETH_DMATxDescFlag (SET or RESET). 01600 */ 01601 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__)) 01602 01603 /** 01604 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not. 01605 * @param __HANDLE__ ETH Handle 01606 * @param __FLAG__ specifies the flag of RDES0 to check. 01607 * @retval the ETH_DMATxDescFlag (SET or RESET). 01608 */ 01609 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__)) 01610 01611 /** 01612 * @brief Enables the specified DMA Rx Desc receive interrupt. 01613 * @param __HANDLE__ ETH Handle 01614 * @retval None 01615 */ 01616 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC)) 01617 01618 /** 01619 * @brief Disables the specified DMA Rx Desc receive interrupt. 01620 * @param __HANDLE__ ETH Handle 01621 * @retval None 01622 */ 01623 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC) 01624 01625 /** 01626 * @brief Set the specified DMA Rx Desc Own bit. 01627 * @param __HANDLE__ ETH Handle 01628 * @retval None 01629 */ 01630 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN) 01631 01632 /** 01633 * @brief Returns the specified ETHERNET DMA Tx Desc collision count. 01634 * @param __HANDLE__ ETH Handle 01635 * @retval The Transmit descriptor collision counter value. 01636 */ 01637 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) 01638 01639 /** 01640 * @brief Set the specified DMA Tx Desc Own bit. 01641 * @param __HANDLE__ ETH Handle 01642 * @retval None 01643 */ 01644 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN) 01645 01646 /** 01647 * @brief Enables the specified DMA Tx Desc Transmit interrupt. 01648 * @param __HANDLE__ ETH Handle 01649 * @retval None 01650 */ 01651 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC) 01652 01653 /** 01654 * @brief Disables the specified DMA Tx Desc Transmit interrupt. 01655 * @param __HANDLE__ ETH Handle 01656 * @retval None 01657 */ 01658 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC) 01659 01660 /** 01661 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion. 01662 * @param __HANDLE__ ETH Handle 01663 * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion. 01664 * This parameter can be one of the following values: 01665 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass 01666 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum 01667 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present 01668 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header 01669 * @retval None 01670 */ 01671 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__)) 01672 01673 /** 01674 * @brief Enables the DMA Tx Desc CRC. 01675 * @param __HANDLE__ ETH Handle 01676 * @retval None 01677 */ 01678 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC) 01679 01680 /** 01681 * @brief Disables the DMA Tx Desc CRC. 01682 * @param __HANDLE__ ETH Handle 01683 * @retval None 01684 */ 01685 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC) 01686 01687 /** 01688 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes. 01689 * @param __HANDLE__ ETH Handle 01690 * @retval None 01691 */ 01692 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP) 01693 01694 /** 01695 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes. 01696 * @param __HANDLE__ ETH Handle 01697 * @retval None 01698 */ 01699 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP) 01700 01701 /** 01702 * @brief Enables the specified ETHERNET MAC interrupts. 01703 * @param __HANDLE__ ETH Handle 01704 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be 01705 * enabled or disabled. 01706 * This parameter can be any combination of the following values: 01707 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 01708 * @arg ETH_MAC_IT_PMT : PMT interrupt 01709 * @retval None 01710 */ 01711 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__)) 01712 01713 /** 01714 * @brief Disables the specified ETHERNET MAC interrupts. 01715 * @param __HANDLE__ ETH Handle 01716 * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be 01717 * enabled or disabled. 01718 * This parameter can be any combination of the following values: 01719 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt 01720 * @arg ETH_MAC_IT_PMT : PMT interrupt 01721 * @retval None 01722 */ 01723 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__)) 01724 01725 /** 01726 * @brief Initiate a Pause Control Frame (Full-duplex only). 01727 * @param __HANDLE__ ETH Handle 01728 * @retval None 01729 */ 01730 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 01731 01732 /** 01733 * @brief Checks whether the ETHERNET flow control busy bit is set or not. 01734 * @param __HANDLE__ ETH Handle 01735 * @retval The new state of flow control busy status bit (SET or RESET). 01736 */ 01737 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA) 01738 01739 /** 01740 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only). 01741 * @param __HANDLE__ ETH Handle 01742 * @retval None 01743 */ 01744 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA) 01745 01746 /** 01747 * @brief Disables the MAC BackPressure operation activation (Half-duplex only). 01748 * @param __HANDLE__ ETH Handle 01749 * @retval None 01750 */ 01751 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA) 01752 01753 /** 01754 * @brief Checks whether the specified ETHERNET MAC flag is set or not. 01755 * @param __HANDLE__ ETH Handle 01756 * @param __FLAG__ specifies the flag to check. 01757 * This parameter can be one of the following values: 01758 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag 01759 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag 01760 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag 01761 * @arg ETH_MAC_FLAG_MMC : MMC flag 01762 * @arg ETH_MAC_FLAG_PMT : PMT flag 01763 * @retval The state of ETHERNET MAC flag. 01764 */ 01765 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__)) 01766 01767 /** 01768 * @brief Enables the specified ETHERNET DMA interrupts. 01769 * @param __HANDLE__ ETH Handle 01770 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be 01771 * enabled @ref ETH_DMA_Interrupts 01772 * @retval None 01773 */ 01774 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__)) 01775 01776 /** 01777 * @brief Disables the specified ETHERNET DMA interrupts. 01778 * @param __HANDLE__ ETH Handle 01779 * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be 01780 * disabled. @ref ETH_DMA_Interrupts 01781 * @retval None 01782 */ 01783 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__)) 01784 01785 /** 01786 * @brief Clears the ETHERNET DMA IT pending bit. 01787 * @param __HANDLE__ ETH Handle 01788 * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts 01789 * @retval None 01790 */ 01791 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__)) 01792 01793 /** 01794 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 01795 * @param __HANDLE__ ETH Handle 01796 * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags 01797 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 01798 */ 01799 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__)) 01800 01801 /** 01802 * @brief Checks whether the specified ETHERNET DMA flag is set or not. 01803 * @param __HANDLE__ ETH Handle 01804 * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags 01805 * @retval The new state of ETH_DMA_FLAG (SET or RESET). 01806 */ 01807 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__)) 01808 01809 /** 01810 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not. 01811 * @param __HANDLE__ ETH Handle 01812 * @param __OVERFLOW__ specifies the DMA overflow flag to check. 01813 * This parameter can be one of the following values: 01814 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter 01815 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter 01816 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET). 01817 */ 01818 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__)) 01819 01820 /** 01821 * @brief Set the DMA Receive status watchdog timer register value 01822 * @param __HANDLE__ ETH Handle 01823 * @param __VALUE__ DMA Receive status watchdog timer register value 01824 * @retval None 01825 */ 01826 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__)) 01827 01828 /** 01829 * @brief Enables any unicast packet filtered by the MAC address 01830 * recognition to be a wake-up frame. 01831 * @param __HANDLE__ ETH Handle. 01832 * @retval None 01833 */ 01834 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU) 01835 01836 /** 01837 * @brief Disables any unicast packet filtered by the MAC address 01838 * recognition to be a wake-up frame. 01839 * @param __HANDLE__ ETH Handle. 01840 * @retval None 01841 */ 01842 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU) 01843 01844 /** 01845 * @brief Enables the MAC Wake-Up Frame Detection. 01846 * @param __HANDLE__ ETH Handle. 01847 * @retval None 01848 */ 01849 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE) 01850 01851 /** 01852 * @brief Disables the MAC Wake-Up Frame Detection. 01853 * @param __HANDLE__ ETH Handle. 01854 * @retval None 01855 */ 01856 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 01857 01858 /** 01859 * @brief Enables the MAC Magic Packet Detection. 01860 * @param __HANDLE__ ETH Handle. 01861 * @retval None 01862 */ 01863 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE) 01864 01865 /** 01866 * @brief Disables the MAC Magic Packet Detection. 01867 * @param __HANDLE__ ETH Handle. 01868 * @retval None 01869 */ 01870 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE) 01871 01872 /** 01873 * @brief Enables the MAC Power Down. 01874 * @param __HANDLE__ ETH Handle 01875 * @retval None 01876 */ 01877 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD) 01878 01879 /** 01880 * @brief Disables the MAC Power Down. 01881 * @param __HANDLE__ ETH Handle 01882 * @retval None 01883 */ 01884 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD) 01885 01886 /** 01887 * @brief Checks whether the specified ETHERNET PMT flag is set or not. 01888 * @param __HANDLE__ ETH Handle. 01889 * @param __FLAG__ specifies the flag to check. 01890 * This parameter can be one of the following values: 01891 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset 01892 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received 01893 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received 01894 * @retval The new state of ETHERNET PMT Flag (SET or RESET). 01895 */ 01896 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__)) 01897 01898 /** 01899 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16) 01900 * @param __HANDLE__ ETH Handle. 01901 * @retval None 01902 */ 01903 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP)) 01904 01905 /** 01906 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16) 01907 * @param __HANDLE__ ETH Handle. 01908 * @retval None 01909 */ 01910 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\ 01911 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0) 01912 01913 /** 01914 * @brief Enables the MMC Counter Freeze. 01915 * @param __HANDLE__ ETH Handle. 01916 * @retval None 01917 */ 01918 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF) 01919 01920 /** 01921 * @brief Disables the MMC Counter Freeze. 01922 * @param __HANDLE__ ETH Handle. 01923 * @retval None 01924 */ 01925 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF) 01926 01927 /** 01928 * @brief Enables the MMC Reset On Read. 01929 * @param __HANDLE__ ETH Handle. 01930 * @retval None 01931 */ 01932 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR) 01933 01934 /** 01935 * @brief Disables the MMC Reset On Read. 01936 * @param __HANDLE__ ETH Handle. 01937 * @retval None 01938 */ 01939 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR) 01940 01941 /** 01942 * @brief Enables the MMC Counter Stop Rollover. 01943 * @param __HANDLE__ ETH Handle. 01944 * @retval None 01945 */ 01946 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR) 01947 01948 /** 01949 * @brief Disables the MMC Counter Stop Rollover. 01950 * @param __HANDLE__ ETH Handle. 01951 * @retval None 01952 */ 01953 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR) 01954 01955 /** 01956 * @brief Resets the MMC Counters. 01957 * @param __HANDLE__ ETH Handle. 01958 * @retval None 01959 */ 01960 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR) 01961 01962 /** 01963 * @brief Enables the specified ETHERNET MMC Rx interrupts. 01964 * @param __HANDLE__ ETH Handle. 01965 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 01966 * This parameter can be one of the following values: 01967 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 01968 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 01969 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 01970 * @retval None 01971 */ 01972 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU) 01973 /** 01974 * @brief Disables the specified ETHERNET MMC Rx interrupts. 01975 * @param __HANDLE__ ETH Handle. 01976 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 01977 * This parameter can be one of the following values: 01978 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value 01979 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value 01980 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value 01981 * @retval None 01982 */ 01983 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU) 01984 /** 01985 * @brief Enables the specified ETHERNET MMC Tx interrupts. 01986 * @param __HANDLE__ ETH Handle. 01987 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 01988 * This parameter can be one of the following values: 01989 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 01990 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 01991 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 01992 * @retval None 01993 */ 01994 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__)) 01995 01996 /** 01997 * @brief Disables the specified ETHERNET MMC Tx interrupts. 01998 * @param __HANDLE__ ETH Handle. 01999 * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled. 02000 * This parameter can be one of the following values: 02001 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value 02002 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value 02003 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value 02004 * @retval None 02005 */ 02006 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__)) 02007 02008 /** 02009 * @brief Enables the ETH External interrupt line. 02010 * @retval None 02011 */ 02012 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP) 02013 02014 /** 02015 * @brief Disables the ETH External interrupt line. 02016 * @retval None 02017 */ 02018 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP) 02019 02020 /** 02021 * @brief Enable event on ETH External event line. 02022 * @retval None. 02023 */ 02024 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP) 02025 02026 /** 02027 * @brief Disable event on ETH External event line 02028 * @retval None. 02029 */ 02030 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP) 02031 02032 /** 02033 * @brief Get flag of the ETH External interrupt line. 02034 * @retval None 02035 */ 02036 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP) 02037 02038 /** 02039 * @brief Clear flag of the ETH External interrupt line. 02040 * @retval None 02041 */ 02042 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP) 02043 02044 /** 02045 * @brief Enables rising edge trigger to the ETH External interrupt line. 02046 * @retval None 02047 */ 02048 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP 02049 02050 /** 02051 * @brief Disables the rising edge trigger to the ETH External interrupt line. 02052 * @retval None 02053 */ 02054 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP) 02055 02056 /** 02057 * @brief Enables falling edge trigger to the ETH External interrupt line. 02058 * @retval None 02059 */ 02060 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP) 02061 02062 /** 02063 * @brief Disables falling edge trigger to the ETH External interrupt line. 02064 * @retval None 02065 */ 02066 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP) 02067 02068 /** 02069 * @brief Enables rising/falling edge trigger to the ETH External interrupt line. 02070 * @retval None 02071 */ 02072 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\ 02073 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\ 02074 }while(0U) 02075 02076 /** 02077 * @brief Disables rising/falling edge trigger to the ETH External interrupt line. 02078 * @retval None 02079 */ 02080 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 02081 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\ 02082 }while(0U) 02083 02084 /** 02085 * @brief Generate a Software interrupt on selected EXTI line. 02086 * @retval None. 02087 */ 02088 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP 02089 02090 /** 02091 * @} 02092 */ 02093 /* Exported functions --------------------------------------------------------*/ 02094 02095 /** @addtogroup ETH_Exported_Functions 02096 * @{ 02097 */ 02098 02099 /* Initialization and de-initialization functions ****************************/ 02100 02101 /** @addtogroup ETH_Exported_Functions_Group1 02102 * @{ 02103 */ 02104 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth); 02105 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth); 02106 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth); 02107 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth); 02108 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount); 02109 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount); 02110 02111 /** 02112 * @} 02113 */ 02114 /* IO operation functions ****************************************************/ 02115 02116 /** @addtogroup ETH_Exported_Functions_Group2 02117 * @{ 02118 */ 02119 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength); 02120 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth); 02121 /* Communication with PHY functions*/ 02122 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue); 02123 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue); 02124 /* Non-Blocking mode: Interrupt */ 02125 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth); 02126 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth); 02127 /* Callback in non blocking modes (Interrupt) */ 02128 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth); 02129 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth); 02130 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth); 02131 /** 02132 * @} 02133 */ 02134 02135 /* Peripheral Control functions **********************************************/ 02136 02137 /** @addtogroup ETH_Exported_Functions_Group3 02138 * @{ 02139 */ 02140 02141 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth); 02142 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth); 02143 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf); 02144 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf); 02145 /** 02146 * @} 02147 */ 02148 02149 /* Peripheral State functions ************************************************/ 02150 02151 /** @addtogroup ETH_Exported_Functions_Group4 02152 * @{ 02153 */ 02154 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth); 02155 /** 02156 * @} 02157 */ 02158 02159 /** 02160 * @} 02161 */ 02162 02163 /** 02164 * @} 02165 */ 02166 02167 /** 02168 * @} 02169 */ 02170 02171 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\ 02172 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */ 02173 02174 #ifdef __cplusplus 02175 } 02176 #endif 02177 02178 #endif /* __STM32F4xx_HAL_ETH_H */ 02179 02180 02181 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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