STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_hal_adc_ex.c 00004 * @author MCD Application Team 00005 * @brief This file provides firmware functions to manage the following 00006 * functionalities of the ADC extension peripheral: 00007 * + Extended features functions 00008 * 00009 @verbatim 00010 ============================================================================== 00011 ##### How to use this driver ##### 00012 ============================================================================== 00013 [..] 00014 (#)Initialize the ADC low level resources by implementing the HAL_ADC_MspInit(): 00015 (##) Enable the ADC interface clock using __HAL_RCC_ADC_CLK_ENABLE() 00016 (##) ADC pins configuration 00017 (+++) Enable the clock for the ADC GPIOs using the following function: 00018 __HAL_RCC_GPIOx_CLK_ENABLE() 00019 (+++) Configure these ADC pins in analog mode using HAL_GPIO_Init() 00020 (##) In case of using interrupts (e.g. HAL_ADC_Start_IT()) 00021 (+++) Configure the ADC interrupt priority using HAL_NVIC_SetPriority() 00022 (+++) Enable the ADC IRQ handler using HAL_NVIC_EnableIRQ() 00023 (+++) In ADC IRQ handler, call HAL_ADC_IRQHandler() 00024 (##) In case of using DMA to control data transfer (e.g. HAL_ADC_Start_DMA()) 00025 (+++) Enable the DMAx interface clock using __HAL_RCC_DMAx_CLK_ENABLE() 00026 (+++) Configure and enable two DMA streams stream for managing data 00027 transfer from peripheral to memory (output stream) 00028 (+++) Associate the initialized DMA handle to the ADC DMA handle 00029 using __HAL_LINKDMA() 00030 (+++) Configure the priority and enable the NVIC for the transfer complete 00031 interrupt on the two DMA Streams. The output stream should have higher 00032 priority than the input stream. 00033 (#) Configure the ADC Prescaler, conversion resolution and data alignment 00034 using the HAL_ADC_Init() function. 00035 00036 (#) Configure the ADC Injected channels group features, use HAL_ADC_Init() 00037 and HAL_ADC_ConfigChannel() functions. 00038 00039 (#) Three operation modes are available within this driver : 00040 00041 *** Polling mode IO operation *** 00042 ================================= 00043 [..] 00044 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart() 00045 (+) Wait for end of conversion using HAL_ADC_PollForConversion(), at this stage 00046 user can specify the value of timeout according to his end application 00047 (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() function. 00048 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop() 00049 00050 *** Interrupt mode IO operation *** 00051 =================================== 00052 [..] 00053 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_IT() 00054 (+) Use HAL_ADC_IRQHandler() called under ADC_IRQHandler() Interrupt subroutine 00055 (+) At ADC end of conversion HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can 00056 add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback 00057 (+) In case of ADC Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can 00058 add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback 00059 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_IT() 00060 00061 00062 *** DMA mode IO operation *** 00063 ============================== 00064 [..] 00065 (+) Start the ADC peripheral using HAL_ADCEx_InjectedStart_DMA(), at this stage the user specify the length 00066 of data to be transferred at each end of conversion 00067 (+) At The end of data transfer ba HAL_ADCEx_InjectedConvCpltCallback() function is executed and user can 00068 add his own code by customization of function pointer HAL_ADCEx_InjectedConvCpltCallback 00069 (+) In case of transfer Error, HAL_ADCEx_InjectedErrorCallback() function is executed and user can 00070 add his own code by customization of function pointer HAL_ADCEx_InjectedErrorCallback 00071 (+) Stop the ADC peripheral using HAL_ADCEx_InjectedStop_DMA() 00072 00073 *** Multi mode ADCs Regular channels configuration *** 00074 ====================================================== 00075 [..] 00076 (+) Select the Multi mode ADC regular channels features (dual or triple mode) 00077 and configure the DMA mode using HAL_ADCEx_MultiModeConfigChannel() functions. 00078 (+) Start the ADC peripheral using HAL_ADCEx_MultiModeStart_DMA(), at this stage the user specify the length 00079 of data to be transferred at each end of conversion 00080 (+) Read the ADCs converted values using the HAL_ADCEx_MultiModeGetValue() function. 00081 00082 00083 @endverbatim 00084 ****************************************************************************** 00085 * @attention 00086 * 00087 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00088 * 00089 * Redistribution and use in source and binary forms, with or without modification, 00090 * are permitted provided that the following conditions are met: 00091 * 1. Redistributions of source code must retain the above copyright notice, 00092 * this list of conditions and the following disclaimer. 00093 * 2. Redistributions in binary form must reproduce the above copyright notice, 00094 * this list of conditions and the following disclaimer in the documentation 00095 * and/or other materials provided with the distribution. 00096 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00097 * may be used to endorse or promote products derived from this software 00098 * without specific prior written permission. 00099 * 00100 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00101 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00102 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00103 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00104 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00105 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00106 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00107 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00108 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00109 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00110 * 00111 ****************************************************************************** 00112 */ 00113 00114 /* Includes ------------------------------------------------------------------*/ 00115 #include "stm32f4xx_hal.h" 00116 00117 /** @addtogroup STM32F4xx_HAL_Driver 00118 * @{ 00119 */ 00120 00121 /** @defgroup ADCEx ADCEx 00122 * @brief ADC Extended driver modules 00123 * @{ 00124 */ 00125 00126 #ifdef HAL_ADC_MODULE_ENABLED 00127 00128 /* Private typedef -----------------------------------------------------------*/ 00129 /* Private define ------------------------------------------------------------*/ 00130 /* Private macro -------------------------------------------------------------*/ 00131 /* Private variables ---------------------------------------------------------*/ 00132 /** @addtogroup ADCEx_Private_Functions 00133 * @{ 00134 */ 00135 /* Private function prototypes -----------------------------------------------*/ 00136 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma); 00137 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma); 00138 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma); 00139 /** 00140 * @} 00141 */ 00142 00143 /* Exported functions --------------------------------------------------------*/ 00144 /** @defgroup ADCEx_Exported_Functions ADC Exported Functions 00145 * @{ 00146 */ 00147 00148 /** @defgroup ADCEx_Exported_Functions_Group1 Extended features functions 00149 * @brief Extended features functions 00150 * 00151 @verbatim 00152 =============================================================================== 00153 ##### Extended features functions ##### 00154 =============================================================================== 00155 [..] This section provides functions allowing to: 00156 (+) Start conversion of injected channel. 00157 (+) Stop conversion of injected channel. 00158 (+) Start multimode and enable DMA transfer. 00159 (+) Stop multimode and disable DMA transfer. 00160 (+) Get result of injected channel conversion. 00161 (+) Get result of multimode conversion. 00162 (+) Configure injected channels. 00163 (+) Configure multimode. 00164 00165 @endverbatim 00166 * @{ 00167 */ 00168 00169 /** 00170 * @brief Enables the selected ADC software start conversion of the injected channels. 00171 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00172 * the configuration information for the specified ADC. 00173 * @retval HAL status 00174 */ 00175 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc) 00176 { 00177 __IO uint32_t counter = 0U; 00178 uint32_t tmp1 = 0U, tmp2 = 0U; 00179 ADC_Common_TypeDef *tmpADC_Common; 00180 00181 /* Process locked */ 00182 __HAL_LOCK(hadc); 00183 00184 /* Enable the ADC peripheral */ 00185 00186 /* Check if ADC peripheral is disabled in order to enable it and wait during 00187 Tstab time the ADC's stabilization */ 00188 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) 00189 { 00190 /* Enable the Peripheral */ 00191 __HAL_ADC_ENABLE(hadc); 00192 00193 /* Delay for ADC stabilization time */ 00194 /* Compute number of CPU cycles to wait for */ 00195 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 00196 while(counter != 0U) 00197 { 00198 counter--; 00199 } 00200 } 00201 00202 /* Start conversion if ADC is effectively enabled */ 00203 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) 00204 { 00205 /* Set ADC state */ 00206 /* - Clear state bitfield related to injected group conversion results */ 00207 /* - Set state bitfield related to injected operation */ 00208 ADC_STATE_CLR_SET(hadc->State, 00209 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, 00210 HAL_ADC_STATE_INJ_BUSY); 00211 00212 /* Check if a regular conversion is ongoing */ 00213 /* Note: On this device, there is no ADC error code fields related to */ 00214 /* conversions on group injected only. In case of conversion on */ 00215 /* going on group regular, no error code is reset. */ 00216 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 00217 { 00218 /* Reset ADC all error code fields */ 00219 ADC_CLEAR_ERRORCODE(hadc); 00220 } 00221 00222 /* Process unlocked */ 00223 /* Unlock before starting ADC conversions: in case of potential */ 00224 /* interruption, to let the process to ADC IRQ Handler. */ 00225 __HAL_UNLOCK(hadc); 00226 00227 /* Clear injected group conversion flag */ 00228 /* (To ensure of no unknown state from potential previous ADC operations) */ 00229 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); 00230 00231 /* Pointer to the common control register to which is belonging hadc */ 00232 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ 00233 /* control register) */ 00234 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 00235 00236 /* Check if Multimode enabled */ 00237 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) 00238 { 00239 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); 00240 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); 00241 if(tmp1 && tmp2) 00242 { 00243 /* Enable the selected ADC software conversion for injected group */ 00244 hadc->Instance->CR2 |= ADC_CR2_JSWSTART; 00245 } 00246 } 00247 else 00248 { 00249 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); 00250 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); 00251 if((hadc->Instance == ADC1) && tmp1 && tmp2) 00252 { 00253 /* Enable the selected ADC software conversion for injected group */ 00254 hadc->Instance->CR2 |= ADC_CR2_JSWSTART; 00255 } 00256 } 00257 } 00258 00259 /* Return function status */ 00260 return HAL_OK; 00261 } 00262 00263 /** 00264 * @brief Enables the interrupt and starts ADC conversion of injected channels. 00265 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00266 * the configuration information for the specified ADC. 00267 * 00268 * @retval HAL status. 00269 */ 00270 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc) 00271 { 00272 __IO uint32_t counter = 0U; 00273 uint32_t tmp1 = 0U, tmp2 = 0U; 00274 ADC_Common_TypeDef *tmpADC_Common; 00275 00276 /* Process locked */ 00277 __HAL_LOCK(hadc); 00278 00279 /* Enable the ADC peripheral */ 00280 00281 /* Check if ADC peripheral is disabled in order to enable it and wait during 00282 Tstab time the ADC's stabilization */ 00283 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) 00284 { 00285 /* Enable the Peripheral */ 00286 __HAL_ADC_ENABLE(hadc); 00287 00288 /* Delay for ADC stabilization time */ 00289 /* Compute number of CPU cycles to wait for */ 00290 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 00291 while(counter != 0U) 00292 { 00293 counter--; 00294 } 00295 } 00296 00297 /* Start conversion if ADC is effectively enabled */ 00298 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) 00299 { 00300 /* Set ADC state */ 00301 /* - Clear state bitfield related to injected group conversion results */ 00302 /* - Set state bitfield related to injected operation */ 00303 ADC_STATE_CLR_SET(hadc->State, 00304 HAL_ADC_STATE_READY | HAL_ADC_STATE_INJ_EOC, 00305 HAL_ADC_STATE_INJ_BUSY); 00306 00307 /* Check if a regular conversion is ongoing */ 00308 /* Note: On this device, there is no ADC error code fields related to */ 00309 /* conversions on group injected only. In case of conversion on */ 00310 /* going on group regular, no error code is reset. */ 00311 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 00312 { 00313 /* Reset ADC all error code fields */ 00314 ADC_CLEAR_ERRORCODE(hadc); 00315 } 00316 00317 /* Process unlocked */ 00318 /* Unlock before starting ADC conversions: in case of potential */ 00319 /* interruption, to let the process to ADC IRQ Handler. */ 00320 __HAL_UNLOCK(hadc); 00321 00322 /* Clear injected group conversion flag */ 00323 /* (To ensure of no unknown state from potential previous ADC operations) */ 00324 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); 00325 00326 /* Enable end of conversion interrupt for injected channels */ 00327 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); 00328 00329 /* Pointer to the common control register to which is belonging hadc */ 00330 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ 00331 /* control register) */ 00332 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 00333 00334 /* Check if Multimode enabled */ 00335 if(HAL_IS_BIT_CLR(tmpADC_Common->CCR, ADC_CCR_MULTI)) 00336 { 00337 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); 00338 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); 00339 if(tmp1 && tmp2) 00340 { 00341 /* Enable the selected ADC software conversion for injected group */ 00342 hadc->Instance->CR2 |= ADC_CR2_JSWSTART; 00343 } 00344 } 00345 else 00346 { 00347 tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); 00348 tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); 00349 if((hadc->Instance == ADC1) && tmp1 && tmp2) 00350 { 00351 /* Enable the selected ADC software conversion for injected group */ 00352 hadc->Instance->CR2 |= ADC_CR2_JSWSTART; 00353 } 00354 } 00355 } 00356 00357 /* Return function status */ 00358 return HAL_OK; 00359 } 00360 00361 /** 00362 * @brief Stop conversion of injected channels. Disable ADC peripheral if 00363 * no regular conversion is on going. 00364 * @note If ADC must be disabled and if conversion is on going on 00365 * regular group, function HAL_ADC_Stop must be used to stop both 00366 * injected and regular groups, and disable the ADC. 00367 * @note If injected group mode auto-injection is enabled, 00368 * function HAL_ADC_Stop must be used. 00369 * @note In case of auto-injection mode, HAL_ADC_Stop must be used. 00370 * @param hadc ADC handle 00371 * @retval None 00372 */ 00373 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) 00374 { 00375 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00376 00377 /* Check the parameters */ 00378 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00379 00380 /* Process locked */ 00381 __HAL_LOCK(hadc); 00382 00383 /* Stop potential conversion and disable ADC peripheral */ 00384 /* Conditioned to: */ 00385 /* - No conversion on the other group (regular group) is intended to */ 00386 /* continue (injected and regular groups stop conversion and ADC disable */ 00387 /* are common) */ 00388 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ 00389 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && 00390 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) 00391 { 00392 /* Stop potential conversion on going, on regular and injected groups */ 00393 /* Disable ADC peripheral */ 00394 __HAL_ADC_DISABLE(hadc); 00395 00396 /* Check if ADC is effectively disabled */ 00397 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) 00398 { 00399 /* Set ADC state */ 00400 ADC_STATE_CLR_SET(hadc->State, 00401 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 00402 HAL_ADC_STATE_READY); 00403 } 00404 } 00405 else 00406 { 00407 /* Update ADC state machine to error */ 00408 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 00409 00410 tmp_hal_status = HAL_ERROR; 00411 } 00412 00413 /* Process unlocked */ 00414 __HAL_UNLOCK(hadc); 00415 00416 /* Return function status */ 00417 return tmp_hal_status; 00418 } 00419 00420 /** 00421 * @brief Poll for injected conversion complete 00422 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00423 * the configuration information for the specified ADC. 00424 * @param Timeout Timeout value in millisecond. 00425 * @retval HAL status 00426 */ 00427 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) 00428 { 00429 uint32_t tickstart = 0U; 00430 00431 /* Get tick */ 00432 tickstart = HAL_GetTick(); 00433 00434 /* Check End of conversion flag */ 00435 while(!(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))) 00436 { 00437 /* Check for the Timeout */ 00438 if(Timeout != HAL_MAX_DELAY) 00439 { 00440 if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout)) 00441 { 00442 hadc->State= HAL_ADC_STATE_TIMEOUT; 00443 /* Process unlocked */ 00444 __HAL_UNLOCK(hadc); 00445 return HAL_TIMEOUT; 00446 } 00447 } 00448 } 00449 00450 /* Clear injected group conversion flag */ 00451 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC); 00452 00453 /* Update ADC state machine */ 00454 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 00455 00456 /* Determine whether any further conversion upcoming on group injected */ 00457 /* by external trigger, continuous mode or scan sequence on going. */ 00458 /* Note: On STM32F4, there is no independent flag of end of sequence. */ 00459 /* The test of scan sequence on going is done either with scan */ 00460 /* sequence disabled or with end of conversion flag set to */ 00461 /* of end of sequence. */ 00462 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) && 00463 (HAL_IS_BIT_CLR(hadc->Instance->JSQR, ADC_JSQR_JL) || 00464 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) && 00465 (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) && 00466 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 00467 (hadc->Init.ContinuousConvMode == DISABLE) ) ) ) 00468 { 00469 /* Set ADC state */ 00470 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 00471 00472 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 00473 { 00474 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 00475 } 00476 } 00477 00478 /* Return ADC state */ 00479 return HAL_OK; 00480 } 00481 00482 /** 00483 * @brief Stop conversion of injected channels, disable interruption of 00484 * end-of-conversion. Disable ADC peripheral if no regular conversion 00485 * is on going. 00486 * @note If ADC must be disabled and if conversion is on going on 00487 * regular group, function HAL_ADC_Stop must be used to stop both 00488 * injected and regular groups, and disable the ADC. 00489 * @note If injected group mode auto-injection is enabled, 00490 * function HAL_ADC_Stop must be used. 00491 * @param hadc ADC handle 00492 * @retval None 00493 */ 00494 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) 00495 { 00496 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00497 00498 /* Check the parameters */ 00499 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00500 00501 /* Process locked */ 00502 __HAL_LOCK(hadc); 00503 00504 /* Stop potential conversion and disable ADC peripheral */ 00505 /* Conditioned to: */ 00506 /* - No conversion on the other group (regular group) is intended to */ 00507 /* continue (injected and regular groups stop conversion and ADC disable */ 00508 /* are common) */ 00509 /* - In case of auto-injection mode, HAL_ADC_Stop must be used. */ 00510 if(((hadc->State & HAL_ADC_STATE_REG_BUSY) == RESET) && 00511 HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) ) 00512 { 00513 /* Stop potential conversion on going, on regular and injected groups */ 00514 /* Disable ADC peripheral */ 00515 __HAL_ADC_DISABLE(hadc); 00516 00517 /* Check if ADC is effectively disabled */ 00518 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) 00519 { 00520 /* Disable ADC end of conversion interrupt for injected channels */ 00521 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 00522 00523 /* Set ADC state */ 00524 ADC_STATE_CLR_SET(hadc->State, 00525 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 00526 HAL_ADC_STATE_READY); 00527 } 00528 } 00529 else 00530 { 00531 /* Update ADC state machine to error */ 00532 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 00533 00534 tmp_hal_status = HAL_ERROR; 00535 } 00536 00537 /* Process unlocked */ 00538 __HAL_UNLOCK(hadc); 00539 00540 /* Return function status */ 00541 return tmp_hal_status; 00542 } 00543 00544 /** 00545 * @brief Gets the converted value from data register of injected channel. 00546 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00547 * the configuration information for the specified ADC. 00548 * @param InjectedRank the ADC injected rank. 00549 * This parameter can be one of the following values: 00550 * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected 00551 * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected 00552 * @arg ADC_INJECTED_RANK_3: Injected Channel3 selected 00553 * @arg ADC_INJECTED_RANK_4: Injected Channel4 selected 00554 * @retval None 00555 */ 00556 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank) 00557 { 00558 __IO uint32_t tmp = 0U; 00559 00560 /* Check the parameters */ 00561 assert_param(IS_ADC_INJECTED_RANK(InjectedRank)); 00562 00563 /* Clear injected group conversion flag to have similar behaviour as */ 00564 /* regular group: reading data register also clears end of conversion flag. */ 00565 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC); 00566 00567 /* Return the selected ADC converted value */ 00568 switch(InjectedRank) 00569 { 00570 case ADC_INJECTED_RANK_4: 00571 { 00572 tmp = hadc->Instance->JDR4; 00573 } 00574 break; 00575 case ADC_INJECTED_RANK_3: 00576 { 00577 tmp = hadc->Instance->JDR3; 00578 } 00579 break; 00580 case ADC_INJECTED_RANK_2: 00581 { 00582 tmp = hadc->Instance->JDR2; 00583 } 00584 break; 00585 case ADC_INJECTED_RANK_1: 00586 { 00587 tmp = hadc->Instance->JDR1; 00588 } 00589 break; 00590 default: 00591 break; 00592 } 00593 return tmp; 00594 } 00595 00596 /** 00597 * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral 00598 * 00599 * @note Caution: This function must be used only with the ADC master. 00600 * 00601 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00602 * the configuration information for the specified ADC. 00603 * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. 00604 * @param Length The length of data to be transferred from ADC peripheral to memory. 00605 * @retval HAL status 00606 */ 00607 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) 00608 { 00609 __IO uint32_t counter = 0U; 00610 ADC_Common_TypeDef *tmpADC_Common; 00611 00612 /* Check the parameters */ 00613 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); 00614 assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 00615 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); 00616 00617 /* Process locked */ 00618 __HAL_LOCK(hadc); 00619 00620 /* Check if ADC peripheral is disabled in order to enable it and wait during 00621 Tstab time the ADC's stabilization */ 00622 if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) 00623 { 00624 /* Enable the Peripheral */ 00625 __HAL_ADC_ENABLE(hadc); 00626 00627 /* Delay for temperature sensor stabilization time */ 00628 /* Compute number of CPU cycles to wait for */ 00629 counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); 00630 while(counter != 0U) 00631 { 00632 counter--; 00633 } 00634 } 00635 00636 /* Start conversion if ADC is effectively enabled */ 00637 if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) 00638 { 00639 /* Set ADC state */ 00640 /* - Clear state bitfield related to regular group conversion results */ 00641 /* - Set state bitfield related to regular group operation */ 00642 ADC_STATE_CLR_SET(hadc->State, 00643 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, 00644 HAL_ADC_STATE_REG_BUSY); 00645 00646 /* If conversions on group regular are also triggering group injected, */ 00647 /* update ADC state. */ 00648 if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) 00649 { 00650 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 00651 } 00652 00653 /* State machine update: Check if an injected conversion is ongoing */ 00654 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 00655 { 00656 /* Reset ADC error code fields related to conversions on group regular */ 00657 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 00658 } 00659 else 00660 { 00661 /* Reset ADC all error code fields */ 00662 ADC_CLEAR_ERRORCODE(hadc); 00663 } 00664 00665 /* Process unlocked */ 00666 /* Unlock before starting ADC conversions: in case of potential */ 00667 /* interruption, to let the process to ADC IRQ Handler. */ 00668 __HAL_UNLOCK(hadc); 00669 00670 /* Set the DMA transfer complete callback */ 00671 hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; 00672 00673 /* Set the DMA half transfer complete callback */ 00674 hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; 00675 00676 /* Set the DMA error callback */ 00677 hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; 00678 00679 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ 00680 /* start (in case of SW start): */ 00681 00682 /* Clear regular group conversion flag and overrun flag */ 00683 /* (To ensure of no unknown state from potential previous ADC operations) */ 00684 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); 00685 00686 /* Enable ADC overrun interrupt */ 00687 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 00688 00689 /* Pointer to the common control register to which is belonging hadc */ 00690 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ 00691 /* control register) */ 00692 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 00693 00694 if (hadc->Init.DMAContinuousRequests != DISABLE) 00695 { 00696 /* Enable the selected ADC DMA request after last transfer */ 00697 tmpADC_Common->CCR |= ADC_CCR_DDS; 00698 } 00699 else 00700 { 00701 /* Disable the selected ADC EOC rising on each regular channel conversion */ 00702 tmpADC_Common->CCR &= ~ADC_CCR_DDS; 00703 } 00704 00705 /* Enable the DMA Stream */ 00706 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&tmpADC_Common->CDR, (uint32_t)pData, Length); 00707 00708 /* if no external trigger present enable software conversion of regular channels */ 00709 if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) 00710 { 00711 /* Enable the selected ADC software conversion for regular group */ 00712 hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; 00713 } 00714 } 00715 00716 /* Return function status */ 00717 return HAL_OK; 00718 } 00719 00720 /** 00721 * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral 00722 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00723 * the configuration information for the specified ADC. 00724 * @retval HAL status 00725 */ 00726 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc) 00727 { 00728 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00729 ADC_Common_TypeDef *tmpADC_Common; 00730 00731 /* Check the parameters */ 00732 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00733 00734 /* Process locked */ 00735 __HAL_LOCK(hadc); 00736 00737 /* Stop potential conversion on going, on regular and injected groups */ 00738 /* Disable ADC peripheral */ 00739 __HAL_ADC_DISABLE(hadc); 00740 00741 /* Pointer to the common control register to which is belonging hadc */ 00742 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ 00743 /* control register) */ 00744 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 00745 00746 /* Check if ADC is effectively disabled */ 00747 if(HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_ADON)) 00748 { 00749 /* Disable the selected ADC DMA mode for multimode */ 00750 tmpADC_Common->CCR &= ~ADC_CCR_DDS; 00751 00752 /* Disable the DMA channel (in case of DMA in circular mode or stop while */ 00753 /* DMA transfer is on going) */ 00754 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 00755 00756 /* Disable ADC overrun interrupt */ 00757 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); 00758 00759 /* Set ADC state */ 00760 ADC_STATE_CLR_SET(hadc->State, 00761 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 00762 HAL_ADC_STATE_READY); 00763 } 00764 00765 /* Process unlocked */ 00766 __HAL_UNLOCK(hadc); 00767 00768 /* Return function status */ 00769 return tmp_hal_status; 00770 } 00771 00772 /** 00773 * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results 00774 * data in the selected multi mode. 00775 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00776 * the configuration information for the specified ADC. 00777 * @retval The converted data value. 00778 */ 00779 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc) 00780 { 00781 ADC_Common_TypeDef *tmpADC_Common; 00782 00783 /* Pointer to the common control register to which is belonging hadc */ 00784 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ 00785 /* control register) */ 00786 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 00787 00788 /* Return the multi mode conversion value */ 00789 return tmpADC_Common->CDR; 00790 } 00791 00792 /** 00793 * @brief Injected conversion complete callback in non blocking mode 00794 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00795 * the configuration information for the specified ADC. 00796 * @retval None 00797 */ 00798 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc) 00799 { 00800 /* Prevent unused argument(s) compilation warning */ 00801 UNUSED(hadc); 00802 /* NOTE : This function Should not be modified, when the callback is needed, 00803 the HAL_ADC_InjectedConvCpltCallback could be implemented in the user file 00804 */ 00805 } 00806 00807 /** 00808 * @brief Configures for the selected ADC injected channel its corresponding 00809 * rank in the sequencer and its sample time. 00810 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00811 * the configuration information for the specified ADC. 00812 * @param sConfigInjected ADC configuration structure for injected channel. 00813 * @retval None 00814 */ 00815 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) 00816 { 00817 00818 #ifdef USE_FULL_ASSERT 00819 uint32_t tmp = 0U; 00820 00821 #endif /* USE_FULL_ASSERT */ 00822 00823 ADC_Common_TypeDef *tmpADC_Common; 00824 00825 /* Check the parameters */ 00826 assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); 00827 assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); 00828 assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); 00829 assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); 00830 assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); 00831 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); 00832 assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); 00833 00834 #ifdef USE_FULL_ASSERT 00835 tmp = ADC_GET_RESOLUTION(hadc); 00836 assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); 00837 #endif /* USE_FULL_ASSERT */ 00838 00839 if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) 00840 { 00841 assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); 00842 } 00843 00844 /* Process locked */ 00845 __HAL_LOCK(hadc); 00846 00847 /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ 00848 if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) 00849 { 00850 /* Clear the old sample time */ 00851 hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); 00852 00853 /* Set the new sample time */ 00854 hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); 00855 } 00856 else /* ADC_Channel include in ADC_Channel_[0..9] */ 00857 { 00858 /* Clear the old sample time */ 00859 hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); 00860 00861 /* Set the new sample time */ 00862 hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); 00863 } 00864 00865 /*---------------------------- ADCx JSQR Configuration -----------------*/ 00866 hadc->Instance->JSQR &= ~(ADC_JSQR_JL); 00867 hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); 00868 00869 /* Rank configuration */ 00870 00871 /* Clear the old SQx bits for the selected rank */ 00872 hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); 00873 00874 /* Set the SQx bits for the selected rank */ 00875 hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); 00876 00877 /* Enable external trigger if trigger selection is different of software */ 00878 /* start. */ 00879 /* Note: This configuration keeps the hardware feature of parameter */ 00880 /* ExternalTrigConvEdge "trigger edge none" equivalent to */ 00881 /* software start. */ 00882 if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) 00883 { 00884 /* Select external trigger to start conversion */ 00885 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); 00886 hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; 00887 00888 /* Select external trigger polarity */ 00889 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); 00890 hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; 00891 } 00892 else 00893 { 00894 /* Reset the external trigger */ 00895 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); 00896 hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); 00897 } 00898 00899 if (sConfigInjected->AutoInjectedConv != DISABLE) 00900 { 00901 /* Enable the selected ADC automatic injected group conversion */ 00902 hadc->Instance->CR1 |= ADC_CR1_JAUTO; 00903 } 00904 else 00905 { 00906 /* Disable the selected ADC automatic injected group conversion */ 00907 hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); 00908 } 00909 00910 if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) 00911 { 00912 /* Enable the selected ADC injected discontinuous mode */ 00913 hadc->Instance->CR1 |= ADC_CR1_JDISCEN; 00914 } 00915 else 00916 { 00917 /* Disable the selected ADC injected discontinuous mode */ 00918 hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); 00919 } 00920 00921 switch(sConfigInjected->InjectedRank) 00922 { 00923 case 1U: 00924 /* Set injected channel 1 offset */ 00925 hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); 00926 hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; 00927 break; 00928 case 2U: 00929 /* Set injected channel 2 offset */ 00930 hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); 00931 hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; 00932 break; 00933 case 3U: 00934 /* Set injected channel 3 offset */ 00935 hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); 00936 hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; 00937 break; 00938 default: 00939 /* Set injected channel 4 offset */ 00940 hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); 00941 hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; 00942 break; 00943 } 00944 00945 /* Pointer to the common control register to which is belonging hadc */ 00946 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ 00947 /* control register) */ 00948 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 00949 00950 /* if ADC1 Channel_18 is selected enable VBAT Channel */ 00951 if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) 00952 { 00953 /* Enable the VBAT channel*/ 00954 tmpADC_Common->CCR |= ADC_CCR_VBATE; 00955 } 00956 00957 /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ 00958 if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))) 00959 { 00960 /* Enable the TSVREFE channel*/ 00961 tmpADC_Common->CCR |= ADC_CCR_TSVREFE; 00962 } 00963 00964 /* Process unlocked */ 00965 __HAL_UNLOCK(hadc); 00966 00967 /* Return function status */ 00968 return HAL_OK; 00969 } 00970 00971 /** 00972 * @brief Configures the ADC multi-mode 00973 * @param hadc pointer to a ADC_HandleTypeDef structure that contains 00974 * the configuration information for the specified ADC. 00975 * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains 00976 * the configuration information for multimode. 00977 * @retval HAL status 00978 */ 00979 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode) 00980 { 00981 00982 ADC_Common_TypeDef *tmpADC_Common; 00983 00984 /* Check the parameters */ 00985 assert_param(IS_ADC_MODE(multimode->Mode)); 00986 assert_param(IS_ADC_DMA_ACCESS_MODE(multimode->DMAAccessMode)); 00987 assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay)); 00988 00989 /* Process locked */ 00990 __HAL_LOCK(hadc); 00991 00992 /* Pointer to the common control register to which is belonging hadc */ 00993 /* (Depending on STM32F4 product, there may be up to 3 ADC and 1 common */ 00994 /* control register) */ 00995 tmpADC_Common = ADC_COMMON_REGISTER(hadc); 00996 00997 /* Set ADC mode */ 00998 tmpADC_Common->CCR &= ~(ADC_CCR_MULTI); 00999 tmpADC_Common->CCR |= multimode->Mode; 01000 01001 /* Set the ADC DMA access mode */ 01002 tmpADC_Common->CCR &= ~(ADC_CCR_DMA); 01003 tmpADC_Common->CCR |= multimode->DMAAccessMode; 01004 01005 /* Set delay between two sampling phases */ 01006 tmpADC_Common->CCR &= ~(ADC_CCR_DELAY); 01007 tmpADC_Common->CCR |= multimode->TwoSamplingDelay; 01008 01009 /* Process unlocked */ 01010 __HAL_UNLOCK(hadc); 01011 01012 /* Return function status */ 01013 return HAL_OK; 01014 } 01015 01016 /** 01017 * @} 01018 */ 01019 01020 /** 01021 * @brief DMA transfer complete callback. 01022 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01023 * the configuration information for the specified DMA module. 01024 * @retval None 01025 */ 01026 static void ADC_MultiModeDMAConvCplt(DMA_HandleTypeDef *hdma) 01027 { 01028 /* Retrieve ADC handle corresponding to current DMA handle */ 01029 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01030 01031 /* Update state machine on conversion status if not in error state */ 01032 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA)) 01033 { 01034 /* Update ADC state machine */ 01035 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 01036 01037 /* Determine whether any further conversion upcoming on group regular */ 01038 /* by external trigger, continuous mode or scan sequence on going. */ 01039 /* Note: On STM32F4, there is no independent flag of end of sequence. */ 01040 /* The test of scan sequence on going is done either with scan */ 01041 /* sequence disabled or with end of conversion flag set to */ 01042 /* of end of sequence. */ 01043 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 01044 (hadc->Init.ContinuousConvMode == DISABLE) && 01045 (HAL_IS_BIT_CLR(hadc->Instance->SQR1, ADC_SQR1_L) || 01046 HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_EOCS) ) ) 01047 { 01048 /* Disable ADC end of single conversion interrupt on group regular */ 01049 /* Note: Overrun interrupt was enabled with EOC interrupt in */ 01050 /* HAL_ADC_Start_IT(), but is not disabled here because can be used */ 01051 /* by overrun IRQ process below. */ 01052 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); 01053 01054 /* Set ADC state */ 01055 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 01056 01057 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 01058 { 01059 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 01060 } 01061 } 01062 01063 /* Conversion complete callback */ 01064 HAL_ADC_ConvCpltCallback(hadc); 01065 } 01066 else 01067 { 01068 /* Call DMA error callback */ 01069 hadc->DMA_Handle->XferErrorCallback(hdma); 01070 } 01071 } 01072 01073 /** 01074 * @brief DMA half transfer complete callback. 01075 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01076 * the configuration information for the specified DMA module. 01077 * @retval None 01078 */ 01079 static void ADC_MultiModeDMAHalfConvCplt(DMA_HandleTypeDef *hdma) 01080 { 01081 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01082 /* Conversion complete callback */ 01083 HAL_ADC_ConvHalfCpltCallback(hadc); 01084 } 01085 01086 /** 01087 * @brief DMA error callback 01088 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01089 * the configuration information for the specified DMA module. 01090 * @retval None 01091 */ 01092 static void ADC_MultiModeDMAError(DMA_HandleTypeDef *hdma) 01093 { 01094 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01095 hadc->State= HAL_ADC_STATE_ERROR_DMA; 01096 /* Set ADC error code to DMA error */ 01097 hadc->ErrorCode |= HAL_ADC_ERROR_DMA; 01098 HAL_ADC_ErrorCallback(hadc); 01099 } 01100 01101 /** 01102 * @} 01103 */ 01104 01105 #endif /* HAL_ADC_MODULE_ENABLED */ 01106 /** 01107 * @} 01108 */ 01109 01110 /** 01111 * @} 01112 */ 01113 01114 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/