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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_tim.h 00004 * @author MCD Application Team 00005 * @brief Header file of TIM LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_TIM_H 00038 #define __STM32L4xx_LL_TIM_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM15) || defined (TIM16) || defined (TIM17) || defined (TIM6) || defined (TIM7) 00052 00053 /** @defgroup TIM_LL TIM 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /** @defgroup TIM_LL_Private_Variables TIM Private Variables 00060 * @{ 00061 */ 00062 static const uint8_t OFFSET_TAB_CCMRx[] = 00063 { 00064 0x00U, /* 0: TIMx_CH1 */ 00065 0x00U, /* 1: TIMx_CH1N */ 00066 0x00U, /* 2: TIMx_CH2 */ 00067 0x00U, /* 3: TIMx_CH2N */ 00068 0x04U, /* 4: TIMx_CH3 */ 00069 0x04U, /* 5: TIMx_CH3N */ 00070 0x04U, /* 6: TIMx_CH4 */ 00071 0x3CU, /* 7: TIMx_CH5 */ 00072 0x3CU /* 8: TIMx_CH6 */ 00073 }; 00074 00075 static const uint8_t SHIFT_TAB_OCxx[] = 00076 { 00077 0U, /* 0: OC1M, OC1FE, OC1PE */ 00078 0U, /* 1: - NA */ 00079 8U, /* 2: OC2M, OC2FE, OC2PE */ 00080 0U, /* 3: - NA */ 00081 0U, /* 4: OC3M, OC3FE, OC3PE */ 00082 0U, /* 5: - NA */ 00083 8U, /* 6: OC4M, OC4FE, OC4PE */ 00084 0U, /* 7: OC5M, OC5FE, OC5PE */ 00085 8U /* 8: OC6M, OC6FE, OC6PE */ 00086 }; 00087 00088 static const uint8_t SHIFT_TAB_ICxx[] = 00089 { 00090 0U, /* 0: CC1S, IC1PSC, IC1F */ 00091 0U, /* 1: - NA */ 00092 8U, /* 2: CC2S, IC2PSC, IC2F */ 00093 0U, /* 3: - NA */ 00094 0U, /* 4: CC3S, IC3PSC, IC3F */ 00095 0U, /* 5: - NA */ 00096 8U, /* 6: CC4S, IC4PSC, IC4F */ 00097 0U, /* 7: - NA */ 00098 0U /* 8: - NA */ 00099 }; 00100 00101 static const uint8_t SHIFT_TAB_CCxP[] = 00102 { 00103 0U, /* 0: CC1P */ 00104 2U, /* 1: CC1NP */ 00105 4U, /* 2: CC2P */ 00106 6U, /* 3: CC2NP */ 00107 8U, /* 4: CC3P */ 00108 10U, /* 5: CC3NP */ 00109 12U, /* 6: CC4P */ 00110 16U, /* 7: CC5P */ 00111 20U /* 8: CC6P */ 00112 }; 00113 00114 static const uint8_t SHIFT_TAB_OISx[] = 00115 { 00116 0U, /* 0: OIS1 */ 00117 1U, /* 1: OIS1N */ 00118 2U, /* 2: OIS2 */ 00119 3U, /* 3: OIS2N */ 00120 4U, /* 4: OIS3 */ 00121 5U, /* 5: OIS3N */ 00122 6U, /* 6: OIS4 */ 00123 8U, /* 7: OIS5 */ 00124 10U /* 8: OIS6 */ 00125 }; 00126 /** 00127 * @} 00128 */ 00129 00130 /* Private constants ---------------------------------------------------------*/ 00131 /** @defgroup TIM_LL_Private_Constants TIM Private Constants 00132 * @{ 00133 */ 00134 00135 /* Defines used for the bit position in the register and perform offsets */ 00136 #define TIM_POSITION_BRK_SOURCE (POSITION_VAL(Source) & 0x1FU) 00137 00138 /* Generic bit definitions for TIMx_OR2 register */ 00139 #define TIMx_OR2_BKINE TIM1_OR2_BKINE /*!< BRK BKIN input enable */ 00140 #define TIMx_OR2_BKCOMP1E TIM1_OR2_BKCMP1E /*!< BRK COMP1 enable */ 00141 #define TIMx_OR2_BKCOMP2E TIM1_OR2_BKCMP2E /*!< BRK COMP2 enable */ 00142 #if defined(DFSDM1_Channel0) 00143 #define TIMx_OR2_BKDF1BK0E TIM1_OR2_BKDF1BK0E /*!< BRK DFSDM1_BREAK[0] enable */ 00144 #endif /* DFSDM1_Channel0 */ 00145 #define TIMx_OR2_BKINP TIM1_OR2_BKINP /*!< BRK BKIN input polarity */ 00146 #define TIMx_OR2_BKCOMP1P TIM1_OR2_BKCMP1P /*!< BRK COMP1 input polarity */ 00147 #define TIMx_OR2_BKCOMP2P TIM1_OR2_BKCMP2P /*!< BRK COMP2 input polarity */ 00148 #define TIMx_OR2_ETRSEL TIM1_OR2_ETRSEL /*!< TIMx ETR source selection */ 00149 00150 /* Generic bit definitions for TIMx_OR3 register */ 00151 #define TIMx_OR3_BK2INE TIM1_OR3_BK2INE /*!< BRK2 BKIN2 input enable */ 00152 #define TIMx_OR3_BK2COMP1E TIM1_OR3_BK2CMP1E /*!< BRK2 COMP1 enable */ 00153 #define TIMx_OR3_BK2COMP2E TIM1_OR3_BK2CMP2E /*!< BRK2 COMP2 enable */ 00154 #if defined(DFSDM1_Channel0) 00155 #define TIMx_OR3_BK2DF1BK1E TIM1_OR3_BK2DF1BK1E /*!< BRK2 DFSDM1_BREAK[1] enable */ 00156 #endif /* DFSDM1_Channel0 */ 00157 #define TIMx_OR3_BK2INP TIM1_OR3_BK2INP /*!< BRK2 BKIN2 input polarity */ 00158 #define TIMx_OR3_BK2COMP1P TIM1_OR3_BK2CMP1P /*!< BRK2 COMP1 input polarity */ 00159 #define TIMx_OR3_BK2COMP2P TIM1_OR3_BK2CMP2P /*!< BRK2 COMP2 input polarity */ 00160 00161 /* Remap mask definitions */ 00162 #define TIMx_OR1_RMP_SHIFT 16U 00163 #define TIMx_OR1_RMP_MASK 0x0000FFFFU 00164 #if defined(ADC3) 00165 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) 00166 #else 00167 #define TIM1_OR1_RMP_MASK ((TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) 00168 #endif /* ADC3 */ 00169 #define TIM2_OR1_RMP_MASK ((TIM2_OR1_TI4_RMP | TIM2_OR1_ETR1_RMP | TIM2_OR1_ITR1_RMP) << TIMx_OR1_RMP_SHIFT) 00170 #define TIM3_OR1_RMP_MASK (TIM3_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) 00171 #if defined(ADC2) && defined(ADC3) 00172 #define TIM8_OR1_RMP_MASK ((TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_TI1_RMP) << TIMx_OR1_RMP_SHIFT) 00173 #else 00174 #define TIM8_OR1_RMP_MASK (TIM8_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) 00175 #endif /* ADC2 & ADC3 */ 00176 #define TIM15_OR1_RMP_MASK (TIM15_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) 00177 #define TIM16_OR1_RMP_MASK (TIM16_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) 00178 #define TIM17_OR1_RMP_MASK (TIM17_OR1_TI1_RMP << TIMx_OR1_RMP_SHIFT) 00179 00180 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ 00181 #define DT_DELAY_1 ((uint8_t)0x7F) 00182 #define DT_DELAY_2 ((uint8_t)0x3F) 00183 #define DT_DELAY_3 ((uint8_t)0x1F) 00184 #define DT_DELAY_4 ((uint8_t)0x1F) 00185 00186 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ 00187 #define DT_RANGE_1 ((uint8_t)0x00) 00188 #define DT_RANGE_2 ((uint8_t)0x80) 00189 #define DT_RANGE_3 ((uint8_t)0xC0) 00190 #define DT_RANGE_4 ((uint8_t)0xE0) 00191 00192 /** Legacy definitions for compatibility purpose 00193 @cond 0 00194 */ 00195 #if defined(DFSDM1_Channel0) 00196 #define TIMx_OR2_BKDFBK0E TIMx_OR2_BKDF1BK0E 00197 #define TIMx_OR3_BK2DFBK1E TIMx_OR3_BK2DF1BK1E 00198 #endif /* DFSDM1_Channel0 */ 00199 /** 00200 @endcond 00201 */ 00202 00203 /** 00204 * @} 00205 */ 00206 00207 /* Private macros ------------------------------------------------------------*/ 00208 /** @defgroup TIM_LL_Private_Macros TIM Private Macros 00209 * @{ 00210 */ 00211 /** @brief Convert channel id into channel index. 00212 * @param __CHANNEL__ This parameter can be one of the following values: 00213 * @arg @ref LL_TIM_CHANNEL_CH1 00214 * @arg @ref LL_TIM_CHANNEL_CH1N 00215 * @arg @ref LL_TIM_CHANNEL_CH2 00216 * @arg @ref LL_TIM_CHANNEL_CH2N 00217 * @arg @ref LL_TIM_CHANNEL_CH3 00218 * @arg @ref LL_TIM_CHANNEL_CH3N 00219 * @arg @ref LL_TIM_CHANNEL_CH4 00220 * @arg @ref LL_TIM_CHANNEL_CH5 00221 * @arg @ref LL_TIM_CHANNEL_CH6 00222 * @retval none 00223 */ 00224 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ 00225 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ 00226 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ 00227 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ 00228 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ 00229 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ 00230 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\ 00231 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\ 00232 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U) 00233 00234 /** @brief Calculate the deadtime sampling period(in ps). 00235 * @param __TIMCLK__ timer input clock frequency (in Hz). 00236 * @param __CKD__ This parameter can be one of the following values: 00237 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 00238 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 00239 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 00240 * @retval none 00241 */ 00242 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ 00243 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ 00244 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ 00245 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) 00246 /** 00247 * @} 00248 */ 00249 00250 00251 /* Exported types ------------------------------------------------------------*/ 00252 #if defined(USE_FULL_LL_DRIVER) 00253 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure 00254 * @{ 00255 */ 00256 00257 /** 00258 * @brief TIM Time Base configuration structure definition. 00259 */ 00260 typedef struct 00261 { 00262 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. 00263 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00264 00265 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ 00266 00267 uint32_t CounterMode; /*!< Specifies the counter mode. 00268 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. 00269 00270 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ 00271 00272 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active 00273 Auto-Reload Register at the next update event. 00274 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00275 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. 00276 00277 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ 00278 00279 uint32_t ClockDivision; /*!< Specifies the clock division. 00280 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. 00281 00282 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ 00283 00284 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter 00285 reaches zero, an update event is generated and counting restarts 00286 from the RCR value (N). 00287 This means in PWM mode that (N+1) corresponds to: 00288 - the number of PWM periods in edge-aligned mode 00289 - the number of half PWM period in center-aligned mode 00290 This parameter must be a number between 0x00 and 0xFF. 00291 00292 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ 00293 } LL_TIM_InitTypeDef; 00294 00295 /** 00296 * @brief TIM Output Compare configuration structure definition. 00297 */ 00298 typedef struct 00299 { 00300 uint32_t OCMode; /*!< Specifies the output mode. 00301 This parameter can be a value of @ref TIM_LL_EC_OCMODE. 00302 00303 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ 00304 00305 uint32_t OCState; /*!< Specifies the TIM Output Compare state. 00306 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 00307 00308 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 00309 00310 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. 00311 This parameter can be a value of @ref TIM_LL_EC_OCSTATE. 00312 00313 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ 00314 00315 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. 00316 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. 00317 00318 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ 00319 00320 uint32_t OCPolarity; /*!< Specifies the output polarity. 00321 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 00322 00323 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ 00324 00325 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. 00326 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. 00327 00328 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ 00329 00330 00331 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00332 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 00333 00334 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ 00335 00336 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. 00337 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. 00338 00339 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ 00340 } LL_TIM_OC_InitTypeDef; 00341 00342 /** 00343 * @brief TIM Input Capture configuration structure definition. 00344 */ 00345 00346 typedef struct 00347 { 00348 00349 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. 00350 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00351 00352 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00353 00354 uint32_t ICActiveInput; /*!< Specifies the input. 00355 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00356 00357 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ 00358 00359 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. 00360 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00361 00362 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00363 00364 uint32_t ICFilter; /*!< Specifies the input capture filter. 00365 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00366 00367 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00368 } LL_TIM_IC_InitTypeDef; 00369 00370 00371 /** 00372 * @brief TIM Encoder interface configuration structure definition. 00373 */ 00374 typedef struct 00375 { 00376 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). 00377 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. 00378 00379 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ 00380 00381 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 00382 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00383 00384 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00385 00386 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source 00387 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00388 00389 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ 00390 00391 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 00392 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00393 00394 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00395 00396 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 00397 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00398 00399 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00400 00401 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. 00402 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00403 00404 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00405 00406 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source 00407 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. 00408 00409 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ 00410 00411 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. 00412 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00413 00414 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00415 00416 uint32_t IC2Filter; /*!< Specifies the TI2 input filter. 00417 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00418 00419 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00420 00421 } LL_TIM_ENCODER_InitTypeDef; 00422 00423 /** 00424 * @brief TIM Hall sensor interface configuration structure definition. 00425 */ 00426 typedef struct 00427 { 00428 00429 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. 00430 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. 00431 00432 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ 00433 00434 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. 00435 Prescaler must be set to get a maximum counter period longer than the 00436 time interval between 2 consecutive changes on the Hall inputs. 00437 This parameter can be a value of @ref TIM_LL_EC_ICPSC. 00438 00439 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ 00440 00441 uint32_t IC1Filter; /*!< Specifies the TI1 input filter. 00442 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. 00443 00444 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ 00445 00446 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. 00447 A positive pulse (TRGO event) is generated with a programmable delay every time 00448 a change occurs on the Hall inputs. 00449 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. 00450 00451 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ 00452 } LL_TIM_HALLSENSOR_InitTypeDef; 00453 00454 /** 00455 * @brief BDTR (Break and Dead Time) structure definition 00456 */ 00457 typedef struct 00458 { 00459 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. 00460 This parameter can be a value of @ref TIM_LL_EC_OSSR 00461 00462 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() 00463 00464 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ 00465 00466 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. 00467 This parameter can be a value of @ref TIM_LL_EC_OSSI 00468 00469 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() 00470 00471 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ 00472 00473 uint32_t LockLevel; /*!< Specifies the LOCK level parameters. 00474 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL 00475 00476 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register 00477 has been written, their content is frozen until the next reset.*/ 00478 00479 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the 00480 switching-on of the outputs. 00481 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. 00482 00483 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() 00484 00485 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ 00486 00487 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. 00488 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE 00489 00490 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() 00491 00492 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ 00493 00494 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. 00495 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY 00496 00497 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() 00498 00499 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ 00500 00501 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter. 00502 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER 00503 00504 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() 00505 00506 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ 00507 00508 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not. 00509 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE 00510 00511 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2() 00512 00513 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ 00514 00515 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity. 00516 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY 00517 00518 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() 00519 00520 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ 00521 00522 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter. 00523 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER 00524 00525 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2() 00526 00527 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ 00528 00529 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 00530 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE 00531 00532 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() 00533 00534 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ 00535 } LL_TIM_BDTR_InitTypeDef; 00536 00537 /** 00538 * @} 00539 */ 00540 #endif /* USE_FULL_LL_DRIVER */ 00541 00542 /* Exported constants --------------------------------------------------------*/ 00543 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants 00544 * @{ 00545 */ 00546 00547 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines 00548 * @brief Flags defines which can be used with LL_TIM_ReadReg function. 00549 * @{ 00550 */ 00551 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ 00552 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ 00553 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ 00554 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ 00555 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ 00556 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */ 00557 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */ 00558 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ 00559 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ 00560 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ 00561 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */ 00562 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ 00563 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ 00564 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ 00565 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ 00566 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */ 00567 /** 00568 * @} 00569 */ 00570 00571 #if defined(USE_FULL_LL_DRIVER) 00572 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable 00573 * @{ 00574 */ 00575 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ 00576 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ 00577 /** 00578 * @} 00579 */ 00580 00581 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable 00582 * @{ 00583 */ 00584 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */ 00585 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */ 00586 /** 00587 * @} 00588 */ 00589 00590 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable 00591 * @{ 00592 */ 00593 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ 00594 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ 00595 /** 00596 * @} 00597 */ 00598 #endif /* USE_FULL_LL_DRIVER */ 00599 00600 /** @defgroup TIM_LL_EC_IT IT Defines 00601 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. 00602 * @{ 00603 */ 00604 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ 00605 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ 00606 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ 00607 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ 00608 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ 00609 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ 00610 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ 00611 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ 00612 /** 00613 * @} 00614 */ 00615 00616 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source 00617 * @{ 00618 */ 00619 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ 00620 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ 00621 /** 00622 * @} 00623 */ 00624 00625 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode 00626 * @{ 00627 */ 00628 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ 00629 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ 00630 /** 00631 * @} 00632 */ 00633 00634 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode 00635 * @{ 00636 */ 00637 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */ 00638 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */ 00639 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */ 00640 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */ 00641 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */ 00642 /** 00643 * @} 00644 */ 00645 00646 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division 00647 * @{ 00648 */ 00649 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */ 00650 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */ 00651 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */ 00652 /** 00653 * @} 00654 */ 00655 00656 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction 00657 * @{ 00658 */ 00659 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */ 00660 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */ 00661 /** 00662 * @} 00663 */ 00664 00665 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source 00666 * @{ 00667 */ 00668 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */ 00669 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */ 00670 /** 00671 * @} 00672 */ 00673 00674 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request 00675 * @{ 00676 */ 00677 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */ 00678 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */ 00679 /** 00680 * @} 00681 */ 00682 00683 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level 00684 * @{ 00685 */ 00686 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */ 00687 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */ 00688 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */ 00689 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */ 00690 /** 00691 * @} 00692 */ 00693 00694 /** @defgroup TIM_LL_EC_CHANNEL Channel 00695 * @{ 00696 */ 00697 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */ 00698 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */ 00699 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */ 00700 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */ 00701 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */ 00702 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */ 00703 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */ 00704 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */ 00705 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */ 00706 /** 00707 * @} 00708 */ 00709 00710 #if defined(USE_FULL_LL_DRIVER) 00711 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State 00712 * @{ 00713 */ 00714 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */ 00715 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */ 00716 /** 00717 * @} 00718 */ 00719 #endif /* USE_FULL_LL_DRIVER */ 00720 00721 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode 00722 * @{ 00723 */ 00724 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */ 00725 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/ 00726 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/ 00727 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/ 00728 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/ 00729 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/ 00730 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/ 00731 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/ 00732 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/ 00733 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/ 00734 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/ 00735 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/ 00736 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/ 00737 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/ 00738 /** 00739 * @} 00740 */ 00741 00742 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity 00743 * @{ 00744 */ 00745 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ 00746 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ 00747 /** 00748 * @} 00749 */ 00750 00751 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State 00752 * @{ 00753 */ 00754 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/ 00755 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/ 00756 /** 00757 * @} 00758 */ 00759 00760 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5 00761 * @{ 00762 */ 00763 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */ 00764 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */ 00765 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */ 00766 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */ 00767 /** 00768 * @} 00769 */ 00770 00771 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection 00772 * @{ 00773 */ 00774 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */ 00775 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */ 00776 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */ 00777 /** 00778 * @} 00779 */ 00780 00781 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler 00782 * @{ 00783 */ 00784 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */ 00785 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */ 00786 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */ 00787 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */ 00788 /** 00789 * @} 00790 */ 00791 00792 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter 00793 * @{ 00794 */ 00795 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ 00796 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */ 00797 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */ 00798 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */ 00799 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */ 00800 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */ 00801 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */ 00802 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */ 00803 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */ 00804 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */ 00805 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */ 00806 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */ 00807 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */ 00808 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */ 00809 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */ 00810 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */ 00811 /** 00812 * @} 00813 */ 00814 00815 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity 00816 * @{ 00817 */ 00818 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */ 00819 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */ 00820 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */ 00821 /** 00822 * @} 00823 */ 00824 00825 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source 00826 * @{ 00827 */ 00828 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */ 00829 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected input*/ 00830 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */ 00831 /** 00832 * @} 00833 */ 00834 00835 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode 00836 * @{ 00837 */ 00838 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Quadrature encoder mode 1, x2 mode - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */ 00839 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Quadrature encoder mode 2, x2 mode - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */ 00840 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Quadrature encoder mode 3, x4 mode - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input */ 00841 /** 00842 * @} 00843 */ 00844 00845 /** @defgroup TIM_LL_EC_TRGO Trigger Output 00846 * @{ 00847 */ 00848 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */ 00849 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */ 00850 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */ 00851 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */ 00852 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */ 00853 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */ 00854 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */ 00855 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */ 00856 /** 00857 * @} 00858 */ 00859 00860 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2 00861 * @{ 00862 */ 00863 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */ 00864 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */ 00865 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */ 00866 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */ 00867 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */ 00868 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */ 00869 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */ 00870 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */ 00871 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */ 00872 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */ 00873 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */ 00874 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */ 00875 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */ 00876 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */ 00877 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */ 00878 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */ 00879 /** 00880 * @} 00881 */ 00882 00883 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode 00884 * @{ 00885 */ 00886 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */ 00887 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */ 00888 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */ 00889 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */ 00890 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */ 00891 /** 00892 * @} 00893 */ 00894 00895 /** @defgroup TIM_LL_EC_TS Trigger Selection 00896 * @{ 00897 */ 00898 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */ 00899 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */ 00900 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */ 00901 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */ 00902 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */ 00903 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */ 00904 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */ 00905 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */ 00906 /** 00907 * @} 00908 */ 00909 00910 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity 00911 * @{ 00912 */ 00913 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */ 00914 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */ 00915 /** 00916 * @} 00917 */ 00918 00919 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler 00920 * @{ 00921 */ 00922 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */ 00923 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */ 00924 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */ 00925 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */ 00926 /** 00927 * @} 00928 */ 00929 00930 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter 00931 * @{ 00932 */ 00933 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */ 00934 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */ 00935 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */ 00936 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */ 00937 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */ 00938 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */ 00939 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */ 00940 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */ 00941 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */ 00942 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */ 00943 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */ 00944 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */ 00945 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */ 00946 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */ 00947 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */ 00948 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */ 00949 /** 00950 * @} 00951 */ 00952 00953 /** @defgroup TIM_LL_EC_ETRSOURCE External Trigger Source 00954 * @{ 00955 */ 00956 #define LL_TIM_ETRSOURCE_LEGACY 0x00000000U /*!< ETR legacy mode */ 00957 #define LL_TIM_ETRSOURCE_COMP1 TIM1_OR2_ETRSEL_0 /*!< COMP1 output connected to ETR input */ 00958 #define LL_TIM_ETRSOURCE_COMP2 TIM1_OR2_ETRSEL_1 /*!< COMP2 output connected to ETR input */ 00959 /** 00960 * @} 00961 */ 00962 00963 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity 00964 * @{ 00965 */ 00966 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */ 00967 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */ 00968 /** 00969 * @} 00970 */ 00971 00972 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter 00973 * @{ 00974 */ 00975 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ 00976 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */ 00977 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */ 00978 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */ 00979 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */ 00980 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */ 00981 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */ 00982 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */ 00983 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */ 00984 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */ 00985 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */ 00986 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */ 00987 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */ 00988 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */ 00989 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */ 00990 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */ 00991 /** 00992 * @} 00993 */ 00994 00995 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY 00996 * @{ 00997 */ 00998 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */ 00999 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */ 01000 /** 01001 * @} 01002 */ 01003 01004 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER 01005 * @{ 01006 */ 01007 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */ 01008 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */ 01009 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */ 01010 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */ 01011 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */ 01012 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */ 01013 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */ 01014 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */ 01015 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */ 01016 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */ 01017 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */ 01018 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */ 01019 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */ 01020 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */ 01021 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */ 01022 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */ 01023 /** 01024 * @} 01025 */ 01026 01027 /** @defgroup TIM_LL_EC_OSSI OSSI 01028 * @{ 01029 */ 01030 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ 01031 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */ 01032 /** 01033 * @} 01034 */ 01035 01036 /** @defgroup TIM_LL_EC_OSSR OSSR 01037 * @{ 01038 */ 01039 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */ 01040 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */ 01041 /** 01042 * @} 01043 */ 01044 01045 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT 01046 * @{ 01047 */ 01048 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */ 01049 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */ 01050 /** 01051 * @} 01052 */ 01053 01054 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE 01055 * @{ 01056 */ 01057 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_OR2_BKINE /*!< BKIN input from AF controller */ 01058 #define LL_TIM_BKIN_SOURCE_BKCOMP1 TIM1_OR2_BKCMP1E /*!< internal signal: COMP1 output */ 01059 #define LL_TIM_BKIN_SOURCE_BKCOMP2 TIM1_OR2_BKCMP2E /*!< internal signal: COMP2 output */ 01060 #if defined(DFSDM1_Channel0) 01061 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_OR2_BKDF1BK0E /*!< internal signal: DFSDM1 break output */ 01062 #endif /* DFSDM1_Channel0 */ 01063 /** 01064 * @} 01065 */ 01066 01067 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY 01068 * @{ 01069 */ 01070 #define LL_TIM_BKIN_POLARITY_LOW TIM1_OR2_BKINP /*!< BRK BKIN input is active low */ 01071 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */ 01072 /** 01073 * @} 01074 */ 01075 01076 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address 01077 * @{ 01078 */ 01079 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */ 01080 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */ 01081 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */ 01082 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */ 01083 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */ 01084 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */ 01085 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */ 01086 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */ 01087 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */ 01088 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */ 01089 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */ 01090 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */ 01091 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */ 01092 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */ 01093 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */ 01094 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */ 01095 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */ 01096 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */ 01097 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */ 01098 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */ 01099 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */ 01100 #define LL_TIM_DMABURST_BASEADDR_OR1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR1 register is the DMA base address for DMA burst */ 01101 #define LL_TIM_DMABURST_BASEADDR_OR2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_OR2 register is the DMA base address for DMA burst */ 01102 #define LL_TIM_DMABURST_BASEADDR_OR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_OR3 register is the DMA base address for DMA burst */ 01103 /** 01104 * @} 01105 */ 01106 01107 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length 01108 * @{ 01109 */ 01110 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */ 01111 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */ 01112 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */ 01113 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */ 01114 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */ 01115 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */ 01116 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */ 01117 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */ 01118 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */ 01119 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */ 01120 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */ 01121 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */ 01122 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */ 01123 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */ 01124 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */ 01125 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */ 01126 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */ 01127 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */ 01128 /** 01129 * @} 01130 */ 01131 01132 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC1_RMP TIM1 External Trigger ADC1 Remap 01133 * @{ 01134 */ 01135 #define LL_TIM_TIM1_ETR_ADC1_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC1 analog watchdog x */ 01136 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 (TIM1_OR1_ETR_ADC1_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 1 */ 01137 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 (TIM1_OR1_ETR_ADC1_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 2 */ 01138 #define LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 (TIM1_OR1_ETR_ADC1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC1 analog watchdog 3 */ 01139 /** 01140 * @} 01141 */ 01142 01143 #if defined(ADC3) 01144 /** @defgroup TIM_LL_EC_TIM1_ETR_ADC3_RMP TIM1 External Trigger ADC3 Remap 01145 * @{ 01146 */ 01147 #define LL_TIM_TIM1_ETR_ADC3_RMP_NC TIM1_OR1_RMP_MASK /*!< TIM1_ETR is not connected to ADC3 analog watchdog x*/ 01148 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 (TIM1_OR1_ETR_ADC3_RMP_0 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 1 */ 01149 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 (TIM1_OR1_ETR_ADC3_RMP_1 | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 2 */ 01150 #define LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 (TIM1_OR1_ETR_ADC3_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1_ETR is connected to ADC3 analog watchdog 3 */ 01151 /** 01152 * @} 01153 */ 01154 #endif /* ADC3 */ 01155 01156 /** @defgroup TIM_LL_EC_TIM1_TI1_RMP TIM1 External Input Ch1 Remap 01157 * @{ 01158 */ 01159 #define LL_TIM_TIM1_TI1_RMP_GPIO TIM1_OR1_RMP_MASK /*!< TIM1 input capture 1 is connected to GPIO */ 01160 #define LL_TIM_TIM1_TI1_RMP_COMP1 (TIM1_OR1_TI1_RMP | TIM1_OR1_RMP_MASK) /*!< TIM1 input capture 1 is connected to COMP1 output */ 01161 /** 01162 * @} 01163 */ 01164 01165 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP TIM2 Internal Trigger1 Remap 01166 * @{ 01167 */ 01168 #if defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 01169 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR1_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */ 01170 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR1_ITR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */ 01171 #endif /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L485xx || STM32L486xx || */ 01172 /* STM32L496xx || STM32L4A6xx || */ 01173 /* STM32L4R5xx || STM32L4R7xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ 01174 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 01175 #define LL_TIM_TIM2_ITR1_RMP_NONE 0x00000000U /* !< No internal trigger on TIM2_ITR1 */ 01176 #define LL_TIM_TIM2_ITR1_RMP_USB_SOF TIM2_OR1_ITR1_RMP /* !< TIM2_ITR1 is connected to USB SOF */ 01177 #endif /* STM32L431xx || STM32L432xx || STM32L442xx || STM32L433xx || STM32L443xx || */ 01178 /* STM32L451xx || STM32L452xx || STM32L462xx */ 01179 #define LL_TIM_TIM2_ETR_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2_ETR is connected to GPIO */ 01180 #define LL_TIM_TIM2_ETR_RMP_LSE (TIM2_OR1_ETR1_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2_ETR is connected to LSE */ 01181 /** 01182 * @} 01183 */ 01184 01185 /** @defgroup TIM_LL_EC_TIM2_TI4_RMP TIM2 External Input Ch4 Remap 01186 * @{ 01187 */ 01188 #define LL_TIM_TIM2_TI4_RMP_GPIO TIM2_OR1_RMP_MASK /*!< TIM2 input capture 4 is connected to GPIO */ 01189 #define LL_TIM_TIM2_TI4_RMP_COMP1 (TIM2_OR1_TI4_RMP_0 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP1_OUT */ 01190 #define LL_TIM_TIM2_TI4_RMP_COMP2 (TIM2_OR1_TI4_RMP_1 | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to COMP2_OUT */ 01191 #define LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 (TIM2_OR1_TI4_RMP | TIM2_OR1_RMP_MASK) /*!< TIM2 input capture 4 is connected to logical OR between COMP1_OUT and COMP2_OUT */ 01192 /** 01193 * @} 01194 */ 01195 01196 #if defined(TIM3) 01197 /** @defgroup TIM_LL_EC_TIM3_TI1_RMP TIM3 External Input Ch1 Remap 01198 * @{ 01199 */ 01200 #define LL_TIM_TIM3_TI1_RMP_GPIO TIM3_OR1_RMP_MASK /*!< TIM3 input capture 1 is connected to GPIO */ 01201 #define LL_TIM_TIM3_TI1_RMP_COMP1 (TIM3_OR1_TI1_RMP_0 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP1_OUT */ 01202 #define LL_TIM_TIM3_TI1_RMP_COMP2 (TIM3_OR1_TI1_RMP_1 | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to COMP2_OUT */ 01203 #define LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 (TIM3_OR1_TI1_RMP | TIM3_OR1_RMP_MASK) /*!< TIM3 input capture 1 is connected to logical OR between COMP1_OUT and COMP2_OUT */ 01204 /** 01205 * @} 01206 */ 01207 #endif /* TIM3 */ 01208 01209 #if defined(TIM8) 01210 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC2_RMP TIM8 External Trigger ADC2 Remap 01211 * @{ 01212 */ 01213 #define LL_TIM_TIM8_ETR_ADC2_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC2 analog watchdog x */ 01214 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 (TIM8_OR1_ETR_ADC2_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog */ 01215 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 (TIM8_OR1_ETR_ADC2_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 2 */ 01216 #define LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 (TIM8_OR1_ETR_ADC2_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC2 analog watchdog 3 */ 01217 /** 01218 * @} 01219 */ 01220 01221 /** @defgroup TIM_LL_EC_TIM8_ETR_ADC3_RMP TIM8 External Trigger ADC3 Remap 01222 * @{ 01223 */ 01224 #define LL_TIM_TIM8_ETR_ADC3_RMP_NC TIM8_OR1_RMP_MASK /*!< TIM8_ETR is not connected to ADC3 analog watchdog x */ 01225 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 (TIM8_OR1_ETR_ADC3_RMP_0 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 1 */ 01226 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 (TIM8_OR1_ETR_ADC3_RMP_1 | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 2 */ 01227 #define LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 (TIM8_OR1_ETR_ADC3_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8_ETR is connected to ADC3 analog watchdog 3 */ 01228 /** 01229 * @} 01230 */ 01231 01232 /** @defgroup TIM_LL_EC_TIM8_TI1_RMP TIM8 External Input Ch1 Remap 01233 * @{ 01234 */ 01235 #define LL_TIM_TIM8_TI1_RMP_GPIO TIM8_OR1_RMP_MASK /*!< TIM8 input capture 1 is connected to GPIO */ 01236 #define LL_TIM_TIM8_TI1_RMP_COMP2 (TIM8_OR1_TI1_RMP | TIM8_OR1_RMP_MASK) /*!< TIM8 input capture 1 is connected to COMP2 output */ 01237 /** 01238 * @} 01239 */ 01240 #endif /* TIM8 */ 01241 01242 /** @defgroup TIM_LL_EC_TIM15_TI1_RMP TIM15 External Input Ch1 Remap 01243 * @{ 01244 */ 01245 #define LL_TIM_TIM15_TI1_RMP_GPIO TIM15_OR1_RMP_MASK /*!< TIM15 input capture 1 is connected to GPIO */ 01246 #define LL_TIM_TIM15_TI1_RMP_LSE (TIM15_OR1_TI1_RMP | TIM15_OR1_RMP_MASK) /*!< TIM15 input capture 1 is connected to LSE */ 01247 /** 01248 * @} 01249 */ 01250 01251 /** @defgroup TIM_LL_EC_TIM15_ENCODERMODE TIM15 ENCODERMODE 01252 * @{ 01253 */ 01254 #define LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION TIM15_OR1_RMP_MASK /*!< No redirection*/ 01255 #define LL_TIM_TIM15_ENCODERMODE_TIM2 (TIM15_OR1_ENCODER_MODE_0 | TIM15_OR1_RMP_MASK) /*!< TIM2 IC1 and TIM2 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 01256 #define LL_TIM_TIM15_ENCODERMODE_TIM3 (TIM15_OR1_ENCODER_MODE_1 | TIM15_OR1_RMP_MASK) /*!< TIM3 IC1 and TIM3 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectivel y*/ 01257 #define LL_TIM_TIM15_ENCODERMODE_TIM4 (TIM15_OR1_ENCODER_MODE | TIM15_OR1_RMP_MASK) /*!< TIM4 IC1 and TIM4 IC2 are connected to TIM15 IC1 and TIM15 IC2 respectively */ 01258 /** 01259 * @} 01260 */ 01261 01262 /** @defgroup TIM_LL_EC_TIM16_TI1_RMP TIM16 External Input Ch1 Remap 01263 * @{ 01264 */ 01265 #define LL_TIM_TIM16_TI1_RMP_GPIO TIM16_OR1_RMP_MASK /*!< TIM16 input capture 1 is connected to GPIO */ 01266 #define LL_TIM_TIM16_TI1_RMP_LSI (TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSI */ 01267 #define LL_TIM_TIM16_TI1_RMP_LSE (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to LSE */ 01268 #define LL_TIM_TIM16_TI1_RMP_RTC (TIM16_OR1_TI1_RMP_1 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to RTC wakeup interrupt */ 01269 #if defined TIM16_OR1_TI1_RMP_2 01270 #define LL_TIM_TIM16_TI1_RMP_MSI (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MSI */ 01271 #define LL_TIM_TIM16_TI1_RMP_HSE_32 (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_0 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to HSE/32 */ 01272 #define LL_TIM_TIM16_TI1_RMP_MCO (TIM16_OR1_TI1_RMP_2 | TIM16_OR1_TI1_RMP_1 | TIM16_OR1_RMP_MASK) /*!< TIM16 input capture 1 is connected to MCO */ 01273 #endif 01274 /** 01275 * @} 01276 */ 01277 01278 #if defined(TIM17) 01279 /** @defgroup TIM_LL_EC_TIM17_TI1_RMP TIM17 Timer Input Ch1 Remap 01280 * @{ 01281 */ 01282 #define LL_TIM_TIM17_TI1_RMP_GPIO TIM17_OR1_RMP_MASK /*!< TIM17 input capture 1 is connected to GPIO */ 01283 #define LL_TIM_TIM17_TI1_RMP_MSI (TIM17_OR1_TI1_RMP_0 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MSI */ 01284 #define LL_TIM_TIM17_TI1_RMP_HSE_32 (TIM17_OR1_TI1_RMP_1 | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to HSE/32 */ 01285 #define LL_TIM_TIM17_TI1_RMP_MCO (TIM17_OR1_TI1_RMP | TIM17_OR1_RMP_MASK) /*!< TIM17 input capture 1 is connected to MCO */ 01286 /** 01287 * @} 01288 */ 01289 #endif /* TIM17 */ 01290 01291 /** @defgroup TIM_LL_EC_OCREF_CLR_INT OCREF clear input selection 01292 * @{ 01293 */ 01294 #define LL_TIM_OCREF_CLR_INT_NC 0x00000000U /*!< OCREF_CLR_INT is not connected */ 01295 #define LL_TIM_OCREF_CLR_INT_ETR TIM_SMCR_OCCS /*!< OCREF_CLR_INT is connected to ETRF */ 01296 /** 01297 * @} 01298 */ 01299 01300 /** Legacy definitions for compatibility purpose 01301 @cond 0 01302 */ 01303 #define LL_TIM_BKIN_SOURCE_DFBK LL_TIM_BKIN_SOURCE_DF1BK 01304 /** 01305 @endcond 01306 */ 01307 /** 01308 * @} 01309 */ 01310 01311 /* Exported macro ------------------------------------------------------------*/ 01312 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros 01313 * @{ 01314 */ 01315 01316 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros 01317 * @{ 01318 */ 01319 /** 01320 * @brief Write a value in TIM register. 01321 * @param __INSTANCE__ TIM Instance 01322 * @param __REG__ Register to be written 01323 * @param __VALUE__ Value to be written in the register 01324 * @retval None 01325 */ 01326 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__)) 01327 01328 /** 01329 * @brief Read a value in TIM register. 01330 * @param __INSTANCE__ TIM Instance 01331 * @param __REG__ Register to be read 01332 * @retval Register value 01333 */ 01334 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) 01335 /** 01336 * @} 01337 */ 01338 01339 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros 01340 * @{ 01341 */ 01342 01343 /** 01344 * @brief HELPER macro retrieving the UIFCPY flag from the counter value. 01345 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ()); 01346 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied 01347 * to TIMx_CNT register bit 31) 01348 * @param __CNT__ Counter value 01349 * @retval UIF status bit 01350 */ 01351 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \ 01352 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos) 01353 01354 /** 01355 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. 01356 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); 01357 * @param __TIMCLK__ timer input clock frequency (in Hz) 01358 * @param __CKD__ This parameter can be one of the following values: 01359 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01360 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01361 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01362 * @param __DT__ deadtime duration (in ns) 01363 * @retval DTG[0:7] 01364 */ 01365 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ 01366 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ 01367 (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ 01368 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ 01369 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ 01370 0U) 01371 01372 /** 01373 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. 01374 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); 01375 * @param __TIMCLK__ timer input clock frequency (in Hz) 01376 * @param __CNTCLK__ counter clock frequency (in Hz) 01377 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) 01378 */ 01379 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ 01380 ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U 01381 01382 /** 01383 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. 01384 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); 01385 * @param __TIMCLK__ timer input clock frequency (in Hz) 01386 * @param __PSC__ prescaler 01387 * @param __FREQ__ output signal frequency (in Hz) 01388 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 01389 */ 01390 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ 01391 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U 01392 01393 /** 01394 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. 01395 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); 01396 * @param __TIMCLK__ timer input clock frequency (in Hz) 01397 * @param __PSC__ prescaler 01398 * @param __DELAY__ timer output compare active/inactive delay (in us) 01399 * @retval Compare value (between Min_Data=0 and Max_Data=65535) 01400 */ 01401 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ 01402 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ 01403 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) 01404 01405 /** 01406 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). 01407 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); 01408 * @param __TIMCLK__ timer input clock frequency (in Hz) 01409 * @param __PSC__ prescaler 01410 * @param __DELAY__ timer output compare active/inactive delay (in us) 01411 * @param __PULSE__ pulse duration (in us) 01412 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) 01413 */ 01414 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ 01415 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ 01416 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) 01417 01418 /** 01419 * @brief HELPER macro retrieving the ratio of the input capture prescaler 01420 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); 01421 * @param __ICPSC__ This parameter can be one of the following values: 01422 * @arg @ref LL_TIM_ICPSC_DIV1 01423 * @arg @ref LL_TIM_ICPSC_DIV2 01424 * @arg @ref LL_TIM_ICPSC_DIV4 01425 * @arg @ref LL_TIM_ICPSC_DIV8 01426 * @retval Input capture prescaler ratio (1, 2, 4 or 8) 01427 */ 01428 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ 01429 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) 01430 01431 01432 /** 01433 * @} 01434 */ 01435 01436 01437 /** 01438 * @} 01439 */ 01440 01441 /* Exported functions --------------------------------------------------------*/ 01442 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions 01443 * @{ 01444 */ 01445 01446 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration 01447 * @{ 01448 */ 01449 /** 01450 * @brief Enable timer counter. 01451 * @rmtoll CR1 CEN LL_TIM_EnableCounter 01452 * @param TIMx Timer instance 01453 * @retval None 01454 */ 01455 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) 01456 { 01457 SET_BIT(TIMx->CR1, TIM_CR1_CEN); 01458 } 01459 01460 /** 01461 * @brief Disable timer counter. 01462 * @rmtoll CR1 CEN LL_TIM_DisableCounter 01463 * @param TIMx Timer instance 01464 * @retval None 01465 */ 01466 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) 01467 { 01468 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); 01469 } 01470 01471 /** 01472 * @brief Indicates whether the timer counter is enabled. 01473 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter 01474 * @param TIMx Timer instance 01475 * @retval State of bit (1 or 0). 01476 */ 01477 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) 01478 { 01479 return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); 01480 } 01481 01482 /** 01483 * @brief Enable update event generation. 01484 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent 01485 * @param TIMx Timer instance 01486 * @retval None 01487 */ 01488 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) 01489 { 01490 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); 01491 } 01492 01493 /** 01494 * @brief Disable update event generation. 01495 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent 01496 * @param TIMx Timer instance 01497 * @retval None 01498 */ 01499 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) 01500 { 01501 SET_BIT(TIMx->CR1, TIM_CR1_UDIS); 01502 } 01503 01504 /** 01505 * @brief Indicates whether update event generation is enabled. 01506 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent 01507 * @param TIMx Timer instance 01508 * @retval Inverted state of bit (0 or 1). 01509 */ 01510 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) 01511 { 01512 return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); 01513 } 01514 01515 /** 01516 * @brief Set update event source 01517 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events 01518 * generate an update interrupt or DMA request if enabled: 01519 * - Counter overflow/underflow 01520 * - Setting the UG bit 01521 * - Update generation through the slave mode controller 01522 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter 01523 * overflow/underflow generates an update interrupt or DMA request if enabled. 01524 * @rmtoll CR1 URS LL_TIM_SetUpdateSource 01525 * @param TIMx Timer instance 01526 * @param UpdateSource This parameter can be one of the following values: 01527 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 01528 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 01529 * @retval None 01530 */ 01531 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) 01532 { 01533 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); 01534 } 01535 01536 /** 01537 * @brief Get actual event update source 01538 * @rmtoll CR1 URS LL_TIM_GetUpdateSource 01539 * @param TIMx Timer instance 01540 * @retval Returned value can be one of the following values: 01541 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR 01542 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER 01543 */ 01544 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) 01545 { 01546 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); 01547 } 01548 01549 /** 01550 * @brief Set one pulse mode (one shot v.s. repetitive). 01551 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode 01552 * @param TIMx Timer instance 01553 * @param OnePulseMode This parameter can be one of the following values: 01554 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 01555 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 01556 * @retval None 01557 */ 01558 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) 01559 { 01560 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); 01561 } 01562 01563 /** 01564 * @brief Get actual one pulse mode. 01565 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode 01566 * @param TIMx Timer instance 01567 * @retval Returned value can be one of the following values: 01568 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE 01569 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE 01570 */ 01571 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) 01572 { 01573 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); 01574 } 01575 01576 /** 01577 * @brief Set the timer counter counting mode. 01578 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 01579 * check whether or not the counter mode selection feature is supported 01580 * by a timer instance. 01581 * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) 01582 * requires a timer reset to avoid unexpected direction 01583 * due to DIR bit readonly in center aligned mode. 01584 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n 01585 * CR1 CMS LL_TIM_SetCounterMode 01586 * @param TIMx Timer instance 01587 * @param CounterMode This parameter can be one of the following values: 01588 * @arg @ref LL_TIM_COUNTERMODE_UP 01589 * @arg @ref LL_TIM_COUNTERMODE_DOWN 01590 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 01591 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 01592 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 01593 * @retval None 01594 */ 01595 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) 01596 { 01597 MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); 01598 } 01599 01600 /** 01601 * @brief Get actual counter mode. 01602 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to 01603 * check whether or not the counter mode selection feature is supported 01604 * by a timer instance. 01605 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n 01606 * CR1 CMS LL_TIM_GetCounterMode 01607 * @param TIMx Timer instance 01608 * @retval Returned value can be one of the following values: 01609 * @arg @ref LL_TIM_COUNTERMODE_UP 01610 * @arg @ref LL_TIM_COUNTERMODE_DOWN 01611 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP 01612 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN 01613 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN 01614 */ 01615 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) 01616 { 01617 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); 01618 } 01619 01620 /** 01621 * @brief Enable auto-reload (ARR) preload. 01622 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload 01623 * @param TIMx Timer instance 01624 * @retval None 01625 */ 01626 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) 01627 { 01628 SET_BIT(TIMx->CR1, TIM_CR1_ARPE); 01629 } 01630 01631 /** 01632 * @brief Disable auto-reload (ARR) preload. 01633 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload 01634 * @param TIMx Timer instance 01635 * @retval None 01636 */ 01637 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) 01638 { 01639 CLEAR_BIT(TIMx->CR1,TIM_CR1_ARPE); 01640 } 01641 01642 /** 01643 * @brief Indicates whether auto-reload (ARR) preload is enabled. 01644 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload 01645 * @param TIMx Timer instance 01646 * @retval State of bit (1 or 0). 01647 */ 01648 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) 01649 { 01650 return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); 01651 } 01652 01653 /** 01654 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. 01655 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 01656 * whether or not the clock division feature is supported by the timer 01657 * instance. 01658 * @rmtoll CR1 CKD LL_TIM_SetClockDivision 01659 * @param TIMx Timer instance 01660 * @param ClockDivision This parameter can be one of the following values: 01661 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01662 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01663 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01664 * @retval None 01665 */ 01666 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) 01667 { 01668 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); 01669 } 01670 01671 /** 01672 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. 01673 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check 01674 * whether or not the clock division feature is supported by the timer 01675 * instance. 01676 * @rmtoll CR1 CKD LL_TIM_GetClockDivision 01677 * @param TIMx Timer instance 01678 * @retval Returned value can be one of the following values: 01679 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 01680 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 01681 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 01682 */ 01683 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) 01684 { 01685 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); 01686 } 01687 01688 /** 01689 * @brief Set the counter value. 01690 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01691 * whether or not a timer instance supports a 32 bits counter. 01692 * @rmtoll CNT CNT LL_TIM_SetCounter 01693 * @param TIMx Timer instance 01694 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 01695 * @retval None 01696 */ 01697 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) 01698 { 01699 WRITE_REG(TIMx->CNT, Counter); 01700 } 01701 01702 /** 01703 * @brief Get the counter value. 01704 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01705 * whether or not a timer instance supports a 32 bits counter. 01706 * @rmtoll CNT CNT LL_TIM_GetCounter 01707 * @param TIMx Timer instance 01708 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF) 01709 */ 01710 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) 01711 { 01712 return (uint32_t)(READ_REG(TIMx->CNT)); 01713 } 01714 01715 /** 01716 * @brief Get the current direction of the counter 01717 * @rmtoll CR1 DIR LL_TIM_GetDirection 01718 * @param TIMx Timer instance 01719 * @retval Returned value can be one of the following values: 01720 * @arg @ref LL_TIM_COUNTERDIRECTION_UP 01721 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN 01722 */ 01723 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) 01724 { 01725 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); 01726 } 01727 01728 /** 01729 * @brief Set the prescaler value. 01730 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). 01731 * @note The prescaler can be changed on the fly as this control register is buffered. The new 01732 * prescaler ratio is taken into account at the next update event. 01733 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter 01734 * @rmtoll PSC PSC LL_TIM_SetPrescaler 01735 * @param TIMx Timer instance 01736 * @param Prescaler between Min_Data=0 and Max_Data=65535 01737 * @retval None 01738 */ 01739 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) 01740 { 01741 WRITE_REG(TIMx->PSC, Prescaler); 01742 } 01743 01744 /** 01745 * @brief Get the prescaler value. 01746 * @rmtoll PSC PSC LL_TIM_GetPrescaler 01747 * @param TIMx Timer instance 01748 * @retval Prescaler value between Min_Data=0 and Max_Data=65535 01749 */ 01750 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) 01751 { 01752 return (uint32_t)(READ_REG(TIMx->PSC)); 01753 } 01754 01755 /** 01756 * @brief Set the auto-reload value. 01757 * @note The counter is blocked while the auto-reload value is null. 01758 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01759 * whether or not a timer instance supports a 32 bits counter. 01760 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter 01761 * @rmtoll ARR ARR LL_TIM_SetAutoReload 01762 * @param TIMx Timer instance 01763 * @param AutoReload between Min_Data=0 and Max_Data=65535 01764 * @retval None 01765 */ 01766 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) 01767 { 01768 WRITE_REG(TIMx->ARR, AutoReload); 01769 } 01770 01771 /** 01772 * @brief Get the auto-reload value. 01773 * @rmtoll ARR ARR LL_TIM_GetAutoReload 01774 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 01775 * whether or not a timer instance supports a 32 bits counter. 01776 * @param TIMx Timer instance 01777 * @retval Auto-reload value 01778 */ 01779 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) 01780 { 01781 return (uint32_t)(READ_REG(TIMx->ARR)); 01782 } 01783 01784 /** 01785 * @brief Set the repetition counter value. 01786 * @note For advanced timer instances RepetitionCounter can be up to 65535. 01787 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 01788 * whether or not a timer instance supports a repetition counter. 01789 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter 01790 * @param TIMx Timer instance 01791 * @param RepetitionCounter between Min_Data=0 and Max_Data=255 01792 * @retval None 01793 */ 01794 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) 01795 { 01796 WRITE_REG(TIMx->RCR, RepetitionCounter); 01797 } 01798 01799 /** 01800 * @brief Get the repetition counter value. 01801 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check 01802 * whether or not a timer instance supports a repetition counter. 01803 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter 01804 * @param TIMx Timer instance 01805 * @retval Repetition counter value 01806 */ 01807 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) 01808 { 01809 return (uint32_t)(READ_REG(TIMx->RCR)); 01810 } 01811 01812 /** 01813 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31). 01814 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way. 01815 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap 01816 * @param TIMx Timer instance 01817 * @retval None 01818 */ 01819 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx) 01820 { 01821 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 01822 } 01823 01824 /** 01825 * @brief Disable update interrupt flag (UIF) remapping. 01826 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap 01827 * @param TIMx Timer instance 01828 * @retval None 01829 */ 01830 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx) 01831 { 01832 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP); 01833 } 01834 01835 /** 01836 * @} 01837 */ 01838 01839 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration 01840 * @{ 01841 */ 01842 /** 01843 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 01844 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, 01845 * they are updated only when a commutation event (COM) occurs. 01846 * @note Only on channels that have a complementary output. 01847 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01848 * whether or not a timer instance is able to generate a commutation event. 01849 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload 01850 * @param TIMx Timer instance 01851 * @retval None 01852 */ 01853 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) 01854 { 01855 SET_BIT(TIMx->CR2, TIM_CR2_CCPC); 01856 } 01857 01858 /** 01859 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. 01860 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01861 * whether or not a timer instance is able to generate a commutation event. 01862 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload 01863 * @param TIMx Timer instance 01864 * @retval None 01865 */ 01866 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) 01867 { 01868 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); 01869 } 01870 01871 /** 01872 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). 01873 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check 01874 * whether or not a timer instance is able to generate a commutation event. 01875 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate 01876 * @param TIMx Timer instance 01877 * @param CCUpdateSource This parameter can be one of the following values: 01878 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY 01879 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI 01880 * @retval None 01881 */ 01882 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) 01883 { 01884 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); 01885 } 01886 01887 /** 01888 * @brief Set the trigger of the capture/compare DMA request. 01889 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger 01890 * @param TIMx Timer instance 01891 * @param DMAReqTrigger This parameter can be one of the following values: 01892 * @arg @ref LL_TIM_CCDMAREQUEST_CC 01893 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 01894 * @retval None 01895 */ 01896 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) 01897 { 01898 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); 01899 } 01900 01901 /** 01902 * @brief Get actual trigger of the capture/compare DMA request. 01903 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger 01904 * @param TIMx Timer instance 01905 * @retval Returned value can be one of the following values: 01906 * @arg @ref LL_TIM_CCDMAREQUEST_CC 01907 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE 01908 */ 01909 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) 01910 { 01911 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); 01912 } 01913 01914 /** 01915 * @brief Set the lock level to freeze the 01916 * configuration of several capture/compare parameters. 01917 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 01918 * the lock mechanism is supported by a timer instance. 01919 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel 01920 * @param TIMx Timer instance 01921 * @param LockLevel This parameter can be one of the following values: 01922 * @arg @ref LL_TIM_LOCKLEVEL_OFF 01923 * @arg @ref LL_TIM_LOCKLEVEL_1 01924 * @arg @ref LL_TIM_LOCKLEVEL_2 01925 * @arg @ref LL_TIM_LOCKLEVEL_3 01926 * @retval None 01927 */ 01928 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) 01929 { 01930 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); 01931 } 01932 01933 /** 01934 * @brief Enable capture/compare channels. 01935 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n 01936 * CCER CC1NE LL_TIM_CC_EnableChannel\n 01937 * CCER CC2E LL_TIM_CC_EnableChannel\n 01938 * CCER CC2NE LL_TIM_CC_EnableChannel\n 01939 * CCER CC3E LL_TIM_CC_EnableChannel\n 01940 * CCER CC3NE LL_TIM_CC_EnableChannel\n 01941 * CCER CC4E LL_TIM_CC_EnableChannel\n 01942 * CCER CC5E LL_TIM_CC_EnableChannel\n 01943 * CCER CC6E LL_TIM_CC_EnableChannel 01944 * @param TIMx Timer instance 01945 * @param Channels This parameter can be a combination of the following values: 01946 * @arg @ref LL_TIM_CHANNEL_CH1 01947 * @arg @ref LL_TIM_CHANNEL_CH1N 01948 * @arg @ref LL_TIM_CHANNEL_CH2 01949 * @arg @ref LL_TIM_CHANNEL_CH2N 01950 * @arg @ref LL_TIM_CHANNEL_CH3 01951 * @arg @ref LL_TIM_CHANNEL_CH3N 01952 * @arg @ref LL_TIM_CHANNEL_CH4 01953 * @arg @ref LL_TIM_CHANNEL_CH5 01954 * @arg @ref LL_TIM_CHANNEL_CH6 01955 * @retval None 01956 */ 01957 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 01958 { 01959 SET_BIT(TIMx->CCER, Channels); 01960 } 01961 01962 /** 01963 * @brief Disable capture/compare channels. 01964 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n 01965 * CCER CC1NE LL_TIM_CC_DisableChannel\n 01966 * CCER CC2E LL_TIM_CC_DisableChannel\n 01967 * CCER CC2NE LL_TIM_CC_DisableChannel\n 01968 * CCER CC3E LL_TIM_CC_DisableChannel\n 01969 * CCER CC3NE LL_TIM_CC_DisableChannel\n 01970 * CCER CC4E LL_TIM_CC_DisableChannel\n 01971 * CCER CC5E LL_TIM_CC_DisableChannel\n 01972 * CCER CC6E LL_TIM_CC_DisableChannel 01973 * @param TIMx Timer instance 01974 * @param Channels This parameter can be a combination of the following values: 01975 * @arg @ref LL_TIM_CHANNEL_CH1 01976 * @arg @ref LL_TIM_CHANNEL_CH1N 01977 * @arg @ref LL_TIM_CHANNEL_CH2 01978 * @arg @ref LL_TIM_CHANNEL_CH2N 01979 * @arg @ref LL_TIM_CHANNEL_CH3 01980 * @arg @ref LL_TIM_CHANNEL_CH3N 01981 * @arg @ref LL_TIM_CHANNEL_CH4 01982 * @arg @ref LL_TIM_CHANNEL_CH5 01983 * @arg @ref LL_TIM_CHANNEL_CH6 01984 * @retval None 01985 */ 01986 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) 01987 { 01988 CLEAR_BIT(TIMx->CCER, Channels); 01989 } 01990 01991 /** 01992 * @brief Indicate whether channel(s) is(are) enabled. 01993 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n 01994 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n 01995 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n 01996 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n 01997 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n 01998 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n 01999 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n 02000 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n 02001 * CCER CC6E LL_TIM_CC_IsEnabledChannel 02002 * @param TIMx Timer instance 02003 * @param Channels This parameter can be a combination of the following values: 02004 * @arg @ref LL_TIM_CHANNEL_CH1 02005 * @arg @ref LL_TIM_CHANNEL_CH1N 02006 * @arg @ref LL_TIM_CHANNEL_CH2 02007 * @arg @ref LL_TIM_CHANNEL_CH2N 02008 * @arg @ref LL_TIM_CHANNEL_CH3 02009 * @arg @ref LL_TIM_CHANNEL_CH3N 02010 * @arg @ref LL_TIM_CHANNEL_CH4 02011 * @arg @ref LL_TIM_CHANNEL_CH5 02012 * @arg @ref LL_TIM_CHANNEL_CH6 02013 * @retval State of bit (1 or 0). 02014 */ 02015 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) 02016 { 02017 return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); 02018 } 02019 02020 /** 02021 * @} 02022 */ 02023 02024 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration 02025 * @{ 02026 */ 02027 /** 02028 * @brief Configure an output channel. 02029 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n 02030 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n 02031 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n 02032 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n 02033 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n 02034 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n 02035 * CCER CC1P LL_TIM_OC_ConfigOutput\n 02036 * CCER CC2P LL_TIM_OC_ConfigOutput\n 02037 * CCER CC3P LL_TIM_OC_ConfigOutput\n 02038 * CCER CC4P LL_TIM_OC_ConfigOutput\n 02039 * CCER CC5P LL_TIM_OC_ConfigOutput\n 02040 * CCER CC6P LL_TIM_OC_ConfigOutput\n 02041 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n 02042 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n 02043 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n 02044 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n 02045 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n 02046 * CR2 OIS6 LL_TIM_OC_ConfigOutput 02047 * @param TIMx Timer instance 02048 * @param Channel This parameter can be one of the following values: 02049 * @arg @ref LL_TIM_CHANNEL_CH1 02050 * @arg @ref LL_TIM_CHANNEL_CH2 02051 * @arg @ref LL_TIM_CHANNEL_CH3 02052 * @arg @ref LL_TIM_CHANNEL_CH4 02053 * @arg @ref LL_TIM_CHANNEL_CH5 02054 * @arg @ref LL_TIM_CHANNEL_CH6 02055 * @param Configuration This parameter must be a combination of all the following values: 02056 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW 02057 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH 02058 * @retval None 02059 */ 02060 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 02061 { 02062 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02063 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02064 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); 02065 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), 02066 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); 02067 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), 02068 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); 02069 } 02070 02071 /** 02072 * @brief Define the behavior of the output reference signal OCxREF from which 02073 * OCx and OCxN (when relevant) are derived. 02074 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n 02075 * CCMR1 OC2M LL_TIM_OC_SetMode\n 02076 * CCMR2 OC3M LL_TIM_OC_SetMode\n 02077 * CCMR2 OC4M LL_TIM_OC_SetMode\n 02078 * CCMR3 OC5M LL_TIM_OC_SetMode\n 02079 * CCMR3 OC6M LL_TIM_OC_SetMode 02080 * @param TIMx Timer instance 02081 * @param Channel This parameter can be one of the following values: 02082 * @arg @ref LL_TIM_CHANNEL_CH1 02083 * @arg @ref LL_TIM_CHANNEL_CH2 02084 * @arg @ref LL_TIM_CHANNEL_CH3 02085 * @arg @ref LL_TIM_CHANNEL_CH4 02086 * @arg @ref LL_TIM_CHANNEL_CH5 02087 * @arg @ref LL_TIM_CHANNEL_CH6 02088 * @param Mode This parameter can be one of the following values: 02089 * @arg @ref LL_TIM_OCMODE_FROZEN 02090 * @arg @ref LL_TIM_OCMODE_ACTIVE 02091 * @arg @ref LL_TIM_OCMODE_INACTIVE 02092 * @arg @ref LL_TIM_OCMODE_TOGGLE 02093 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 02094 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 02095 * @arg @ref LL_TIM_OCMODE_PWM1 02096 * @arg @ref LL_TIM_OCMODE_PWM2 02097 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 02098 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 02099 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 02100 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 02101 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 02102 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 02103 * @retval None 02104 */ 02105 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) 02106 { 02107 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02108 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02109 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); 02110 } 02111 02112 /** 02113 * @brief Get the output compare mode of an output channel. 02114 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n 02115 * CCMR1 OC2M LL_TIM_OC_GetMode\n 02116 * CCMR2 OC3M LL_TIM_OC_GetMode\n 02117 * CCMR2 OC4M LL_TIM_OC_GetMode\n 02118 * CCMR3 OC5M LL_TIM_OC_GetMode\n 02119 * CCMR3 OC6M LL_TIM_OC_GetMode 02120 * @param TIMx Timer instance 02121 * @param Channel This parameter can be one of the following values: 02122 * @arg @ref LL_TIM_CHANNEL_CH1 02123 * @arg @ref LL_TIM_CHANNEL_CH2 02124 * @arg @ref LL_TIM_CHANNEL_CH3 02125 * @arg @ref LL_TIM_CHANNEL_CH4 02126 * @arg @ref LL_TIM_CHANNEL_CH5 02127 * @arg @ref LL_TIM_CHANNEL_CH6 02128 * @retval Returned value can be one of the following values: 02129 * @arg @ref LL_TIM_OCMODE_FROZEN 02130 * @arg @ref LL_TIM_OCMODE_ACTIVE 02131 * @arg @ref LL_TIM_OCMODE_INACTIVE 02132 * @arg @ref LL_TIM_OCMODE_TOGGLE 02133 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE 02134 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE 02135 * @arg @ref LL_TIM_OCMODE_PWM1 02136 * @arg @ref LL_TIM_OCMODE_PWM2 02137 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1 02138 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 02139 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 02140 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 02141 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 02142 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 02143 */ 02144 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) 02145 { 02146 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02147 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02148 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); 02149 } 02150 02151 /** 02152 * @brief Set the polarity of an output channel. 02153 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n 02154 * CCER CC1NP LL_TIM_OC_SetPolarity\n 02155 * CCER CC2P LL_TIM_OC_SetPolarity\n 02156 * CCER CC2NP LL_TIM_OC_SetPolarity\n 02157 * CCER CC3P LL_TIM_OC_SetPolarity\n 02158 * CCER CC3NP LL_TIM_OC_SetPolarity\n 02159 * CCER CC4P LL_TIM_OC_SetPolarity\n 02160 * CCER CC5P LL_TIM_OC_SetPolarity\n 02161 * CCER CC6P LL_TIM_OC_SetPolarity 02162 * @param TIMx Timer instance 02163 * @param Channel This parameter can be one of the following values: 02164 * @arg @ref LL_TIM_CHANNEL_CH1 02165 * @arg @ref LL_TIM_CHANNEL_CH1N 02166 * @arg @ref LL_TIM_CHANNEL_CH2 02167 * @arg @ref LL_TIM_CHANNEL_CH2N 02168 * @arg @ref LL_TIM_CHANNEL_CH3 02169 * @arg @ref LL_TIM_CHANNEL_CH3N 02170 * @arg @ref LL_TIM_CHANNEL_CH4 02171 * @arg @ref LL_TIM_CHANNEL_CH5 02172 * @arg @ref LL_TIM_CHANNEL_CH6 02173 * @param Polarity This parameter can be one of the following values: 02174 * @arg @ref LL_TIM_OCPOLARITY_HIGH 02175 * @arg @ref LL_TIM_OCPOLARITY_LOW 02176 * @retval None 02177 */ 02178 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) 02179 { 02180 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02181 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); 02182 } 02183 02184 /** 02185 * @brief Get the polarity of an output channel. 02186 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n 02187 * CCER CC1NP LL_TIM_OC_GetPolarity\n 02188 * CCER CC2P LL_TIM_OC_GetPolarity\n 02189 * CCER CC2NP LL_TIM_OC_GetPolarity\n 02190 * CCER CC3P LL_TIM_OC_GetPolarity\n 02191 * CCER CC3NP LL_TIM_OC_GetPolarity\n 02192 * CCER CC4P LL_TIM_OC_GetPolarity\n 02193 * CCER CC5P LL_TIM_OC_GetPolarity\n 02194 * CCER CC6P LL_TIM_OC_GetPolarity 02195 * @param TIMx Timer instance 02196 * @param Channel This parameter can be one of the following values: 02197 * @arg @ref LL_TIM_CHANNEL_CH1 02198 * @arg @ref LL_TIM_CHANNEL_CH1N 02199 * @arg @ref LL_TIM_CHANNEL_CH2 02200 * @arg @ref LL_TIM_CHANNEL_CH2N 02201 * @arg @ref LL_TIM_CHANNEL_CH3 02202 * @arg @ref LL_TIM_CHANNEL_CH3N 02203 * @arg @ref LL_TIM_CHANNEL_CH4 02204 * @arg @ref LL_TIM_CHANNEL_CH5 02205 * @arg @ref LL_TIM_CHANNEL_CH6 02206 * @retval Returned value can be one of the following values: 02207 * @arg @ref LL_TIM_OCPOLARITY_HIGH 02208 * @arg @ref LL_TIM_OCPOLARITY_LOW 02209 */ 02210 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) 02211 { 02212 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02213 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); 02214 } 02215 02216 /** 02217 * @brief Set the IDLE state of an output channel 02218 * @note This function is significant only for the timer instances 02219 * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) 02220 * can be used to check whether or not a timer instance provides 02221 * a break input. 02222 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n 02223 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 02224 * CR2 OIS2 LL_TIM_OC_SetIdleState\n 02225 * CR2 OIS2N LL_TIM_OC_SetIdleState\n 02226 * CR2 OIS3 LL_TIM_OC_SetIdleState\n 02227 * CR2 OIS3N LL_TIM_OC_SetIdleState\n 02228 * CR2 OIS4 LL_TIM_OC_SetIdleState\n 02229 * CR2 OIS5 LL_TIM_OC_SetIdleState\n 02230 * CR2 OIS6 LL_TIM_OC_SetIdleState 02231 * @param TIMx Timer instance 02232 * @param Channel This parameter can be one of the following values: 02233 * @arg @ref LL_TIM_CHANNEL_CH1 02234 * @arg @ref LL_TIM_CHANNEL_CH1N 02235 * @arg @ref LL_TIM_CHANNEL_CH2 02236 * @arg @ref LL_TIM_CHANNEL_CH2N 02237 * @arg @ref LL_TIM_CHANNEL_CH3 02238 * @arg @ref LL_TIM_CHANNEL_CH3N 02239 * @arg @ref LL_TIM_CHANNEL_CH4 02240 * @arg @ref LL_TIM_CHANNEL_CH5 02241 * @arg @ref LL_TIM_CHANNEL_CH6 02242 * @param IdleState This parameter can be one of the following values: 02243 * @arg @ref LL_TIM_OCIDLESTATE_LOW 02244 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 02245 * @retval None 02246 */ 02247 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) 02248 { 02249 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02250 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); 02251 } 02252 02253 /** 02254 * @brief Get the IDLE state of an output channel 02255 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n 02256 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 02257 * CR2 OIS2 LL_TIM_OC_GetIdleState\n 02258 * CR2 OIS2N LL_TIM_OC_GetIdleState\n 02259 * CR2 OIS3 LL_TIM_OC_GetIdleState\n 02260 * CR2 OIS3N LL_TIM_OC_GetIdleState\n 02261 * CR2 OIS4 LL_TIM_OC_GetIdleState\n 02262 * CR2 OIS5 LL_TIM_OC_GetIdleState\n 02263 * CR2 OIS6 LL_TIM_OC_GetIdleState 02264 * @param TIMx Timer instance 02265 * @param Channel This parameter can be one of the following values: 02266 * @arg @ref LL_TIM_CHANNEL_CH1 02267 * @arg @ref LL_TIM_CHANNEL_CH1N 02268 * @arg @ref LL_TIM_CHANNEL_CH2 02269 * @arg @ref LL_TIM_CHANNEL_CH2N 02270 * @arg @ref LL_TIM_CHANNEL_CH3 02271 * @arg @ref LL_TIM_CHANNEL_CH3N 02272 * @arg @ref LL_TIM_CHANNEL_CH4 02273 * @arg @ref LL_TIM_CHANNEL_CH5 02274 * @arg @ref LL_TIM_CHANNEL_CH6 02275 * @retval Returned value can be one of the following values: 02276 * @arg @ref LL_TIM_OCIDLESTATE_LOW 02277 * @arg @ref LL_TIM_OCIDLESTATE_HIGH 02278 */ 02279 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) 02280 { 02281 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02282 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); 02283 } 02284 02285 /** 02286 * @brief Enable fast mode for the output channel. 02287 * @note Acts only if the channel is configured in PWM1 or PWM2 mode. 02288 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n 02289 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n 02290 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n 02291 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n 02292 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n 02293 * CCMR3 OC6FE LL_TIM_OC_EnableFast 02294 * @param TIMx Timer instance 02295 * @param Channel This parameter can be one of the following values: 02296 * @arg @ref LL_TIM_CHANNEL_CH1 02297 * @arg @ref LL_TIM_CHANNEL_CH2 02298 * @arg @ref LL_TIM_CHANNEL_CH3 02299 * @arg @ref LL_TIM_CHANNEL_CH4 02300 * @arg @ref LL_TIM_CHANNEL_CH5 02301 * @arg @ref LL_TIM_CHANNEL_CH6 02302 * @retval None 02303 */ 02304 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) 02305 { 02306 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02307 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02308 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 02309 02310 } 02311 02312 /** 02313 * @brief Disable fast mode for the output channel. 02314 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n 02315 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n 02316 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n 02317 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n 02318 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n 02319 * CCMR3 OC6FE LL_TIM_OC_DisableFast 02320 * @param TIMx Timer instance 02321 * @param Channel This parameter can be one of the following values: 02322 * @arg @ref LL_TIM_CHANNEL_CH1 02323 * @arg @ref LL_TIM_CHANNEL_CH2 02324 * @arg @ref LL_TIM_CHANNEL_CH3 02325 * @arg @ref LL_TIM_CHANNEL_CH4 02326 * @arg @ref LL_TIM_CHANNEL_CH5 02327 * @arg @ref LL_TIM_CHANNEL_CH6 02328 * @retval None 02329 */ 02330 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) 02331 { 02332 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02333 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02334 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); 02335 02336 } 02337 02338 /** 02339 * @brief Indicates whether fast mode is enabled for the output channel. 02340 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n 02341 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n 02342 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n 02343 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n 02344 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n 02345 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast 02346 * @param TIMx Timer instance 02347 * @param Channel This parameter can be one of the following values: 02348 * @arg @ref LL_TIM_CHANNEL_CH1 02349 * @arg @ref LL_TIM_CHANNEL_CH2 02350 * @arg @ref LL_TIM_CHANNEL_CH3 02351 * @arg @ref LL_TIM_CHANNEL_CH4 02352 * @arg @ref LL_TIM_CHANNEL_CH5 02353 * @arg @ref LL_TIM_CHANNEL_CH6 02354 * @retval State of bit (1 or 0). 02355 */ 02356 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) 02357 { 02358 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02359 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02360 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; 02361 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 02362 } 02363 02364 /** 02365 * @brief Enable compare register (TIMx_CCRx) preload for the output channel. 02366 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n 02367 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n 02368 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n 02369 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n 02370 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n 02371 * CCMR3 OC6PE LL_TIM_OC_EnablePreload 02372 * @param TIMx Timer instance 02373 * @param Channel This parameter can be one of the following values: 02374 * @arg @ref LL_TIM_CHANNEL_CH1 02375 * @arg @ref LL_TIM_CHANNEL_CH2 02376 * @arg @ref LL_TIM_CHANNEL_CH3 02377 * @arg @ref LL_TIM_CHANNEL_CH4 02378 * @arg @ref LL_TIM_CHANNEL_CH5 02379 * @arg @ref LL_TIM_CHANNEL_CH6 02380 * @retval None 02381 */ 02382 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 02383 { 02384 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02385 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02386 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 02387 } 02388 02389 /** 02390 * @brief Disable compare register (TIMx_CCRx) preload for the output channel. 02391 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n 02392 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n 02393 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n 02394 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n 02395 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n 02396 * CCMR3 OC6PE LL_TIM_OC_DisablePreload 02397 * @param TIMx Timer instance 02398 * @param Channel This parameter can be one of the following values: 02399 * @arg @ref LL_TIM_CHANNEL_CH1 02400 * @arg @ref LL_TIM_CHANNEL_CH2 02401 * @arg @ref LL_TIM_CHANNEL_CH3 02402 * @arg @ref LL_TIM_CHANNEL_CH4 02403 * @arg @ref LL_TIM_CHANNEL_CH5 02404 * @arg @ref LL_TIM_CHANNEL_CH6 02405 * @retval None 02406 */ 02407 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) 02408 { 02409 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02410 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02411 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); 02412 } 02413 02414 /** 02415 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. 02416 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n 02417 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n 02418 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n 02419 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n 02420 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n 02421 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload 02422 * @param TIMx Timer instance 02423 * @param Channel This parameter can be one of the following values: 02424 * @arg @ref LL_TIM_CHANNEL_CH1 02425 * @arg @ref LL_TIM_CHANNEL_CH2 02426 * @arg @ref LL_TIM_CHANNEL_CH3 02427 * @arg @ref LL_TIM_CHANNEL_CH4 02428 * @arg @ref LL_TIM_CHANNEL_CH5 02429 * @arg @ref LL_TIM_CHANNEL_CH6 02430 * @retval State of bit (1 or 0). 02431 */ 02432 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) 02433 { 02434 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02435 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02436 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; 02437 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 02438 } 02439 02440 /** 02441 * @brief Enable clearing the output channel on an external event. 02442 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 02443 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02444 * or not a timer instance can clear the OCxREF signal on an external event. 02445 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n 02446 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n 02447 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n 02448 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n 02449 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n 02450 * CCMR3 OC6CE LL_TIM_OC_EnableClear 02451 * @param TIMx Timer instance 02452 * @param Channel This parameter can be one of the following values: 02453 * @arg @ref LL_TIM_CHANNEL_CH1 02454 * @arg @ref LL_TIM_CHANNEL_CH2 02455 * @arg @ref LL_TIM_CHANNEL_CH3 02456 * @arg @ref LL_TIM_CHANNEL_CH4 02457 * @arg @ref LL_TIM_CHANNEL_CH5 02458 * @arg @ref LL_TIM_CHANNEL_CH6 02459 * @retval None 02460 */ 02461 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) 02462 { 02463 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02464 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02465 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 02466 } 02467 02468 /** 02469 * @brief Disable clearing the output channel on an external event. 02470 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02471 * or not a timer instance can clear the OCxREF signal on an external event. 02472 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n 02473 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n 02474 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n 02475 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n 02476 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n 02477 * CCMR3 OC6CE LL_TIM_OC_DisableClear 02478 * @param TIMx Timer instance 02479 * @param Channel This parameter can be one of the following values: 02480 * @arg @ref LL_TIM_CHANNEL_CH1 02481 * @arg @ref LL_TIM_CHANNEL_CH2 02482 * @arg @ref LL_TIM_CHANNEL_CH3 02483 * @arg @ref LL_TIM_CHANNEL_CH4 02484 * @arg @ref LL_TIM_CHANNEL_CH5 02485 * @arg @ref LL_TIM_CHANNEL_CH6 02486 * @retval None 02487 */ 02488 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) 02489 { 02490 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02491 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02492 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); 02493 } 02494 02495 /** 02496 * @brief Indicates clearing the output channel on an external event is enabled for the output channel. 02497 * @note This function enables clearing the output channel on an external event. 02498 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. 02499 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether 02500 * or not a timer instance can clear the OCxREF signal on an external event. 02501 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n 02502 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n 02503 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n 02504 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n 02505 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n 02506 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear 02507 * @param TIMx Timer instance 02508 * @param Channel This parameter can be one of the following values: 02509 * @arg @ref LL_TIM_CHANNEL_CH1 02510 * @arg @ref LL_TIM_CHANNEL_CH2 02511 * @arg @ref LL_TIM_CHANNEL_CH3 02512 * @arg @ref LL_TIM_CHANNEL_CH4 02513 * @arg @ref LL_TIM_CHANNEL_CH5 02514 * @arg @ref LL_TIM_CHANNEL_CH6 02515 * @retval State of bit (1 or 0). 02516 */ 02517 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) 02518 { 02519 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02520 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02521 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; 02522 return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); 02523 } 02524 02525 /** 02526 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). 02527 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 02528 * dead-time insertion feature is supported by a timer instance. 02529 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter 02530 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime 02531 * @param TIMx Timer instance 02532 * @param DeadTime between Min_Data=0 and Max_Data=255 02533 * @retval None 02534 */ 02535 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) 02536 { 02537 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); 02538 } 02539 02540 /** 02541 * @brief Set compare value for output channel 1 (TIMx_CCR1). 02542 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02543 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02544 * whether or not a timer instance supports a 32 bits counter. 02545 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02546 * output channel 1 is supported by a timer instance. 02547 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 02548 * @param TIMx Timer instance 02549 * @param CompareValue between Min_Data=0 and Max_Data=65535 02550 * @retval None 02551 */ 02552 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) 02553 { 02554 WRITE_REG(TIMx->CCR1, CompareValue); 02555 } 02556 02557 /** 02558 * @brief Set compare value for output channel 2 (TIMx_CCR2). 02559 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02560 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02561 * whether or not a timer instance supports a 32 bits counter. 02562 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02563 * output channel 2 is supported by a timer instance. 02564 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 02565 * @param TIMx Timer instance 02566 * @param CompareValue between Min_Data=0 and Max_Data=65535 02567 * @retval None 02568 */ 02569 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) 02570 { 02571 WRITE_REG(TIMx->CCR2, CompareValue); 02572 } 02573 02574 /** 02575 * @brief Set compare value for output channel 3 (TIMx_CCR3). 02576 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02577 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02578 * whether or not a timer instance supports a 32 bits counter. 02579 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02580 * output channel is supported by a timer instance. 02581 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 02582 * @param TIMx Timer instance 02583 * @param CompareValue between Min_Data=0 and Max_Data=65535 02584 * @retval None 02585 */ 02586 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) 02587 { 02588 WRITE_REG(TIMx->CCR3, CompareValue); 02589 } 02590 02591 /** 02592 * @brief Set compare value for output channel 4 (TIMx_CCR4). 02593 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF. 02594 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02595 * whether or not a timer instance supports a 32 bits counter. 02596 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02597 * output channel 4 is supported by a timer instance. 02598 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 02599 * @param TIMx Timer instance 02600 * @param CompareValue between Min_Data=0 and Max_Data=65535 02601 * @retval None 02602 */ 02603 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) 02604 { 02605 WRITE_REG(TIMx->CCR4, CompareValue); 02606 } 02607 02608 /** 02609 * @brief Set compare value for output channel 5 (TIMx_CCR5). 02610 * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 02611 * output channel 5 is supported by a timer instance. 02612 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5 02613 * @param TIMx Timer instance 02614 * @param CompareValue between Min_Data=0 and Max_Data=65535 02615 * @retval None 02616 */ 02617 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue) 02618 { 02619 WRITE_REG(TIMx->CCR5, CompareValue); 02620 } 02621 02622 /** 02623 * @brief Set compare value for output channel 6 (TIMx_CCR6). 02624 * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 02625 * output channel 6 is supported by a timer instance. 02626 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6 02627 * @param TIMx Timer instance 02628 * @param CompareValue between Min_Data=0 and Max_Data=65535 02629 * @retval None 02630 */ 02631 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue) 02632 { 02633 WRITE_REG(TIMx->CCR6, CompareValue); 02634 } 02635 02636 /** 02637 * @brief Get compare value (TIMx_CCR1) set for output channel 1. 02638 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02639 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02640 * whether or not a timer instance supports a 32 bits counter. 02641 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 02642 * output channel 1 is supported by a timer instance. 02643 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 02644 * @param TIMx Timer instance 02645 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02646 */ 02647 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) 02648 { 02649 return (uint32_t)(READ_REG(TIMx->CCR1)); 02650 } 02651 02652 /** 02653 * @brief Get compare value (TIMx_CCR2) set for output channel 2. 02654 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02655 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02656 * whether or not a timer instance supports a 32 bits counter. 02657 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 02658 * output channel 2 is supported by a timer instance. 02659 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 02660 * @param TIMx Timer instance 02661 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02662 */ 02663 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) 02664 { 02665 return (uint32_t)(READ_REG(TIMx->CCR2)); 02666 } 02667 02668 /** 02669 * @brief Get compare value (TIMx_CCR3) set for output channel 3. 02670 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02671 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02672 * whether or not a timer instance supports a 32 bits counter. 02673 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 02674 * output channel 3 is supported by a timer instance. 02675 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 02676 * @param TIMx Timer instance 02677 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02678 */ 02679 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) 02680 { 02681 return (uint32_t)(READ_REG(TIMx->CCR3)); 02682 } 02683 02684 /** 02685 * @brief Get compare value (TIMx_CCR4) set for output channel 4. 02686 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF. 02687 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 02688 * whether or not a timer instance supports a 32 bits counter. 02689 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 02690 * output channel 4 is supported by a timer instance. 02691 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 02692 * @param TIMx Timer instance 02693 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02694 */ 02695 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) 02696 { 02697 return (uint32_t)(READ_REG(TIMx->CCR4)); 02698 } 02699 02700 /** 02701 * @brief Get compare value (TIMx_CCR5) set for output channel 5. 02702 * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not 02703 * output channel 5 is supported by a timer instance. 02704 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5 02705 * @param TIMx Timer instance 02706 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02707 */ 02708 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx) 02709 { 02710 return (uint32_t)(READ_REG(TIMx->CCR5)); 02711 } 02712 02713 /** 02714 * @brief Get compare value (TIMx_CCR6) set for output channel 6. 02715 * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not 02716 * output channel 6 is supported by a timer instance. 02717 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6 02718 * @param TIMx Timer instance 02719 * @retval CompareValue (between Min_Data=0 and Max_Data=65535) 02720 */ 02721 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx) 02722 { 02723 return (uint32_t)(READ_REG(TIMx->CCR6)); 02724 } 02725 02726 /** 02727 * @brief Select on which reference signal the OC5REF is combined to. 02728 * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check 02729 * whether or not a timer instance supports the combined 3-phase PWM mode. 02730 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n 02731 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n 02732 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels 02733 * @param TIMx Timer instance 02734 * @param GroupCH5 This parameter can be one of the following values: 02735 * @arg @ref LL_TIM_GROUPCH5_NONE 02736 * @arg @ref LL_TIM_GROUPCH5_OC1REFC 02737 * @arg @ref LL_TIM_GROUPCH5_OC2REFC 02738 * @arg @ref LL_TIM_GROUPCH5_OC3REFC 02739 * @retval None 02740 */ 02741 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5) 02742 { 02743 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5); 02744 } 02745 02746 /** 02747 * @} 02748 */ 02749 02750 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration 02751 * @{ 02752 */ 02753 /** 02754 * @brief Configure input channel. 02755 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n 02756 * CCMR1 IC1PSC LL_TIM_IC_Config\n 02757 * CCMR1 IC1F LL_TIM_IC_Config\n 02758 * CCMR1 CC2S LL_TIM_IC_Config\n 02759 * CCMR1 IC2PSC LL_TIM_IC_Config\n 02760 * CCMR1 IC2F LL_TIM_IC_Config\n 02761 * CCMR2 CC3S LL_TIM_IC_Config\n 02762 * CCMR2 IC3PSC LL_TIM_IC_Config\n 02763 * CCMR2 IC3F LL_TIM_IC_Config\n 02764 * CCMR2 CC4S LL_TIM_IC_Config\n 02765 * CCMR2 IC4PSC LL_TIM_IC_Config\n 02766 * CCMR2 IC4F LL_TIM_IC_Config\n 02767 * CCER CC1P LL_TIM_IC_Config\n 02768 * CCER CC1NP LL_TIM_IC_Config\n 02769 * CCER CC2P LL_TIM_IC_Config\n 02770 * CCER CC2NP LL_TIM_IC_Config\n 02771 * CCER CC3P LL_TIM_IC_Config\n 02772 * CCER CC3NP LL_TIM_IC_Config\n 02773 * CCER CC4P LL_TIM_IC_Config\n 02774 * CCER CC4NP LL_TIM_IC_Config 02775 * @param TIMx Timer instance 02776 * @param Channel This parameter can be one of the following values: 02777 * @arg @ref LL_TIM_CHANNEL_CH1 02778 * @arg @ref LL_TIM_CHANNEL_CH2 02779 * @arg @ref LL_TIM_CHANNEL_CH3 02780 * @arg @ref LL_TIM_CHANNEL_CH4 02781 * @param Configuration This parameter must be a combination of all the following values: 02782 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC 02783 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 02784 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 02785 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE 02786 * @retval None 02787 */ 02788 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) 02789 { 02790 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02791 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02792 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), 02793 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); 02794 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 02795 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); 02796 } 02797 02798 /** 02799 * @brief Set the active input. 02800 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n 02801 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n 02802 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n 02803 * CCMR2 CC4S LL_TIM_IC_SetActiveInput 02804 * @param TIMx Timer instance 02805 * @param Channel This parameter can be one of the following values: 02806 * @arg @ref LL_TIM_CHANNEL_CH1 02807 * @arg @ref LL_TIM_CHANNEL_CH2 02808 * @arg @ref LL_TIM_CHANNEL_CH3 02809 * @arg @ref LL_TIM_CHANNEL_CH4 02810 * @param ICActiveInput This parameter can be one of the following values: 02811 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 02812 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 02813 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 02814 * @retval None 02815 */ 02816 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) 02817 { 02818 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02819 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02820 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02821 } 02822 02823 /** 02824 * @brief Get the current active input. 02825 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n 02826 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n 02827 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n 02828 * CCMR2 CC4S LL_TIM_IC_GetActiveInput 02829 * @param TIMx Timer instance 02830 * @param Channel This parameter can be one of the following values: 02831 * @arg @ref LL_TIM_CHANNEL_CH1 02832 * @arg @ref LL_TIM_CHANNEL_CH2 02833 * @arg @ref LL_TIM_CHANNEL_CH3 02834 * @arg @ref LL_TIM_CHANNEL_CH4 02835 * @retval Returned value can be one of the following values: 02836 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI 02837 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI 02838 * @arg @ref LL_TIM_ACTIVEINPUT_TRC 02839 */ 02840 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) 02841 { 02842 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02843 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02844 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02845 } 02846 02847 /** 02848 * @brief Set the prescaler of input channel. 02849 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n 02850 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n 02851 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n 02852 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler 02853 * @param TIMx Timer instance 02854 * @param Channel This parameter can be one of the following values: 02855 * @arg @ref LL_TIM_CHANNEL_CH1 02856 * @arg @ref LL_TIM_CHANNEL_CH2 02857 * @arg @ref LL_TIM_CHANNEL_CH3 02858 * @arg @ref LL_TIM_CHANNEL_CH4 02859 * @param ICPrescaler This parameter can be one of the following values: 02860 * @arg @ref LL_TIM_ICPSC_DIV1 02861 * @arg @ref LL_TIM_ICPSC_DIV2 02862 * @arg @ref LL_TIM_ICPSC_DIV4 02863 * @arg @ref LL_TIM_ICPSC_DIV8 02864 * @retval None 02865 */ 02866 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) 02867 { 02868 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02869 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02870 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02871 } 02872 02873 /** 02874 * @brief Get the current prescaler value acting on an input channel. 02875 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n 02876 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n 02877 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n 02878 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler 02879 * @param TIMx Timer instance 02880 * @param Channel This parameter can be one of the following values: 02881 * @arg @ref LL_TIM_CHANNEL_CH1 02882 * @arg @ref LL_TIM_CHANNEL_CH2 02883 * @arg @ref LL_TIM_CHANNEL_CH3 02884 * @arg @ref LL_TIM_CHANNEL_CH4 02885 * @retval Returned value can be one of the following values: 02886 * @arg @ref LL_TIM_ICPSC_DIV1 02887 * @arg @ref LL_TIM_ICPSC_DIV2 02888 * @arg @ref LL_TIM_ICPSC_DIV4 02889 * @arg @ref LL_TIM_ICPSC_DIV8 02890 */ 02891 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) 02892 { 02893 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02894 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02895 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02896 } 02897 02898 /** 02899 * @brief Set the input filter duration. 02900 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n 02901 * CCMR1 IC2F LL_TIM_IC_SetFilter\n 02902 * CCMR2 IC3F LL_TIM_IC_SetFilter\n 02903 * CCMR2 IC4F LL_TIM_IC_SetFilter 02904 * @param TIMx Timer instance 02905 * @param Channel This parameter can be one of the following values: 02906 * @arg @ref LL_TIM_CHANNEL_CH1 02907 * @arg @ref LL_TIM_CHANNEL_CH2 02908 * @arg @ref LL_TIM_CHANNEL_CH3 02909 * @arg @ref LL_TIM_CHANNEL_CH4 02910 * @param ICFilter This parameter can be one of the following values: 02911 * @arg @ref LL_TIM_IC_FILTER_FDIV1 02912 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 02913 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 02914 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 02915 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 02916 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 02917 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 02918 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 02919 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 02920 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 02921 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 02922 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 02923 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 02924 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 02925 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 02926 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 02927 * @retval None 02928 */ 02929 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) 02930 { 02931 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02932 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02933 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); 02934 } 02935 02936 /** 02937 * @brief Get the input filter duration. 02938 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n 02939 * CCMR1 IC2F LL_TIM_IC_GetFilter\n 02940 * CCMR2 IC3F LL_TIM_IC_GetFilter\n 02941 * CCMR2 IC4F LL_TIM_IC_GetFilter 02942 * @param TIMx Timer instance 02943 * @param Channel This parameter can be one of the following values: 02944 * @arg @ref LL_TIM_CHANNEL_CH1 02945 * @arg @ref LL_TIM_CHANNEL_CH2 02946 * @arg @ref LL_TIM_CHANNEL_CH3 02947 * @arg @ref LL_TIM_CHANNEL_CH4 02948 * @retval Returned value can be one of the following values: 02949 * @arg @ref LL_TIM_IC_FILTER_FDIV1 02950 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 02951 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 02952 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 02953 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 02954 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 02955 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 02956 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 02957 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 02958 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 02959 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 02960 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 02961 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 02962 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 02963 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 02964 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 02965 */ 02966 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) 02967 { 02968 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02969 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); 02970 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); 02971 } 02972 02973 /** 02974 * @brief Set the input channel polarity. 02975 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n 02976 * CCER CC1NP LL_TIM_IC_SetPolarity\n 02977 * CCER CC2P LL_TIM_IC_SetPolarity\n 02978 * CCER CC2NP LL_TIM_IC_SetPolarity\n 02979 * CCER CC3P LL_TIM_IC_SetPolarity\n 02980 * CCER CC3NP LL_TIM_IC_SetPolarity\n 02981 * CCER CC4P LL_TIM_IC_SetPolarity\n 02982 * CCER CC4NP LL_TIM_IC_SetPolarity 02983 * @param TIMx Timer instance 02984 * @param Channel This parameter can be one of the following values: 02985 * @arg @ref LL_TIM_CHANNEL_CH1 02986 * @arg @ref LL_TIM_CHANNEL_CH2 02987 * @arg @ref LL_TIM_CHANNEL_CH3 02988 * @arg @ref LL_TIM_CHANNEL_CH4 02989 * @param ICPolarity This parameter can be one of the following values: 02990 * @arg @ref LL_TIM_IC_POLARITY_RISING 02991 * @arg @ref LL_TIM_IC_POLARITY_FALLING 02992 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 02993 * @retval None 02994 */ 02995 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) 02996 { 02997 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 02998 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), 02999 ICPolarity << SHIFT_TAB_CCxP[iChannel]); 03000 } 03001 03002 /** 03003 * @brief Get the current input channel polarity. 03004 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n 03005 * CCER CC1NP LL_TIM_IC_GetPolarity\n 03006 * CCER CC2P LL_TIM_IC_GetPolarity\n 03007 * CCER CC2NP LL_TIM_IC_GetPolarity\n 03008 * CCER CC3P LL_TIM_IC_GetPolarity\n 03009 * CCER CC3NP LL_TIM_IC_GetPolarity\n 03010 * CCER CC4P LL_TIM_IC_GetPolarity\n 03011 * CCER CC4NP LL_TIM_IC_GetPolarity 03012 * @param TIMx Timer instance 03013 * @param Channel This parameter can be one of the following values: 03014 * @arg @ref LL_TIM_CHANNEL_CH1 03015 * @arg @ref LL_TIM_CHANNEL_CH2 03016 * @arg @ref LL_TIM_CHANNEL_CH3 03017 * @arg @ref LL_TIM_CHANNEL_CH4 03018 * @retval Returned value can be one of the following values: 03019 * @arg @ref LL_TIM_IC_POLARITY_RISING 03020 * @arg @ref LL_TIM_IC_POLARITY_FALLING 03021 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE 03022 */ 03023 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) 03024 { 03025 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); 03026 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> 03027 SHIFT_TAB_CCxP[iChannel]); 03028 } 03029 03030 /** 03031 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). 03032 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 03033 * a timer instance provides an XOR input. 03034 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination 03035 * @param TIMx Timer instance 03036 * @retval None 03037 */ 03038 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) 03039 { 03040 SET_BIT(TIMx->CR2, TIM_CR2_TI1S); 03041 } 03042 03043 /** 03044 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. 03045 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 03046 * a timer instance provides an XOR input. 03047 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination 03048 * @param TIMx Timer instance 03049 * @retval None 03050 */ 03051 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) 03052 { 03053 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); 03054 } 03055 03056 /** 03057 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. 03058 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not 03059 * a timer instance provides an XOR input. 03060 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination 03061 * @param TIMx Timer instance 03062 * @retval State of bit (1 or 0). 03063 */ 03064 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) 03065 { 03066 return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); 03067 } 03068 03069 /** 03070 * @brief Get captured value for input channel 1. 03071 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03072 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03073 * whether or not a timer instance supports a 32 bits counter. 03074 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not 03075 * input channel 1 is supported by a timer instance. 03076 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 03077 * @param TIMx Timer instance 03078 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03079 */ 03080 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) 03081 { 03082 return (uint32_t)(READ_REG(TIMx->CCR1)); 03083 } 03084 03085 /** 03086 * @brief Get captured value for input channel 2. 03087 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03088 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03089 * whether or not a timer instance supports a 32 bits counter. 03090 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not 03091 * input channel 2 is supported by a timer instance. 03092 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 03093 * @param TIMx Timer instance 03094 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03095 */ 03096 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) 03097 { 03098 return (uint32_t)(READ_REG(TIMx->CCR2)); 03099 } 03100 03101 /** 03102 * @brief Get captured value for input channel 3. 03103 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03104 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03105 * whether or not a timer instance supports a 32 bits counter. 03106 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not 03107 * input channel 3 is supported by a timer instance. 03108 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 03109 * @param TIMx Timer instance 03110 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03111 */ 03112 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) 03113 { 03114 return (uint32_t)(READ_REG(TIMx->CCR3)); 03115 } 03116 03117 /** 03118 * @brief Get captured value for input channel 4. 03119 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF. 03120 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check 03121 * whether or not a timer instance supports a 32 bits counter. 03122 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not 03123 * input channel 4 is supported by a timer instance. 03124 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 03125 * @param TIMx Timer instance 03126 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) 03127 */ 03128 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) 03129 { 03130 return (uint32_t)(READ_REG(TIMx->CCR4)); 03131 } 03132 03133 /** 03134 * @} 03135 */ 03136 03137 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection 03138 * @{ 03139 */ 03140 /** 03141 * @brief Enable external clock mode 2. 03142 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. 03143 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03144 * whether or not a timer instance supports external clock mode2. 03145 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock 03146 * @param TIMx Timer instance 03147 * @retval None 03148 */ 03149 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) 03150 { 03151 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); 03152 } 03153 03154 /** 03155 * @brief Disable external clock mode 2. 03156 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03157 * whether or not a timer instance supports external clock mode2. 03158 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock 03159 * @param TIMx Timer instance 03160 * @retval None 03161 */ 03162 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) 03163 { 03164 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); 03165 } 03166 03167 /** 03168 * @brief Indicate whether external clock mode 2 is enabled. 03169 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03170 * whether or not a timer instance supports external clock mode2. 03171 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock 03172 * @param TIMx Timer instance 03173 * @retval State of bit (1 or 0). 03174 */ 03175 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) 03176 { 03177 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); 03178 } 03179 03180 /** 03181 * @brief Set the clock source of the counter clock. 03182 * @note when selected clock source is external clock mode 1, the timer input 03183 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() 03184 * function. This timer input must be configured by calling 03185 * the @ref LL_TIM_IC_Config() function. 03186 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check 03187 * whether or not a timer instance supports external clock mode1. 03188 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check 03189 * whether or not a timer instance supports external clock mode2. 03190 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n 03191 * SMCR ECE LL_TIM_SetClockSource 03192 * @param TIMx Timer instance 03193 * @param ClockSource This parameter can be one of the following values: 03194 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL 03195 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 03196 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 03197 * @retval None 03198 */ 03199 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) 03200 { 03201 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); 03202 } 03203 03204 /** 03205 * @brief Set the encoder interface mode. 03206 * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check 03207 * whether or not a timer instance supports the encoder mode. 03208 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode 03209 * @param TIMx Timer instance 03210 * @param EncoderMode This parameter can be one of the following values: 03211 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 03212 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 03213 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 03214 * @retval None 03215 */ 03216 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) 03217 { 03218 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); 03219 } 03220 03221 /** 03222 * @} 03223 */ 03224 03225 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration 03226 * @{ 03227 */ 03228 /** 03229 * @brief Set the trigger output (TRGO) used for timer synchronization . 03230 * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check 03231 * whether or not a timer instance can operate as a master timer. 03232 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput 03233 * @param TIMx Timer instance 03234 * @param TimerSynchronization This parameter can be one of the following values: 03235 * @arg @ref LL_TIM_TRGO_RESET 03236 * @arg @ref LL_TIM_TRGO_ENABLE 03237 * @arg @ref LL_TIM_TRGO_UPDATE 03238 * @arg @ref LL_TIM_TRGO_CC1IF 03239 * @arg @ref LL_TIM_TRGO_OC1REF 03240 * @arg @ref LL_TIM_TRGO_OC2REF 03241 * @arg @ref LL_TIM_TRGO_OC3REF 03242 * @arg @ref LL_TIM_TRGO_OC4REF 03243 * @retval None 03244 */ 03245 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) 03246 { 03247 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); 03248 } 03249 03250 /** 03251 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization . 03252 * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check 03253 * whether or not a timer instance can be used for ADC synchronization. 03254 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2 03255 * @param TIMx Timer Instance 03256 * @param ADCSynchronization This parameter can be one of the following values: 03257 * @arg @ref LL_TIM_TRGO2_RESET 03258 * @arg @ref LL_TIM_TRGO2_ENABLE 03259 * @arg @ref LL_TIM_TRGO2_UPDATE 03260 * @arg @ref LL_TIM_TRGO2_CC1F 03261 * @arg @ref LL_TIM_TRGO2_OC1 03262 * @arg @ref LL_TIM_TRGO2_OC2 03263 * @arg @ref LL_TIM_TRGO2_OC3 03264 * @arg @ref LL_TIM_TRGO2_OC4 03265 * @arg @ref LL_TIM_TRGO2_OC5 03266 * @arg @ref LL_TIM_TRGO2_OC6 03267 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING 03268 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING 03269 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING 03270 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING 03271 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING 03272 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING 03273 * @retval None 03274 */ 03275 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization) 03276 { 03277 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization); 03278 } 03279 03280 /** 03281 * @brief Set the synchronization mode of a slave timer. 03282 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03283 * a timer instance can operate as a slave timer. 03284 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode 03285 * @param TIMx Timer instance 03286 * @param SlaveMode This parameter can be one of the following values: 03287 * @arg @ref LL_TIM_SLAVEMODE_DISABLED 03288 * @arg @ref LL_TIM_SLAVEMODE_RESET 03289 * @arg @ref LL_TIM_SLAVEMODE_GATED 03290 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER 03291 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER 03292 * @retval None 03293 */ 03294 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) 03295 { 03296 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); 03297 } 03298 03299 /** 03300 * @brief Set the selects the trigger input to be used to synchronize the counter. 03301 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03302 * a timer instance can operate as a slave timer. 03303 * @rmtoll SMCR TS LL_TIM_SetTriggerInput 03304 * @param TIMx Timer instance 03305 * @param TriggerInput This parameter can be one of the following values: 03306 * @arg @ref LL_TIM_TS_ITR0 03307 * @arg @ref LL_TIM_TS_ITR1 03308 * @arg @ref LL_TIM_TS_ITR2 03309 * @arg @ref LL_TIM_TS_ITR3 03310 * @arg @ref LL_TIM_TS_TI1F_ED 03311 * @arg @ref LL_TIM_TS_TI1FP1 03312 * @arg @ref LL_TIM_TS_TI2FP2 03313 * @arg @ref LL_TIM_TS_ETRF 03314 * @retval None 03315 */ 03316 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) 03317 { 03318 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); 03319 } 03320 03321 /** 03322 * @brief Enable the Master/Slave mode. 03323 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03324 * a timer instance can operate as a slave timer. 03325 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode 03326 * @param TIMx Timer instance 03327 * @retval None 03328 */ 03329 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) 03330 { 03331 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); 03332 } 03333 03334 /** 03335 * @brief Disable the Master/Slave mode. 03336 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03337 * a timer instance can operate as a slave timer. 03338 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode 03339 * @param TIMx Timer instance 03340 * @retval None 03341 */ 03342 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) 03343 { 03344 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); 03345 } 03346 03347 /** 03348 * @brief Indicates whether the Master/Slave mode is enabled. 03349 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not 03350 * a timer instance can operate as a slave timer. 03351 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode 03352 * @param TIMx Timer instance 03353 * @retval State of bit (1 or 0). 03354 */ 03355 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) 03356 { 03357 return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); 03358 } 03359 03360 /** 03361 * @brief Configure the external trigger (ETR) input. 03362 * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not 03363 * a timer instance provides an external trigger input. 03364 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n 03365 * SMCR ETPS LL_TIM_ConfigETR\n 03366 * SMCR ETF LL_TIM_ConfigETR 03367 * @param TIMx Timer instance 03368 * @param ETRPolarity This parameter can be one of the following values: 03369 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED 03370 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED 03371 * @param ETRPrescaler This parameter can be one of the following values: 03372 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 03373 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 03374 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 03375 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 03376 * @param ETRFilter This parameter can be one of the following values: 03377 * @arg @ref LL_TIM_ETR_FILTER_FDIV1 03378 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 03379 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 03380 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 03381 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 03382 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 03383 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 03384 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 03385 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 03386 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 03387 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 03388 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 03389 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 03390 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 03391 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 03392 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 03393 * @retval None 03394 */ 03395 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, 03396 uint32_t ETRFilter) 03397 { 03398 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); 03399 } 03400 03401 /** 03402 * @brief Select the external trigger (ETR) input source. 03403 * @note Macro @ref IS_TIM_ETRSEL_INSTANCE(TIMx) can be used to check whether or 03404 * not a timer instance supports ETR source selection. 03405 * @rmtoll OR2 ETRSEL LL_TIM_SetETRSource 03406 * @param TIMx Timer instance 03407 * @param ETRSource This parameter can be one of the following values: 03408 * @arg @ref LL_TIM_ETRSOURCE_LEGACY 03409 * @arg @ref LL_TIM_ETRSOURCE_COMP1 03410 * @arg @ref LL_TIM_ETRSOURCE_COMP2 03411 * @retval None 03412 */ 03413 __STATIC_INLINE void LL_TIM_SetETRSource(TIM_TypeDef *TIMx, uint32_t ETRSource) 03414 { 03415 03416 MODIFY_REG(TIMx->OR2, TIMx_OR2_ETRSEL, ETRSource); 03417 } 03418 03419 /** 03420 * @} 03421 */ 03422 03423 /** @defgroup TIM_LL_EF_Break_Function Break function configuration 03424 * @{ 03425 */ 03426 /** 03427 * @brief Enable the break function. 03428 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03429 * a timer instance provides a break input. 03430 * @rmtoll BDTR BKE LL_TIM_EnableBRK 03431 * @param TIMx Timer instance 03432 * @retval None 03433 */ 03434 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) 03435 { 03436 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); 03437 } 03438 03439 /** 03440 * @brief Disable the break function. 03441 * @rmtoll BDTR BKE LL_TIM_DisableBRK 03442 * @param TIMx Timer instance 03443 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03444 * a timer instance provides a break input. 03445 * @retval None 03446 */ 03447 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) 03448 { 03449 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); 03450 } 03451 03452 /** 03453 * @brief Configure the break input. 03454 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03455 * a timer instance provides a break input. 03456 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n 03457 * BDTR BKF LL_TIM_ConfigBRK 03458 * @param TIMx Timer instance 03459 * @param BreakPolarity This parameter can be one of the following values: 03460 * @arg @ref LL_TIM_BREAK_POLARITY_LOW 03461 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH 03462 * @param BreakFilter This parameter can be one of the following values: 03463 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1 03464 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2 03465 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4 03466 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8 03467 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6 03468 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8 03469 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6 03470 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8 03471 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6 03472 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8 03473 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5 03474 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6 03475 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8 03476 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5 03477 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6 03478 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8 03479 * @retval None 03480 */ 03481 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter) 03482 { 03483 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter); 03484 } 03485 03486 /** 03487 * @brief Enable the break 2 function. 03488 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03489 * a timer instance provides a second break input. 03490 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2 03491 * @param TIMx Timer instance 03492 * @retval None 03493 */ 03494 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx) 03495 { 03496 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 03497 } 03498 03499 /** 03500 * @brief Disable the break 2 function. 03501 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03502 * a timer instance provides a second break input. 03503 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2 03504 * @param TIMx Timer instance 03505 * @retval None 03506 */ 03507 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx) 03508 { 03509 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E); 03510 } 03511 03512 /** 03513 * @brief Configure the break 2 input. 03514 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not 03515 * a timer instance provides a second break input. 03516 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n 03517 * BDTR BK2F LL_TIM_ConfigBRK2 03518 * @param TIMx Timer instance 03519 * @param Break2Polarity This parameter can be one of the following values: 03520 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW 03521 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH 03522 * @param Break2Filter This parameter can be one of the following values: 03523 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1 03524 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2 03525 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4 03526 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8 03527 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6 03528 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8 03529 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6 03530 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8 03531 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6 03532 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8 03533 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5 03534 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6 03535 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8 03536 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5 03537 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6 03538 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8 03539 * @retval None 03540 */ 03541 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter) 03542 { 03543 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter); 03544 } 03545 03546 /** 03547 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. 03548 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03549 * a timer instance provides a break input. 03550 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n 03551 * BDTR OSSR LL_TIM_SetOffStates 03552 * @param TIMx Timer instance 03553 * @param OffStateIdle This parameter can be one of the following values: 03554 * @arg @ref LL_TIM_OSSI_DISABLE 03555 * @arg @ref LL_TIM_OSSI_ENABLE 03556 * @param OffStateRun This parameter can be one of the following values: 03557 * @arg @ref LL_TIM_OSSR_DISABLE 03558 * @arg @ref LL_TIM_OSSR_ENABLE 03559 * @retval None 03560 */ 03561 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) 03562 { 03563 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); 03564 } 03565 03566 /** 03567 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). 03568 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03569 * a timer instance provides a break input. 03570 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput 03571 * @param TIMx Timer instance 03572 * @retval None 03573 */ 03574 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) 03575 { 03576 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); 03577 } 03578 03579 /** 03580 * @brief Disable automatic output (MOE can be set only by software). 03581 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03582 * a timer instance provides a break input. 03583 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput 03584 * @param TIMx Timer instance 03585 * @retval None 03586 */ 03587 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) 03588 { 03589 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); 03590 } 03591 03592 /** 03593 * @brief Indicate whether automatic output is enabled. 03594 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03595 * a timer instance provides a break input. 03596 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput 03597 * @param TIMx Timer instance 03598 * @retval State of bit (1 or 0). 03599 */ 03600 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) 03601 { 03602 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); 03603 } 03604 03605 /** 03606 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). 03607 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 03608 * software and is reset in case of break or break2 event 03609 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03610 * a timer instance provides a break input. 03611 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs 03612 * @param TIMx Timer instance 03613 * @retval None 03614 */ 03615 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) 03616 { 03617 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); 03618 } 03619 03620 /** 03621 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). 03622 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by 03623 * software and is reset in case of break or break2 event. 03624 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03625 * a timer instance provides a break input. 03626 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs 03627 * @param TIMx Timer instance 03628 * @retval None 03629 */ 03630 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) 03631 { 03632 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); 03633 } 03634 03635 /** 03636 * @brief Indicates whether outputs are enabled. 03637 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 03638 * a timer instance provides a break input. 03639 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs 03640 * @param TIMx Timer instance 03641 * @retval State of bit (1 or 0). 03642 */ 03643 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) 03644 { 03645 return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); 03646 } 03647 03648 /** 03649 * @brief Enable the signals connected to the designated timer break input. 03650 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03651 * or not a timer instance allows for break input selection. 03652 * @rmtoll OR2 BKINE LL_TIM_EnableBreakInputSource\n 03653 * OR2 BKCMP1E LL_TIM_EnableBreakInputSource\n 03654 * OR2 BKCMP2E LL_TIM_EnableBreakInputSource\n 03655 * OR2 BKDF1BK0E LL_TIM_EnableBreakInputSource\n 03656 * OR3 BK2INE LL_TIM_EnableBreakInputSource\n 03657 * OR3 BK2CMP1E LL_TIM_EnableBreakInputSource\n 03658 * OR3 BK2CMP2E LL_TIM_EnableBreakInputSource\n 03659 * OR3 BK2DF1BK1E LL_TIM_EnableBreakInputSource 03660 * @param TIMx Timer instance 03661 * @param BreakInput This parameter can be one of the following values: 03662 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03663 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03664 * @param Source This parameter can be one of the following values: 03665 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03666 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03667 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 03668 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 03669 * @retval None 03670 */ 03671 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) 03672 { 03673 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); 03674 SET_BIT(*pReg, Source); 03675 } 03676 03677 /** 03678 * @brief Disable the signals connected to the designated timer break input. 03679 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03680 * or not a timer instance allows for break input selection. 03681 * @rmtoll OR2 BKINE LL_TIM_DisableBreakInputSource\n 03682 * OR2 BKCMP1E LL_TIM_DisableBreakInputSource\n 03683 * OR2 BKCMP2E LL_TIM_DisableBreakInputSource\n 03684 * OR2 BKDF1BK0E LL_TIM_DisableBreakInputSource\n 03685 * OR3 BK2INE LL_TIM_DisableBreakInputSource\n 03686 * OR3 BK2CMP1E LL_TIM_DisableBreakInputSource\n 03687 * OR3 BK2CMP2E LL_TIM_DisableBreakInputSource\n 03688 * OR3 BK2DF1BK1E LL_TIM_DisableBreakInputSource 03689 * @param TIMx Timer instance 03690 * @param BreakInput This parameter can be one of the following values: 03691 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03692 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03693 * @param Source This parameter can be one of the following values: 03694 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03695 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03696 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 03697 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK 03698 * @retval None 03699 */ 03700 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source) 03701 { 03702 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); 03703 CLEAR_BIT(*pReg, Source); 03704 } 03705 03706 /** 03707 * @brief Set the polarity of the break signal for the timer break input. 03708 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether 03709 * or not a timer instance allows for break input selection. 03710 * @rmtoll OR2 BKINP LL_TIM_SetBreakInputSourcePolarity\n 03711 * OR2 BKCMP1P LL_TIM_SetBreakInputSourcePolarity\n 03712 * OR2 BKCMP2P LL_TIM_SetBreakInputSourcePolarity\n 03713 * OR3 BK2INP LL_TIM_SetBreakInputSourcePolarity\n 03714 * OR3 BK2CMP1P LL_TIM_SetBreakInputSourcePolarity\n 03715 * OR3 BK2CMP2P LL_TIM_SetBreakInputSourcePolarity 03716 * @param TIMx Timer instance 03717 * @param BreakInput This parameter can be one of the following values: 03718 * @arg @ref LL_TIM_BREAK_INPUT_BKIN 03719 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2 03720 * @param Source This parameter can be one of the following values: 03721 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN 03722 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP1 03723 * @arg @ref LL_TIM_BKIN_SOURCE_BKCOMP2 03724 * @param Polarity This parameter can be one of the following values: 03725 * @arg @ref LL_TIM_BKIN_POLARITY_LOW 03726 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH 03727 * @retval None 03728 */ 03729 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source, 03730 uint32_t Polarity) 03731 { 03732 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->OR2) + BreakInput)); 03733 MODIFY_REG(*pReg, (TIMx_OR2_BKINP << TIM_POSITION_BRK_SOURCE), (Polarity << TIM_POSITION_BRK_SOURCE)); 03734 } 03735 /** 03736 * @} 03737 */ 03738 03739 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration 03740 * @{ 03741 */ 03742 /** 03743 * @brief Configures the timer DMA burst feature. 03744 * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or 03745 * not a timer instance supports the DMA burst mode. 03746 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n 03747 * DCR DBA LL_TIM_ConfigDMABurst 03748 * @param TIMx Timer instance 03749 * @param DMABurstBaseAddress This parameter can be one of the following values: 03750 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 03751 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 03752 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR 03753 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER 03754 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR 03755 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR 03756 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 03757 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 03758 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER 03759 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT 03760 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC 03761 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR 03762 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR 03763 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 03764 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 03765 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 03766 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 03767 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR 03768 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3 03769 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5 03770 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6 03771 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR1 03772 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR2 03773 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR3 03774 * @param DMABurstLength This parameter can be one of the following values: 03775 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER 03776 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS 03777 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS 03778 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS 03779 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS 03780 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS 03781 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS 03782 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS 03783 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS 03784 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS 03785 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS 03786 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS 03787 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS 03788 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS 03789 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS 03790 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS 03791 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS 03792 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS 03793 * @retval None 03794 */ 03795 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) 03796 { 03797 MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); 03798 } 03799 03800 /** 03801 * @} 03802 */ 03803 03804 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping 03805 * @{ 03806 */ 03807 /** 03808 * @brief Remap TIM inputs (input channel, internal/external triggers). 03809 * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not 03810 * a some timer inputs can be remapped. 03811 @if STM32L486xx 03812 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n 03813 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n 03814 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n 03815 * TIM8_OR1 ETR_ADC2_RMP LL_TIM_SetRemap\n 03816 * TIM8_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n 03817 * TIM8_OR1 TI1_RMP LL_TIM_SetRemap\n 03818 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n 03819 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n 03820 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n 03821 * TIM3_OR1 TI1_RMP LL_TIM_SetRemap\n 03822 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n 03823 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n 03824 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n 03825 * TIM17_OR1 TI1_RMP LL_TIM_SetRemap 03826 @endif 03827 @if STM32L443xx 03828 * @rmtoll TIM1_OR1 ETR_ADC1_RMP LL_TIM_SetRemap\n 03829 * TIM1_OR1 ETR_ADC3_RMP LL_TIM_SetRemap\n 03830 * TIM1_OR1 TI1_RMP LL_TIM_SetRemap\n 03831 * TIM2_OR1 ITR1_RMP LL_TIM_SetRemap\n 03832 * TIM2_OR1 TI4_RMP LL_TIM_SetRemap\n 03833 * TIM2_OR1 TI1_RMP LL_TIM_SetRemap\n 03834 * TIM15_OR1 TI1_RMP LL_TIM_SetRemap\n 03835 * TIM15_OR1 ENCODER_MODE LL_TIM_SetRemap\n 03836 * TIM16_OR1 TI1_RMP LL_TIM_SetRemap\n 03837 @endif 03838 * @param TIMx Timer instance 03839 * @param Remap Remap param depends on the TIMx. Description available only 03840 * in CHM version of the User Manual (not in .pdf). 03841 * Otherwise see Reference Manual description of OR registers. 03842 * 03843 * Below description summarizes "Timer Instance" and "Remap" param combinations: 03844 * 03845 @if STM32L486xx 03846 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where 03847 * 03848 * . . ADC1_RMP can be one of the following values 03849 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC 03850 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 03851 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 03852 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 03853 * 03854 * . . ADC3_RMP can be one of the following values 03855 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_NC 03856 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD1 03857 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD2 03858 * @arg @ref LL_TIM_TIM1_ETR_ADC3_RMP_AWD3 03859 * 03860 * . . TI1_RMP can be one of the following values 03861 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO 03862 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 03863 * 03864 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where 03865 * 03866 * ITR1_RMP can be one of the following values 03867 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO 03868 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF 03869 * 03870 * . . ETR1_RMP can be one of the following values 03871 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO 03872 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE 03873 * 03874 * . . TI4_RMP can be one of the following values 03875 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO 03876 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 03877 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 03878 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 03879 * 03880 * TIM3: one of the following values 03881 * 03882 * @arg @ref LL_TIM_TIM3_TI1_RMP_GPIO 03883 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1 03884 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP2 03885 * @arg @ref LL_TIM_TIM3_TI1_RMP_COMP1_COMP2 03886 * 03887 * TIM8: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where 03888 * 03889 * . . ADC1_RMP can be one of the following values 03890 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_NC 03891 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD1 03892 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD2 03893 * @arg @ref LL_TIM_TIM8_ETR_ADC2_RMP_AWD3 03894 * 03895 * . . ADC3_RMP can be one of the following values 03896 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_NC 03897 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD1 03898 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD2 03899 * @arg @ref LL_TIM_TIM8_ETR_ADC3_RMP_AWD3 03900 * 03901 * . . TI1_RMP can be one of the following values 03902 * @arg @ref LL_TIM_TIM8_TI1_RMP_GPIO 03903 * @arg @ref LL_TIM_TIM8_TI1_RMP_COMP2 03904 * 03905 * TIM15: any combination of TI1_RMP, ENCODER_MODE where 03906 * 03907 * . . TI1_RMP can be one of the following values 03908 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO 03909 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE 03910 * 03911 * . . ENCODER_MODE can be one of the following values 03912 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION 03913 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2 03914 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3 03915 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4 03916 * 03917 * TIM16: one of the following values 03918 * 03919 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO 03920 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI 03921 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE 03922 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC 03923 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI 03924 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 03925 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO 03926 * 03927 * TIM17: one of the following values 03928 * 03929 * @arg @ref LL_TIM_TIM17_TI1_RMP_GPIO 03930 * @arg @ref LL_TIM_TIM17_TI1_RMP_MSI 03931 * @arg @ref LL_TIM_TIM17_TI1_RMP_HSE_32 03932 * @arg @ref LL_TIM_TIM17_TI1_RMP_MCO 03933 @endif 03934 @if STM32L443xx 03935 * TIM1: any combination of TI1_RMP, ADC3_RMP, ADC1_RMP where 03936 * 03937 * . . ADC1_RMP can be one of the following values 03938 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_NC 03939 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD1 03940 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD2 03941 * @arg @ref LL_TIM_TIM1_ETR_ADC1_RMP_AWD3 03942 * 03943 * . . TI1_RMP can be one of the following values 03944 * @arg @ref LL_TIM_TIM1_TI1_RMP_GPIO 03945 * @arg @ref LL_TIM_TIM1_TI1_RMP_COMP1 03946 * 03947 * TIM2: any combination of ITR1_RMP, ETR1_RMP, TI4_RMP where 03948 * 03949 * ITR1_RMP can be one of the following values 03950 * @arg @ref LL_TIM_TIM2_ITR1_RMP_NONE 03951 * @arg @ref LL_TIM_TIM2_ITR1_RMP_USB_SOF 03952 * 03953 * . . ETR1_RMP can be one of the following values 03954 * @arg @ref LL_TIM_TIM2_ETR_RMP_GPIO 03955 * @arg @ref LL_TIM_TIM2_ETR_RMP_LSE 03956 * 03957 * . . TI4_RMP can be one of the following values 03958 * @arg @ref LL_TIM_TIM2_TI4_RMP_GPIO 03959 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1 03960 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP2 03961 * @arg @ref LL_TIM_TIM2_TI4_RMP_COMP1_COMP2 03962 * 03963 * TIM15: any combination of TI1_RMP, ENCODER_MODE where 03964 * 03965 * . . TI1_RMP can be one of the following values 03966 * @arg @ref LL_TIM_TIM15_TI1_RMP_GPIO 03967 * @arg @ref LL_TIM_TIM15_TI1_RMP_LSE 03968 * 03969 * . . ENCODER_MODE can be one of the following values 03970 * @arg @ref LL_TIM_TIM15_ENCODERMODE_NOREDIRECTION 03971 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM2 03972 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM3 03973 * @arg @ref LL_TIM_TIM15_ENCODERMODE_TIM4 03974 * 03975 * TIM16: one of the following values 03976 * 03977 * @arg @ref LL_TIM_TIM16_TI1_RMP_GPIO 03978 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSI 03979 * @arg @ref LL_TIM_TIM16_TI1_RMP_LSE 03980 * @arg @ref LL_TIM_TIM16_TI1_RMP_RTC 03981 * @arg @ref LL_TIM_TIM16_TI1_RMP_MSI 03982 * @arg @ref LL_TIM_TIM16_TI1_RMP_HSE_32 03983 * @arg @ref LL_TIM_TIM16_TI1_RMP_MCO 03984 @endif 03985 * @retval None 03986 */ 03987 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap) 03988 { 03989 MODIFY_REG(TIMx->OR1, (Remap >> TIMx_OR1_RMP_SHIFT), (Remap & TIMx_OR1_RMP_MASK)); 03990 } 03991 03992 /** 03993 * @} 03994 */ 03995 03996 /** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management 03997 * @{ 03998 */ 03999 /** 04000 * @brief Set the OCREF clear input source 04001 * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT 04002 * @note This function can only be used in Output compare and PWM modes. 04003 * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource 04004 * @param TIMx Timer instance 04005 * @param OCRefClearInputSource This parameter can be one of the following values: 04006 * @arg @ref LL_TIM_OCREF_CLR_INT_NC 04007 * @arg @ref LL_TIM_OCREF_CLR_INT_ETR 04008 * @retval None 04009 */ 04010 __STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) 04011 { 04012 MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); 04013 } 04014 /** 04015 * @} 04016 */ 04017 04018 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management 04019 * @{ 04020 */ 04021 /** 04022 * @brief Clear the update interrupt flag (UIF). 04023 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE 04024 * @param TIMx Timer instance 04025 * @retval None 04026 */ 04027 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) 04028 { 04029 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); 04030 } 04031 04032 /** 04033 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). 04034 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE 04035 * @param TIMx Timer instance 04036 * @retval State of bit (1 or 0). 04037 */ 04038 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) 04039 { 04040 return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); 04041 } 04042 04043 /** 04044 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). 04045 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 04046 * @param TIMx Timer instance 04047 * @retval None 04048 */ 04049 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) 04050 { 04051 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); 04052 } 04053 04054 /** 04055 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). 04056 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 04057 * @param TIMx Timer instance 04058 * @retval State of bit (1 or 0). 04059 */ 04060 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) 04061 { 04062 return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); 04063 } 04064 04065 /** 04066 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). 04067 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 04068 * @param TIMx Timer instance 04069 * @retval None 04070 */ 04071 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) 04072 { 04073 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); 04074 } 04075 04076 /** 04077 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). 04078 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 04079 * @param TIMx Timer instance 04080 * @retval State of bit (1 or 0). 04081 */ 04082 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) 04083 { 04084 return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); 04085 } 04086 04087 /** 04088 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). 04089 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 04090 * @param TIMx Timer instance 04091 * @retval None 04092 */ 04093 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) 04094 { 04095 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); 04096 } 04097 04098 /** 04099 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). 04100 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 04101 * @param TIMx Timer instance 04102 * @retval State of bit (1 or 0). 04103 */ 04104 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) 04105 { 04106 return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); 04107 } 04108 04109 /** 04110 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). 04111 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 04112 * @param TIMx Timer instance 04113 * @retval None 04114 */ 04115 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) 04116 { 04117 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); 04118 } 04119 04120 /** 04121 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). 04122 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 04123 * @param TIMx Timer instance 04124 * @retval State of bit (1 or 0). 04125 */ 04126 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) 04127 { 04128 return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); 04129 } 04130 04131 /** 04132 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F). 04133 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5 04134 * @param TIMx Timer instance 04135 * @retval None 04136 */ 04137 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx) 04138 { 04139 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF)); 04140 } 04141 04142 /** 04143 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending). 04144 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5 04145 * @param TIMx Timer instance 04146 * @retval State of bit (1 or 0). 04147 */ 04148 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx) 04149 { 04150 return ((READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF)) ? 1UL : 0UL); 04151 } 04152 04153 /** 04154 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F). 04155 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6 04156 * @param TIMx Timer instance 04157 * @retval None 04158 */ 04159 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx) 04160 { 04161 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF)); 04162 } 04163 04164 /** 04165 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending). 04166 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6 04167 * @param TIMx Timer instance 04168 * @retval State of bit (1 or 0). 04169 */ 04170 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx) 04171 { 04172 return ((READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF)) ? 1UL : 0UL); 04173 } 04174 04175 /** 04176 * @brief Clear the commutation interrupt flag (COMIF). 04177 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM 04178 * @param TIMx Timer instance 04179 * @retval None 04180 */ 04181 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) 04182 { 04183 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); 04184 } 04185 04186 /** 04187 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). 04188 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM 04189 * @param TIMx Timer instance 04190 * @retval State of bit (1 or 0). 04191 */ 04192 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) 04193 { 04194 return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); 04195 } 04196 04197 /** 04198 * @brief Clear the trigger interrupt flag (TIF). 04199 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG 04200 * @param TIMx Timer instance 04201 * @retval None 04202 */ 04203 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) 04204 { 04205 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); 04206 } 04207 04208 /** 04209 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). 04210 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG 04211 * @param TIMx Timer instance 04212 * @retval State of bit (1 or 0). 04213 */ 04214 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) 04215 { 04216 return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); 04217 } 04218 04219 /** 04220 * @brief Clear the break interrupt flag (BIF). 04221 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK 04222 * @param TIMx Timer instance 04223 * @retval None 04224 */ 04225 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) 04226 { 04227 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); 04228 } 04229 04230 /** 04231 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). 04232 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK 04233 * @param TIMx Timer instance 04234 * @retval State of bit (1 or 0). 04235 */ 04236 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) 04237 { 04238 return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); 04239 } 04240 04241 /** 04242 * @brief Clear the break 2 interrupt flag (B2IF). 04243 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2 04244 * @param TIMx Timer instance 04245 * @retval None 04246 */ 04247 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx) 04248 { 04249 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF)); 04250 } 04251 04252 /** 04253 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending). 04254 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2 04255 * @param TIMx Timer instance 04256 * @retval State of bit (1 or 0). 04257 */ 04258 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx) 04259 { 04260 return ((READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF)) ? 1UL : 0UL); 04261 } 04262 04263 /** 04264 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). 04265 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR 04266 * @param TIMx Timer instance 04267 * @retval None 04268 */ 04269 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) 04270 { 04271 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); 04272 } 04273 04274 /** 04275 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). 04276 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR 04277 * @param TIMx Timer instance 04278 * @retval State of bit (1 or 0). 04279 */ 04280 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) 04281 { 04282 return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); 04283 } 04284 04285 /** 04286 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). 04287 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR 04288 * @param TIMx Timer instance 04289 * @retval None 04290 */ 04291 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) 04292 { 04293 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); 04294 } 04295 04296 /** 04297 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). 04298 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR 04299 * @param TIMx Timer instance 04300 * @retval State of bit (1 or 0). 04301 */ 04302 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) 04303 { 04304 return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); 04305 } 04306 04307 /** 04308 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). 04309 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR 04310 * @param TIMx Timer instance 04311 * @retval None 04312 */ 04313 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) 04314 { 04315 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); 04316 } 04317 04318 /** 04319 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). 04320 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR 04321 * @param TIMx Timer instance 04322 * @retval State of bit (1 or 0). 04323 */ 04324 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) 04325 { 04326 return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); 04327 } 04328 04329 /** 04330 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). 04331 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR 04332 * @param TIMx Timer instance 04333 * @retval None 04334 */ 04335 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) 04336 { 04337 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); 04338 } 04339 04340 /** 04341 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). 04342 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR 04343 * @param TIMx Timer instance 04344 * @retval State of bit (1 or 0). 04345 */ 04346 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) 04347 { 04348 return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); 04349 } 04350 04351 /** 04352 * @brief Clear the system break interrupt flag (SBIF). 04353 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK 04354 * @param TIMx Timer instance 04355 * @retval None 04356 */ 04357 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx) 04358 { 04359 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF)); 04360 } 04361 04362 /** 04363 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending). 04364 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK 04365 * @param TIMx Timer instance 04366 * @retval State of bit (1 or 0). 04367 */ 04368 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx) 04369 { 04370 return ((READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF)) ? 1UL : 0UL); 04371 } 04372 04373 /** 04374 * @} 04375 */ 04376 04377 /** @defgroup TIM_LL_EF_IT_Management IT-Management 04378 * @{ 04379 */ 04380 /** 04381 * @brief Enable update interrupt (UIE). 04382 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE 04383 * @param TIMx Timer instance 04384 * @retval None 04385 */ 04386 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) 04387 { 04388 SET_BIT(TIMx->DIER, TIM_DIER_UIE); 04389 } 04390 04391 /** 04392 * @brief Disable update interrupt (UIE). 04393 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE 04394 * @param TIMx Timer instance 04395 * @retval None 04396 */ 04397 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) 04398 { 04399 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); 04400 } 04401 04402 /** 04403 * @brief Indicates whether the update interrupt (UIE) is enabled. 04404 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE 04405 * @param TIMx Timer instance 04406 * @retval State of bit (1 or 0). 04407 */ 04408 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) 04409 { 04410 return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); 04411 } 04412 04413 /** 04414 * @brief Enable capture/compare 1 interrupt (CC1IE). 04415 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 04416 * @param TIMx Timer instance 04417 * @retval None 04418 */ 04419 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) 04420 { 04421 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); 04422 } 04423 04424 /** 04425 * @brief Disable capture/compare 1 interrupt (CC1IE). 04426 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 04427 * @param TIMx Timer instance 04428 * @retval None 04429 */ 04430 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) 04431 { 04432 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); 04433 } 04434 04435 /** 04436 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. 04437 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 04438 * @param TIMx Timer instance 04439 * @retval State of bit (1 or 0). 04440 */ 04441 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) 04442 { 04443 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); 04444 } 04445 04446 /** 04447 * @brief Enable capture/compare 2 interrupt (CC2IE). 04448 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 04449 * @param TIMx Timer instance 04450 * @retval None 04451 */ 04452 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) 04453 { 04454 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); 04455 } 04456 04457 /** 04458 * @brief Disable capture/compare 2 interrupt (CC2IE). 04459 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 04460 * @param TIMx Timer instance 04461 * @retval None 04462 */ 04463 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) 04464 { 04465 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); 04466 } 04467 04468 /** 04469 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. 04470 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 04471 * @param TIMx Timer instance 04472 * @retval State of bit (1 or 0). 04473 */ 04474 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) 04475 { 04476 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); 04477 } 04478 04479 /** 04480 * @brief Enable capture/compare 3 interrupt (CC3IE). 04481 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 04482 * @param TIMx Timer instance 04483 * @retval None 04484 */ 04485 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) 04486 { 04487 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); 04488 } 04489 04490 /** 04491 * @brief Disable capture/compare 3 interrupt (CC3IE). 04492 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 04493 * @param TIMx Timer instance 04494 * @retval None 04495 */ 04496 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) 04497 { 04498 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); 04499 } 04500 04501 /** 04502 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. 04503 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 04504 * @param TIMx Timer instance 04505 * @retval State of bit (1 or 0). 04506 */ 04507 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) 04508 { 04509 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); 04510 } 04511 04512 /** 04513 * @brief Enable capture/compare 4 interrupt (CC4IE). 04514 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 04515 * @param TIMx Timer instance 04516 * @retval None 04517 */ 04518 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) 04519 { 04520 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); 04521 } 04522 04523 /** 04524 * @brief Disable capture/compare 4 interrupt (CC4IE). 04525 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 04526 * @param TIMx Timer instance 04527 * @retval None 04528 */ 04529 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) 04530 { 04531 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); 04532 } 04533 04534 /** 04535 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. 04536 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 04537 * @param TIMx Timer instance 04538 * @retval State of bit (1 or 0). 04539 */ 04540 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) 04541 { 04542 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); 04543 } 04544 04545 /** 04546 * @brief Enable commutation interrupt (COMIE). 04547 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM 04548 * @param TIMx Timer instance 04549 * @retval None 04550 */ 04551 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) 04552 { 04553 SET_BIT(TIMx->DIER, TIM_DIER_COMIE); 04554 } 04555 04556 /** 04557 * @brief Disable commutation interrupt (COMIE). 04558 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM 04559 * @param TIMx Timer instance 04560 * @retval None 04561 */ 04562 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) 04563 { 04564 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); 04565 } 04566 04567 /** 04568 * @brief Indicates whether the commutation interrupt (COMIE) is enabled. 04569 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM 04570 * @param TIMx Timer instance 04571 * @retval State of bit (1 or 0). 04572 */ 04573 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) 04574 { 04575 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); 04576 } 04577 04578 /** 04579 * @brief Enable trigger interrupt (TIE). 04580 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG 04581 * @param TIMx Timer instance 04582 * @retval None 04583 */ 04584 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) 04585 { 04586 SET_BIT(TIMx->DIER, TIM_DIER_TIE); 04587 } 04588 04589 /** 04590 * @brief Disable trigger interrupt (TIE). 04591 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG 04592 * @param TIMx Timer instance 04593 * @retval None 04594 */ 04595 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) 04596 { 04597 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); 04598 } 04599 04600 /** 04601 * @brief Indicates whether the trigger interrupt (TIE) is enabled. 04602 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG 04603 * @param TIMx Timer instance 04604 * @retval State of bit (1 or 0). 04605 */ 04606 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) 04607 { 04608 return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); 04609 } 04610 04611 /** 04612 * @brief Enable break interrupt (BIE). 04613 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK 04614 * @param TIMx Timer instance 04615 * @retval None 04616 */ 04617 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) 04618 { 04619 SET_BIT(TIMx->DIER, TIM_DIER_BIE); 04620 } 04621 04622 /** 04623 * @brief Disable break interrupt (BIE). 04624 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK 04625 * @param TIMx Timer instance 04626 * @retval None 04627 */ 04628 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) 04629 { 04630 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); 04631 } 04632 04633 /** 04634 * @brief Indicates whether the break interrupt (BIE) is enabled. 04635 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK 04636 * @param TIMx Timer instance 04637 * @retval State of bit (1 or 0). 04638 */ 04639 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) 04640 { 04641 return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); 04642 } 04643 04644 /** 04645 * @} 04646 */ 04647 04648 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management 04649 * @{ 04650 */ 04651 /** 04652 * @brief Enable update DMA request (UDE). 04653 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE 04654 * @param TIMx Timer instance 04655 * @retval None 04656 */ 04657 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) 04658 { 04659 SET_BIT(TIMx->DIER, TIM_DIER_UDE); 04660 } 04661 04662 /** 04663 * @brief Disable update DMA request (UDE). 04664 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE 04665 * @param TIMx Timer instance 04666 * @retval None 04667 */ 04668 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) 04669 { 04670 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); 04671 } 04672 04673 /** 04674 * @brief Indicates whether the update DMA request (UDE) is enabled. 04675 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE 04676 * @param TIMx Timer instance 04677 * @retval State of bit (1 or 0). 04678 */ 04679 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) 04680 { 04681 return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); 04682 } 04683 04684 /** 04685 * @brief Enable capture/compare 1 DMA request (CC1DE). 04686 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 04687 * @param TIMx Timer instance 04688 * @retval None 04689 */ 04690 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) 04691 { 04692 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); 04693 } 04694 04695 /** 04696 * @brief Disable capture/compare 1 DMA request (CC1DE). 04697 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 04698 * @param TIMx Timer instance 04699 * @retval None 04700 */ 04701 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) 04702 { 04703 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); 04704 } 04705 04706 /** 04707 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. 04708 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 04709 * @param TIMx Timer instance 04710 * @retval State of bit (1 or 0). 04711 */ 04712 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) 04713 { 04714 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); 04715 } 04716 04717 /** 04718 * @brief Enable capture/compare 2 DMA request (CC2DE). 04719 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 04720 * @param TIMx Timer instance 04721 * @retval None 04722 */ 04723 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) 04724 { 04725 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); 04726 } 04727 04728 /** 04729 * @brief Disable capture/compare 2 DMA request (CC2DE). 04730 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 04731 * @param TIMx Timer instance 04732 * @retval None 04733 */ 04734 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) 04735 { 04736 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); 04737 } 04738 04739 /** 04740 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. 04741 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 04742 * @param TIMx Timer instance 04743 * @retval State of bit (1 or 0). 04744 */ 04745 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) 04746 { 04747 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); 04748 } 04749 04750 /** 04751 * @brief Enable capture/compare 3 DMA request (CC3DE). 04752 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 04753 * @param TIMx Timer instance 04754 * @retval None 04755 */ 04756 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) 04757 { 04758 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); 04759 } 04760 04761 /** 04762 * @brief Disable capture/compare 3 DMA request (CC3DE). 04763 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 04764 * @param TIMx Timer instance 04765 * @retval None 04766 */ 04767 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) 04768 { 04769 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); 04770 } 04771 04772 /** 04773 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. 04774 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 04775 * @param TIMx Timer instance 04776 * @retval State of bit (1 or 0). 04777 */ 04778 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) 04779 { 04780 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); 04781 } 04782 04783 /** 04784 * @brief Enable capture/compare 4 DMA request (CC4DE). 04785 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 04786 * @param TIMx Timer instance 04787 * @retval None 04788 */ 04789 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) 04790 { 04791 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); 04792 } 04793 04794 /** 04795 * @brief Disable capture/compare 4 DMA request (CC4DE). 04796 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 04797 * @param TIMx Timer instance 04798 * @retval None 04799 */ 04800 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) 04801 { 04802 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); 04803 } 04804 04805 /** 04806 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. 04807 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 04808 * @param TIMx Timer instance 04809 * @retval State of bit (1 or 0). 04810 */ 04811 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) 04812 { 04813 return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); 04814 } 04815 04816 /** 04817 * @brief Enable commutation DMA request (COMDE). 04818 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM 04819 * @param TIMx Timer instance 04820 * @retval None 04821 */ 04822 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) 04823 { 04824 SET_BIT(TIMx->DIER, TIM_DIER_COMDE); 04825 } 04826 04827 /** 04828 * @brief Disable commutation DMA request (COMDE). 04829 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM 04830 * @param TIMx Timer instance 04831 * @retval None 04832 */ 04833 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) 04834 { 04835 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); 04836 } 04837 04838 /** 04839 * @brief Indicates whether the commutation DMA request (COMDE) is enabled. 04840 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM 04841 * @param TIMx Timer instance 04842 * @retval State of bit (1 or 0). 04843 */ 04844 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) 04845 { 04846 return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); 04847 } 04848 04849 /** 04850 * @brief Enable trigger interrupt (TDE). 04851 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG 04852 * @param TIMx Timer instance 04853 * @retval None 04854 */ 04855 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) 04856 { 04857 SET_BIT(TIMx->DIER, TIM_DIER_TDE); 04858 } 04859 04860 /** 04861 * @brief Disable trigger interrupt (TDE). 04862 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG 04863 * @param TIMx Timer instance 04864 * @retval None 04865 */ 04866 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) 04867 { 04868 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); 04869 } 04870 04871 /** 04872 * @brief Indicates whether the trigger interrupt (TDE) is enabled. 04873 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG 04874 * @param TIMx Timer instance 04875 * @retval State of bit (1 or 0). 04876 */ 04877 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) 04878 { 04879 return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); 04880 } 04881 04882 /** 04883 * @} 04884 */ 04885 04886 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management 04887 * @{ 04888 */ 04889 /** 04890 * @brief Generate an update event. 04891 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE 04892 * @param TIMx Timer instance 04893 * @retval None 04894 */ 04895 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) 04896 { 04897 SET_BIT(TIMx->EGR, TIM_EGR_UG); 04898 } 04899 04900 /** 04901 * @brief Generate Capture/Compare 1 event. 04902 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 04903 * @param TIMx Timer instance 04904 * @retval None 04905 */ 04906 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) 04907 { 04908 SET_BIT(TIMx->EGR, TIM_EGR_CC1G); 04909 } 04910 04911 /** 04912 * @brief Generate Capture/Compare 2 event. 04913 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 04914 * @param TIMx Timer instance 04915 * @retval None 04916 */ 04917 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) 04918 { 04919 SET_BIT(TIMx->EGR, TIM_EGR_CC2G); 04920 } 04921 04922 /** 04923 * @brief Generate Capture/Compare 3 event. 04924 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 04925 * @param TIMx Timer instance 04926 * @retval None 04927 */ 04928 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) 04929 { 04930 SET_BIT(TIMx->EGR, TIM_EGR_CC3G); 04931 } 04932 04933 /** 04934 * @brief Generate Capture/Compare 4 event. 04935 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 04936 * @param TIMx Timer instance 04937 * @retval None 04938 */ 04939 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) 04940 { 04941 SET_BIT(TIMx->EGR, TIM_EGR_CC4G); 04942 } 04943 04944 /** 04945 * @brief Generate commutation event. 04946 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM 04947 * @param TIMx Timer instance 04948 * @retval None 04949 */ 04950 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) 04951 { 04952 SET_BIT(TIMx->EGR, TIM_EGR_COMG); 04953 } 04954 04955 /** 04956 * @brief Generate trigger event. 04957 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG 04958 * @param TIMx Timer instance 04959 * @retval None 04960 */ 04961 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) 04962 { 04963 SET_BIT(TIMx->EGR, TIM_EGR_TG); 04964 } 04965 04966 /** 04967 * @brief Generate break event. 04968 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK 04969 * @param TIMx Timer instance 04970 * @retval None 04971 */ 04972 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) 04973 { 04974 SET_BIT(TIMx->EGR, TIM_EGR_BG); 04975 } 04976 04977 /** 04978 * @brief Generate break 2 event. 04979 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2 04980 * @param TIMx Timer instance 04981 * @retval None 04982 */ 04983 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) 04984 { 04985 SET_BIT(TIMx->EGR, TIM_EGR_B2G); 04986 } 04987 04988 /** 04989 * @} 04990 */ 04991 04992 #if defined(USE_FULL_LL_DRIVER) 04993 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions 04994 * @{ 04995 */ 04996 04997 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); 04998 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); 04999 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); 05000 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); 05001 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); 05002 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 05003 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); 05004 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); 05005 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); 05006 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); 05007 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); 05008 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); 05009 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); 05010 /** 05011 * @} 05012 */ 05013 #endif /* USE_FULL_LL_DRIVER */ 05014 05015 /** 05016 * @} 05017 */ 05018 05019 /** 05020 * @} 05021 */ 05022 05023 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 || TIM15 || TIM16 || TIM17 || TIM6 || TIM7 */ 05024 05025 /** 05026 * @} 05027 */ 05028 05029 #ifdef __cplusplus 05030 } 05031 #endif 05032 05033 #endif /* __STM32L4xx_LL_TIM_H */ 05034 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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