STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_swpmi.h 00004 * @author MCD Application Team 00005 * @brief Header file of SWPMI LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_SWPMI_H 00038 #define __STM32L4xx_LL_SWPMI_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined(SWPMI1) 00052 00053 /** @defgroup SWPMI_LL SWPMI 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /* Private constants ---------------------------------------------------------*/ 00060 /* Private macros ------------------------------------------------------------*/ 00061 #if defined(USE_FULL_LL_DRIVER) 00062 /** @defgroup SWPMI_LL_Private_Macros SWPMI Private Macros 00063 * @{ 00064 */ 00065 /** 00066 * @} 00067 */ 00068 #endif /*USE_FULL_LL_DRIVER*/ 00069 00070 /* Exported types ------------------------------------------------------------*/ 00071 #if defined(USE_FULL_LL_DRIVER) 00072 /** @defgroup SWPMI_LL_ES_INIT SWPMI Exported Init structure 00073 * @{ 00074 */ 00075 00076 /** 00077 * @brief SWPMI Init structures definition 00078 */ 00079 typedef struct 00080 { 00081 uint32_t VoltageClass; /*!< Specifies the SWP Voltage Class. 00082 This parameter can be a value of @ref SWPMI_LL_EC_VOLTAGE_CLASS 00083 00084 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetVoltageClass. */ 00085 00086 uint32_t BitRatePrescaler; /*!< Specifies the SWPMI bitrate prescaler. 00087 This parameter must be a number between Min_Data=0 and Max_Data=63. 00088 00089 The value can be calculated thanks to helper macro @ref __LL_SWPMI_CALC_BITRATE_PRESCALER 00090 00091 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetBitRatePrescaler. */ 00092 00093 uint32_t TxBufferingMode; /*!< Specifies the transmission buffering mode. 00094 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_TX 00095 00096 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetTransmissionMode. */ 00097 00098 uint32_t RxBufferingMode; /*!< Specifies the reception buffering mode. 00099 This parameter can be a value of @ref SWPMI_LL_EC_SW_BUFFER_RX 00100 00101 This feature can be modified afterwards using unitary function @ref LL_SWPMI_SetReceptionMode. */ 00102 } LL_SWPMI_InitTypeDef; 00103 00104 /** 00105 * @} 00106 */ 00107 #endif /* USE_FULL_LL_DRIVER */ 00108 00109 /* Exported constants --------------------------------------------------------*/ 00110 /** @defgroup SWPMI_LL_Exported_Constants SWPMI Exported Constants 00111 * @{ 00112 */ 00113 00114 /** @defgroup SWPMI_LL_EC_CLEAR_FLAG Clear Flags Defines 00115 * @brief Flags defines which can be used with LL_SWPMI_WriteReg function 00116 * @{ 00117 */ 00118 #define LL_SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF /*!< Clear receive buffer full flag */ 00119 #define LL_SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF /*!< Clear transmit buffer empty flag */ 00120 #define LL_SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF /*!< Clear receive CRC error flag */ 00121 #define LL_SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF /*!< Clear receive overrun error flag */ 00122 #define LL_SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF /*!< Clear transmit underrun error flag */ 00123 #define LL_SWPMI_ICR_CTCF SWPMI_ICR_CTCF /*!< Clear transfer complete flag */ 00124 #define LL_SWPMI_ICR_CSRF SWPMI_ICR_CSRF /*!< Clear slave resume flag */ 00125 /** 00126 * @} 00127 */ 00128 00129 /** @defgroup SWPMI_LL_EC_GET_FLAG Get Flags Defines 00130 * @brief Flags defines which can be used with LL_SWPMI_ReadReg function 00131 * @{ 00132 */ 00133 #define LL_SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF /*!< Receive buffer full flag */ 00134 #define LL_SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF /*!< Transmit buffer empty flag */ 00135 #define LL_SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF /*!< Receive CRC error flag */ 00136 #define LL_SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF /*!< Receive overrun error flag */ 00137 #define LL_SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF /*!< Transmit underrun error flag */ 00138 #define LL_SWPMI_ISR_RXNE SWPMI_ISR_RXNE /*!< Receive data register not empty */ 00139 #define LL_SWPMI_ISR_TXE SWPMI_ISR_TXE /*!< Transmit data register empty */ 00140 #define LL_SWPMI_ISR_TCF SWPMI_ISR_TCF /*!< Transfer complete flag */ 00141 #define LL_SWPMI_ISR_SRF SWPMI_ISR_SRF /*!< Slave resume flag */ 00142 #define LL_SWPMI_ISR_SUSP SWPMI_ISR_SUSP /*!< SUSPEND flag */ 00143 #define LL_SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF /*!< DEACTIVATED flag */ 00144 /** 00145 * @} 00146 */ 00147 00148 /** @defgroup SWPMI_LL_EC_IT IT Defines 00149 * @brief IT defines which can be used with LL_SWPMI_ReadReg and LL_SWPMI_WriteReg functions 00150 * @{ 00151 */ 00152 #define LL_SWPMI_IER_SRIE SWPMI_IER_SRIE /*!< Slave resume interrupt enable */ 00153 #define LL_SWPMI_IER_TCIE SWPMI_IER_TCIE /*!< Transmit complete interrupt enable */ 00154 #define LL_SWPMI_IER_TIE SWPMI_IER_TIE /*!< Transmit interrupt enable */ 00155 #define LL_SWPMI_IER_RIE SWPMI_IER_RIE /*!< Receive interrupt enable */ 00156 #define LL_SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE /*!< Transmit underrun error interrupt enable */ 00157 #define LL_SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE /*!< Receive overrun error interrupt enable */ 00158 #define LL_SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE /*!< Receive CRC error interrupt enable */ 00159 #define LL_SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE /*!< Transmit buffer empty interrupt enable */ 00160 #define LL_SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE /*!< Receive buffer full interrupt enable */ 00161 /** 00162 * @} 00163 */ 00164 00165 /** @defgroup SWPMI_LL_EC_SW_BUFFER_RX SW BUFFER RX 00166 * @{ 00167 */ 00168 #define LL_SWPMI_SW_BUFFER_RX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for reception */ 00169 #define LL_SWPMI_SW_BUFFER_RX_MULTI SWPMI_CR_RXMODE /*!< Multi software buffermode for reception */ 00170 /** 00171 * @} 00172 */ 00173 00174 /** @defgroup SWPMI_LL_EC_SW_BUFFER_TX SW BUFFER TX 00175 * @{ 00176 */ 00177 #define LL_SWPMI_SW_BUFFER_TX_SINGLE ((uint32_t)0x00000000) /*!< Single software buffer mode for transmission */ 00178 #define LL_SWPMI_SW_BUFFER_TX_MULTI SWPMI_CR_TXMODE /*!< Multi software buffermode for transmission */ 00179 /** 00180 * @} 00181 */ 00182 00183 /** @defgroup SWPMI_LL_EC_VOLTAGE_CLASS VOLTAGE CLASS 00184 * @{ 00185 */ 00186 #define LL_SWPMI_VOLTAGE_CLASS_C ((uint32_t)0x00000000) /*!< SWPMI_IO uses directly VDD voltage to operate in class C */ 00187 #define LL_SWPMI_VOLTAGE_CLASS_B SWPMI_OR_CLASS /*!< SWPMI_IO uses an internal voltage regulator to operate in class B */ 00188 /** 00189 * @} 00190 */ 00191 00192 /** @defgroup SWPMI_LL_EC_DMA_REG_DATA DMA register data 00193 * @{ 00194 */ 00195 #define LL_SWPMI_DMA_REG_DATA_TRANSMIT (uint32_t)0 /*!< Get address of data register used for transmission */ 00196 #define LL_SWPMI_DMA_REG_DATA_RECEIVE (uint32_t)1 /*!< Get address of data register used for reception */ 00197 /** 00198 * @} 00199 */ 00200 00201 /** 00202 * @} 00203 */ 00204 00205 /* Exported macro ------------------------------------------------------------*/ 00206 /** @defgroup SWPMI_LL_Exported_Macros SWPMI Exported Macros 00207 * @{ 00208 */ 00209 00210 /** @defgroup SWPMI_LL_EM_WRITE_READ Common Write and read registers Macros 00211 * @{ 00212 */ 00213 00214 /** 00215 * @brief Write a value in SWPMI register 00216 * @param __INSTANCE__ SWPMI Instance 00217 * @param __REG__ Register to be written 00218 * @param __VALUE__ Value to be written in the register 00219 * @retval None 00220 */ 00221 #define LL_SWPMI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00222 00223 /** 00224 * @brief Read a value in SWPMI register 00225 * @param __INSTANCE__ SWPMI Instance 00226 * @param __REG__ Register to be read 00227 * @retval Register value 00228 */ 00229 #define LL_SWPMI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00230 /** 00231 * @} 00232 */ 00233 00234 /** @defgroup SWPMI_LL_EM_BitRate Bit rate calculation helper Macros 00235 * @{ 00236 */ 00237 00238 /** 00239 * @brief Helper macro to calculate bit rate value to set in BRR register (@ref LL_SWPMI_SetBitRatePrescaler function) 00240 * @note ex: @ref __LL_SWPMI_CALC_BITRATE_PRESCALER(2000000, 80000000); 00241 * @param __FSWP__ Within the following range: from 100 Kbit/s up to 2Mbit/s (in bit/s) 00242 * @param __FSWPCLK__ PCLK or HSI frequency (in Hz) 00243 * @retval Bitrate prescaler (BRR register) 00244 */ 00245 #define __LL_SWPMI_CALC_BITRATE_PRESCALER(__FSWP__, __FSWPCLK__) ((uint32_t)(((__FSWPCLK__) / ((__FSWP__) * 4)) - 1)) 00246 00247 /** 00248 * @} 00249 */ 00250 00251 /** 00252 * @} 00253 */ 00254 00255 /* Exported functions --------------------------------------------------------*/ 00256 /** @defgroup SWPMI_LL_Exported_Functions SWPMI Exported Functions 00257 * @{ 00258 */ 00259 00260 /** @defgroup SWPMI_LL_EF_Configuration Configuration 00261 * @{ 00262 */ 00263 00264 /** 00265 * @brief Set Reception buffering mode 00266 * @note If Multi software buffer mode is chosen, RXDMA bits must also be set. 00267 * @rmtoll CR RXMODE LL_SWPMI_SetReceptionMode 00268 * @param SWPMIx SWPMI Instance 00269 * @param RxBufferingMode This parameter can be one of the following values: 00270 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE 00271 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI 00272 * @retval None 00273 */ 00274 __STATIC_INLINE void LL_SWPMI_SetReceptionMode(SWPMI_TypeDef *SWPMIx, uint32_t RxBufferingMode) 00275 { 00276 MODIFY_REG(SWPMIx->CR, SWPMI_CR_RXMODE, RxBufferingMode); 00277 } 00278 00279 /** 00280 * @brief Get Reception buffering mode 00281 * @rmtoll CR RXMODE LL_SWPMI_GetReceptionMode 00282 * @param SWPMIx SWPMI Instance 00283 * @retval Returned value can be one of the following values: 00284 * @arg @ref LL_SWPMI_SW_BUFFER_RX_SINGLE 00285 * @arg @ref LL_SWPMI_SW_BUFFER_RX_MULTI 00286 */ 00287 __STATIC_INLINE uint32_t LL_SWPMI_GetReceptionMode(SWPMI_TypeDef *SWPMIx) 00288 { 00289 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_RXMODE)); 00290 } 00291 00292 /** 00293 * @brief Set Transmission buffering mode 00294 * @note If Multi software buffer mode is chosen, TXDMA bits must also be set. 00295 * @rmtoll CR TXMODE LL_SWPMI_SetTransmissionMode 00296 * @param SWPMIx SWPMI Instance 00297 * @param TxBufferingMode This parameter can be one of the following values: 00298 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE 00299 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI 00300 * @retval None 00301 */ 00302 __STATIC_INLINE void LL_SWPMI_SetTransmissionMode(SWPMI_TypeDef *SWPMIx, uint32_t TxBufferingMode) 00303 { 00304 MODIFY_REG(SWPMIx->CR, SWPMI_CR_TXMODE, TxBufferingMode); 00305 } 00306 00307 /** 00308 * @brief Get Transmission buffering mode 00309 * @rmtoll CR TXMODE LL_SWPMI_GetTransmissionMode 00310 * @param SWPMIx SWPMI Instance 00311 * @retval Returned value can be one of the following values: 00312 * @arg @ref LL_SWPMI_SW_BUFFER_TX_SINGLE 00313 * @arg @ref LL_SWPMI_SW_BUFFER_TX_MULTI 00314 */ 00315 __STATIC_INLINE uint32_t LL_SWPMI_GetTransmissionMode(SWPMI_TypeDef *SWPMIx) 00316 { 00317 return (uint32_t)(READ_BIT(SWPMIx->CR, SWPMI_CR_TXMODE)); 00318 } 00319 00320 /** 00321 * @brief Enable loopback mode 00322 * @rmtoll CR LPBK LL_SWPMI_EnableLoopback 00323 * @param SWPMIx SWPMI Instance 00324 * @retval None 00325 */ 00326 __STATIC_INLINE void LL_SWPMI_EnableLoopback(SWPMI_TypeDef *SWPMIx) 00327 { 00328 SET_BIT(SWPMIx->CR, SWPMI_CR_LPBK); 00329 } 00330 00331 /** 00332 * @brief Disable loopback mode 00333 * @rmtoll CR LPBK LL_SWPMI_DisableLoopback 00334 * @param SWPMIx SWPMI Instance 00335 * @retval None 00336 */ 00337 __STATIC_INLINE void LL_SWPMI_DisableLoopback(SWPMI_TypeDef *SWPMIx) 00338 { 00339 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_LPBK); 00340 } 00341 00342 /** 00343 * @brief Activate Single wire protocol bus (SUSPENDED or ACTIVATED state) 00344 * @note SWP bus stays in the ACTIVATED state as long as there is a communication 00345 * with the slave, either in transmission or in reception. The SWP bus switches back 00346 * to the SUSPENDED state as soon as there is no more transmission or reception 00347 * activity, after 7 idle bits. 00348 * @rmtoll CR SWPACT LL_SWPMI_Activate 00349 * @param SWPMIx SWPMI Instance 00350 * @retval None 00351 */ 00352 __STATIC_INLINE void LL_SWPMI_Activate(SWPMI_TypeDef *SWPMIx) 00353 { 00354 /* In order to activate SWP again, the software must clear DEACT bit*/ 00355 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_DEACT); 00356 00357 /* Set SWACT bit */ 00358 SET_BIT(SWPMIx->CR, SWPMI_CR_SWPACT); 00359 } 00360 00361 /** 00362 * @brief Check if Single wire protocol bus is in ACTIVATED state. 00363 * @rmtoll CR SWPACT LL_SWPMI_Activate 00364 * @param SWPMIx SWPMI Instance 00365 * @retval State of bit (1 or 0). 00366 */ 00367 __STATIC_INLINE uint32_t LL_SWPMI_IsActivated(SWPMI_TypeDef *SWPMIx) 00368 { 00369 return (READ_BIT(SWPMIx->CR, SWPMI_CR_SWPACT) == (SWPMI_CR_SWPACT)); 00370 } 00371 00372 /** 00373 * @brief Deactivate immediately Single wire protocol bus (immediate transition to 00374 * DEACTIVATED state) 00375 * @rmtoll CR SWPACT LL_SWPMI_Deactivate 00376 * @param SWPMIx SWPMI Instance 00377 * @retval None 00378 */ 00379 __STATIC_INLINE void LL_SWPMI_Deactivate(SWPMI_TypeDef *SWPMIx) 00380 { 00381 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_SWPACT); 00382 } 00383 00384 /** 00385 * @brief Request a deactivation of Single wire protocol bus (request to go in DEACTIVATED 00386 * state if no resume from slave) 00387 * @rmtoll CR DEACT LL_SWPMI_RequestDeactivation 00388 * @param SWPMIx SWPMI Instance 00389 * @retval None 00390 */ 00391 __STATIC_INLINE void LL_SWPMI_RequestDeactivation(SWPMI_TypeDef *SWPMIx) 00392 { 00393 SET_BIT(SWPMIx->CR, SWPMI_CR_DEACT); 00394 } 00395 00396 /** 00397 * @brief Set Bitrate prescaler SWPMI_freq = SWPMI_clk / (((BitRate) + 1) * 4) 00398 * @rmtoll BRR BR LL_SWPMI_SetBitRatePrescaler 00399 * @param SWPMIx SWPMI Instance 00400 * @param BitRatePrescaler A number between Min_Data=0 and Max_Data=63 00401 * @retval None 00402 */ 00403 __STATIC_INLINE void LL_SWPMI_SetBitRatePrescaler(SWPMI_TypeDef *SWPMIx, uint32_t BitRatePrescaler) 00404 { 00405 WRITE_REG(SWPMIx->BRR, BitRatePrescaler); 00406 } 00407 00408 /** 00409 * @brief Get Bitrate prescaler 00410 * @rmtoll BRR BR LL_SWPMI_GetBitRatePrescaler 00411 * @param SWPMIx SWPMI Instance 00412 * @retval A number between Min_Data=0 and Max_Data=63 00413 */ 00414 __STATIC_INLINE uint32_t LL_SWPMI_GetBitRatePrescaler(SWPMI_TypeDef *SWPMIx) 00415 { 00416 return (uint32_t)(READ_BIT(SWPMIx->BRR, SWPMI_BRR_BR)); 00417 } 00418 00419 /** 00420 * @brief Set SWP Voltage Class 00421 * @rmtoll OR CLASS LL_SWPMI_SetVoltageClass 00422 * @param SWPMIx SWPMI Instance 00423 * @param VoltageClass This parameter can be one of the following values: 00424 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C 00425 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B 00426 * @retval None 00427 */ 00428 __STATIC_INLINE void LL_SWPMI_SetVoltageClass(SWPMI_TypeDef *SWPMIx, uint32_t VoltageClass) 00429 { 00430 MODIFY_REG(SWPMIx->OR, SWPMI_OR_CLASS, VoltageClass); 00431 } 00432 00433 /** 00434 * @brief Get SWP Voltage Class 00435 * @rmtoll OR CLASS LL_SWPMI_GetVoltageClass 00436 * @param SWPMIx SWPMI Instance 00437 * @retval Returned value can be one of the following values: 00438 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_C 00439 * @arg @ref LL_SWPMI_VOLTAGE_CLASS_B 00440 */ 00441 __STATIC_INLINE uint32_t LL_SWPMI_GetVoltageClass(SWPMI_TypeDef *SWPMIx) 00442 { 00443 return (uint32_t)(READ_BIT(SWPMIx->OR, SWPMI_OR_CLASS)); 00444 } 00445 00446 /** 00447 * @} 00448 */ 00449 00450 /** @defgroup SWPMI_LL_EF_FLAG_Management FLAG_Management 00451 * @{ 00452 */ 00453 00454 /** 00455 * @brief Check if the last word of the frame under reception has arrived in SWPMI_RDR. 00456 * @rmtoll ISR RXBFF LL_SWPMI_IsActiveFlag_RXBF 00457 * @param SWPMIx SWPMI Instance 00458 * @retval State of bit (1 or 0). 00459 */ 00460 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBF(SWPMI_TypeDef *SWPMIx) 00461 { 00462 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBFF) == (SWPMI_ISR_RXBFF)); 00463 } 00464 00465 /** 00466 * @brief Check if Frame transmission buffer has been emptied 00467 * @rmtoll ISR TXBEF LL_SWPMI_IsActiveFlag_TXBE 00468 * @param SWPMIx SWPMI Instance 00469 * @retval State of bit (1 or 0). 00470 */ 00471 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXBE(SWPMI_TypeDef *SWPMIx) 00472 { 00473 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXBEF) == (SWPMI_ISR_TXBEF)); 00474 } 00475 00476 /** 00477 * @brief Check if CRC error in reception has been detected 00478 * @rmtoll ISR RXBERF LL_SWPMI_IsActiveFlag_RXBER 00479 * @param SWPMIx SWPMI Instance 00480 * @retval State of bit (1 or 0). 00481 */ 00482 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXBER(SWPMI_TypeDef *SWPMIx) 00483 { 00484 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXBERF) == (SWPMI_ISR_RXBERF)); 00485 } 00486 00487 /** 00488 * @brief Check if Overrun in reception has been detected 00489 * @rmtoll ISR RXOVRF LL_SWPMI_IsActiveFlag_RXOVR 00490 * @param SWPMIx SWPMI Instance 00491 * @retval State of bit (1 or 0). 00492 */ 00493 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXOVR(SWPMI_TypeDef *SWPMIx) 00494 { 00495 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXOVRF) == (SWPMI_ISR_RXOVRF)); 00496 } 00497 00498 /** 00499 * @brief Check if underrun error in transmission has been detected 00500 * @rmtoll ISR TXUNRF LL_SWPMI_IsActiveFlag_TXUNR 00501 * @param SWPMIx SWPMI Instance 00502 * @retval State of bit (1 or 0). 00503 */ 00504 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXUNR(SWPMI_TypeDef *SWPMIx) 00505 { 00506 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXUNRF) == (SWPMI_ISR_TXUNRF)); 00507 } 00508 00509 /** 00510 * @brief Check if Receive data register not empty (it means that Received data is ready 00511 * to be read in the SWPMI_RDR register) 00512 * @rmtoll ISR RXNE LL_SWPMI_IsActiveFlag_RXNE 00513 * @param SWPMIx SWPMI Instance 00514 * @retval State of bit (1 or 0). 00515 */ 00516 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_RXNE(SWPMI_TypeDef *SWPMIx) 00517 { 00518 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_RXNE) == (SWPMI_ISR_RXNE)); 00519 } 00520 00521 /** 00522 * @brief Check if Transmit data register is empty (it means that Data written in transmit 00523 * data register SWPMI_TDR has been transmitted and SWPMI_TDR can be written to again) 00524 * @rmtoll ISR TXE LL_SWPMI_IsActiveFlag_TXE 00525 * @param SWPMIx SWPMI Instance 00526 * @retval State of bit (1 or 0). 00527 */ 00528 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TXE(SWPMI_TypeDef *SWPMIx) 00529 { 00530 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TXE) == (SWPMI_ISR_TXE)); 00531 } 00532 00533 /** 00534 * @brief Check if Both transmission and reception are completed and SWP is switched to 00535 * the SUSPENDED state 00536 * @rmtoll ISR TCF LL_SWPMI_IsActiveFlag_TC 00537 * @param SWPMIx SWPMI Instance 00538 * @retval State of bit (1 or 0). 00539 */ 00540 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_TC(SWPMI_TypeDef *SWPMIx) 00541 { 00542 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_TCF) == (SWPMI_ISR_TCF)); 00543 } 00544 00545 /** 00546 * @brief Check if a Resume by slave state has been detected during the SWP bus SUSPENDED 00547 * state 00548 * @rmtoll ISR SRF LL_SWPMI_IsActiveFlag_SR 00549 * @param SWPMIx SWPMI Instance 00550 * @retval State of bit (1 or 0). 00551 */ 00552 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SR(SWPMI_TypeDef *SWPMIx) 00553 { 00554 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SRF) == (SWPMI_ISR_SRF)); 00555 } 00556 00557 /** 00558 * @brief Check if SWP bus is in SUSPENDED or DEACTIVATED state 00559 * @rmtoll ISR SUSP LL_SWPMI_IsActiveFlag_SUSP 00560 * @param SWPMIx SWPMI Instance 00561 * @retval State of bit (1 or 0). 00562 */ 00563 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_SUSP(SWPMI_TypeDef *SWPMIx) 00564 { 00565 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_SUSP) == (SWPMI_ISR_SUSP)); 00566 } 00567 00568 /** 00569 * @brief Check if SWP bus is in DEACTIVATED state 00570 * @rmtoll ISR DEACTF LL_SWPMI_IsActiveFlag_DEACT 00571 * @param SWPMIx SWPMI Instance 00572 * @retval State of bit (1 or 0). 00573 */ 00574 __STATIC_INLINE uint32_t LL_SWPMI_IsActiveFlag_DEACT(SWPMI_TypeDef *SWPMIx) 00575 { 00576 return (READ_BIT(SWPMIx->ISR, SWPMI_ISR_DEACTF) == (SWPMI_ISR_DEACTF)); 00577 } 00578 00579 /** 00580 * @brief Clear receive buffer full flag 00581 * @rmtoll ICR CRXBFF LL_SWPMI_ClearFlag_RXBF 00582 * @param SWPMIx SWPMI Instance 00583 * @retval None 00584 */ 00585 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBF(SWPMI_TypeDef *SWPMIx) 00586 { 00587 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBFF); 00588 } 00589 00590 /** 00591 * @brief Clear transmit buffer empty flag 00592 * @rmtoll ICR CTXBEF LL_SWPMI_ClearFlag_TXBE 00593 * @param SWPMIx SWPMI Instance 00594 * @retval None 00595 */ 00596 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXBE(SWPMI_TypeDef *SWPMIx) 00597 { 00598 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXBEF); 00599 } 00600 00601 /** 00602 * @brief Clear receive CRC error flag 00603 * @rmtoll ICR CRXBERF LL_SWPMI_ClearFlag_RXBER 00604 * @param SWPMIx SWPMI Instance 00605 * @retval None 00606 */ 00607 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXBER(SWPMI_TypeDef *SWPMIx) 00608 { 00609 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXBERF); 00610 } 00611 00612 /** 00613 * @brief Clear receive overrun error flag 00614 * @rmtoll ICR CRXOVRF LL_SWPMI_ClearFlag_RXOVR 00615 * @param SWPMIx SWPMI Instance 00616 * @retval None 00617 */ 00618 __STATIC_INLINE void LL_SWPMI_ClearFlag_RXOVR(SWPMI_TypeDef *SWPMIx) 00619 { 00620 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CRXOVRF); 00621 } 00622 00623 /** 00624 * @brief Clear transmit underrun error flag 00625 * @rmtoll ICR CTXUNRF LL_SWPMI_ClearFlag_TXUNR 00626 * @param SWPMIx SWPMI Instance 00627 * @retval None 00628 */ 00629 __STATIC_INLINE void LL_SWPMI_ClearFlag_TXUNR(SWPMI_TypeDef *SWPMIx) 00630 { 00631 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTXUNRF); 00632 } 00633 00634 /** 00635 * @brief Clear transfer complete flag 00636 * @rmtoll ICR CTCF LL_SWPMI_ClearFlag_TC 00637 * @param SWPMIx SWPMI Instance 00638 * @retval None 00639 */ 00640 __STATIC_INLINE void LL_SWPMI_ClearFlag_TC(SWPMI_TypeDef *SWPMIx) 00641 { 00642 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CTCF); 00643 } 00644 00645 /** 00646 * @brief Clear slave resume flag 00647 * @rmtoll ICR CSRF LL_SWPMI_ClearFlag_SR 00648 * @param SWPMIx SWPMI Instance 00649 * @retval None 00650 */ 00651 __STATIC_INLINE void LL_SWPMI_ClearFlag_SR(SWPMI_TypeDef *SWPMIx) 00652 { 00653 WRITE_REG(SWPMIx->ICR, SWPMI_ICR_CSRF); 00654 } 00655 00656 /** 00657 * @} 00658 */ 00659 00660 /** @defgroup SWPMI_LL_EF_IT_Management IT_Management 00661 * @{ 00662 */ 00663 00664 /** 00665 * @brief Enable Slave resume interrupt 00666 * @rmtoll IER SRIE LL_SWPMI_EnableIT_SR 00667 * @param SWPMIx SWPMI Instance 00668 * @retval None 00669 */ 00670 __STATIC_INLINE void LL_SWPMI_EnableIT_SR(SWPMI_TypeDef *SWPMIx) 00671 { 00672 SET_BIT(SWPMIx->IER, SWPMI_IER_SRIE); 00673 } 00674 00675 /** 00676 * @brief Enable Transmit complete interrupt 00677 * @rmtoll IER TCIE LL_SWPMI_EnableIT_TC 00678 * @param SWPMIx SWPMI Instance 00679 * @retval None 00680 */ 00681 __STATIC_INLINE void LL_SWPMI_EnableIT_TC(SWPMI_TypeDef *SWPMIx) 00682 { 00683 SET_BIT(SWPMIx->IER, SWPMI_IER_TCIE); 00684 } 00685 00686 /** 00687 * @brief Enable Transmit interrupt 00688 * @rmtoll IER TIE LL_SWPMI_EnableIT_TX 00689 * @param SWPMIx SWPMI Instance 00690 * @retval None 00691 */ 00692 __STATIC_INLINE void LL_SWPMI_EnableIT_TX(SWPMI_TypeDef *SWPMIx) 00693 { 00694 SET_BIT(SWPMIx->IER, SWPMI_IER_TIE); 00695 } 00696 00697 /** 00698 * @brief Enable Receive interrupt 00699 * @rmtoll IER RIE LL_SWPMI_EnableIT_RX 00700 * @param SWPMIx SWPMI Instance 00701 * @retval None 00702 */ 00703 __STATIC_INLINE void LL_SWPMI_EnableIT_RX(SWPMI_TypeDef *SWPMIx) 00704 { 00705 SET_BIT(SWPMIx->IER, SWPMI_IER_RIE); 00706 } 00707 00708 /** 00709 * @brief Enable Transmit underrun error interrupt 00710 * @rmtoll IER TXUNRIE LL_SWPMI_EnableIT_TXUNR 00711 * @param SWPMIx SWPMI Instance 00712 * @retval None 00713 */ 00714 __STATIC_INLINE void LL_SWPMI_EnableIT_TXUNR(SWPMI_TypeDef *SWPMIx) 00715 { 00716 SET_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE); 00717 } 00718 00719 /** 00720 * @brief Enable Receive overrun error interrupt 00721 * @rmtoll IER RXOVRIE LL_SWPMI_EnableIT_RXOVR 00722 * @param SWPMIx SWPMI Instance 00723 * @retval None 00724 */ 00725 __STATIC_INLINE void LL_SWPMI_EnableIT_RXOVR(SWPMI_TypeDef *SWPMIx) 00726 { 00727 SET_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE); 00728 } 00729 00730 /** 00731 * @brief Enable Receive CRC error interrupt 00732 * @rmtoll IER RXBERIE LL_SWPMI_EnableIT_RXBER 00733 * @param SWPMIx SWPMI Instance 00734 * @retval None 00735 */ 00736 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBER(SWPMI_TypeDef *SWPMIx) 00737 { 00738 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE); 00739 } 00740 00741 /** 00742 * @brief Enable Transmit buffer empty interrupt 00743 * @rmtoll IER TXBEIE LL_SWPMI_EnableIT_TXBE 00744 * @param SWPMIx SWPMI Instance 00745 * @retval None 00746 */ 00747 __STATIC_INLINE void LL_SWPMI_EnableIT_TXBE(SWPMI_TypeDef *SWPMIx) 00748 { 00749 SET_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE); 00750 } 00751 00752 /** 00753 * @brief Enable Receive buffer full interrupt 00754 * @rmtoll IER RXBFIE LL_SWPMI_EnableIT_RXBF 00755 * @param SWPMIx SWPMI Instance 00756 * @retval None 00757 */ 00758 __STATIC_INLINE void LL_SWPMI_EnableIT_RXBF(SWPMI_TypeDef *SWPMIx) 00759 { 00760 SET_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE); 00761 } 00762 00763 /** 00764 * @brief Disable Slave resume interrupt 00765 * @rmtoll IER SRIE LL_SWPMI_DisableIT_SR 00766 * @param SWPMIx SWPMI Instance 00767 * @retval None 00768 */ 00769 __STATIC_INLINE void LL_SWPMI_DisableIT_SR(SWPMI_TypeDef *SWPMIx) 00770 { 00771 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_SRIE); 00772 } 00773 00774 /** 00775 * @brief Disable Transmit complete interrupt 00776 * @rmtoll IER TCIE LL_SWPMI_DisableIT_TC 00777 * @param SWPMIx SWPMI Instance 00778 * @retval None 00779 */ 00780 __STATIC_INLINE void LL_SWPMI_DisableIT_TC(SWPMI_TypeDef *SWPMIx) 00781 { 00782 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TCIE); 00783 } 00784 00785 /** 00786 * @brief Disable Transmit interrupt 00787 * @rmtoll IER TIE LL_SWPMI_DisableIT_TX 00788 * @param SWPMIx SWPMI Instance 00789 * @retval None 00790 */ 00791 __STATIC_INLINE void LL_SWPMI_DisableIT_TX(SWPMI_TypeDef *SWPMIx) 00792 { 00793 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TIE); 00794 } 00795 00796 /** 00797 * @brief Disable Receive interrupt 00798 * @rmtoll IER RIE LL_SWPMI_DisableIT_RX 00799 * @param SWPMIx SWPMI Instance 00800 * @retval None 00801 */ 00802 __STATIC_INLINE void LL_SWPMI_DisableIT_RX(SWPMI_TypeDef *SWPMIx) 00803 { 00804 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RIE); 00805 } 00806 00807 /** 00808 * @brief Disable Transmit underrun error interrupt 00809 * @rmtoll IER TXUNRIE LL_SWPMI_DisableIT_TXUNR 00810 * @param SWPMIx SWPMI Instance 00811 * @retval None 00812 */ 00813 __STATIC_INLINE void LL_SWPMI_DisableIT_TXUNR(SWPMI_TypeDef *SWPMIx) 00814 { 00815 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE); 00816 } 00817 00818 /** 00819 * @brief Disable Receive overrun error interrupt 00820 * @rmtoll IER RXOVRIE LL_SWPMI_DisableIT_RXOVR 00821 * @param SWPMIx SWPMI Instance 00822 * @retval None 00823 */ 00824 __STATIC_INLINE void LL_SWPMI_DisableIT_RXOVR(SWPMI_TypeDef *SWPMIx) 00825 { 00826 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE); 00827 } 00828 00829 /** 00830 * @brief Disable Receive CRC error interrupt 00831 * @rmtoll IER RXBERIE LL_SWPMI_DisableIT_RXBER 00832 * @param SWPMIx SWPMI Instance 00833 * @retval None 00834 */ 00835 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBER(SWPMI_TypeDef *SWPMIx) 00836 { 00837 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE); 00838 } 00839 00840 /** 00841 * @brief Disable Transmit buffer empty interrupt 00842 * @rmtoll IER TXBEIE LL_SWPMI_DisableIT_TXBE 00843 * @param SWPMIx SWPMI Instance 00844 * @retval None 00845 */ 00846 __STATIC_INLINE void LL_SWPMI_DisableIT_TXBE(SWPMI_TypeDef *SWPMIx) 00847 { 00848 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE); 00849 } 00850 00851 /** 00852 * @brief Disable Receive buffer full interrupt 00853 * @rmtoll IER RXBFIE LL_SWPMI_DisableIT_RXBF 00854 * @param SWPMIx SWPMI Instance 00855 * @retval None 00856 */ 00857 __STATIC_INLINE void LL_SWPMI_DisableIT_RXBF(SWPMI_TypeDef *SWPMIx) 00858 { 00859 CLEAR_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE); 00860 } 00861 00862 /** 00863 * @brief Check if Slave resume interrupt is enabled 00864 * @rmtoll IER SRIE LL_SWPMI_IsEnabledIT_SR 00865 * @param SWPMIx SWPMI Instance 00866 * @retval State of bit (1 or 0). 00867 */ 00868 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_SR(SWPMI_TypeDef *SWPMIx) 00869 { 00870 return (READ_BIT(SWPMIx->IER, SWPMI_IER_SRIE) == (SWPMI_IER_SRIE)); 00871 } 00872 00873 /** 00874 * @brief Check if Transmit complete interrupt is enabled 00875 * @rmtoll IER TCIE LL_SWPMI_IsEnabledIT_TC 00876 * @param SWPMIx SWPMI Instance 00877 * @retval State of bit (1 or 0). 00878 */ 00879 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TC(SWPMI_TypeDef *SWPMIx) 00880 { 00881 return (READ_BIT(SWPMIx->IER, SWPMI_IER_TCIE) == (SWPMI_IER_TCIE)); 00882 } 00883 00884 /** 00885 * @brief Check if Transmit interrupt is enabled 00886 * @rmtoll IER TIE LL_SWPMI_IsEnabledIT_TX 00887 * @param SWPMIx SWPMI Instance 00888 * @retval State of bit (1 or 0). 00889 */ 00890 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TX(SWPMI_TypeDef *SWPMIx) 00891 { 00892 return (READ_BIT(SWPMIx->IER, SWPMI_IER_TIE) == (SWPMI_IER_TIE)); 00893 } 00894 00895 /** 00896 * @brief Check if Receive interrupt is enabled 00897 * @rmtoll IER RIE LL_SWPMI_IsEnabledIT_RX 00898 * @param SWPMIx SWPMI Instance 00899 * @retval State of bit (1 or 0). 00900 */ 00901 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RX(SWPMI_TypeDef *SWPMIx) 00902 { 00903 return (READ_BIT(SWPMIx->IER, SWPMI_IER_RIE) == (SWPMI_IER_RIE)); 00904 } 00905 00906 /** 00907 * @brief Check if Transmit underrun error interrupt is enabled 00908 * @rmtoll IER TXUNRIE LL_SWPMI_IsEnabledIT_TXUNR 00909 * @param SWPMIx SWPMI Instance 00910 * @retval State of bit (1 or 0). 00911 */ 00912 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXUNR(SWPMI_TypeDef *SWPMIx) 00913 { 00914 return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXUNRIE) == (SWPMI_IER_TXUNRIE)); 00915 } 00916 00917 /** 00918 * @brief Check if Receive overrun error interrupt is enabled 00919 * @rmtoll IER RXOVRIE LL_SWPMI_IsEnabledIT_RXOVR 00920 * @param SWPMIx SWPMI Instance 00921 * @retval State of bit (1 or 0). 00922 */ 00923 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXOVR(SWPMI_TypeDef *SWPMIx) 00924 { 00925 return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXOVRIE) == (SWPMI_IER_RXOVRIE)); 00926 } 00927 00928 /** 00929 * @brief Check if Receive CRC error interrupt is enabled 00930 * @rmtoll IER RXBERIE LL_SWPMI_IsEnabledIT_RXBER 00931 * @param SWPMIx SWPMI Instance 00932 * @retval State of bit (1 or 0). 00933 */ 00934 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBER(SWPMI_TypeDef *SWPMIx) 00935 { 00936 return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBERIE) == (SWPMI_IER_RXBERIE)); 00937 } 00938 00939 /** 00940 * @brief Check if Transmit buffer empty interrupt is enabled 00941 * @rmtoll IER TXBEIE LL_SWPMI_IsEnabledIT_TXBE 00942 * @param SWPMIx SWPMI Instance 00943 * @retval State of bit (1 or 0). 00944 */ 00945 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_TXBE(SWPMI_TypeDef *SWPMIx) 00946 { 00947 return (READ_BIT(SWPMIx->IER, SWPMI_IER_TXBEIE) == (SWPMI_IER_TXBEIE)); 00948 } 00949 00950 /** 00951 * @brief Check if Receive buffer full interrupt is enabled 00952 * @rmtoll IER RXBFIE LL_SWPMI_IsEnabledIT_RXBF 00953 * @param SWPMIx SWPMI Instance 00954 * @retval State of bit (1 or 0). 00955 */ 00956 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledIT_RXBF(SWPMI_TypeDef *SWPMIx) 00957 { 00958 return (READ_BIT(SWPMIx->IER, SWPMI_IER_RXBFIE) == (SWPMI_IER_RXBFIE)); 00959 } 00960 00961 /** 00962 * @} 00963 */ 00964 00965 /** @defgroup SWPMI_LL_EF_DMA_Management DMA_Management 00966 * @{ 00967 */ 00968 00969 /** 00970 * @brief Enable DMA mode for reception 00971 * @rmtoll CR RXDMA LL_SWPMI_EnableDMAReq_RX 00972 * @param SWPMIx SWPMI Instance 00973 * @retval None 00974 */ 00975 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_RX(SWPMI_TypeDef *SWPMIx) 00976 { 00977 SET_BIT(SWPMIx->CR, SWPMI_CR_RXDMA); 00978 } 00979 00980 /** 00981 * @brief Disable DMA mode for reception 00982 * @rmtoll CR RXDMA LL_SWPMI_DisableDMAReq_RX 00983 * @param SWPMIx SWPMI Instance 00984 * @retval None 00985 */ 00986 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_RX(SWPMI_TypeDef *SWPMIx) 00987 { 00988 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_RXDMA); 00989 } 00990 00991 /** 00992 * @brief Check if DMA mode for reception is enabled 00993 * @rmtoll CR RXDMA LL_SWPMI_IsEnabledDMAReq_RX 00994 * @param SWPMIx SWPMI Instance 00995 * @retval State of bit (1 or 0). 00996 */ 00997 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_RX(SWPMI_TypeDef *SWPMIx) 00998 { 00999 return (READ_BIT(SWPMIx->CR, SWPMI_CR_RXDMA) == (SWPMI_CR_RXDMA)); 01000 } 01001 01002 /** 01003 * @brief Enable DMA mode for transmission 01004 * @rmtoll CR TXDMA LL_SWPMI_EnableDMAReq_TX 01005 * @param SWPMIx SWPMI Instance 01006 * @retval None 01007 */ 01008 __STATIC_INLINE void LL_SWPMI_EnableDMAReq_TX(SWPMI_TypeDef *SWPMIx) 01009 { 01010 SET_BIT(SWPMIx->CR, SWPMI_CR_TXDMA); 01011 } 01012 01013 /** 01014 * @brief Disable DMA mode for transmission 01015 * @rmtoll CR TXDMA LL_SWPMI_DisableDMAReq_TX 01016 * @param SWPMIx SWPMI Instance 01017 * @retval None 01018 */ 01019 __STATIC_INLINE void LL_SWPMI_DisableDMAReq_TX(SWPMI_TypeDef *SWPMIx) 01020 { 01021 CLEAR_BIT(SWPMIx->CR, SWPMI_CR_TXDMA); 01022 } 01023 01024 /** 01025 * @brief Check if DMA mode for transmission is enabled 01026 * @rmtoll CR TXDMA LL_SWPMI_IsEnabledDMAReq_TX 01027 * @param SWPMIx SWPMI Instance 01028 * @retval State of bit (1 or 0). 01029 */ 01030 __STATIC_INLINE uint32_t LL_SWPMI_IsEnabledDMAReq_TX(SWPMI_TypeDef *SWPMIx) 01031 { 01032 return (READ_BIT(SWPMIx->CR, SWPMI_CR_TXDMA) == (SWPMI_CR_TXDMA)); 01033 } 01034 01035 /** 01036 * @brief Get the data register address used for DMA transfer 01037 * @rmtoll TDR TD LL_SWPMI_DMA_GetRegAddr\n 01038 * RDR RD LL_SWPMI_DMA_GetRegAddr 01039 * @param SWPMIx SWPMI Instance 01040 * @param Direction This parameter can be one of the following values: 01041 * @arg @ref LL_SWPMI_DMA_REG_DATA_TRANSMIT 01042 * @arg @ref LL_SWPMI_DMA_REG_DATA_RECEIVE 01043 * @retval Address of data register 01044 */ 01045 __STATIC_INLINE uint32_t LL_SWPMI_DMA_GetRegAddr(SWPMI_TypeDef *SWPMIx, uint32_t Direction) 01046 { 01047 register uint32_t data_reg_addr = 0; 01048 01049 if (Direction == LL_SWPMI_DMA_REG_DATA_TRANSMIT) 01050 { 01051 /* return address of TDR register */ 01052 data_reg_addr = (uint32_t)&(SWPMIx->TDR); 01053 } 01054 else 01055 { 01056 /* return address of RDR register */ 01057 data_reg_addr = (uint32_t)&(SWPMIx->RDR); 01058 } 01059 01060 return data_reg_addr; 01061 } 01062 01063 /** 01064 * @} 01065 */ 01066 01067 /** @defgroup SWPMI_LL_EF_Data_Management Data_Management 01068 * @{ 01069 */ 01070 01071 /** 01072 * @brief Retrieve number of data bytes present in payload of received frame 01073 * @rmtoll RFL RFL LL_SWPMI_GetReceiveFrameLength 01074 * @param SWPMIx SWPMI Instance 01075 * @retval Value between Min_Data=0x00 and Max_Data=0x1F 01076 */ 01077 __STATIC_INLINE uint32_t LL_SWPMI_GetReceiveFrameLength(SWPMI_TypeDef *SWPMIx) 01078 { 01079 return (uint32_t)(READ_BIT(SWPMIx->RFL, SWPMI_RFL_RFL)); 01080 } 01081 01082 /** 01083 * @brief Transmit Data Register 01084 * @rmtoll TDR TD LL_SWPMI_TransmitData32 01085 * @param SWPMIx SWPMI Instance 01086 * @param TxData Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 01087 * @retval None 01088 */ 01089 __STATIC_INLINE void LL_SWPMI_TransmitData32(SWPMI_TypeDef *SWPMIx, uint32_t TxData) 01090 { 01091 WRITE_REG(SWPMIx->TDR, TxData); 01092 } 01093 01094 /** 01095 * @brief Receive Data Register 01096 * @rmtoll RDR RD LL_SWPMI_ReceiveData32 01097 * @param SWPMIx SWPMI Instance 01098 * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF 01099 */ 01100 __STATIC_INLINE uint32_t LL_SWPMI_ReceiveData32(SWPMI_TypeDef *SWPMIx) 01101 { 01102 return (uint32_t)(READ_BIT(SWPMIx->RDR, SWPMI_RDR_RD)); 01103 } 01104 01105 /** 01106 * @brief Enable SWP Transceiver Bypass 01107 * @note The external interface for SWPMI is SWPMI_IO 01108 * (SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are not available on GPIOs) 01109 * @rmtoll OR TBYP LL_SWPMI_EnableTXBypass 01110 * @param SWPMIx SWPMI Instance 01111 * @retval None 01112 */ 01113 __STATIC_INLINE void LL_SWPMI_EnableTXBypass(SWPMI_TypeDef *SWPMIx) 01114 { 01115 CLEAR_BIT(SWPMIx->OR, SWPMI_OR_TBYP); 01116 } 01117 01118 /** 01119 * @brief Disable SWP Transceiver Bypass 01120 * @note SWPMI_RX, SWPMI_TX and SWPMI_SUSPEND signals are available as alternate 01121 * function on GPIOs. This configuration is selected to connect an external transceiver 01122 * @rmtoll OR TBYP LL_SWPMI_DisableTXBypass 01123 * @param SWPMIx SWPMI Instance 01124 * @retval None 01125 */ 01126 __STATIC_INLINE void LL_SWPMI_DisableTXBypass(SWPMI_TypeDef *SWPMIx) 01127 { 01128 SET_BIT(SWPMIx->OR, SWPMI_OR_TBYP); 01129 } 01130 01131 /** 01132 * @} 01133 */ 01134 01135 #if defined(USE_FULL_LL_DRIVER) 01136 /** @defgroup SWPMI_LL_EF_Init Initialization and de-initialization functions 01137 * @{ 01138 */ 01139 01140 ErrorStatus LL_SWPMI_DeInit(SWPMI_TypeDef *SWPMIx); 01141 ErrorStatus LL_SWPMI_Init(SWPMI_TypeDef *SWPMIx, LL_SWPMI_InitTypeDef *SWPMI_InitStruct); 01142 void LL_SWPMI_StructInit(LL_SWPMI_InitTypeDef *SWPMI_InitStruct); 01143 01144 /** 01145 * @} 01146 */ 01147 #endif /*USE_FULL_LL_DRIVER*/ 01148 01149 /** 01150 * @} 01151 */ 01152 01153 /** 01154 * @} 01155 */ 01156 01157 #endif /* SWPMI1 */ 01158 01159 /** 01160 * @} 01161 */ 01162 01163 #ifdef __cplusplus 01164 } 01165 #endif 01166 01167 #endif /* __STM32L4xx_LL_SWPMI_H */ 01168 01169 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/