STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_spi.h 00004 * @author MCD Application Team 00005 * @brief Header file of SPI LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_SPI_H 00038 #define __STM32L4xx_LL_SPI_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (SPI1) || defined (SPI2) || defined (SPI3) 00052 00053 /** @defgroup SPI_LL SPI 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /* Private macros ------------------------------------------------------------*/ 00060 00061 /* Exported types ------------------------------------------------------------*/ 00062 #if defined(USE_FULL_LL_DRIVER) 00063 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure 00064 * @{ 00065 */ 00066 00067 /** 00068 * @brief SPI Init structures definition 00069 */ 00070 typedef struct 00071 { 00072 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. 00073 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. 00074 00075 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ 00076 00077 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). 00078 This parameter can be a value of @ref SPI_LL_EC_MODE. 00079 00080 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ 00081 00082 uint32_t DataWidth; /*!< Specifies the SPI data width. 00083 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. 00084 00085 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ 00086 00087 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. 00088 This parameter can be a value of @ref SPI_LL_EC_POLARITY. 00089 00090 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ 00091 00092 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. 00093 This parameter can be a value of @ref SPI_LL_EC_PHASE. 00094 00095 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ 00096 00097 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. 00098 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. 00099 00100 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ 00101 00102 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. 00103 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. 00104 @note The communication clock is derived from the master clock. The slave clock does not need to be set. 00105 00106 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ 00107 00108 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. 00109 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. 00110 00111 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ 00112 00113 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 00114 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. 00115 00116 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ 00117 00118 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. 00119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. 00120 00121 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ 00122 00123 } LL_SPI_InitTypeDef; 00124 00125 /** 00126 * @} 00127 */ 00128 #endif /* USE_FULL_LL_DRIVER */ 00129 00130 /* Exported constants --------------------------------------------------------*/ 00131 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants 00132 * @{ 00133 */ 00134 00135 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines 00136 * @brief Flags defines which can be used with LL_SPI_ReadReg function 00137 * @{ 00138 */ 00139 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ 00140 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ 00141 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ 00142 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ 00143 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ 00144 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ 00145 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ 00146 /** 00147 * @} 00148 */ 00149 00150 /** @defgroup SPI_LL_EC_IT IT Defines 00151 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions 00152 * @{ 00153 */ 00154 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ 00155 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ 00156 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ 00157 /** 00158 * @} 00159 */ 00160 00161 /** @defgroup SPI_LL_EC_MODE Operation Mode 00162 * @{ 00163 */ 00164 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ 00165 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ 00166 /** 00167 * @} 00168 */ 00169 00170 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol 00171 * @{ 00172 */ 00173 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ 00174 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ 00175 /** 00176 * @} 00177 */ 00178 00179 /** @defgroup SPI_LL_EC_PHASE Clock Phase 00180 * @{ 00181 */ 00182 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ 00183 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ 00184 /** 00185 * @} 00186 */ 00187 00188 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity 00189 * @{ 00190 */ 00191 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ 00192 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ 00193 /** 00194 * @} 00195 */ 00196 00197 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler 00198 * @{ 00199 */ 00200 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ 00201 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ 00202 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ 00203 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ 00204 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ 00205 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ 00206 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ 00207 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ 00208 /** 00209 * @} 00210 */ 00211 00212 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order 00213 * @{ 00214 */ 00215 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ 00216 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ 00217 /** 00218 * @} 00219 */ 00220 00221 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode 00222 * @{ 00223 */ 00224 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ 00225 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ 00226 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ 00227 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode 00233 * @{ 00234 */ 00235 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ 00236 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ 00237 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ 00238 /** 00239 * @} 00240 */ 00241 00242 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth 00243 * @{ 00244 */ 00245 #define LL_SPI_DATAWIDTH_4BIT (SPI_CR2_DS_0 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 4 bits */ 00246 #define LL_SPI_DATAWIDTH_5BIT (SPI_CR2_DS_2) /*!< Data length for SPI transfer: 5 bits */ 00247 #define LL_SPI_DATAWIDTH_6BIT (SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 6 bits */ 00248 #define LL_SPI_DATAWIDTH_7BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 7 bits */ 00249 #define LL_SPI_DATAWIDTH_8BIT (SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 8 bits */ 00250 #define LL_SPI_DATAWIDTH_9BIT (SPI_CR2_DS_3) /*!< Data length for SPI transfer: 9 bits */ 00251 #define LL_SPI_DATAWIDTH_10BIT (SPI_CR2_DS_3 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 10 bits */ 00252 #define LL_SPI_DATAWIDTH_11BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 11 bits */ 00253 #define LL_SPI_DATAWIDTH_12BIT (SPI_CR2_DS_3 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 12 bits */ 00254 #define LL_SPI_DATAWIDTH_13BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2) /*!< Data length for SPI transfer: 13 bits */ 00255 #define LL_SPI_DATAWIDTH_14BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 14 bits */ 00256 #define LL_SPI_DATAWIDTH_15BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1) /*!< Data length for SPI transfer: 15 bits */ 00257 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS_3 | SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0) /*!< Data length for SPI transfer: 16 bits */ 00258 /** 00259 * @} 00260 */ 00261 #if defined(USE_FULL_LL_DRIVER) 00262 00263 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation 00264 * @{ 00265 */ 00266 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ 00267 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ 00268 /** 00269 * @} 00270 */ 00271 #endif /* USE_FULL_LL_DRIVER */ 00272 00273 /** @defgroup SPI_LL_EC_CRC_LENGTH CRC Length 00274 * @{ 00275 */ 00276 #define LL_SPI_CRC_8BIT 0x00000000U /*!< 8-bit CRC length */ 00277 #define LL_SPI_CRC_16BIT (SPI_CR1_CRCL) /*!< 16-bit CRC length */ 00278 /** 00279 * @} 00280 */ 00281 00282 /** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold 00283 * @{ 00284 */ 00285 #define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equel to 1/2 (16-bit) */ 00286 #define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equel to 1/4 (8-bit) */ 00287 /** 00288 * @} 00289 */ 00290 00291 /** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level 00292 * @{ 00293 */ 00294 #define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ 00295 #define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ 00296 #define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ 00297 #define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ 00298 /** 00299 * @} 00300 */ 00301 00302 /** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level 00303 * @{ 00304 */ 00305 #define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ 00306 #define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ 00307 #define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ 00308 #define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ 00309 /** 00310 * @} 00311 */ 00312 00313 /** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity 00314 * @{ 00315 */ 00316 #define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ 00317 #define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ 00318 00319 /** 00320 * @} 00321 */ 00322 00323 /** 00324 * @} 00325 */ 00326 00327 /* Exported macro ------------------------------------------------------------*/ 00328 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros 00329 * @{ 00330 */ 00331 00332 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros 00333 * @{ 00334 */ 00335 00336 /** 00337 * @brief Write a value in SPI register 00338 * @param __INSTANCE__ SPI Instance 00339 * @param __REG__ Register to be written 00340 * @param __VALUE__ Value to be written in the register 00341 * @retval None 00342 */ 00343 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00344 00345 /** 00346 * @brief Read a value in SPI register 00347 * @param __INSTANCE__ SPI Instance 00348 * @param __REG__ Register to be read 00349 * @retval Register value 00350 */ 00351 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00352 /** 00353 * @} 00354 */ 00355 00356 /** 00357 * @} 00358 */ 00359 00360 /* Exported functions --------------------------------------------------------*/ 00361 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions 00362 * @{ 00363 */ 00364 00365 /** @defgroup SPI_LL_EF_Configuration Configuration 00366 * @{ 00367 */ 00368 00369 /** 00370 * @brief Enable SPI peripheral 00371 * @rmtoll CR1 SPE LL_SPI_Enable 00372 * @param SPIx SPI Instance 00373 * @retval None 00374 */ 00375 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) 00376 { 00377 SET_BIT(SPIx->CR1, SPI_CR1_SPE); 00378 } 00379 00380 /** 00381 * @brief Disable SPI peripheral 00382 * @note When disabling the SPI, follow the procedure described in the Reference Manual. 00383 * @rmtoll CR1 SPE LL_SPI_Disable 00384 * @param SPIx SPI Instance 00385 * @retval None 00386 */ 00387 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) 00388 { 00389 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 00390 } 00391 00392 /** 00393 * @brief Check if SPI peripheral is enabled 00394 * @rmtoll CR1 SPE LL_SPI_IsEnabled 00395 * @param SPIx SPI Instance 00396 * @retval State of bit (1 or 0). 00397 */ 00398 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) 00399 { 00400 return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); 00401 } 00402 00403 /** 00404 * @brief Set SPI operation mode to Master or Slave 00405 * @note This bit should not be changed when communication is ongoing. 00406 * @rmtoll CR1 MSTR LL_SPI_SetMode\n 00407 * CR1 SSI LL_SPI_SetMode 00408 * @param SPIx SPI Instance 00409 * @param Mode This parameter can be one of the following values: 00410 * @arg @ref LL_SPI_MODE_MASTER 00411 * @arg @ref LL_SPI_MODE_SLAVE 00412 * @retval None 00413 */ 00414 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) 00415 { 00416 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); 00417 } 00418 00419 /** 00420 * @brief Get SPI operation mode (Master or Slave) 00421 * @rmtoll CR1 MSTR LL_SPI_GetMode\n 00422 * CR1 SSI LL_SPI_GetMode 00423 * @param SPIx SPI Instance 00424 * @retval Returned value can be one of the following values: 00425 * @arg @ref LL_SPI_MODE_MASTER 00426 * @arg @ref LL_SPI_MODE_SLAVE 00427 */ 00428 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) 00429 { 00430 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); 00431 } 00432 00433 /** 00434 * @brief Set serial protocol used 00435 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00436 * @rmtoll CR2 FRF LL_SPI_SetStandard 00437 * @param SPIx SPI Instance 00438 * @param Standard This parameter can be one of the following values: 00439 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 00440 * @arg @ref LL_SPI_PROTOCOL_TI 00441 * @retval None 00442 */ 00443 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) 00444 { 00445 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); 00446 } 00447 00448 /** 00449 * @brief Get serial protocol used 00450 * @rmtoll CR2 FRF LL_SPI_GetStandard 00451 * @param SPIx SPI Instance 00452 * @retval Returned value can be one of the following values: 00453 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 00454 * @arg @ref LL_SPI_PROTOCOL_TI 00455 */ 00456 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) 00457 { 00458 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); 00459 } 00460 00461 /** 00462 * @brief Set clock phase 00463 * @note This bit should not be changed when communication is ongoing. 00464 * This bit is not used in SPI TI mode. 00465 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase 00466 * @param SPIx SPI Instance 00467 * @param ClockPhase This parameter can be one of the following values: 00468 * @arg @ref LL_SPI_PHASE_1EDGE 00469 * @arg @ref LL_SPI_PHASE_2EDGE 00470 * @retval None 00471 */ 00472 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) 00473 { 00474 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); 00475 } 00476 00477 /** 00478 * @brief Get clock phase 00479 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase 00480 * @param SPIx SPI Instance 00481 * @retval Returned value can be one of the following values: 00482 * @arg @ref LL_SPI_PHASE_1EDGE 00483 * @arg @ref LL_SPI_PHASE_2EDGE 00484 */ 00485 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) 00486 { 00487 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); 00488 } 00489 00490 /** 00491 * @brief Set clock polarity 00492 * @note This bit should not be changed when communication is ongoing. 00493 * This bit is not used in SPI TI mode. 00494 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity 00495 * @param SPIx SPI Instance 00496 * @param ClockPolarity This parameter can be one of the following values: 00497 * @arg @ref LL_SPI_POLARITY_LOW 00498 * @arg @ref LL_SPI_POLARITY_HIGH 00499 * @retval None 00500 */ 00501 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) 00502 { 00503 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); 00504 } 00505 00506 /** 00507 * @brief Get clock polarity 00508 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity 00509 * @param SPIx SPI Instance 00510 * @retval Returned value can be one of the following values: 00511 * @arg @ref LL_SPI_POLARITY_LOW 00512 * @arg @ref LL_SPI_POLARITY_HIGH 00513 */ 00514 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) 00515 { 00516 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); 00517 } 00518 00519 /** 00520 * @brief Set baud rate prescaler 00521 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. 00522 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler 00523 * @param SPIx SPI Instance 00524 * @param BaudRate This parameter can be one of the following values: 00525 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 00526 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 00527 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 00528 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 00529 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 00530 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 00531 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 00532 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 00533 * @retval None 00534 */ 00535 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) 00536 { 00537 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); 00538 } 00539 00540 /** 00541 * @brief Get baud rate prescaler 00542 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler 00543 * @param SPIx SPI Instance 00544 * @retval Returned value can be one of the following values: 00545 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 00546 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 00547 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 00548 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 00549 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 00550 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 00551 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 00552 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 00553 */ 00554 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) 00555 { 00556 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); 00557 } 00558 00559 /** 00560 * @brief Set transfer bit order 00561 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00562 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder 00563 * @param SPIx SPI Instance 00564 * @param BitOrder This parameter can be one of the following values: 00565 * @arg @ref LL_SPI_LSB_FIRST 00566 * @arg @ref LL_SPI_MSB_FIRST 00567 * @retval None 00568 */ 00569 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) 00570 { 00571 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); 00572 } 00573 00574 /** 00575 * @brief Get transfer bit order 00576 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder 00577 * @param SPIx SPI Instance 00578 * @retval Returned value can be one of the following values: 00579 * @arg @ref LL_SPI_LSB_FIRST 00580 * @arg @ref LL_SPI_MSB_FIRST 00581 */ 00582 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) 00583 { 00584 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); 00585 } 00586 00587 /** 00588 * @brief Set transfer direction mode 00589 * @note For Half-Duplex mode, Rx Direction is set by default. 00590 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. 00591 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n 00592 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n 00593 * CR1 BIDIOE LL_SPI_SetTransferDirection 00594 * @param SPIx SPI Instance 00595 * @param TransferDirection This parameter can be one of the following values: 00596 * @arg @ref LL_SPI_FULL_DUPLEX 00597 * @arg @ref LL_SPI_SIMPLEX_RX 00598 * @arg @ref LL_SPI_HALF_DUPLEX_RX 00599 * @arg @ref LL_SPI_HALF_DUPLEX_TX 00600 * @retval None 00601 */ 00602 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) 00603 { 00604 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); 00605 } 00606 00607 /** 00608 * @brief Get transfer direction mode 00609 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n 00610 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n 00611 * CR1 BIDIOE LL_SPI_GetTransferDirection 00612 * @param SPIx SPI Instance 00613 * @retval Returned value can be one of the following values: 00614 * @arg @ref LL_SPI_FULL_DUPLEX 00615 * @arg @ref LL_SPI_SIMPLEX_RX 00616 * @arg @ref LL_SPI_HALF_DUPLEX_RX 00617 * @arg @ref LL_SPI_HALF_DUPLEX_TX 00618 */ 00619 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) 00620 { 00621 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); 00622 } 00623 00624 /** 00625 * @brief Set frame data width 00626 * @rmtoll CR2 DS LL_SPI_SetDataWidth 00627 * @param SPIx SPI Instance 00628 * @param DataWidth This parameter can be one of the following values: 00629 * @arg @ref LL_SPI_DATAWIDTH_4BIT 00630 * @arg @ref LL_SPI_DATAWIDTH_5BIT 00631 * @arg @ref LL_SPI_DATAWIDTH_6BIT 00632 * @arg @ref LL_SPI_DATAWIDTH_7BIT 00633 * @arg @ref LL_SPI_DATAWIDTH_8BIT 00634 * @arg @ref LL_SPI_DATAWIDTH_9BIT 00635 * @arg @ref LL_SPI_DATAWIDTH_10BIT 00636 * @arg @ref LL_SPI_DATAWIDTH_11BIT 00637 * @arg @ref LL_SPI_DATAWIDTH_12BIT 00638 * @arg @ref LL_SPI_DATAWIDTH_13BIT 00639 * @arg @ref LL_SPI_DATAWIDTH_14BIT 00640 * @arg @ref LL_SPI_DATAWIDTH_15BIT 00641 * @arg @ref LL_SPI_DATAWIDTH_16BIT 00642 * @retval None 00643 */ 00644 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) 00645 { 00646 MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); 00647 } 00648 00649 /** 00650 * @brief Get frame data width 00651 * @rmtoll CR2 DS LL_SPI_GetDataWidth 00652 * @param SPIx SPI Instance 00653 * @retval Returned value can be one of the following values: 00654 * @arg @ref LL_SPI_DATAWIDTH_4BIT 00655 * @arg @ref LL_SPI_DATAWIDTH_5BIT 00656 * @arg @ref LL_SPI_DATAWIDTH_6BIT 00657 * @arg @ref LL_SPI_DATAWIDTH_7BIT 00658 * @arg @ref LL_SPI_DATAWIDTH_8BIT 00659 * @arg @ref LL_SPI_DATAWIDTH_9BIT 00660 * @arg @ref LL_SPI_DATAWIDTH_10BIT 00661 * @arg @ref LL_SPI_DATAWIDTH_11BIT 00662 * @arg @ref LL_SPI_DATAWIDTH_12BIT 00663 * @arg @ref LL_SPI_DATAWIDTH_13BIT 00664 * @arg @ref LL_SPI_DATAWIDTH_14BIT 00665 * @arg @ref LL_SPI_DATAWIDTH_15BIT 00666 * @arg @ref LL_SPI_DATAWIDTH_16BIT 00667 */ 00668 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) 00669 { 00670 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); 00671 } 00672 00673 /** 00674 * @brief Set threshold of RXFIFO that triggers an RXNE event 00675 * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold 00676 * @param SPIx SPI Instance 00677 * @param Threshold This parameter can be one of the following values: 00678 * @arg @ref LL_SPI_RX_FIFO_TH_HALF 00679 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 00680 * @retval None 00681 */ 00682 __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) 00683 { 00684 MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); 00685 } 00686 00687 /** 00688 * @brief Get threshold of RXFIFO that triggers an RXNE event 00689 * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold 00690 * @param SPIx SPI Instance 00691 * @retval Returned value can be one of the following values: 00692 * @arg @ref LL_SPI_RX_FIFO_TH_HALF 00693 * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER 00694 */ 00695 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) 00696 { 00697 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); 00698 } 00699 00700 /** 00701 * @} 00702 */ 00703 00704 /** @defgroup SPI_LL_EF_CRC_Management CRC Management 00705 * @{ 00706 */ 00707 00708 /** 00709 * @brief Enable CRC 00710 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00711 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC 00712 * @param SPIx SPI Instance 00713 * @retval None 00714 */ 00715 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) 00716 { 00717 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); 00718 } 00719 00720 /** 00721 * @brief Disable CRC 00722 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00723 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC 00724 * @param SPIx SPI Instance 00725 * @retval None 00726 */ 00727 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) 00728 { 00729 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); 00730 } 00731 00732 /** 00733 * @brief Check if CRC is enabled 00734 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00735 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC 00736 * @param SPIx SPI Instance 00737 * @retval State of bit (1 or 0). 00738 */ 00739 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) 00740 { 00741 return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); 00742 } 00743 00744 /** 00745 * @brief Set CRC Length 00746 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00747 * @rmtoll CR1 CRCL LL_SPI_SetCRCWidth 00748 * @param SPIx SPI Instance 00749 * @param CRCLength This parameter can be one of the following values: 00750 * @arg @ref LL_SPI_CRC_8BIT 00751 * @arg @ref LL_SPI_CRC_16BIT 00752 * @retval None 00753 */ 00754 __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) 00755 { 00756 MODIFY_REG(SPIx->CR1, SPI_CR1_CRCL, CRCLength); 00757 } 00758 00759 /** 00760 * @brief Get CRC Length 00761 * @rmtoll CR1 CRCL LL_SPI_GetCRCWidth 00762 * @param SPIx SPI Instance 00763 * @retval Returned value can be one of the following values: 00764 * @arg @ref LL_SPI_CRC_8BIT 00765 * @arg @ref LL_SPI_CRC_16BIT 00766 */ 00767 __STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) 00768 { 00769 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); 00770 } 00771 00772 /** 00773 * @brief Set CRCNext to transfer CRC on the line 00774 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. 00775 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext 00776 * @param SPIx SPI Instance 00777 * @retval None 00778 */ 00779 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) 00780 { 00781 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); 00782 } 00783 00784 /** 00785 * @brief Set polynomial for CRC calculation 00786 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial 00787 * @param SPIx SPI Instance 00788 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00789 * @retval None 00790 */ 00791 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) 00792 { 00793 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); 00794 } 00795 00796 /** 00797 * @brief Get polynomial for CRC calculation 00798 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial 00799 * @param SPIx SPI Instance 00800 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00801 */ 00802 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) 00803 { 00804 return (uint32_t)(READ_REG(SPIx->CRCPR)); 00805 } 00806 00807 /** 00808 * @brief Get Rx CRC 00809 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC 00810 * @param SPIx SPI Instance 00811 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00812 */ 00813 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) 00814 { 00815 return (uint32_t)(READ_REG(SPIx->RXCRCR)); 00816 } 00817 00818 /** 00819 * @brief Get Tx CRC 00820 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC 00821 * @param SPIx SPI Instance 00822 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00823 */ 00824 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) 00825 { 00826 return (uint32_t)(READ_REG(SPIx->TXCRCR)); 00827 } 00828 00829 /** 00830 * @} 00831 */ 00832 00833 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management 00834 * @{ 00835 */ 00836 00837 /** 00838 * @brief Set NSS mode 00839 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. 00840 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n 00841 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode 00842 * @param SPIx SPI Instance 00843 * @param NSS This parameter can be one of the following values: 00844 * @arg @ref LL_SPI_NSS_SOFT 00845 * @arg @ref LL_SPI_NSS_HARD_INPUT 00846 * @arg @ref LL_SPI_NSS_HARD_OUTPUT 00847 * @retval None 00848 */ 00849 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) 00850 { 00851 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); 00852 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); 00853 } 00854 00855 /** 00856 * @brief Get NSS mode 00857 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n 00858 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode 00859 * @param SPIx SPI Instance 00860 * @retval Returned value can be one of the following values: 00861 * @arg @ref LL_SPI_NSS_SOFT 00862 * @arg @ref LL_SPI_NSS_HARD_INPUT 00863 * @arg @ref LL_SPI_NSS_HARD_OUTPUT 00864 */ 00865 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) 00866 { 00867 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); 00868 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); 00869 return (Ssm | Ssoe); 00870 } 00871 00872 /** 00873 * @brief Enable NSS pulse management 00874 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00875 * @rmtoll CR2 NSSP LL_SPI_EnableNSSPulseMgt 00876 * @param SPIx SPI Instance 00877 * @retval None 00878 */ 00879 __STATIC_INLINE void LL_SPI_EnableNSSPulseMgt(SPI_TypeDef *SPIx) 00880 { 00881 SET_BIT(SPIx->CR2, SPI_CR2_NSSP); 00882 } 00883 00884 /** 00885 * @brief Disable NSS pulse management 00886 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00887 * @rmtoll CR2 NSSP LL_SPI_DisableNSSPulseMgt 00888 * @param SPIx SPI Instance 00889 * @retval None 00890 */ 00891 __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) 00892 { 00893 CLEAR_BIT(SPIx->CR2, SPI_CR2_NSSP); 00894 } 00895 00896 /** 00897 * @brief Check if NSS pulse is enabled 00898 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00899 * @rmtoll CR2 NSSP LL_SPI_IsEnabledNSSPulse 00900 * @param SPIx SPI Instance 00901 * @retval State of bit (1 or 0). 00902 */ 00903 __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) 00904 { 00905 return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); 00906 } 00907 00908 /** 00909 * @} 00910 */ 00911 00912 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management 00913 * @{ 00914 */ 00915 00916 /** 00917 * @brief Check if Rx buffer is not empty 00918 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE 00919 * @param SPIx SPI Instance 00920 * @retval State of bit (1 or 0). 00921 */ 00922 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) 00923 { 00924 return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); 00925 } 00926 00927 /** 00928 * @brief Check if Tx buffer is empty 00929 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE 00930 * @param SPIx SPI Instance 00931 * @retval State of bit (1 or 0). 00932 */ 00933 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) 00934 { 00935 return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); 00936 } 00937 00938 /** 00939 * @brief Get CRC error flag 00940 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR 00941 * @param SPIx SPI Instance 00942 * @retval State of bit (1 or 0). 00943 */ 00944 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) 00945 { 00946 return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); 00947 } 00948 00949 /** 00950 * @brief Get mode fault error flag 00951 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF 00952 * @param SPIx SPI Instance 00953 * @retval State of bit (1 or 0). 00954 */ 00955 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) 00956 { 00957 return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); 00958 } 00959 00960 /** 00961 * @brief Get overrun error flag 00962 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR 00963 * @param SPIx SPI Instance 00964 * @retval State of bit (1 or 0). 00965 */ 00966 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) 00967 { 00968 return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); 00969 } 00970 00971 /** 00972 * @brief Get busy flag 00973 * @note The BSY flag is cleared under any one of the following conditions: 00974 * -When the SPI is correctly disabled 00975 * -When a fault is detected in Master mode (MODF bit set to 1) 00976 * -In Master mode, when it finishes a data transmission and no new data is ready to be 00977 * sent 00978 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between 00979 * each data transfer. 00980 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY 00981 * @param SPIx SPI Instance 00982 * @retval State of bit (1 or 0). 00983 */ 00984 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) 00985 { 00986 return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); 00987 } 00988 00989 /** 00990 * @brief Get frame format error flag 00991 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE 00992 * @param SPIx SPI Instance 00993 * @retval State of bit (1 or 0). 00994 */ 00995 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) 00996 { 00997 return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); 00998 } 00999 01000 /** 01001 * @brief Get FIFO reception Level 01002 * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel 01003 * @param SPIx SPI Instance 01004 * @retval Returned value can be one of the following values: 01005 * @arg @ref LL_SPI_RX_FIFO_EMPTY 01006 * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL 01007 * @arg @ref LL_SPI_RX_FIFO_HALF_FULL 01008 * @arg @ref LL_SPI_RX_FIFO_FULL 01009 */ 01010 __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) 01011 { 01012 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); 01013 } 01014 01015 /** 01016 * @brief Get FIFO Transmission Level 01017 * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel 01018 * @param SPIx SPI Instance 01019 * @retval Returned value can be one of the following values: 01020 * @arg @ref LL_SPI_TX_FIFO_EMPTY 01021 * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL 01022 * @arg @ref LL_SPI_TX_FIFO_HALF_FULL 01023 * @arg @ref LL_SPI_TX_FIFO_FULL 01024 */ 01025 __STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) 01026 { 01027 return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); 01028 } 01029 01030 /** 01031 * @brief Clear CRC error flag 01032 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR 01033 * @param SPIx SPI Instance 01034 * @retval None 01035 */ 01036 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) 01037 { 01038 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); 01039 } 01040 01041 /** 01042 * @brief Clear mode fault error flag 01043 * @note Clearing this flag is done by a read access to the SPIx_SR 01044 * register followed by a write access to the SPIx_CR1 register 01045 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF 01046 * @param SPIx SPI Instance 01047 * @retval None 01048 */ 01049 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) 01050 { 01051 __IO uint32_t tmpreg; 01052 tmpreg = SPIx->SR; 01053 (void) tmpreg; 01054 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 01055 (void) tmpreg; 01056 } 01057 01058 /** 01059 * @brief Clear overrun error flag 01060 * @note Clearing this flag is done by a read access to the SPIx_DR 01061 * register followed by a read access to the SPIx_SR register 01062 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR 01063 * @param SPIx SPI Instance 01064 * @retval None 01065 */ 01066 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) 01067 { 01068 __IO uint32_t tmpreg; 01069 tmpreg = SPIx->DR; 01070 (void) tmpreg; 01071 tmpreg = SPIx->SR; 01072 (void) tmpreg; 01073 } 01074 01075 /** 01076 * @brief Clear frame format error flag 01077 * @note Clearing this flag is done by reading SPIx_SR register 01078 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE 01079 * @param SPIx SPI Instance 01080 * @retval None 01081 */ 01082 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) 01083 { 01084 __IO uint32_t tmpreg; 01085 tmpreg = SPIx->SR; 01086 (void) tmpreg; 01087 } 01088 01089 /** 01090 * @} 01091 */ 01092 01093 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management 01094 * @{ 01095 */ 01096 01097 /** 01098 * @brief Enable error interrupt 01099 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). 01100 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR 01101 * @param SPIx SPI Instance 01102 * @retval None 01103 */ 01104 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) 01105 { 01106 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); 01107 } 01108 01109 /** 01110 * @brief Enable Rx buffer not empty interrupt 01111 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE 01112 * @param SPIx SPI Instance 01113 * @retval None 01114 */ 01115 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) 01116 { 01117 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 01118 } 01119 01120 /** 01121 * @brief Enable Tx buffer empty interrupt 01122 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE 01123 * @param SPIx SPI Instance 01124 * @retval None 01125 */ 01126 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) 01127 { 01128 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); 01129 } 01130 01131 /** 01132 * @brief Disable error interrupt 01133 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). 01134 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR 01135 * @param SPIx SPI Instance 01136 * @retval None 01137 */ 01138 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) 01139 { 01140 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); 01141 } 01142 01143 /** 01144 * @brief Disable Rx buffer not empty interrupt 01145 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE 01146 * @param SPIx SPI Instance 01147 * @retval None 01148 */ 01149 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) 01150 { 01151 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 01152 } 01153 01154 /** 01155 * @brief Disable Tx buffer empty interrupt 01156 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE 01157 * @param SPIx SPI Instance 01158 * @retval None 01159 */ 01160 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) 01161 { 01162 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); 01163 } 01164 01165 /** 01166 * @brief Check if error interrupt is enabled 01167 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR 01168 * @param SPIx SPI Instance 01169 * @retval State of bit (1 or 0). 01170 */ 01171 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) 01172 { 01173 return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); 01174 } 01175 01176 /** 01177 * @brief Check if Rx buffer not empty interrupt is enabled 01178 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE 01179 * @param SPIx SPI Instance 01180 * @retval State of bit (1 or 0). 01181 */ 01182 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) 01183 { 01184 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); 01185 } 01186 01187 /** 01188 * @brief Check if Tx buffer empty interrupt 01189 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE 01190 * @param SPIx SPI Instance 01191 * @retval State of bit (1 or 0). 01192 */ 01193 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) 01194 { 01195 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); 01196 } 01197 01198 /** 01199 * @} 01200 */ 01201 01202 /** @defgroup SPI_LL_EF_DMA_Management DMA Management 01203 * @{ 01204 */ 01205 01206 /** 01207 * @brief Enable DMA Rx 01208 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX 01209 * @param SPIx SPI Instance 01210 * @retval None 01211 */ 01212 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) 01213 { 01214 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 01215 } 01216 01217 /** 01218 * @brief Disable DMA Rx 01219 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX 01220 * @param SPIx SPI Instance 01221 * @retval None 01222 */ 01223 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) 01224 { 01225 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 01226 } 01227 01228 /** 01229 * @brief Check if DMA Rx is enabled 01230 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX 01231 * @param SPIx SPI Instance 01232 * @retval State of bit (1 or 0). 01233 */ 01234 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) 01235 { 01236 return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); 01237 } 01238 01239 /** 01240 * @brief Enable DMA Tx 01241 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX 01242 * @param SPIx SPI Instance 01243 * @retval None 01244 */ 01245 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) 01246 { 01247 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 01248 } 01249 01250 /** 01251 * @brief Disable DMA Tx 01252 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX 01253 * @param SPIx SPI Instance 01254 * @retval None 01255 */ 01256 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) 01257 { 01258 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 01259 } 01260 01261 /** 01262 * @brief Check if DMA Tx is enabled 01263 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX 01264 * @param SPIx SPI Instance 01265 * @retval State of bit (1 or 0). 01266 */ 01267 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) 01268 { 01269 return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); 01270 } 01271 01272 /** 01273 * @brief Set parity of Last DMA reception 01274 * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX 01275 * @param SPIx SPI Instance 01276 * @param Parity This parameter can be one of the following values: 01277 * @arg @ref LL_SPI_DMA_PARITY_ODD 01278 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01279 * @retval None 01280 */ 01281 __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) 01282 { 01283 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMARX, (Parity << SPI_CR2_LDMARX_Pos)); 01284 } 01285 01286 /** 01287 * @brief Get parity configuration for Last DMA reception 01288 * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX 01289 * @param SPIx SPI Instance 01290 * @retval Returned value can be one of the following values: 01291 * @arg @ref LL_SPI_DMA_PARITY_ODD 01292 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01293 */ 01294 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) 01295 { 01296 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); 01297 } 01298 01299 /** 01300 * @brief Set parity of Last DMA transmission 01301 * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX 01302 * @param SPIx SPI Instance 01303 * @param Parity This parameter can be one of the following values: 01304 * @arg @ref LL_SPI_DMA_PARITY_ODD 01305 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01306 * @retval None 01307 */ 01308 __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) 01309 { 01310 MODIFY_REG(SPIx->CR2, SPI_CR2_LDMATX, (Parity << SPI_CR2_LDMATX_Pos)); 01311 } 01312 01313 /** 01314 * @brief Get parity configuration for Last DMA transmission 01315 * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX 01316 * @param SPIx SPI Instance 01317 * @retval Returned value can be one of the following values: 01318 * @arg @ref LL_SPI_DMA_PARITY_ODD 01319 * @arg @ref LL_SPI_DMA_PARITY_EVEN 01320 */ 01321 __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) 01322 { 01323 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); 01324 } 01325 01326 /** 01327 * @brief Get the data register address used for DMA transfer 01328 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr 01329 * @param SPIx SPI Instance 01330 * @retval Address of data register 01331 */ 01332 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) 01333 { 01334 return (uint32_t) & (SPIx->DR); 01335 } 01336 01337 /** 01338 * @} 01339 */ 01340 01341 /** @defgroup SPI_LL_EF_DATA_Management DATA Management 01342 * @{ 01343 */ 01344 01345 /** 01346 * @brief Read 8-Bits in the data register 01347 * @rmtoll DR DR LL_SPI_ReceiveData8 01348 * @param SPIx SPI Instance 01349 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF 01350 */ 01351 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) 01352 { 01353 return (uint8_t)(READ_REG(SPIx->DR)); 01354 } 01355 01356 /** 01357 * @brief Read 16-Bits in the data register 01358 * @rmtoll DR DR LL_SPI_ReceiveData16 01359 * @param SPIx SPI Instance 01360 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF 01361 */ 01362 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) 01363 { 01364 return (uint16_t)(READ_REG(SPIx->DR)); 01365 } 01366 01367 /** 01368 * @brief Write 8-Bits in the data register 01369 * @rmtoll DR DR LL_SPI_TransmitData8 01370 * @param SPIx SPI Instance 01371 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF 01372 * @retval None 01373 */ 01374 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) 01375 { 01376 #if defined (__GNUC__) 01377 __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); 01378 *spidr = TxData; 01379 #else 01380 *((__IO uint8_t *)&SPIx->DR) = TxData; 01381 #endif 01382 } 01383 01384 /** 01385 * @brief Write 16-Bits in the data register 01386 * @rmtoll DR DR LL_SPI_TransmitData16 01387 * @param SPIx SPI Instance 01388 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF 01389 * @retval None 01390 */ 01391 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) 01392 { 01393 #if defined (__GNUC__) 01394 __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); 01395 *spidr = TxData; 01396 #else 01397 *((__IO uint16_t *)&SPIx->DR) = TxData; 01398 #endif 01399 } 01400 01401 /** 01402 * @} 01403 */ 01404 #if defined(USE_FULL_LL_DRIVER) 01405 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions 01406 * @{ 01407 */ 01408 01409 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); 01410 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); 01411 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); 01412 01413 /** 01414 * @} 01415 */ 01416 #endif /* USE_FULL_LL_DRIVER */ 01417 /** 01418 * @} 01419 */ 01420 01421 /** 01422 * @} 01423 */ 01424 01425 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) */ 01426 01427 /** 01428 * @} 01429 */ 01430 01431 #ifdef __cplusplus 01432 } 01433 #endif 01434 01435 #endif /* __STM32L4xx_LL_SPI_H */ 01436 01437 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/