STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_pwr.h 00004 * @author MCD Application Team 00005 * @brief Header file of PWR LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_PWR_H 00038 #define __STM32L4xx_LL_PWR_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined(PWR) 00052 00053 /** @defgroup PWR_LL PWR 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 00060 /* Private constants ---------------------------------------------------------*/ 00061 00062 /* Private macros ------------------------------------------------------------*/ 00063 00064 /* Exported types ------------------------------------------------------------*/ 00065 /* Exported constants --------------------------------------------------------*/ 00066 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants 00067 * @{ 00068 */ 00069 00070 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines 00071 * @brief Flags defines which can be used with LL_PWR_WriteReg function 00072 * @{ 00073 */ 00074 #define LL_PWR_SCR_CSBF PWR_SCR_CSBF 00075 #define LL_PWR_SCR_CWUF PWR_SCR_CWUF 00076 #define LL_PWR_SCR_CWUF5 PWR_SCR_CWUF5 00077 #define LL_PWR_SCR_CWUF4 PWR_SCR_CWUF4 00078 #define LL_PWR_SCR_CWUF3 PWR_SCR_CWUF3 00079 #define LL_PWR_SCR_CWUF2 PWR_SCR_CWUF2 00080 #define LL_PWR_SCR_CWUF1 PWR_SCR_CWUF1 00081 /** 00082 * @} 00083 */ 00084 00085 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines 00086 * @brief Flags defines which can be used with LL_PWR_ReadReg function 00087 * @{ 00088 */ 00089 #define LL_PWR_SR1_WUFI PWR_SR1_WUFI 00090 #define LL_PWR_SR1_SBF PWR_SR1_SBF 00091 #define LL_PWR_SR1_WUF5 PWR_SR1_WUF5 00092 #define LL_PWR_SR1_WUF4 PWR_SR1_WUF4 00093 #define LL_PWR_SR1_WUF3 PWR_SR1_WUF3 00094 #define LL_PWR_SR1_WUF2 PWR_SR1_WUF2 00095 #define LL_PWR_SR1_WUF1 PWR_SR1_WUF1 00096 #if defined(PWR_SR2_PVMO4) 00097 #define LL_PWR_SR2_PVMO4 PWR_SR2_PVMO4 00098 #endif /* PWR_SR2_PVMO4 */ 00099 #if defined(PWR_SR2_PVMO3) 00100 #define LL_PWR_SR2_PVMO3 PWR_SR2_PVMO3 00101 #endif /* PWR_SR2_PVMO3 */ 00102 #if defined(PWR_SR2_PVMO2) 00103 #define LL_PWR_SR2_PVMO2 PWR_SR2_PVMO2 00104 #endif /* PWR_SR2_PVMO2 */ 00105 #if defined(PWR_SR2_PVMO1) 00106 #define LL_PWR_SR2_PVMO1 PWR_SR2_PVMO1 00107 #endif /* PWR_SR2_PVMO1 */ 00108 #define LL_PWR_SR2_PVDO PWR_SR2_PVDO 00109 #define LL_PWR_SR2_VOSF PWR_SR2_VOSF 00110 #define LL_PWR_SR2_REGLPF PWR_SR2_REGLPF 00111 #define LL_PWR_SR2_REGLPS PWR_SR2_REGLPS 00112 /** 00113 * @} 00114 */ 00115 00116 /** @defgroup PWR_LL_EC_REGU_VOLTAGE REGU VOLTAGE 00117 * @{ 00118 */ 00119 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_CR1_VOS_0) 00120 #define LL_PWR_REGU_VOLTAGE_SCALE2 (PWR_CR1_VOS_1) 00121 /** 00122 * @} 00123 */ 00124 00125 /** @defgroup PWR_LL_EC_MODE_PWR MODE PWR 00126 * @{ 00127 */ 00128 #define LL_PWR_MODE_STOP0 (PWR_CR1_LPMS_STOP0) 00129 #define LL_PWR_MODE_STOP1 (PWR_CR1_LPMS_STOP1) 00130 #define LL_PWR_MODE_STOP2 (PWR_CR1_LPMS_STOP2) 00131 #define LL_PWR_MODE_STANDBY (PWR_CR1_LPMS_STANDBY) 00132 #define LL_PWR_MODE_SHUTDOWN (PWR_CR1_LPMS_SHUTDOWN) 00133 /** 00134 * @} 00135 */ 00136 00137 /** @defgroup PWR_LL_EC_PVM_VDDUSB_1 Peripheral voltage monitoring 00138 * @{ 00139 */ 00140 #if defined(PWR_CR2_PVME1) 00141 #define LL_PWR_PVM_VDDUSB_1_2V (PWR_CR2_PVME1) /* Monitoring VDDUSB vs. 1.2V */ 00142 #endif 00143 #if defined(PWR_CR2_PVME2) 00144 #define LL_PWR_PVM_VDDIO2_0_9V (PWR_CR2_PVME2) /* Monitoring VDDIO2 vs. 0.9V */ 00145 #endif 00146 #if defined(PWR_CR2_PVME3) 00147 #define LL_PWR_PVM_VDDA_1_62V (PWR_CR2_PVME3) /* Monitoring VDDA vs. 1.62V */ 00148 #endif 00149 #if defined(PWR_CR2_PVME4) 00150 #define LL_PWR_PVM_VDDA_2_2V (PWR_CR2_PVME4) /* Monitoring VDDA vs. 2.2V */ 00151 #endif 00152 /** 00153 * @} 00154 */ 00155 00156 /** @defgroup PWR_LL_EC_PVDLEVEL PVDLEVEL 00157 * @{ 00158 */ 00159 #define LL_PWR_PVDLEVEL_0 (PWR_CR2_PLS_LEV0) /* VPVD0 around 2.0 V */ 00160 #define LL_PWR_PVDLEVEL_1 (PWR_CR2_PLS_LEV1) /* VPVD1 around 2.2 V */ 00161 #define LL_PWR_PVDLEVEL_2 (PWR_CR2_PLS_LEV2) /* VPVD2 around 2.4 V */ 00162 #define LL_PWR_PVDLEVEL_3 (PWR_CR2_PLS_LEV3) /* VPVD3 around 2.5 V */ 00163 #define LL_PWR_PVDLEVEL_4 (PWR_CR2_PLS_LEV4) /* VPVD4 around 2.6 V */ 00164 #define LL_PWR_PVDLEVEL_5 (PWR_CR2_PLS_LEV5) /* VPVD5 around 2.8 V */ 00165 #define LL_PWR_PVDLEVEL_6 (PWR_CR2_PLS_LEV6) /* VPVD6 around 2.9 V */ 00166 #define LL_PWR_PVDLEVEL_7 (PWR_CR2_PLS_LEV7) /* External input analog voltage (Compare internally to VREFINT) */ 00167 /** 00168 * @} 00169 */ 00170 00171 /** @defgroup PWR_LL_EC_WAKEUP WAKEUP 00172 * @{ 00173 */ 00174 #define LL_PWR_WAKEUP_PIN1 (PWR_CR3_EWUP1) 00175 #define LL_PWR_WAKEUP_PIN2 (PWR_CR3_EWUP2) 00176 #define LL_PWR_WAKEUP_PIN3 (PWR_CR3_EWUP3) 00177 #define LL_PWR_WAKEUP_PIN4 (PWR_CR3_EWUP4) 00178 #define LL_PWR_WAKEUP_PIN5 (PWR_CR3_EWUP5) 00179 /** 00180 * @} 00181 */ 00182 00183 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR BATT CHARG RESISTOR 00184 * @{ 00185 */ 00186 #define LL_PWR_BATT_CHARG_RESISTOR_5K (0x00000000U) 00187 #define LL_PWR_BATT_CHARGRESISTOR_1_5K (PWR_CR4_VBRS) 00188 /** 00189 * @} 00190 */ 00191 00192 /** @defgroup PWR_LL_EC_GPIO GPIO 00193 * @{ 00194 */ 00195 #define LL_PWR_GPIO_A ((uint32_t)(&(PWR->PUCRA))) 00196 #define LL_PWR_GPIO_B ((uint32_t)(&(PWR->PUCRB))) 00197 #define LL_PWR_GPIO_C ((uint32_t)(&(PWR->PUCRC))) 00198 #define LL_PWR_GPIO_D ((uint32_t)(&(PWR->PUCRD))) 00199 #define LL_PWR_GPIO_E ((uint32_t)(&(PWR->PUCRE))) 00200 #if defined(GPIOF) 00201 #define LL_PWR_GPIO_F ((uint32_t)(&(PWR->PUCRF))) 00202 #endif 00203 #if defined(GPIOG) 00204 #define LL_PWR_GPIO_G ((uint32_t)(&(PWR->PUCRG))) 00205 #endif 00206 #if defined(GPIOH) 00207 #define LL_PWR_GPIO_H ((uint32_t)(&(PWR->PUCRH))) 00208 #endif 00209 #if defined(GPIOI) 00210 #define LL_PWR_GPIO_I ((uint32_t)(&(PWR->PUCRI))) 00211 #endif 00212 /** 00213 * @} 00214 */ 00215 00216 /** @defgroup PWR_LL_EC_GPIO_BIT GPIO BIT 00217 * @{ 00218 */ 00219 #define LL_PWR_GPIO_BIT_0 (0x00000001U) 00220 #define LL_PWR_GPIO_BIT_1 (0x00000002U) 00221 #define LL_PWR_GPIO_BIT_2 (0x00000004U) 00222 #define LL_PWR_GPIO_BIT_3 (0x00000008U) 00223 #define LL_PWR_GPIO_BIT_4 (0x00000010U) 00224 #define LL_PWR_GPIO_BIT_5 (0x00000020U) 00225 #define LL_PWR_GPIO_BIT_6 (0x00000040U) 00226 #define LL_PWR_GPIO_BIT_7 (0x00000080U) 00227 #define LL_PWR_GPIO_BIT_8 (0x00000100U) 00228 #define LL_PWR_GPIO_BIT_9 (0x00000200U) 00229 #define LL_PWR_GPIO_BIT_10 (0x00000400U) 00230 #define LL_PWR_GPIO_BIT_11 (0x00000800U) 00231 #define LL_PWR_GPIO_BIT_12 (0x00001000U) 00232 #define LL_PWR_GPIO_BIT_13 (0x00002000U) 00233 #define LL_PWR_GPIO_BIT_14 (0x00004000U) 00234 #define LL_PWR_GPIO_BIT_15 (0x00008000U) 00235 /** 00236 * @} 00237 */ 00238 00239 /** 00240 * @} 00241 */ 00242 00243 /* Exported macro ------------------------------------------------------------*/ 00244 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros 00245 * @{ 00246 */ 00247 00248 /** @defgroup PWR_LL_EM_WRITE_READ Common Write and read registers Macros 00249 * @{ 00250 */ 00251 00252 /** 00253 * @brief Write a value in PWR register 00254 * @param __REG__ Register to be written 00255 * @param __VALUE__ Value to be written in the register 00256 * @retval None 00257 */ 00258 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__)) 00259 00260 /** 00261 * @brief Read a value in PWR register 00262 * @param __REG__ Register to be read 00263 * @retval Register value 00264 */ 00265 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__) 00266 /** 00267 * @} 00268 */ 00269 00270 /** 00271 * @} 00272 */ 00273 00274 00275 /* Exported functions --------------------------------------------------------*/ 00276 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions 00277 * @{ 00278 */ 00279 00280 /** @defgroup PWR_LL_EF_Configuration Configuration 00281 * @{ 00282 */ 00283 00284 /** 00285 * @brief Switch the regulator from main mode to low-power mode 00286 * @rmtoll CR1 LPR LL_PWR_EnableLowPowerRunMode 00287 * @retval None 00288 */ 00289 __STATIC_INLINE void LL_PWR_EnableLowPowerRunMode(void) 00290 { 00291 SET_BIT(PWR->CR1, PWR_CR1_LPR); 00292 } 00293 00294 /** 00295 * @brief Switch the regulator from low-power mode to main mode 00296 * @rmtoll CR1 LPR LL_PWR_DisableLowPowerRunMode 00297 * @retval None 00298 */ 00299 __STATIC_INLINE void LL_PWR_DisableLowPowerRunMode(void) 00300 { 00301 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); 00302 } 00303 00304 /** 00305 * @brief Switch from run main mode to run low-power mode. 00306 * @rmtoll CR1 LPR LL_PWR_EnterLowPowerRunMode 00307 * @retval None 00308 */ 00309 __STATIC_INLINE void LL_PWR_EnterLowPowerRunMode(void) 00310 { 00311 LL_PWR_EnableLowPowerRunMode(); 00312 } 00313 00314 /** 00315 * @brief Switch from run main mode to low-power mode. 00316 * @rmtoll CR1 LPR LL_PWR_ExitLowPowerRunMode 00317 * @retval None 00318 */ 00319 __STATIC_INLINE void LL_PWR_ExitLowPowerRunMode(void) 00320 { 00321 LL_PWR_DisableLowPowerRunMode(); 00322 } 00323 00324 /** 00325 * @brief Check if the regulator is in low-power mode 00326 * @rmtoll CR1 LPR LL_PWR_IsEnabledLowPowerRunMode 00327 * @retval State of bit (1 or 0). 00328 */ 00329 __STATIC_INLINE uint32_t LL_PWR_IsEnabledLowPowerRunMode(void) 00330 { 00331 return (READ_BIT(PWR->CR1, PWR_CR1_LPR) == (PWR_CR1_LPR)); 00332 } 00333 00334 /** 00335 * @brief Set the main internal regulator output voltage 00336 * @note This configuration may be completed with LL_PWR_EnableRange1BoostMode() on STM32L4Rx/STM32L4Sx devices. 00337 * @rmtoll CR1 VOS LL_PWR_SetRegulVoltageScaling 00338 * @param VoltageScaling This parameter can be one of the following values: 00339 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 00340 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 00341 * @retval None 00342 */ 00343 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling) 00344 { 00345 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, VoltageScaling); 00346 } 00347 00348 /** 00349 * @brief Get the main internal regulator output voltage 00350 * @rmtoll CR1 VOS LL_PWR_GetRegulVoltageScaling 00351 * @retval Returned value can be one of the following values: 00352 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1 00353 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2 00354 */ 00355 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void) 00356 { 00357 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_VOS)); 00358 } 00359 00360 #if defined(PWR_CR5_R1MODE) 00361 /** 00362 * @brief Enable main regulator voltage range 1 boost mode 00363 * @rmtoll CR5 R1MODE LL_PWR_EnableRange1BoostMode 00364 * @retval None 00365 */ 00366 __STATIC_INLINE void LL_PWR_EnableRange1BoostMode(void) 00367 { 00368 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 00369 } 00370 00371 /** 00372 * @brief Disable main regulator voltage range 1 boost mode 00373 * @rmtoll CR5 R1MODE LL_PWR_DisableRange1BoostMode 00374 * @retval None 00375 */ 00376 __STATIC_INLINE void LL_PWR_DisableRange1BoostMode(void) 00377 { 00378 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 00379 } 00380 00381 /** 00382 * @brief Check if the main regulator voltage range 1 boost mode is enabled 00383 * @rmtoll CR5 R1MODE LL_PWR_IsEnabledRange1BoostMode 00384 * @retval Inverted state of bit (0 or 1). 00385 */ 00386 __STATIC_INLINE uint32_t LL_PWR_IsEnabledRange1BoostMode(void) 00387 { 00388 return (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == RESET); 00389 } 00390 #endif /* PWR_CR5_R1MODE */ 00391 00392 /** 00393 * @brief Enable access to the backup domain 00394 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess 00395 * @retval None 00396 */ 00397 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void) 00398 { 00399 SET_BIT(PWR->CR1, PWR_CR1_DBP); 00400 } 00401 00402 /** 00403 * @brief Disable access to the backup domain 00404 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess 00405 * @retval None 00406 */ 00407 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void) 00408 { 00409 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP); 00410 } 00411 00412 /** 00413 * @brief Check if the backup domain is enabled 00414 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess 00415 * @retval State of bit (1 or 0). 00416 */ 00417 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void) 00418 { 00419 return (READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)); 00420 } 00421 00422 /** 00423 * @brief Set Low-Power mode 00424 * @rmtoll CR1 LPMS LL_PWR_SetPowerMode 00425 * @param LowPowerMode This parameter can be one of the following values: 00426 * @arg @ref LL_PWR_MODE_STOP0 00427 * @arg @ref LL_PWR_MODE_STOP1 00428 * @arg @ref LL_PWR_MODE_STOP2 00429 * @arg @ref LL_PWR_MODE_STANDBY 00430 * @arg @ref LL_PWR_MODE_SHUTDOWN 00431 * @retval None 00432 */ 00433 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t LowPowerMode) 00434 { 00435 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, LowPowerMode); 00436 } 00437 00438 /** 00439 * @brief Get Low-Power mode 00440 * @rmtoll CR1 LPMS LL_PWR_GetPowerMode 00441 * @retval Returned value can be one of the following values: 00442 * @arg @ref LL_PWR_MODE_STOP0 00443 * @arg @ref LL_PWR_MODE_STOP1 00444 * @arg @ref LL_PWR_MODE_STOP2 00445 * @arg @ref LL_PWR_MODE_STANDBY 00446 * @arg @ref LL_PWR_MODE_SHUTDOWN 00447 */ 00448 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void) 00449 { 00450 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPMS)); 00451 } 00452 00453 #if defined(PWR_CR1_RRSTP) 00454 /** 00455 * @brief Enable SRAM3 content retention in Stop mode 00456 * @rmtoll CR1 RRSTP LL_PWR_EnableSRAM3Retention 00457 * @retval None 00458 */ 00459 __STATIC_INLINE void LL_PWR_EnableSRAM3Retention(void) 00460 { 00461 SET_BIT(PWR->CR1, PWR_CR1_RRSTP); 00462 } 00463 00464 /** 00465 * @brief Disable SRAM3 content retention in Stop mode 00466 * @rmtoll CR1 RRSTP LL_PWR_DisableSRAM3Retention 00467 * @retval None 00468 */ 00469 __STATIC_INLINE void LL_PWR_DisableSRAM3Retention(void) 00470 { 00471 CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); 00472 } 00473 00474 /** 00475 * @brief Check if SRAM3 content retention in Stop mode is enabled 00476 * @rmtoll CR1 RRSTP LL_PWR_IsEnabledSRAM3Retention 00477 * @retval State of bit (1 or 0). 00478 */ 00479 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM3Retention(void) 00480 { 00481 return (READ_BIT(PWR->CR1, PWR_CR1_RRSTP) == (PWR_CR1_RRSTP)); 00482 } 00483 #endif /* PWR_CR1_RRSTP */ 00484 00485 #if defined(PWR_CR3_DSIPDEN) 00486 /** 00487 * @brief Enable pull-down activation on DSI pins 00488 * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPinsPDActivation 00489 * @retval None 00490 */ 00491 __STATIC_INLINE void LL_PWR_EnableDSIPinsPDActivation(void) 00492 { 00493 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); 00494 } 00495 00496 /** 00497 * @brief Disable pull-down activation on DSI pins 00498 * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPinsPDActivation 00499 * @retval None 00500 */ 00501 __STATIC_INLINE void LL_PWR_DisableDSIPinsPDActivation(void) 00502 { 00503 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); 00504 } 00505 00506 /** 00507 * @brief Check if pull-down activation on DSI pins is enabled 00508 * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPinsPDActivation 00509 * @retval State of bit (1 or 0). 00510 */ 00511 __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPinsPDActivation(void) 00512 { 00513 return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); 00514 } 00515 #endif /* PWR_CR3_DSIPDEN */ 00516 00517 #if defined(PWR_CR2_PVME1) 00518 /** 00519 * @brief Enable VDDUSB supply 00520 * @rmtoll CR2 USV LL_PWR_EnableVddUSB 00521 * @retval None 00522 */ 00523 __STATIC_INLINE void LL_PWR_EnableVddUSB(void) 00524 { 00525 SET_BIT(PWR->CR2, PWR_CR2_USV); 00526 } 00527 00528 /** 00529 * @brief Disable VDDUSB supply 00530 * @rmtoll CR2 USV LL_PWR_DisableVddUSB 00531 * @retval None 00532 */ 00533 __STATIC_INLINE void LL_PWR_DisableVddUSB(void) 00534 { 00535 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); 00536 } 00537 00538 /** 00539 * @brief Check if VDDUSB supply is enabled 00540 * @rmtoll CR2 USV LL_PWR_IsEnabledVddUSB 00541 * @retval State of bit (1 or 0). 00542 */ 00543 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddUSB(void) 00544 { 00545 return (READ_BIT(PWR->CR2, PWR_CR2_USV) == (PWR_CR2_USV)); 00546 } 00547 #endif 00548 00549 #if defined(PWR_CR2_IOSV) 00550 /** 00551 * @brief Enable VDDIO2 supply 00552 * @rmtoll CR2 IOSV LL_PWR_EnableVddIO2 00553 * @retval None 00554 */ 00555 __STATIC_INLINE void LL_PWR_EnableVddIO2(void) 00556 { 00557 SET_BIT(PWR->CR2, PWR_CR2_IOSV); 00558 } 00559 00560 /** 00561 * @brief Disable VDDIO2 supply 00562 * @rmtoll CR2 IOSV LL_PWR_DisableVddIO2 00563 * @retval None 00564 */ 00565 __STATIC_INLINE void LL_PWR_DisableVddIO2(void) 00566 { 00567 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); 00568 } 00569 00570 /** 00571 * @brief Check if VDDIO2 supply is enabled 00572 * @rmtoll CR2 IOSV LL_PWR_IsEnabledVddIO2 00573 * @retval State of bit (1 or 0). 00574 */ 00575 __STATIC_INLINE uint32_t LL_PWR_IsEnabledVddIO2(void) 00576 { 00577 return (READ_BIT(PWR->CR2, PWR_CR2_IOSV) == (PWR_CR2_IOSV)); 00578 } 00579 #endif 00580 00581 /** 00582 * @brief Enable the Power Voltage Monitoring on a peripheral 00583 * @rmtoll CR2 PVME1 LL_PWR_EnablePVM\n 00584 * CR2 PVME2 LL_PWR_EnablePVM\n 00585 * CR2 PVME3 LL_PWR_EnablePVM\n 00586 * CR2 PVME4 LL_PWR_EnablePVM 00587 * @param PeriphVoltage This parameter can be one of the following values: 00588 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00589 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) 00590 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00591 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00592 * 00593 * (*) value not defined in all devices 00594 * @retval None 00595 */ 00596 __STATIC_INLINE void LL_PWR_EnablePVM(uint32_t PeriphVoltage) 00597 { 00598 SET_BIT(PWR->CR2, PeriphVoltage); 00599 } 00600 00601 /** 00602 * @brief Disable the Power Voltage Monitoring on a peripheral 00603 * @rmtoll CR2 PVME1 LL_PWR_DisablePVM\n 00604 * CR2 PVME2 LL_PWR_DisablePVM\n 00605 * CR2 PVME3 LL_PWR_DisablePVM\n 00606 * CR2 PVME4 LL_PWR_DisablePVM 00607 * @param PeriphVoltage This parameter can be one of the following values: 00608 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00609 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) 00610 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00611 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00612 * 00613 * (*) value not defined in all devices 00614 * @retval None 00615 */ 00616 __STATIC_INLINE void LL_PWR_DisablePVM(uint32_t PeriphVoltage) 00617 { 00618 CLEAR_BIT(PWR->CR2, PeriphVoltage); 00619 } 00620 00621 /** 00622 * @brief Check if Power Voltage Monitoring is enabled on a peripheral 00623 * @rmtoll CR2 PVME1 LL_PWR_IsEnabledPVM\n 00624 * CR2 PVME2 LL_PWR_IsEnabledPVM\n 00625 * CR2 PVME3 LL_PWR_IsEnabledPVM\n 00626 * CR2 PVME4 LL_PWR_IsEnabledPVM 00627 * @param PeriphVoltage This parameter can be one of the following values: 00628 * @arg @ref LL_PWR_PVM_VDDUSB_1_2V (*) 00629 * @arg @ref LL_PWR_PVM_VDDIO2_0_9V (*) 00630 * @arg @ref LL_PWR_PVM_VDDA_1_62V 00631 * @arg @ref LL_PWR_PVM_VDDA_2_2V 00632 * 00633 * (*) value not defined in all devices 00634 * @retval State of bit (1 or 0). 00635 */ 00636 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVM(uint32_t PeriphVoltage) 00637 { 00638 return (READ_BIT(PWR->CR2, PeriphVoltage) == (PeriphVoltage)); 00639 } 00640 00641 /** 00642 * @brief Configure the voltage threshold detected by the Power Voltage Detector 00643 * @rmtoll CR2 PLS LL_PWR_SetPVDLevel 00644 * @param PVDLevel This parameter can be one of the following values: 00645 * @arg @ref LL_PWR_PVDLEVEL_0 00646 * @arg @ref LL_PWR_PVDLEVEL_1 00647 * @arg @ref LL_PWR_PVDLEVEL_2 00648 * @arg @ref LL_PWR_PVDLEVEL_3 00649 * @arg @ref LL_PWR_PVDLEVEL_4 00650 * @arg @ref LL_PWR_PVDLEVEL_5 00651 * @arg @ref LL_PWR_PVDLEVEL_6 00652 * @arg @ref LL_PWR_PVDLEVEL_7 00653 * @retval None 00654 */ 00655 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel) 00656 { 00657 MODIFY_REG(PWR->CR2, PWR_CR2_PLS, PVDLevel); 00658 } 00659 00660 /** 00661 * @brief Get the voltage threshold detection 00662 * @rmtoll CR2 PLS LL_PWR_GetPVDLevel 00663 * @retval Returned value can be one of the following values: 00664 * @arg @ref LL_PWR_PVDLEVEL_0 00665 * @arg @ref LL_PWR_PVDLEVEL_1 00666 * @arg @ref LL_PWR_PVDLEVEL_2 00667 * @arg @ref LL_PWR_PVDLEVEL_3 00668 * @arg @ref LL_PWR_PVDLEVEL_4 00669 * @arg @ref LL_PWR_PVDLEVEL_5 00670 * @arg @ref LL_PWR_PVDLEVEL_6 00671 * @arg @ref LL_PWR_PVDLEVEL_7 00672 */ 00673 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void) 00674 { 00675 return (uint32_t)(READ_BIT(PWR->CR2, PWR_CR2_PLS)); 00676 } 00677 00678 /** 00679 * @brief Enable Power Voltage Detector 00680 * @rmtoll CR2 PVDE LL_PWR_EnablePVD 00681 * @retval None 00682 */ 00683 __STATIC_INLINE void LL_PWR_EnablePVD(void) 00684 { 00685 SET_BIT(PWR->CR2, PWR_CR2_PVDE); 00686 } 00687 00688 /** 00689 * @brief Disable Power Voltage Detector 00690 * @rmtoll CR2 PVDE LL_PWR_DisablePVD 00691 * @retval None 00692 */ 00693 __STATIC_INLINE void LL_PWR_DisablePVD(void) 00694 { 00695 CLEAR_BIT(PWR->CR2, PWR_CR2_PVDE); 00696 } 00697 00698 /** 00699 * @brief Check if Power Voltage Detector is enabled 00700 * @rmtoll CR2 PVDE LL_PWR_IsEnabledPVD 00701 * @retval State of bit (1 or 0). 00702 */ 00703 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void) 00704 { 00705 return (READ_BIT(PWR->CR2, PWR_CR2_PVDE) == (PWR_CR2_PVDE)); 00706 } 00707 00708 /** 00709 * @brief Enable Internal Wake-up line 00710 * @rmtoll CR3 EIWF LL_PWR_EnableInternWU 00711 * @retval None 00712 */ 00713 __STATIC_INLINE void LL_PWR_EnableInternWU(void) 00714 { 00715 SET_BIT(PWR->CR3, PWR_CR3_EIWF); 00716 } 00717 00718 /** 00719 * @brief Disable Internal Wake-up line 00720 * @rmtoll CR3 EIWF LL_PWR_DisableInternWU 00721 * @retval None 00722 */ 00723 __STATIC_INLINE void LL_PWR_DisableInternWU(void) 00724 { 00725 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); 00726 } 00727 00728 /** 00729 * @brief Check if Internal Wake-up line is enabled 00730 * @rmtoll CR3 EIWF LL_PWR_IsEnabledInternWU 00731 * @retval State of bit (1 or 0). 00732 */ 00733 __STATIC_INLINE uint32_t LL_PWR_IsEnabledInternWU(void) 00734 { 00735 return (READ_BIT(PWR->CR3, PWR_CR3_EIWF) == (PWR_CR3_EIWF)); 00736 } 00737 00738 /** 00739 * @brief Enable pull-up and pull-down configuration 00740 * @rmtoll CR3 APC LL_PWR_EnablePUPDCfg 00741 * @retval None 00742 */ 00743 __STATIC_INLINE void LL_PWR_EnablePUPDCfg(void) 00744 { 00745 SET_BIT(PWR->CR3, PWR_CR3_APC); 00746 } 00747 00748 /** 00749 * @brief Disable pull-up and pull-down configuration 00750 * @rmtoll CR3 APC LL_PWR_DisablePUPDCfg 00751 * @retval None 00752 */ 00753 __STATIC_INLINE void LL_PWR_DisablePUPDCfg(void) 00754 { 00755 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); 00756 } 00757 00758 /** 00759 * @brief Check if pull-up and pull-down configuration is enabled 00760 * @rmtoll CR3 APC LL_PWR_IsEnabledPUPDCfg 00761 * @retval State of bit (1 or 0). 00762 */ 00763 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPUPDCfg(void) 00764 { 00765 return (READ_BIT(PWR->CR3, PWR_CR3_APC) == (PWR_CR3_APC)); 00766 } 00767 00768 #if defined(PWR_CR3_DSIPDEN) 00769 /** 00770 * @brief Enable pull-down activation on DSI pins 00771 * @rmtoll CR3 DSIPDEN LL_PWR_EnableDSIPullDown 00772 * @retval None 00773 */ 00774 __STATIC_INLINE void LL_PWR_EnableDSIPullDown(void) 00775 { 00776 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); 00777 } 00778 00779 /** 00780 * @brief Disable pull-down activation on DSI pins 00781 * @rmtoll CR3 DSIPDEN LL_PWR_DisableDSIPullDown 00782 * @retval None 00783 */ 00784 __STATIC_INLINE void LL_PWR_DisableDSIPullDown(void) 00785 { 00786 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); 00787 } 00788 00789 /** 00790 * @brief Check if pull-down activation on DSI pins is enabled 00791 * @rmtoll CR3 DSIPDEN LL_PWR_IsEnabledDSIPullDown 00792 * @retval State of bit (1 or 0). 00793 */ 00794 __STATIC_INLINE uint32_t LL_PWR_IsEnabledDSIPullDown(void) 00795 { 00796 return (READ_BIT(PWR->CR3, PWR_CR3_DSIPDEN) == (PWR_CR3_DSIPDEN)); 00797 } 00798 #endif /* PWR_CR3_DSIPDEN */ 00799 00800 /** 00801 * @brief Enable SRAM2 content retention in Standby mode 00802 * @rmtoll CR3 RRS LL_PWR_EnableSRAM2Retention 00803 * @retval None 00804 */ 00805 __STATIC_INLINE void LL_PWR_EnableSRAM2Retention(void) 00806 { 00807 SET_BIT(PWR->CR3, PWR_CR3_RRS); 00808 } 00809 00810 /** 00811 * @brief Disable SRAM2 content retention in Standby mode 00812 * @rmtoll CR3 RRS LL_PWR_DisableSRAM2Retention 00813 * @retval None 00814 */ 00815 __STATIC_INLINE void LL_PWR_DisableSRAM2Retention(void) 00816 { 00817 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); 00818 } 00819 00820 /** 00821 * @brief Check if SRAM2 content retention in Standby mode is enabled 00822 * @rmtoll CR3 RRS LL_PWR_IsEnabledSRAM2Retention 00823 * @retval State of bit (1 or 0). 00824 */ 00825 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRAM2Retention(void) 00826 { 00827 return (READ_BIT(PWR->CR3, PWR_CR3_RRS) == (PWR_CR3_RRS)); 00828 } 00829 00830 /** 00831 * @brief Enable the WakeUp PINx functionality 00832 * @rmtoll CR3 EWUP1 LL_PWR_EnableWakeUpPin\n 00833 * CR3 EWUP2 LL_PWR_EnableWakeUpPin\n 00834 * CR3 EWUP3 LL_PWR_EnableWakeUpPin\n 00835 * CR3 EWUP4 LL_PWR_EnableWakeUpPin\n 00836 * CR3 EWUP5 LL_PWR_EnableWakeUpPin\n 00837 * @param WakeUpPin This parameter can be one of the following values: 00838 * @arg @ref LL_PWR_WAKEUP_PIN1 00839 * @arg @ref LL_PWR_WAKEUP_PIN2 00840 * @arg @ref LL_PWR_WAKEUP_PIN3 00841 * @arg @ref LL_PWR_WAKEUP_PIN4 00842 * @arg @ref LL_PWR_WAKEUP_PIN5 00843 * @retval None 00844 */ 00845 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin) 00846 { 00847 SET_BIT(PWR->CR3, WakeUpPin); 00848 } 00849 00850 /** 00851 * @brief Disable the WakeUp PINx functionality 00852 * @rmtoll CR3 EWUP1 LL_PWR_DisableWakeUpPin\n 00853 * CR3 EWUP2 LL_PWR_DisableWakeUpPin\n 00854 * CR3 EWUP3 LL_PWR_DisableWakeUpPin\n 00855 * CR3 EWUP4 LL_PWR_DisableWakeUpPin\n 00856 * CR3 EWUP5 LL_PWR_DisableWakeUpPin\n 00857 * @param WakeUpPin This parameter can be one of the following values: 00858 * @arg @ref LL_PWR_WAKEUP_PIN1 00859 * @arg @ref LL_PWR_WAKEUP_PIN2 00860 * @arg @ref LL_PWR_WAKEUP_PIN3 00861 * @arg @ref LL_PWR_WAKEUP_PIN4 00862 * @arg @ref LL_PWR_WAKEUP_PIN5 00863 * @retval None 00864 */ 00865 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin) 00866 { 00867 CLEAR_BIT(PWR->CR3, WakeUpPin); 00868 } 00869 00870 /** 00871 * @brief Check if the WakeUp PINx functionality is enabled 00872 * @rmtoll CR3 EWUP1 LL_PWR_IsEnabledWakeUpPin\n 00873 * CR3 EWUP2 LL_PWR_IsEnabledWakeUpPin\n 00874 * CR3 EWUP3 LL_PWR_IsEnabledWakeUpPin\n 00875 * CR3 EWUP4 LL_PWR_IsEnabledWakeUpPin\n 00876 * CR3 EWUP5 LL_PWR_IsEnabledWakeUpPin\n 00877 * @param WakeUpPin This parameter can be one of the following values: 00878 * @arg @ref LL_PWR_WAKEUP_PIN1 00879 * @arg @ref LL_PWR_WAKEUP_PIN2 00880 * @arg @ref LL_PWR_WAKEUP_PIN3 00881 * @arg @ref LL_PWR_WAKEUP_PIN4 00882 * @arg @ref LL_PWR_WAKEUP_PIN5 00883 * @retval State of bit (1 or 0). 00884 */ 00885 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin) 00886 { 00887 return (READ_BIT(PWR->CR3, WakeUpPin) == (WakeUpPin)); 00888 } 00889 00890 /** 00891 * @brief Set the resistor impedance 00892 * @rmtoll CR4 VBRS LL_PWR_SetBattChargResistor 00893 * @param Resistor This parameter can be one of the following values: 00894 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 00895 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 00896 * @retval None 00897 */ 00898 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor) 00899 { 00900 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, Resistor); 00901 } 00902 00903 /** 00904 * @brief Get the resistor impedance 00905 * @rmtoll CR4 VBRS LL_PWR_GetBattChargResistor 00906 * @retval Returned value can be one of the following values: 00907 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K 00908 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K 00909 */ 00910 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void) 00911 { 00912 return (uint32_t)(READ_BIT(PWR->CR4, PWR_CR4_VBRS)); 00913 } 00914 00915 /** 00916 * @brief Enable battery charging 00917 * @rmtoll CR4 VBE LL_PWR_EnableBatteryCharging 00918 * @retval None 00919 */ 00920 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void) 00921 { 00922 SET_BIT(PWR->CR4, PWR_CR4_VBE); 00923 } 00924 00925 /** 00926 * @brief Disable battery charging 00927 * @rmtoll CR4 VBE LL_PWR_DisableBatteryCharging 00928 * @retval None 00929 */ 00930 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void) 00931 { 00932 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); 00933 } 00934 00935 /** 00936 * @brief Check if battery charging is enabled 00937 * @rmtoll CR4 VBE LL_PWR_IsEnabledBatteryCharging 00938 * @retval State of bit (1 or 0). 00939 */ 00940 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void) 00941 { 00942 return (READ_BIT(PWR->CR4, PWR_CR4_VBE) == (PWR_CR4_VBE)); 00943 } 00944 00945 /** 00946 * @brief Set the Wake-Up pin polarity low for the event detection 00947 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityLow\n 00948 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityLow\n 00949 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityLow\n 00950 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityLow\n 00951 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityLow 00952 * @param WakeUpPin This parameter can be one of the following values: 00953 * @arg @ref LL_PWR_WAKEUP_PIN1 00954 * @arg @ref LL_PWR_WAKEUP_PIN2 00955 * @arg @ref LL_PWR_WAKEUP_PIN3 00956 * @arg @ref LL_PWR_WAKEUP_PIN4 00957 * @arg @ref LL_PWR_WAKEUP_PIN5 00958 * @retval None 00959 */ 00960 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin) 00961 { 00962 SET_BIT(PWR->CR4, WakeUpPin); 00963 } 00964 00965 /** 00966 * @brief Set the Wake-Up pin polarity high for the event detection 00967 * @rmtoll CR4 WP1 LL_PWR_SetWakeUpPinPolarityHigh\n 00968 * CR4 WP2 LL_PWR_SetWakeUpPinPolarityHigh\n 00969 * CR4 WP3 LL_PWR_SetWakeUpPinPolarityHigh\n 00970 * CR4 WP4 LL_PWR_SetWakeUpPinPolarityHigh\n 00971 * CR4 WP5 LL_PWR_SetWakeUpPinPolarityHigh 00972 * @param WakeUpPin This parameter can be one of the following values: 00973 * @arg @ref LL_PWR_WAKEUP_PIN1 00974 * @arg @ref LL_PWR_WAKEUP_PIN2 00975 * @arg @ref LL_PWR_WAKEUP_PIN3 00976 * @arg @ref LL_PWR_WAKEUP_PIN4 00977 * @arg @ref LL_PWR_WAKEUP_PIN5 00978 * @retval None 00979 */ 00980 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin) 00981 { 00982 CLEAR_BIT(PWR->CR4, WakeUpPin); 00983 } 00984 00985 /** 00986 * @brief Get the Wake-Up pin polarity for the event detection 00987 * @rmtoll CR4 WP1 LL_PWR_IsWakeUpPinPolarityLow\n 00988 * CR4 WP2 LL_PWR_IsWakeUpPinPolarityLow\n 00989 * CR4 WP3 LL_PWR_IsWakeUpPinPolarityLow\n 00990 * CR4 WP4 LL_PWR_IsWakeUpPinPolarityLow\n 00991 * CR4 WP5 LL_PWR_IsWakeUpPinPolarityLow 00992 * @param WakeUpPin This parameter can be one of the following values: 00993 * @arg @ref LL_PWR_WAKEUP_PIN1 00994 * @arg @ref LL_PWR_WAKEUP_PIN2 00995 * @arg @ref LL_PWR_WAKEUP_PIN3 00996 * @arg @ref LL_PWR_WAKEUP_PIN4 00997 * @arg @ref LL_PWR_WAKEUP_PIN5 00998 * @retval State of bit (1 or 0). 00999 */ 01000 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin) 01001 { 01002 return (READ_BIT(PWR->CR4, WakeUpPin) == (WakeUpPin)); 01003 } 01004 01005 /** 01006 * @brief Enable GPIO pull-up state in Standby and Shutdown modes 01007 * @rmtoll PUCRA PU0-15 LL_PWR_EnableGPIOPullUp\n 01008 * PUCRB PU0-15 LL_PWR_EnableGPIOPullUp\n 01009 * PUCRC PU0-15 LL_PWR_EnableGPIOPullUp\n 01010 * PUCRD PU0-15 LL_PWR_EnableGPIOPullUp\n 01011 * PUCRE PU0-15 LL_PWR_EnableGPIOPullUp\n 01012 * PUCRF PU0-15 LL_PWR_EnableGPIOPullUp\n 01013 * PUCRG PU0-15 LL_PWR_EnableGPIOPullUp\n 01014 * PUCRH PU0-15 LL_PWR_EnableGPIOPullUp\n 01015 * PUCRI PU0-11 LL_PWR_EnableGPIOPullUp 01016 * @param GPIO This parameter can be one of the following values: 01017 * @arg @ref LL_PWR_GPIO_A 01018 * @arg @ref LL_PWR_GPIO_B 01019 * @arg @ref LL_PWR_GPIO_C 01020 * @arg @ref LL_PWR_GPIO_D 01021 * @arg @ref LL_PWR_GPIO_E 01022 * @arg @ref LL_PWR_GPIO_F (*) 01023 * @arg @ref LL_PWR_GPIO_G (*) 01024 * @arg @ref LL_PWR_GPIO_H 01025 * @arg @ref LL_PWR_GPIO_I (*) 01026 * 01027 * (*) value not defined in all devices 01028 * @param GPIONumber This parameter can be one of the following values: 01029 * @arg @ref LL_PWR_GPIO_BIT_0 01030 * @arg @ref LL_PWR_GPIO_BIT_1 01031 * @arg @ref LL_PWR_GPIO_BIT_2 01032 * @arg @ref LL_PWR_GPIO_BIT_3 01033 * @arg @ref LL_PWR_GPIO_BIT_4 01034 * @arg @ref LL_PWR_GPIO_BIT_5 01035 * @arg @ref LL_PWR_GPIO_BIT_6 01036 * @arg @ref LL_PWR_GPIO_BIT_7 01037 * @arg @ref LL_PWR_GPIO_BIT_8 01038 * @arg @ref LL_PWR_GPIO_BIT_9 01039 * @arg @ref LL_PWR_GPIO_BIT_10 01040 * @arg @ref LL_PWR_GPIO_BIT_11 01041 * @arg @ref LL_PWR_GPIO_BIT_12 01042 * @arg @ref LL_PWR_GPIO_BIT_13 01043 * @arg @ref LL_PWR_GPIO_BIT_14 01044 * @arg @ref LL_PWR_GPIO_BIT_15 01045 * @retval None 01046 */ 01047 __STATIC_INLINE void LL_PWR_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 01048 { 01049 SET_BIT(*((uint32_t *)GPIO), GPIONumber); 01050 } 01051 01052 /** 01053 * @brief Disable GPIO pull-up state in Standby and Shutdown modes 01054 * @rmtoll PUCRA PU0-15 LL_PWR_DisableGPIOPullUp\n 01055 * PUCRB PU0-15 LL_PWR_DisableGPIOPullUp\n 01056 * PUCRC PU0-15 LL_PWR_DisableGPIOPullUp\n 01057 * PUCRD PU0-15 LL_PWR_DisableGPIOPullUp\n 01058 * PUCRE PU0-15 LL_PWR_DisableGPIOPullUp\n 01059 * PUCRF PU0-15 LL_PWR_DisableGPIOPullUp\n 01060 * PUCRG PU0-15 LL_PWR_DisableGPIOPullUp\n 01061 * PUCRH PU0-15 LL_PWR_DisableGPIOPullUp\n 01062 * PUCRI PU0-11 LL_PWR_DisableGPIOPullUp 01063 * @param GPIO This parameter can be one of the following values: 01064 * @arg @ref LL_PWR_GPIO_A 01065 * @arg @ref LL_PWR_GPIO_B 01066 * @arg @ref LL_PWR_GPIO_C 01067 * @arg @ref LL_PWR_GPIO_D 01068 * @arg @ref LL_PWR_GPIO_E 01069 * @arg @ref LL_PWR_GPIO_F (*) 01070 * @arg @ref LL_PWR_GPIO_G (*) 01071 * @arg @ref LL_PWR_GPIO_H 01072 * @arg @ref LL_PWR_GPIO_I (*) 01073 * 01074 * (*) value not defined in all devices 01075 * @param GPIONumber This parameter can be one of the following values: 01076 * @arg @ref LL_PWR_GPIO_BIT_0 01077 * @arg @ref LL_PWR_GPIO_BIT_1 01078 * @arg @ref LL_PWR_GPIO_BIT_2 01079 * @arg @ref LL_PWR_GPIO_BIT_3 01080 * @arg @ref LL_PWR_GPIO_BIT_4 01081 * @arg @ref LL_PWR_GPIO_BIT_5 01082 * @arg @ref LL_PWR_GPIO_BIT_6 01083 * @arg @ref LL_PWR_GPIO_BIT_7 01084 * @arg @ref LL_PWR_GPIO_BIT_8 01085 * @arg @ref LL_PWR_GPIO_BIT_9 01086 * @arg @ref LL_PWR_GPIO_BIT_10 01087 * @arg @ref LL_PWR_GPIO_BIT_11 01088 * @arg @ref LL_PWR_GPIO_BIT_12 01089 * @arg @ref LL_PWR_GPIO_BIT_13 01090 * @arg @ref LL_PWR_GPIO_BIT_14 01091 * @arg @ref LL_PWR_GPIO_BIT_15 01092 * @retval None 01093 */ 01094 __STATIC_INLINE void LL_PWR_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 01095 { 01096 CLEAR_BIT(*((uint32_t *)GPIO), GPIONumber); 01097 } 01098 01099 /** 01100 * @brief Check if GPIO pull-up state is enabled 01101 * @rmtoll PUCRA PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01102 * PUCRB PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01103 * PUCRC PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01104 * PUCRD PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01105 * PUCRE PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01106 * PUCRF PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01107 * PUCRG PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01108 * PUCRH PU0-15 LL_PWR_IsEnabledGPIOPullUp\n 01109 * PUCRI PU0-11 LL_PWR_IsEnabledGPIOPullUp 01110 * @param GPIO This parameter can be one of the following values: 01111 * @arg @ref LL_PWR_GPIO_A 01112 * @arg @ref LL_PWR_GPIO_B 01113 * @arg @ref LL_PWR_GPIO_C 01114 * @arg @ref LL_PWR_GPIO_D 01115 * @arg @ref LL_PWR_GPIO_E 01116 * @arg @ref LL_PWR_GPIO_F (*) 01117 * @arg @ref LL_PWR_GPIO_G (*) 01118 * @arg @ref LL_PWR_GPIO_H 01119 * @arg @ref LL_PWR_GPIO_I (*) 01120 * 01121 * (*) value not defined in all devices 01122 * @param GPIONumber This parameter can be one of the following values: 01123 * @arg @ref LL_PWR_GPIO_BIT_0 01124 * @arg @ref LL_PWR_GPIO_BIT_1 01125 * @arg @ref LL_PWR_GPIO_BIT_2 01126 * @arg @ref LL_PWR_GPIO_BIT_3 01127 * @arg @ref LL_PWR_GPIO_BIT_4 01128 * @arg @ref LL_PWR_GPIO_BIT_5 01129 * @arg @ref LL_PWR_GPIO_BIT_6 01130 * @arg @ref LL_PWR_GPIO_BIT_7 01131 * @arg @ref LL_PWR_GPIO_BIT_8 01132 * @arg @ref LL_PWR_GPIO_BIT_9 01133 * @arg @ref LL_PWR_GPIO_BIT_10 01134 * @arg @ref LL_PWR_GPIO_BIT_11 01135 * @arg @ref LL_PWR_GPIO_BIT_12 01136 * @arg @ref LL_PWR_GPIO_BIT_13 01137 * @arg @ref LL_PWR_GPIO_BIT_14 01138 * @arg @ref LL_PWR_GPIO_BIT_15 01139 * @retval State of bit (1 or 0). 01140 */ 01141 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 01142 { 01143 return (READ_BIT(*((uint32_t *)(GPIO)), GPIONumber) == (GPIONumber)); 01144 } 01145 01146 /** 01147 * @brief Enable GPIO pull-down state in Standby and Shutdown modes 01148 * @rmtoll PDCRA PD0-15 LL_PWR_EnableGPIOPullDown\n 01149 * PDCRB PD0-15 LL_PWR_EnableGPIOPullDown\n 01150 * PDCRC PD0-15 LL_PWR_EnableGPIOPullDown\n 01151 * PDCRD PD0-15 LL_PWR_EnableGPIOPullDown\n 01152 * PDCRE PD0-15 LL_PWR_EnableGPIOPullDown\n 01153 * PDCRF PD0-15 LL_PWR_EnableGPIOPullDown\n 01154 * PDCRG PD0-15 LL_PWR_EnableGPIOPullDown\n 01155 * PDCRH PD0-15 LL_PWR_EnableGPIOPullDown\n 01156 * PDCRI PD0-11 LL_PWR_EnableGPIOPullDown 01157 * @param GPIO This parameter can be one of the following values: 01158 * @arg @ref LL_PWR_GPIO_A 01159 * @arg @ref LL_PWR_GPIO_B 01160 * @arg @ref LL_PWR_GPIO_C 01161 * @arg @ref LL_PWR_GPIO_D 01162 * @arg @ref LL_PWR_GPIO_E 01163 * @arg @ref LL_PWR_GPIO_F (*) 01164 * @arg @ref LL_PWR_GPIO_G (*) 01165 * @arg @ref LL_PWR_GPIO_H 01166 * @arg @ref LL_PWR_GPIO_I (*) 01167 * 01168 * (*) value not defined in all devices 01169 * @param GPIONumber This parameter can be one of the following values: 01170 * @arg @ref LL_PWR_GPIO_BIT_0 01171 * @arg @ref LL_PWR_GPIO_BIT_1 01172 * @arg @ref LL_PWR_GPIO_BIT_2 01173 * @arg @ref LL_PWR_GPIO_BIT_3 01174 * @arg @ref LL_PWR_GPIO_BIT_4 01175 * @arg @ref LL_PWR_GPIO_BIT_5 01176 * @arg @ref LL_PWR_GPIO_BIT_6 01177 * @arg @ref LL_PWR_GPIO_BIT_7 01178 * @arg @ref LL_PWR_GPIO_BIT_8 01179 * @arg @ref LL_PWR_GPIO_BIT_9 01180 * @arg @ref LL_PWR_GPIO_BIT_10 01181 * @arg @ref LL_PWR_GPIO_BIT_11 01182 * @arg @ref LL_PWR_GPIO_BIT_12 01183 * @arg @ref LL_PWR_GPIO_BIT_13 01184 * @arg @ref LL_PWR_GPIO_BIT_14 01185 * @arg @ref LL_PWR_GPIO_BIT_15 01186 * @retval None 01187 */ 01188 __STATIC_INLINE void LL_PWR_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01189 { 01190 register uint32_t temp = (uint32_t)(GPIO) + 4; 01191 SET_BIT(*((uint32_t *)(temp)), GPIONumber); 01192 } 01193 01194 /** 01195 * @brief Disable GPIO pull-down state in Standby and Shutdown modes 01196 * @rmtoll PDCRA PD0-15 LL_PWR_DisableGPIOPullDown\n 01197 * PDCRB PD0-15 LL_PWR_DisableGPIOPullDown\n 01198 * PDCRC PD0-15 LL_PWR_DisableGPIOPullDown\n 01199 * PDCRD PD0-15 LL_PWR_DisableGPIOPullDown\n 01200 * PDCRE PD0-15 LL_PWR_DisableGPIOPullDown\n 01201 * PDCRF PD0-15 LL_PWR_DisableGPIOPullDown\n 01202 * PDCRG PD0-15 LL_PWR_DisableGPIOPullDown\n 01203 * PDCRH PD0-15 LL_PWR_DisableGPIOPullDown\n 01204 * PDCRI PD0-11 LL_PWR_DisableGPIOPullDown 01205 * @param GPIO This parameter can be one of the following values: 01206 * @arg @ref LL_PWR_GPIO_A 01207 * @arg @ref LL_PWR_GPIO_B 01208 * @arg @ref LL_PWR_GPIO_C 01209 * @arg @ref LL_PWR_GPIO_D 01210 * @arg @ref LL_PWR_GPIO_E 01211 * @arg @ref LL_PWR_GPIO_F (*) 01212 * @arg @ref LL_PWR_GPIO_G (*) 01213 * @arg @ref LL_PWR_GPIO_H 01214 * @arg @ref LL_PWR_GPIO_I (*) 01215 * 01216 * (*) value not defined in all devices 01217 * @param GPIONumber This parameter can be one of the following values: 01218 * @arg @ref LL_PWR_GPIO_BIT_0 01219 * @arg @ref LL_PWR_GPIO_BIT_1 01220 * @arg @ref LL_PWR_GPIO_BIT_2 01221 * @arg @ref LL_PWR_GPIO_BIT_3 01222 * @arg @ref LL_PWR_GPIO_BIT_4 01223 * @arg @ref LL_PWR_GPIO_BIT_5 01224 * @arg @ref LL_PWR_GPIO_BIT_6 01225 * @arg @ref LL_PWR_GPIO_BIT_7 01226 * @arg @ref LL_PWR_GPIO_BIT_8 01227 * @arg @ref LL_PWR_GPIO_BIT_9 01228 * @arg @ref LL_PWR_GPIO_BIT_10 01229 * @arg @ref LL_PWR_GPIO_BIT_11 01230 * @arg @ref LL_PWR_GPIO_BIT_12 01231 * @arg @ref LL_PWR_GPIO_BIT_13 01232 * @arg @ref LL_PWR_GPIO_BIT_14 01233 * @arg @ref LL_PWR_GPIO_BIT_15 01234 * @retval None 01235 */ 01236 __STATIC_INLINE void LL_PWR_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01237 { 01238 register uint32_t temp = (uint32_t)(GPIO) + 4; 01239 CLEAR_BIT(*((uint32_t *)(temp)), GPIONumber); 01240 } 01241 01242 /** 01243 * @brief Check if GPIO pull-down state is enabled 01244 * @rmtoll PDCRA PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01245 * PDCRB PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01246 * PDCRC PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01247 * PDCRD PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01248 * PDCRE PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01249 * PDCRF PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01250 * PDCRG PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01251 * PDCRH PD0-15 LL_PWR_IsEnabledGPIOPullDown\n 01252 * PDCRI PD0-11 LL_PWR_IsEnabledGPIOPullDown 01253 * @param GPIO This parameter can be one of the following values: 01254 * @arg @ref LL_PWR_GPIO_A 01255 * @arg @ref LL_PWR_GPIO_B 01256 * @arg @ref LL_PWR_GPIO_C 01257 * @arg @ref LL_PWR_GPIO_D 01258 * @arg @ref LL_PWR_GPIO_E 01259 * @arg @ref LL_PWR_GPIO_F (*) 01260 * @arg @ref LL_PWR_GPIO_G (*) 01261 * @arg @ref LL_PWR_GPIO_H 01262 * @arg @ref LL_PWR_GPIO_I (*) 01263 * 01264 * (*) value not defined in all devices 01265 * @param GPIONumber This parameter can be one of the following values: 01266 * @arg @ref LL_PWR_GPIO_BIT_0 01267 * @arg @ref LL_PWR_GPIO_BIT_1 01268 * @arg @ref LL_PWR_GPIO_BIT_2 01269 * @arg @ref LL_PWR_GPIO_BIT_3 01270 * @arg @ref LL_PWR_GPIO_BIT_4 01271 * @arg @ref LL_PWR_GPIO_BIT_5 01272 * @arg @ref LL_PWR_GPIO_BIT_6 01273 * @arg @ref LL_PWR_GPIO_BIT_7 01274 * @arg @ref LL_PWR_GPIO_BIT_8 01275 * @arg @ref LL_PWR_GPIO_BIT_9 01276 * @arg @ref LL_PWR_GPIO_BIT_10 01277 * @arg @ref LL_PWR_GPIO_BIT_11 01278 * @arg @ref LL_PWR_GPIO_BIT_12 01279 * @arg @ref LL_PWR_GPIO_BIT_13 01280 * @arg @ref LL_PWR_GPIO_BIT_14 01281 * @arg @ref LL_PWR_GPIO_BIT_15 01282 * @retval State of bit (1 or 0). 01283 */ 01284 __STATIC_INLINE uint32_t LL_PWR_IsEnabledGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 01285 { 01286 register uint32_t temp = (uint32_t)(GPIO) + 4; 01287 return (READ_BIT(*((uint32_t *)(temp)), GPIONumber) == (GPIONumber)); 01288 } 01289 01290 /** 01291 * @} 01292 */ 01293 01294 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management 01295 * @{ 01296 */ 01297 01298 /** 01299 * @brief Get Internal Wake-up line Flag 01300 * @rmtoll SR1 WUFI LL_PWR_IsActiveFlag_InternWU 01301 * @retval State of bit (1 or 0). 01302 */ 01303 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_InternWU(void) 01304 { 01305 return (READ_BIT(PWR->SR1, PWR_SR1_WUFI) == (PWR_SR1_WUFI)); 01306 } 01307 01308 /** 01309 * @brief Get Stand-By Flag 01310 * @rmtoll SR1 SBF LL_PWR_IsActiveFlag_SB 01311 * @retval State of bit (1 or 0). 01312 */ 01313 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void) 01314 { 01315 return (READ_BIT(PWR->SR1, PWR_SR1_SBF) == (PWR_SR1_SBF)); 01316 } 01317 01318 /** 01319 * @brief Get Wake-up Flag 5 01320 * @rmtoll SR1 WUF5 LL_PWR_IsActiveFlag_WU5 01321 * @retval State of bit (1 or 0). 01322 */ 01323 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void) 01324 { 01325 return (READ_BIT(PWR->SR1, PWR_SR1_WUF5) == (PWR_SR1_WUF5)); 01326 } 01327 01328 /** 01329 * @brief Get Wake-up Flag 4 01330 * @rmtoll SR1 WUF4 LL_PWR_IsActiveFlag_WU4 01331 * @retval State of bit (1 or 0). 01332 */ 01333 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void) 01334 { 01335 return (READ_BIT(PWR->SR1, PWR_SR1_WUF4) == (PWR_SR1_WUF4)); 01336 } 01337 01338 /** 01339 * @brief Get Wake-up Flag 3 01340 * @rmtoll SR1 WUF3 LL_PWR_IsActiveFlag_WU3 01341 * @retval State of bit (1 or 0). 01342 */ 01343 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void) 01344 { 01345 return (READ_BIT(PWR->SR1, PWR_SR1_WUF3) == (PWR_SR1_WUF3)); 01346 } 01347 01348 /** 01349 * @brief Get Wake-up Flag 2 01350 * @rmtoll SR1 WUF2 LL_PWR_IsActiveFlag_WU2 01351 * @retval State of bit (1 or 0). 01352 */ 01353 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void) 01354 { 01355 return (READ_BIT(PWR->SR1, PWR_SR1_WUF2) == (PWR_SR1_WUF2)); 01356 } 01357 01358 /** 01359 * @brief Get Wake-up Flag 1 01360 * @rmtoll SR1 WUF1 LL_PWR_IsActiveFlag_WU1 01361 * @retval State of bit (1 or 0). 01362 */ 01363 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void) 01364 { 01365 return (READ_BIT(PWR->SR1, PWR_SR1_WUF1) == (PWR_SR1_WUF1)); 01366 } 01367 01368 /** 01369 * @brief Clear Stand-By Flag 01370 * @rmtoll SCR CSBF LL_PWR_ClearFlag_SB 01371 * @retval None 01372 */ 01373 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void) 01374 { 01375 WRITE_REG(PWR->SCR, PWR_SCR_CSBF); 01376 } 01377 01378 /** 01379 * @brief Clear Wake-up Flags 01380 * @rmtoll SCR CWUF LL_PWR_ClearFlag_WU 01381 * @retval None 01382 */ 01383 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void) 01384 { 01385 WRITE_REG(PWR->SCR, PWR_SCR_CWUF); 01386 } 01387 01388 /** 01389 * @brief Clear Wake-up Flag 5 01390 * @rmtoll SCR CWUF5 LL_PWR_ClearFlag_WU5 01391 * @retval None 01392 */ 01393 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void) 01394 { 01395 WRITE_REG(PWR->SCR, PWR_SCR_CWUF5); 01396 } 01397 01398 /** 01399 * @brief Clear Wake-up Flag 4 01400 * @rmtoll SCR CWUF4 LL_PWR_ClearFlag_WU4 01401 * @retval None 01402 */ 01403 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void) 01404 { 01405 WRITE_REG(PWR->SCR, PWR_SCR_CWUF4); 01406 } 01407 01408 /** 01409 * @brief Clear Wake-up Flag 3 01410 * @rmtoll SCR CWUF3 LL_PWR_ClearFlag_WU3 01411 * @retval None 01412 */ 01413 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void) 01414 { 01415 WRITE_REG(PWR->SCR, PWR_SCR_CWUF3); 01416 } 01417 01418 /** 01419 * @brief Clear Wake-up Flag 2 01420 * @rmtoll SCR CWUF2 LL_PWR_ClearFlag_WU2 01421 * @retval None 01422 */ 01423 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void) 01424 { 01425 WRITE_REG(PWR->SCR, PWR_SCR_CWUF2); 01426 } 01427 01428 /** 01429 * @brief Clear Wake-up Flag 1 01430 * @rmtoll SCR CWUF1 LL_PWR_ClearFlag_WU1 01431 * @retval None 01432 */ 01433 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void) 01434 { 01435 WRITE_REG(PWR->SCR, PWR_SCR_CWUF1); 01436 } 01437 01438 /** 01439 * @brief Indicate whether VDDA voltage is below or above PVM4 threshold 01440 * @rmtoll SR2 PVMO4 LL_PWR_IsActiveFlag_PVMO4 01441 * @retval State of bit (1 or 0). 01442 */ 01443 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO4(void) 01444 { 01445 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO4) == (PWR_SR2_PVMO4)); 01446 } 01447 01448 /** 01449 * @brief Indicate whether VDDA voltage is below or above PVM3 threshold 01450 * @rmtoll SR2 PVMO3 LL_PWR_IsActiveFlag_PVMO3 01451 * @retval State of bit (1 or 0). 01452 */ 01453 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO3(void) 01454 { 01455 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO3) == (PWR_SR2_PVMO3)); 01456 } 01457 01458 #if defined(PWR_SR2_PVMO2) 01459 /** 01460 * @brief Indicate whether VDDIO2 voltage is below or above PVM2 threshold 01461 * @rmtoll SR2 PVMO2 LL_PWR_IsActiveFlag_PVMO2 01462 * @retval State of bit (1 or 0). 01463 */ 01464 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO2(void) 01465 { 01466 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO2) == (PWR_SR2_PVMO2)); 01467 } 01468 #endif /* PWR_SR2_PVMO2 */ 01469 01470 #if defined(PWR_SR2_PVMO1) 01471 /** 01472 * @brief Indicate whether VDDUSB voltage is below or above PVM1 threshold 01473 * @rmtoll SR2 PVMO1 LL_PWR_IsActiveFlag_PVMO1 01474 * @retval State of bit (1 or 0). 01475 */ 01476 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVMO1(void) 01477 { 01478 return (READ_BIT(PWR->SR2, PWR_SR2_PVMO1) == (PWR_SR2_PVMO1)); 01479 } 01480 #endif /* PWR_SR2_PVMO1 */ 01481 01482 /** 01483 * @brief Indicate whether VDD voltage is below or above the selected PVD threshold 01484 * @rmtoll SR2 PVDO LL_PWR_IsActiveFlag_PVDO 01485 * @retval State of bit (1 or 0). 01486 */ 01487 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void) 01488 { 01489 return (READ_BIT(PWR->SR2, PWR_SR2_PVDO) == (PWR_SR2_PVDO)); 01490 } 01491 01492 /** 01493 * @brief Indicate whether the regulator is ready in the selected voltage range or if its output voltage is still changing to the required voltage level 01494 * @rmtoll SR2 VOSF LL_PWR_IsActiveFlag_VOS 01495 * @retval State of bit (1 or 0). 01496 */ 01497 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void) 01498 { 01499 return (READ_BIT(PWR->SR2, PWR_SR2_VOSF) == (PWR_SR2_VOSF)); 01500 } 01501 01502 /** 01503 * @brief Indicate whether the regulator is ready in main mode or is in low-power mode 01504 * @note Take care, return value "0" means the regulator is ready. Return value "1" means the output voltage range is still changing. 01505 * @rmtoll SR2 REGLPF LL_PWR_IsActiveFlag_REGLPF 01506 * @retval State of bit (1 or 0). 01507 */ 01508 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPF(void) 01509 { 01510 return (READ_BIT(PWR->SR2, PWR_SR2_REGLPF) == (PWR_SR2_REGLPF)); 01511 } 01512 01513 /** 01514 * @brief Indicate whether or not the low-power regulator is ready 01515 * @rmtoll SR2 REGLPS LL_PWR_IsActiveFlag_REGLPS 01516 * @retval State of bit (1 or 0). 01517 */ 01518 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_REGLPS(void) 01519 { 01520 return (READ_BIT(PWR->SR2, PWR_SR2_REGLPS) == (PWR_SR2_REGLPS)); 01521 } 01522 01523 /** 01524 * @} 01525 */ 01526 01527 #if defined(USE_FULL_LL_DRIVER) 01528 /** @defgroup PWR_LL_EF_Init De-initialization function 01529 * @{ 01530 */ 01531 ErrorStatus LL_PWR_DeInit(void); 01532 /** 01533 * @} 01534 */ 01535 #endif /* USE_FULL_LL_DRIVER */ 01536 01537 /** @defgroup PWR_LL_EF_Legacy_Functions Legacy functions name 01538 * @{ 01539 */ 01540 /* Old functions name kept for legacy purpose, to be replaced by the */ 01541 /* current functions name. */ 01542 #define LL_PWR_IsActiveFlag_VOSF LL_PWR_IsActiveFlag_VOS 01543 /** 01544 * @} 01545 */ 01546 01547 /** 01548 * @} 01549 */ 01550 01551 /** 01552 * @} 01553 */ 01554 01555 #endif /* defined(PWR) */ 01556 01557 /** 01558 * @} 01559 */ 01560 01561 #ifdef __cplusplus 01562 } 01563 #endif 01564 01565 #endif /* __STM32L4xx_LL_PWR_H */ 01566 01567 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/