STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_lpuart.h 00004 * @author MCD Application Team 00005 * @brief Header file of LPUART LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_LPUART_H 00038 #define __STM32L4xx_LL_LPUART_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (LPUART1) 00052 00053 /** @defgroup LPUART_LL LPUART 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 #if defined(USART_PRESC_PRESCALER) 00060 /** @defgroup LPUART_LL_Private_Variables LPUART Private Variables 00061 * @{ 00062 */ 00063 /* Array used to get the LPUART prescaler division decimal values versus @ref LPUART_LL_EC_PRESCALER values */ 00064 static const uint16_t LPUART_PRESCALER_TAB[] = 00065 { 00066 (uint16_t)1, 00067 (uint16_t)2, 00068 (uint16_t)4, 00069 (uint16_t)6, 00070 (uint16_t)8, 00071 (uint16_t)10, 00072 (uint16_t)12, 00073 (uint16_t)16, 00074 (uint16_t)32, 00075 (uint16_t)64, 00076 (uint16_t)128, 00077 (uint16_t)256 00078 }; 00079 /** 00080 * @} 00081 */ 00082 #endif 00083 00084 /* Private constants ---------------------------------------------------------*/ 00085 /** @defgroup LPUART_LL_Private_Constants LPUART Private Constants 00086 * @{ 00087 */ 00088 /* Defines used in Baud Rate related macros and corresponding register setting computation */ 00089 #define LPUART_LPUARTDIV_FREQ_MUL 256U 00090 #define LPUART_BRR_MASK 0x000FFFFFU 00091 #define LPUART_BRR_MIN_VALUE 0x00000300U 00092 /** 00093 * @} 00094 */ 00095 00096 00097 /* Private macros ------------------------------------------------------------*/ 00098 #if defined(USE_FULL_LL_DRIVER) 00099 /** @defgroup LPUART_LL_Private_Macros LPUART Private Macros 00100 * @{ 00101 */ 00102 /** 00103 * @} 00104 */ 00105 #endif /*USE_FULL_LL_DRIVER*/ 00106 00107 /* Exported types ------------------------------------------------------------*/ 00108 #if defined(USE_FULL_LL_DRIVER) 00109 /** @defgroup LPUART_LL_ES_INIT LPUART Exported Init structures 00110 * @{ 00111 */ 00112 00113 /** 00114 * @brief LL LPUART Init Structure definition 00115 */ 00116 typedef struct 00117 { 00118 #if defined(USART_PRESC_PRESCALER) 00119 uint32_t PrescalerValue; /*!< Specifies the Prescaler to compute the communication baud rate. 00120 This parameter can be a value of @ref LPUART_LL_EC_PRESCALER. 00121 00122 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetPrescaler().*/ 00123 00124 #endif 00125 uint32_t BaudRate; /*!< This field defines expected LPUART communication baud rate. 00126 00127 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetBaudRate().*/ 00128 00129 uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. 00130 This parameter can be a value of @ref LPUART_LL_EC_DATAWIDTH. 00131 00132 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetDataWidth().*/ 00133 00134 uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. 00135 This parameter can be a value of @ref LPUART_LL_EC_STOPBITS. 00136 00137 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetStopBitsLength().*/ 00138 00139 uint32_t Parity; /*!< Specifies the parity mode. 00140 This parameter can be a value of @ref LPUART_LL_EC_PARITY. 00141 00142 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetParity().*/ 00143 00144 uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. 00145 This parameter can be a value of @ref LPUART_LL_EC_DIRECTION. 00146 00147 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetTransferDirection().*/ 00148 00149 uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. 00150 This parameter can be a value of @ref LPUART_LL_EC_HWCONTROL. 00151 00152 This feature can be modified afterwards using unitary function @ref LL_LPUART_SetHWFlowCtrl().*/ 00153 00154 } LL_LPUART_InitTypeDef; 00155 00156 /** 00157 * @} 00158 */ 00159 #endif /* USE_FULL_LL_DRIVER */ 00160 00161 /* Exported constants --------------------------------------------------------*/ 00162 /** @defgroup LPUART_LL_Exported_Constants LPUART Exported Constants 00163 * @{ 00164 */ 00165 00166 /** @defgroup LPUART_LL_EC_CLEAR_FLAG Clear Flags Defines 00167 * @brief Flags defines which can be used with LL_LPUART_WriteReg function 00168 * @{ 00169 */ 00170 #define LL_LPUART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ 00171 #define LL_LPUART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ 00172 #define LL_LPUART_ICR_NCF USART_ICR_NECF /*!< Noise error detected flag */ 00173 #define LL_LPUART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ 00174 #define LL_LPUART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ 00175 #if defined(USART_CR1_FIFOEN) 00176 #define LL_LPUART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ 00177 #endif 00178 #define LL_LPUART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ 00179 #define LL_LPUART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ 00180 #define LL_LPUART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ 00181 #define LL_LPUART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ 00182 /** 00183 * @} 00184 */ 00185 00186 /** @defgroup LPUART_LL_EC_GET_FLAG Get Flags Defines 00187 * @brief Flags defines which can be used with LL_LPUART_ReadReg function 00188 * @{ 00189 */ 00190 #define LL_LPUART_ISR_PE USART_ISR_PE /*!< Parity error flag */ 00191 #define LL_LPUART_ISR_FE USART_ISR_FE /*!< Framing error flag */ 00192 #define LL_LPUART_ISR_NE USART_ISR_NE /*!< Noise detected flag */ 00193 #define LL_LPUART_ISR_ORE USART_ISR_ORE /*!< Overrun error flag */ 00194 #define LL_LPUART_ISR_IDLE USART_ISR_IDLE /*!< Idle line detected flag */ 00195 #if defined(USART_CR1_FIFOEN) 00196 #define LL_LPUART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE /*!< Read data register or RX FIFO not empty flag */ 00197 #else 00198 #define LL_LPUART_ISR_RXNE USART_ISR_RXNE /*!< Read data register not empty flag */ 00199 #endif 00200 #define LL_LPUART_ISR_TC USART_ISR_TC /*!< Transmission complete flag */ 00201 #if defined(USART_CR1_FIFOEN) 00202 #define LL_LPUART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF /*!< Transmit data register empty or TX FIFO Not Full flag*/ 00203 #else 00204 #define LL_LPUART_ISR_TXE USART_ISR_TXE /*!< Transmit data register empty flag */ 00205 #endif 00206 #define LL_LPUART_ISR_CTSIF USART_ISR_CTSIF /*!< CTS interrupt flag */ 00207 #define LL_LPUART_ISR_CTS USART_ISR_CTS /*!< CTS flag */ 00208 #define LL_LPUART_ISR_BUSY USART_ISR_BUSY /*!< Busy flag */ 00209 #define LL_LPUART_ISR_CMF USART_ISR_CMF /*!< Character match flag */ 00210 #define LL_LPUART_ISR_SBKF USART_ISR_SBKF /*!< Send break flag */ 00211 #define LL_LPUART_ISR_RWU USART_ISR_RWU /*!< Receiver wakeup from Mute mode flag */ 00212 #define LL_LPUART_ISR_WUF USART_ISR_WUF /*!< Wakeup from Stop mode flag */ 00213 #define LL_LPUART_ISR_TEACK USART_ISR_TEACK /*!< Transmit enable acknowledge flag */ 00214 #define LL_LPUART_ISR_REACK USART_ISR_REACK /*!< Receive enable acknowledge flag */ 00215 #if defined(USART_CR1_FIFOEN) 00216 #define LL_LPUART_ISR_TXFE USART_ISR_TXFE /*!< TX FIFO empty flag */ 00217 #define LL_LPUART_ISR_RXFF USART_ISR_RXFF /*!< RX FIFO full flag */ 00218 #define LL_LPUART_ISR_RXFT USART_ISR_RXFT /*!< RX FIFO threshold flag */ 00219 #define LL_LPUART_ISR_TXFT USART_ISR_TXFT /*!< TX FIFO threshold flag */ 00220 #endif 00221 /** 00222 * @} 00223 */ 00224 00225 /** @defgroup LPUART_LL_EC_IT IT Defines 00226 * @brief IT defines which can be used with LL_LPUART_ReadReg and LL_LPUART_WriteReg functions 00227 * @{ 00228 */ 00229 #define LL_LPUART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ 00230 #if defined(USART_CR1_FIFOEN) 00231 #define LL_LPUART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE /*!< Read data register and RXFIFO not empty interrupt enable */ 00232 #else 00233 #define LL_LPUART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ 00234 #endif 00235 #define LL_LPUART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ 00236 #if defined(USART_CR1_FIFOEN) 00237 #define LL_LPUART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE /*!< Transmit data register empty and TX FIFO not full interrupt enable */ 00238 #else 00239 #define LL_LPUART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ 00240 #endif 00241 #define LL_LPUART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ 00242 #define LL_LPUART_CR1_CMIE USART_CR1_CMIE /*!< Character match interrupt enable */ 00243 #if defined(USART_CR1_FIFOEN) 00244 #define LL_LPUART_CR1_TXFEIE USART_CR1_TXFEIE /*!< TX FIFO empty interrupt enable */ 00245 #define LL_LPUART_CR1_RXFFIE USART_CR1_RXFFIE /*!< RX FIFO full interrupt enable */ 00246 #endif 00247 #define LL_LPUART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ 00248 #define LL_LPUART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ 00249 #define LL_LPUART_CR3_WUFIE USART_CR3_WUFIE /*!< Wakeup from Stop mode interrupt enable */ 00250 #if defined(USART_CR1_FIFOEN) 00251 #define LL_LPUART_CR3_TXFTIE USART_CR3_TXFTIE /*!< TX FIFO threshold interrupt enable */ 00252 #define LL_LPUART_CR3_RXFTIE USART_CR3_RXFTIE /*!< RX FIFO threshold interrupt enable */ 00253 #endif 00254 /** 00255 * @} 00256 */ 00257 #if defined(USART_CR1_FIFOEN) 00258 00259 /** @defgroup LPUART_LL_EC_FIFOTHRESHOLD FIFO Threshold 00260 * @{ 00261 */ 00262 #define LL_LPUART_FIFOTHRESHOLD_1_8 0x00000000U /*!< FIFO reaches 1/8 of its depth */ 00263 #define LL_LPUART_FIFOTHRESHOLD_1_4 0x00000001U /*!< FIFO reaches 1/4 of its depth */ 00264 #define LL_LPUART_FIFOTHRESHOLD_1_2 0x00000002U /*!< FIFO reaches 1/2 of its depth */ 00265 #define LL_LPUART_FIFOTHRESHOLD_3_4 0x00000003U /*!< FIFO reaches 3/4 of its depth */ 00266 #define LL_LPUART_FIFOTHRESHOLD_7_8 0x00000004U /*!< FIFO reaches 7/8 of its depth */ 00267 #define LL_LPUART_FIFOTHRESHOLD_8_8 0x00000005U /*!< FIFO becomes empty for TX and full for RX */ 00268 /** 00269 * @} 00270 */ 00271 #endif 00272 00273 /** @defgroup LPUART_LL_EC_DIRECTION Direction 00274 * @{ 00275 */ 00276 #define LL_LPUART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ 00277 #define LL_LPUART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ 00278 #define LL_LPUART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ 00279 #define LL_LPUART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ 00280 /** 00281 * @} 00282 */ 00283 00284 /** @defgroup LPUART_LL_EC_PARITY Parity Control 00285 * @{ 00286 */ 00287 #define LL_LPUART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ 00288 #define LL_LPUART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ 00289 #define LL_LPUART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ 00290 /** 00291 * @} 00292 */ 00293 00294 /** @defgroup LPUART_LL_EC_WAKEUP Wakeup 00295 * @{ 00296 */ 00297 #define LL_LPUART_WAKEUP_IDLELINE 0x00000000U /*!< LPUART wake up from Mute mode on Idle Line */ 00298 #define LL_LPUART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< LPUART wake up from Mute mode on Address Mark */ 00299 /** 00300 * @} 00301 */ 00302 00303 /** @defgroup LPUART_LL_EC_DATAWIDTH Datawidth 00304 * @{ 00305 */ 00306 #define LL_LPUART_DATAWIDTH_7B USART_CR1_M1 /*!< 7 bits word length : Start bit, 7 data bits, n stop bits */ 00307 #define LL_LPUART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ 00308 #define LL_LPUART_DATAWIDTH_9B USART_CR1_M0 /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ 00309 /** 00310 * @} 00311 */ 00312 #if defined(USART_PRESC_PRESCALER) 00313 00314 /** @defgroup LPUART_LL_EC_PRESCALER Clock Source Prescaler 00315 * @{ 00316 */ 00317 #define LL_LPUART_PRESCALER_DIV1 0x00000000U /*!< Input clock not devided */ 00318 #define LL_LPUART_PRESCALER_DIV2 (USART_PRESC_PRESCALER_0) /*!< Input clock devided by 2 */ 00319 #define LL_LPUART_PRESCALER_DIV4 (USART_PRESC_PRESCALER_1) /*!< Input clock devided by 4 */ 00320 #define LL_LPUART_PRESCALER_DIV6 (USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 6 */ 00321 #define LL_LPUART_PRESCALER_DIV8 (USART_PRESC_PRESCALER_2) /*!< Input clock devided by 8 */ 00322 #define LL_LPUART_PRESCALER_DIV10 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 10 */ 00323 #define LL_LPUART_PRESCALER_DIV12 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 12 */ 00324 #define LL_LPUART_PRESCALER_DIV16 (USART_PRESC_PRESCALER_2 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 16 */ 00325 #define LL_LPUART_PRESCALER_DIV32 (USART_PRESC_PRESCALER_3) /*!< Input clock devided by 32 */ 00326 #define LL_LPUART_PRESCALER_DIV64 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 64 */ 00327 #define LL_LPUART_PRESCALER_DIV128 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1) /*!< Input clock devided by 128 */ 00328 #define LL_LPUART_PRESCALER_DIV256 (USART_PRESC_PRESCALER_3 | USART_PRESC_PRESCALER_1 | USART_PRESC_PRESCALER_0) /*!< Input clock devided by 256 */ 00329 /** 00330 * @} 00331 */ 00332 #endif 00333 00334 /** @defgroup LPUART_LL_EC_STOPBITS Stop Bits 00335 * @{ 00336 */ 00337 #define LL_LPUART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ 00338 #define LL_LPUART_STOPBITS_2 USART_CR2_STOP_1 /*!< 2 stop bits */ 00339 /** 00340 * @} 00341 */ 00342 00343 /** @defgroup LPUART_LL_EC_TXRX TX RX Pins Swap 00344 * @{ 00345 */ 00346 #define LL_LPUART_TXRX_STANDARD 0x00000000U /*!< TX/RX pins are used as defined in standard pinout */ 00347 #define LL_LPUART_TXRX_SWAPPED (USART_CR2_SWAP) /*!< TX and RX pins functions are swapped. */ 00348 /** 00349 * @} 00350 */ 00351 00352 /** @defgroup LPUART_LL_EC_RXPIN_LEVEL RX Pin Active Level Inversion 00353 * @{ 00354 */ 00355 #define LL_LPUART_RXPIN_LEVEL_STANDARD 0x00000000U /*!< RX pin signal works using the standard logic levels */ 00356 #define LL_LPUART_RXPIN_LEVEL_INVERTED (USART_CR2_RXINV) /*!< RX pin signal values are inverted. */ 00357 /** 00358 * @} 00359 */ 00360 00361 /** @defgroup LPUART_LL_EC_TXPIN_LEVEL TX Pin Active Level Inversion 00362 * @{ 00363 */ 00364 #define LL_LPUART_TXPIN_LEVEL_STANDARD 0x00000000U /*!< TX pin signal works using the standard logic levels */ 00365 #define LL_LPUART_TXPIN_LEVEL_INVERTED (USART_CR2_TXINV) /*!< TX pin signal values are inverted. */ 00366 /** 00367 * @} 00368 */ 00369 00370 /** @defgroup LPUART_LL_EC_BINARY_LOGIC Binary Data Inversion 00371 * @{ 00372 */ 00373 #define LL_LPUART_BINARY_LOGIC_POSITIVE 0x00000000U /*!< Logical data from the data register are send/received in positive/direct logic. (1=H, 0=L) */ 00374 #define LL_LPUART_BINARY_LOGIC_NEGATIVE USART_CR2_DATAINV /*!< Logical data from the data register are send/received in negative/inverse logic. (1=L, 0=H). The parity bit is also inverted. */ 00375 /** 00376 * @} 00377 */ 00378 00379 /** @defgroup LPUART_LL_EC_BITORDER Bit Order 00380 * @{ 00381 */ 00382 #define LL_LPUART_BITORDER_LSBFIRST 0x00000000U /*!< data is transmitted/received with data bit 0 first, following the start bit */ 00383 #define LL_LPUART_BITORDER_MSBFIRST USART_CR2_MSBFIRST /*!< data is transmitted/received with the MSB first, following the start bit */ 00384 /** 00385 * @} 00386 */ 00387 00388 /** @defgroup LPUART_LL_EC_ADDRESS_DETECT Address Length Detection 00389 * @{ 00390 */ 00391 #define LL_LPUART_ADDRESS_DETECT_4B 0x00000000U /*!< 4-bit address detection method selected */ 00392 #define LL_LPUART_ADDRESS_DETECT_7B USART_CR2_ADDM7 /*!< 7-bit address detection (in 8-bit data mode) method selected */ 00393 /** 00394 * @} 00395 */ 00396 00397 /** @defgroup LPUART_LL_EC_HWCONTROL Hardware Control 00398 * @{ 00399 */ 00400 #define LL_LPUART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ 00401 #define LL_LPUART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ 00402 #define LL_LPUART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ 00403 #define LL_LPUART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ 00404 /** 00405 * @} 00406 */ 00407 00408 /** @defgroup LPUART_LL_EC_WAKEUP_ON Wakeup Activation 00409 * @{ 00410 */ 00411 #define LL_LPUART_WAKEUP_ON_ADDRESS 0x00000000U /*!< Wake up active on address match */ 00412 #define LL_LPUART_WAKEUP_ON_STARTBIT USART_CR3_WUS_1 /*!< Wake up active on Start bit detection */ 00413 #define LL_LPUART_WAKEUP_ON_RXNE (USART_CR3_WUS_0 | USART_CR3_WUS_1) /*!< Wake up active on RXNE */ 00414 /** 00415 * @} 00416 */ 00417 00418 /** @defgroup LPUART_LL_EC_DE_POLARITY Driver Enable Polarity 00419 * @{ 00420 */ 00421 #define LL_LPUART_DE_POLARITY_HIGH 0x00000000U /*!< DE signal is active high */ 00422 #define LL_LPUART_DE_POLARITY_LOW USART_CR3_DEP /*!< DE signal is active low */ 00423 /** 00424 * @} 00425 */ 00426 00427 /** @defgroup LPUART_LL_EC_DMA_REG_DATA DMA Register Data 00428 * @{ 00429 */ 00430 #define LL_LPUART_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */ 00431 #define LL_LPUART_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */ 00432 /** 00433 * @} 00434 */ 00435 00436 /** 00437 * @} 00438 */ 00439 00440 /* Exported macro ------------------------------------------------------------*/ 00441 /** @defgroup LPUART_LL_Exported_Macros LPUART Exported Macros 00442 * @{ 00443 */ 00444 00445 /** @defgroup LPUART_LL_EM_WRITE_READ Common Write and read registers Macros 00446 * @{ 00447 */ 00448 00449 /** 00450 * @brief Write a value in LPUART register 00451 * @param __INSTANCE__ LPUART Instance 00452 * @param __REG__ Register to be written 00453 * @param __VALUE__ Value to be written in the register 00454 * @retval None 00455 */ 00456 #define LL_LPUART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00457 00458 /** 00459 * @brief Read a value in LPUART register 00460 * @param __INSTANCE__ LPUART Instance 00461 * @param __REG__ Register to be read 00462 * @retval Register value 00463 */ 00464 #define LL_LPUART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00465 /** 00466 * @} 00467 */ 00468 00469 /** @defgroup LPUART_LL_EM_Exported_Macros_Helper Helper Macros 00470 * @{ 00471 */ 00472 00473 /** 00474 * @brief Compute LPUARTDIV value according to Peripheral Clock and 00475 * expected Baud Rate (20-bit value of LPUARTDIV is returned) 00476 * @param __PERIPHCLK__ Peripheral Clock frequency used for LPUART Instance 00477 @if USART_PRESC_PRESCALER 00478 * @param __PRESCALER__ This parameter can be one of the following values: 00479 * @arg @ref LL_LPUART_PRESCALER_DIV1 00480 * @arg @ref LL_LPUART_PRESCALER_DIV2 00481 * @arg @ref LL_LPUART_PRESCALER_DIV4 00482 * @arg @ref LL_LPUART_PRESCALER_DIV6 00483 * @arg @ref LL_LPUART_PRESCALER_DIV8 00484 * @arg @ref LL_LPUART_PRESCALER_DIV10 00485 * @arg @ref LL_LPUART_PRESCALER_DIV12 00486 * @arg @ref LL_LPUART_PRESCALER_DIV16 00487 * @arg @ref LL_LPUART_PRESCALER_DIV32 00488 * @arg @ref LL_LPUART_PRESCALER_DIV64 00489 * @arg @ref LL_LPUART_PRESCALER_DIV128 00490 * @arg @ref LL_LPUART_PRESCALER_DIV256 00491 @endif 00492 * @param __BAUDRATE__ Baud Rate value to achieve 00493 * @retval LPUARTDIV value to be used for BRR register filling 00494 */ 00495 #if defined(USART_PRESC_PRESCALER) 00496 #define __LL_LPUART_DIV(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((((uint64_t)(__PERIPHCLK__)/(uint64_t)(LPUART_PRESCALER_TAB[(__PRESCALER__)]))*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) 00497 #else 00498 #define __LL_LPUART_DIV(__PERIPHCLK__, __BAUDRATE__) (((((uint64_t)(__PERIPHCLK__)*LPUART_LPUARTDIV_FREQ_MUL) + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) & LPUART_BRR_MASK) 00499 #endif 00500 00501 /** 00502 * @} 00503 */ 00504 00505 /** 00506 * @} 00507 */ 00508 00509 /* Exported functions --------------------------------------------------------*/ 00510 /** @defgroup LPUART_LL_Exported_Functions LPUART Exported Functions 00511 * @{ 00512 */ 00513 00514 /** @defgroup LPUART_LL_EF_Configuration Configuration functions 00515 * @{ 00516 */ 00517 00518 /** 00519 * @brief LPUART Enable 00520 * @rmtoll CR1 UE LL_LPUART_Enable 00521 * @param LPUARTx LPUART Instance 00522 * @retval None 00523 */ 00524 __STATIC_INLINE void LL_LPUART_Enable(USART_TypeDef *LPUARTx) 00525 { 00526 SET_BIT(LPUARTx->CR1, USART_CR1_UE); 00527 } 00528 00529 /** 00530 * @brief LPUART Disable 00531 * @note When LPUART is disabled, LPUART prescalers and outputs are stopped immediately, 00532 * and current operations are discarded. The configuration of the LPUART is kept, but all the status 00533 * flags, in the LPUARTx_ISR are set to their default values. 00534 * @note In order to go into low-power mode without generating errors on the line, 00535 * the TE bit must be reset before and the software must wait 00536 * for the TC bit in the LPUART_ISR to be set before resetting the UE bit. 00537 * The DMA requests are also reset when UE = 0 so the DMA channel must 00538 * be disabled before resetting the UE bit. 00539 * @rmtoll CR1 UE LL_LPUART_Disable 00540 * @param LPUARTx LPUART Instance 00541 * @retval None 00542 */ 00543 __STATIC_INLINE void LL_LPUART_Disable(USART_TypeDef *LPUARTx) 00544 { 00545 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UE); 00546 } 00547 00548 /** 00549 * @brief Indicate if LPUART is enabled 00550 * @rmtoll CR1 UE LL_LPUART_IsEnabled 00551 * @param LPUARTx LPUART Instance 00552 * @retval State of bit (1 or 0). 00553 */ 00554 __STATIC_INLINE uint32_t LL_LPUART_IsEnabled(USART_TypeDef *LPUARTx) 00555 { 00556 return (READ_BIT(LPUARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); 00557 } 00558 00559 #if defined(USART_CR1_FIFOEN) 00560 /** 00561 * @brief FIFO Mode Enable 00562 * @rmtoll CR1 FIFOEN LL_LPUART_EnableFIFO 00563 * @param LPUARTx LPUART Instance 00564 * @retval None 00565 */ 00566 __STATIC_INLINE void LL_LPUART_EnableFIFO(USART_TypeDef *LPUARTx) 00567 { 00568 SET_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); 00569 } 00570 00571 /** 00572 * @brief FIFO Mode Disable 00573 * @rmtoll CR1 FIFOEN LL_LPUART_DisableFIFO 00574 * @param LPUARTx LPUART Instance 00575 * @retval None 00576 */ 00577 __STATIC_INLINE void LL_LPUART_DisableFIFO(USART_TypeDef *LPUARTx) 00578 { 00579 CLEAR_BIT(LPUARTx->CR1, USART_CR1_FIFOEN); 00580 } 00581 00582 /** 00583 * @brief Indicate if FIFO Mode is enabled 00584 * @rmtoll CR1 FIFOEN LL_LPUART_IsEnabledFIFO 00585 * @param LPUARTx LPUART Instance 00586 * @retval State of bit (1 or 0). 00587 */ 00588 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledFIFO(USART_TypeDef *LPUARTx) 00589 { 00590 return (READ_BIT(LPUARTx->CR1, USART_CR1_FIFOEN) == (USART_CR1_FIFOEN)); 00591 } 00592 00593 /** 00594 * @brief Configure TX FIFO Threshold 00595 * @rmtoll CR3 TXFTCFG LL_LPUART_SetTXFIFOThreshold 00596 * @param LPUARTx LPUART Instance 00597 * @param Threshold This parameter can be one of the following values: 00598 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 00599 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 00600 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 00601 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 00602 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 00603 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 00604 * @retval None 00605 */ 00606 __STATIC_INLINE void LL_LPUART_SetTXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) 00607 { 00608 MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG, Threshold << USART_CR3_TXFTCFG_Pos); 00609 } 00610 00611 /** 00612 * @brief Return TX FIFO Threshold Configuration 00613 * @rmtoll CR3 TXFTCFG LL_LPUART_GetTXFIFOThreshold 00614 * @param LPUARTx LPUART Instance 00615 * @retval Returned value can be one of the following values: 00616 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 00617 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 00618 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 00619 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 00620 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 00621 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 00622 */ 00623 __STATIC_INLINE uint32_t LL_LPUART_GetTXFIFOThreshold(USART_TypeDef *LPUARTx) 00624 { 00625 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_TXFTCFG) >> USART_CR3_TXFTCFG_Pos); 00626 } 00627 00628 /** 00629 * @brief Configure RX FIFO Threshold 00630 * @rmtoll CR3 RXFTCFG LL_LPUART_SetRXFIFOThreshold 00631 * @param LPUARTx LPUART Instance 00632 * @param Threshold This parameter can be one of the following values: 00633 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 00634 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 00635 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 00636 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 00637 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 00638 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 00639 * @retval None 00640 */ 00641 __STATIC_INLINE void LL_LPUART_SetRXFIFOThreshold(USART_TypeDef *LPUARTx, uint32_t Threshold) 00642 { 00643 MODIFY_REG(LPUARTx->CR3, USART_CR3_RXFTCFG, Threshold << USART_CR3_RXFTCFG_Pos); 00644 } 00645 00646 /** 00647 * @brief Return RX FIFO Threshold Configuration 00648 * @rmtoll CR3 RXFTCFG LL_LPUART_GetRXFIFOThreshold 00649 * @param LPUARTx LPUART Instance 00650 * @retval Returned value can be one of the following values: 00651 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 00652 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 00653 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 00654 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 00655 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 00656 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 00657 */ 00658 __STATIC_INLINE uint32_t LL_LPUART_GetRXFIFOThreshold(USART_TypeDef *LPUARTx) 00659 { 00660 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RXFTCFG) >> USART_CR3_RXFTCFG_Pos); 00661 } 00662 00663 /** 00664 * @brief Configure TX and RX FIFOs Threshold 00665 * @rmtoll CR3 TXFTCFG LL_LPUART_ConfigFIFOsThreshold\n 00666 * CR3 RXFTCFG LL_LPUART_ConfigFIFOsThreshold 00667 * @param LPUARTx LPUART Instance 00668 * @param TXThreshold This parameter can be one of the following values: 00669 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 00670 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 00671 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 00672 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 00673 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 00674 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 00675 * @param RXThreshold This parameter can be one of the following values: 00676 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_8 00677 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_4 00678 * @arg @ref LL_LPUART_FIFOTHRESHOLD_1_2 00679 * @arg @ref LL_LPUART_FIFOTHRESHOLD_3_4 00680 * @arg @ref LL_LPUART_FIFOTHRESHOLD_7_8 00681 * @arg @ref LL_LPUART_FIFOTHRESHOLD_8_8 00682 * @retval None 00683 */ 00684 __STATIC_INLINE void LL_LPUART_ConfigFIFOsThreshold(USART_TypeDef *LPUARTx, uint32_t TXThreshold, uint32_t RXThreshold) 00685 { 00686 MODIFY_REG(LPUARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, TXThreshold << USART_CR3_TXFTCFG_Pos | RXThreshold << USART_CR3_RXFTCFG_Pos); 00687 } 00688 #endif 00689 00690 /** 00691 * @brief LPUART enabled in STOP Mode 00692 * @note When this function is enabled, LPUART is able to wake up the MCU from Stop mode, provided that 00693 * LPUART clock selection is HSI or LSE in RCC. 00694 * @rmtoll CR1 UESM LL_LPUART_EnableInStopMode 00695 * @param LPUARTx LPUART Instance 00696 * @retval None 00697 */ 00698 __STATIC_INLINE void LL_LPUART_EnableInStopMode(USART_TypeDef *LPUARTx) 00699 { 00700 SET_BIT(LPUARTx->CR1, USART_CR1_UESM); 00701 } 00702 00703 /** 00704 * @brief LPUART disabled in STOP Mode 00705 * @note When this function is disabled, LPUART is not able to wake up the MCU from Stop mode 00706 * @rmtoll CR1 UESM LL_LPUART_DisableInStopMode 00707 * @param LPUARTx LPUART Instance 00708 * @retval None 00709 */ 00710 __STATIC_INLINE void LL_LPUART_DisableInStopMode(USART_TypeDef *LPUARTx) 00711 { 00712 CLEAR_BIT(LPUARTx->CR1, USART_CR1_UESM); 00713 } 00714 00715 /** 00716 * @brief Indicate if LPUART is enabled in STOP Mode 00717 * (able to wake up MCU from Stop mode or not) 00718 * @rmtoll CR1 UESM LL_LPUART_IsEnabledInStopMode 00719 * @param LPUARTx LPUART Instance 00720 * @retval State of bit (1 or 0). 00721 */ 00722 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledInStopMode(USART_TypeDef *LPUARTx) 00723 { 00724 return (READ_BIT(LPUARTx->CR1, USART_CR1_UESM) == (USART_CR1_UESM)); 00725 } 00726 00727 #if defined(USART_CR3_UCESM) 00728 /** 00729 * @brief LPUART Clock enabled in STOP Mode 00730 * @note When this function is called, LPUART Clock is enabled while in STOP mode 00731 * @rmtoll CR3 UCESM LL_LPUART_EnableClockInStopMode 00732 * @param LPUARTx LPUART Instance 00733 * @retval None 00734 */ 00735 __STATIC_INLINE void LL_LPUART_EnableClockInStopMode(USART_TypeDef *LPUARTx) 00736 { 00737 SET_BIT(LPUARTx->CR3, USART_CR3_UCESM); 00738 } 00739 00740 /** 00741 * @brief LPUART clock disabled in STOP Mode 00742 * @note When this function is called, LPUART Clock is disabled while in STOP mode 00743 * @rmtoll CR3 UCESM LL_LPUART_DisableClockInStopMode 00744 * @param LPUARTx LPUART Instance 00745 * @retval None 00746 */ 00747 __STATIC_INLINE void LL_LPUART_DisableClockInStopMode(USART_TypeDef *LPUARTx) 00748 { 00749 CLEAR_BIT(LPUARTx->CR3, USART_CR3_UCESM); 00750 } 00751 00752 /** 00753 * @brief Indicate if LPUART clock is enabled in STOP Mode 00754 * @rmtoll CR3 UCESM LL_LPUART_IsClockEnabledInStopMode 00755 * @param LPUARTx LPUART Instance 00756 * @retval State of bit (1 or 0). 00757 */ 00758 __STATIC_INLINE uint32_t LL_LPUART_IsClockEnabledInStopMode(USART_TypeDef *LPUARTx) 00759 { 00760 return (READ_BIT(LPUARTx->CR3, USART_CR3_UCESM) == (USART_CR3_UCESM)); 00761 } 00762 00763 #endif /* USART_CR3_UCESM */ 00764 /** 00765 * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) 00766 * @rmtoll CR1 RE LL_LPUART_EnableDirectionRx 00767 * @param LPUARTx LPUART Instance 00768 * @retval None 00769 */ 00770 __STATIC_INLINE void LL_LPUART_EnableDirectionRx(USART_TypeDef *LPUARTx) 00771 { 00772 SET_BIT(LPUARTx->CR1, USART_CR1_RE); 00773 } 00774 00775 /** 00776 * @brief Receiver Disable 00777 * @rmtoll CR1 RE LL_LPUART_DisableDirectionRx 00778 * @param LPUARTx LPUART Instance 00779 * @retval None 00780 */ 00781 __STATIC_INLINE void LL_LPUART_DisableDirectionRx(USART_TypeDef *LPUARTx) 00782 { 00783 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RE); 00784 } 00785 00786 /** 00787 * @brief Transmitter Enable 00788 * @rmtoll CR1 TE LL_LPUART_EnableDirectionTx 00789 * @param LPUARTx LPUART Instance 00790 * @retval None 00791 */ 00792 __STATIC_INLINE void LL_LPUART_EnableDirectionTx(USART_TypeDef *LPUARTx) 00793 { 00794 SET_BIT(LPUARTx->CR1, USART_CR1_TE); 00795 } 00796 00797 /** 00798 * @brief Transmitter Disable 00799 * @rmtoll CR1 TE LL_LPUART_DisableDirectionTx 00800 * @param LPUARTx LPUART Instance 00801 * @retval None 00802 */ 00803 __STATIC_INLINE void LL_LPUART_DisableDirectionTx(USART_TypeDef *LPUARTx) 00804 { 00805 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TE); 00806 } 00807 00808 /** 00809 * @brief Configure simultaneously enabled/disabled states 00810 * of Transmitter and Receiver 00811 * @rmtoll CR1 RE LL_LPUART_SetTransferDirection\n 00812 * CR1 TE LL_LPUART_SetTransferDirection 00813 * @param LPUARTx LPUART Instance 00814 * @param TransferDirection This parameter can be one of the following values: 00815 * @arg @ref LL_LPUART_DIRECTION_NONE 00816 * @arg @ref LL_LPUART_DIRECTION_RX 00817 * @arg @ref LL_LPUART_DIRECTION_TX 00818 * @arg @ref LL_LPUART_DIRECTION_TX_RX 00819 * @retval None 00820 */ 00821 __STATIC_INLINE void LL_LPUART_SetTransferDirection(USART_TypeDef *LPUARTx, uint32_t TransferDirection) 00822 { 00823 MODIFY_REG(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); 00824 } 00825 00826 /** 00827 * @brief Return enabled/disabled states of Transmitter and Receiver 00828 * @rmtoll CR1 RE LL_LPUART_GetTransferDirection\n 00829 * CR1 TE LL_LPUART_GetTransferDirection 00830 * @param LPUARTx LPUART Instance 00831 * @retval Returned value can be one of the following values: 00832 * @arg @ref LL_LPUART_DIRECTION_NONE 00833 * @arg @ref LL_LPUART_DIRECTION_RX 00834 * @arg @ref LL_LPUART_DIRECTION_TX 00835 * @arg @ref LL_LPUART_DIRECTION_TX_RX 00836 */ 00837 __STATIC_INLINE uint32_t LL_LPUART_GetTransferDirection(USART_TypeDef *LPUARTx) 00838 { 00839 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_RE | USART_CR1_TE)); 00840 } 00841 00842 /** 00843 * @brief Configure Parity (enabled/disabled and parity mode if enabled) 00844 * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. 00845 * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position 00846 * (depending on data width) and parity is checked on the received data. 00847 * @rmtoll CR1 PS LL_LPUART_SetParity\n 00848 * CR1 PCE LL_LPUART_SetParity 00849 * @param LPUARTx LPUART Instance 00850 * @param Parity This parameter can be one of the following values: 00851 * @arg @ref LL_LPUART_PARITY_NONE 00852 * @arg @ref LL_LPUART_PARITY_EVEN 00853 * @arg @ref LL_LPUART_PARITY_ODD 00854 * @retval None 00855 */ 00856 __STATIC_INLINE void LL_LPUART_SetParity(USART_TypeDef *LPUARTx, uint32_t Parity) 00857 { 00858 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); 00859 } 00860 00861 /** 00862 * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) 00863 * @rmtoll CR1 PS LL_LPUART_GetParity\n 00864 * CR1 PCE LL_LPUART_GetParity 00865 * @param LPUARTx LPUART Instance 00866 * @retval Returned value can be one of the following values: 00867 * @arg @ref LL_LPUART_PARITY_NONE 00868 * @arg @ref LL_LPUART_PARITY_EVEN 00869 * @arg @ref LL_LPUART_PARITY_ODD 00870 */ 00871 __STATIC_INLINE uint32_t LL_LPUART_GetParity(USART_TypeDef *LPUARTx) 00872 { 00873 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); 00874 } 00875 00876 /** 00877 * @brief Set Receiver Wake Up method from Mute mode. 00878 * @rmtoll CR1 WAKE LL_LPUART_SetWakeUpMethod 00879 * @param LPUARTx LPUART Instance 00880 * @param Method This parameter can be one of the following values: 00881 * @arg @ref LL_LPUART_WAKEUP_IDLELINE 00882 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK 00883 * @retval None 00884 */ 00885 __STATIC_INLINE void LL_LPUART_SetWakeUpMethod(USART_TypeDef *LPUARTx, uint32_t Method) 00886 { 00887 MODIFY_REG(LPUARTx->CR1, USART_CR1_WAKE, Method); 00888 } 00889 00890 /** 00891 * @brief Return Receiver Wake Up method from Mute mode 00892 * @rmtoll CR1 WAKE LL_LPUART_GetWakeUpMethod 00893 * @param LPUARTx LPUART Instance 00894 * @retval Returned value can be one of the following values: 00895 * @arg @ref LL_LPUART_WAKEUP_IDLELINE 00896 * @arg @ref LL_LPUART_WAKEUP_ADDRESSMARK 00897 */ 00898 __STATIC_INLINE uint32_t LL_LPUART_GetWakeUpMethod(USART_TypeDef *LPUARTx) 00899 { 00900 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_WAKE)); 00901 } 00902 00903 /** 00904 * @brief Set Word length (nb of data bits, excluding start and stop bits) 00905 * @rmtoll CR1 M LL_LPUART_SetDataWidth 00906 * @param LPUARTx LPUART Instance 00907 * @param DataWidth This parameter can be one of the following values: 00908 * @arg @ref LL_LPUART_DATAWIDTH_7B 00909 * @arg @ref LL_LPUART_DATAWIDTH_8B 00910 * @arg @ref LL_LPUART_DATAWIDTH_9B 00911 * @retval None 00912 */ 00913 __STATIC_INLINE void LL_LPUART_SetDataWidth(USART_TypeDef *LPUARTx, uint32_t DataWidth) 00914 { 00915 MODIFY_REG(LPUARTx->CR1, USART_CR1_M, DataWidth); 00916 } 00917 00918 /** 00919 * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) 00920 * @rmtoll CR1 M LL_LPUART_GetDataWidth 00921 * @param LPUARTx LPUART Instance 00922 * @retval Returned value can be one of the following values: 00923 * @arg @ref LL_LPUART_DATAWIDTH_7B 00924 * @arg @ref LL_LPUART_DATAWIDTH_8B 00925 * @arg @ref LL_LPUART_DATAWIDTH_9B 00926 */ 00927 __STATIC_INLINE uint32_t LL_LPUART_GetDataWidth(USART_TypeDef *LPUARTx) 00928 { 00929 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_M)); 00930 } 00931 00932 /** 00933 * @brief Allow switch between Mute Mode and Active mode 00934 * @rmtoll CR1 MME LL_LPUART_EnableMuteMode 00935 * @param LPUARTx LPUART Instance 00936 * @retval None 00937 */ 00938 __STATIC_INLINE void LL_LPUART_EnableMuteMode(USART_TypeDef *LPUARTx) 00939 { 00940 SET_BIT(LPUARTx->CR1, USART_CR1_MME); 00941 } 00942 00943 /** 00944 * @brief Prevent Mute Mode use. Set Receiver in active mode permanently. 00945 * @rmtoll CR1 MME LL_LPUART_DisableMuteMode 00946 * @param LPUARTx LPUART Instance 00947 * @retval None 00948 */ 00949 __STATIC_INLINE void LL_LPUART_DisableMuteMode(USART_TypeDef *LPUARTx) 00950 { 00951 CLEAR_BIT(LPUARTx->CR1, USART_CR1_MME); 00952 } 00953 00954 /** 00955 * @brief Indicate if switch between Mute Mode and Active mode is allowed 00956 * @rmtoll CR1 MME LL_LPUART_IsEnabledMuteMode 00957 * @param LPUARTx LPUART Instance 00958 * @retval State of bit (1 or 0). 00959 */ 00960 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledMuteMode(USART_TypeDef *LPUARTx) 00961 { 00962 return (READ_BIT(LPUARTx->CR1, USART_CR1_MME) == (USART_CR1_MME)); 00963 } 00964 00965 #if defined(USART_PRESC_PRESCALER) 00966 /** 00967 * @brief Configure Clock source prescaler for baudrate generator and oversampling 00968 * @rmtoll PRESC PRESCALER LL_LPUART_SetPrescaler 00969 * @param LPUARTx LPUART Instance 00970 * @param PrescalerValue This parameter can be one of the following values: 00971 * @arg @ref LL_LPUART_PRESCALER_DIV1 00972 * @arg @ref LL_LPUART_PRESCALER_DIV2 00973 * @arg @ref LL_LPUART_PRESCALER_DIV4 00974 * @arg @ref LL_LPUART_PRESCALER_DIV6 00975 * @arg @ref LL_LPUART_PRESCALER_DIV8 00976 * @arg @ref LL_LPUART_PRESCALER_DIV10 00977 * @arg @ref LL_LPUART_PRESCALER_DIV12 00978 * @arg @ref LL_LPUART_PRESCALER_DIV16 00979 * @arg @ref LL_LPUART_PRESCALER_DIV32 00980 * @arg @ref LL_LPUART_PRESCALER_DIV64 00981 * @arg @ref LL_LPUART_PRESCALER_DIV128 00982 * @arg @ref LL_LPUART_PRESCALER_DIV256 00983 * @retval None 00984 */ 00985 __STATIC_INLINE void LL_LPUART_SetPrescaler(USART_TypeDef *LPUARTx, uint32_t PrescalerValue) 00986 { 00987 MODIFY_REG(LPUARTx->PRESC, USART_PRESC_PRESCALER, (uint16_t)PrescalerValue); 00988 } 00989 00990 /** 00991 * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling 00992 * @rmtoll PRESC PRESCALER LL_LPUART_GetPrescaler 00993 * @param LPUARTx LPUART Instance 00994 * @retval Returned value can be one of the following values: 00995 * @arg @ref LL_LPUART_PRESCALER_DIV1 00996 * @arg @ref LL_LPUART_PRESCALER_DIV2 00997 * @arg @ref LL_LPUART_PRESCALER_DIV4 00998 * @arg @ref LL_LPUART_PRESCALER_DIV6 00999 * @arg @ref LL_LPUART_PRESCALER_DIV8 01000 * @arg @ref LL_LPUART_PRESCALER_DIV10 01001 * @arg @ref LL_LPUART_PRESCALER_DIV12 01002 * @arg @ref LL_LPUART_PRESCALER_DIV16 01003 * @arg @ref LL_LPUART_PRESCALER_DIV32 01004 * @arg @ref LL_LPUART_PRESCALER_DIV64 01005 * @arg @ref LL_LPUART_PRESCALER_DIV128 01006 * @arg @ref LL_LPUART_PRESCALER_DIV256 01007 */ 01008 __STATIC_INLINE uint32_t LL_LPUART_GetPrescaler(USART_TypeDef *LPUARTx) 01009 { 01010 return (uint32_t)(READ_BIT(LPUARTx->PRESC, USART_PRESC_PRESCALER)); 01011 } 01012 #endif 01013 01014 /** 01015 * @brief Set the length of the stop bits 01016 * @rmtoll CR2 STOP LL_LPUART_SetStopBitsLength 01017 * @param LPUARTx LPUART Instance 01018 * @param StopBits This parameter can be one of the following values: 01019 * @arg @ref LL_LPUART_STOPBITS_1 01020 * @arg @ref LL_LPUART_STOPBITS_2 01021 * @retval None 01022 */ 01023 __STATIC_INLINE void LL_LPUART_SetStopBitsLength(USART_TypeDef *LPUARTx, uint32_t StopBits) 01024 { 01025 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); 01026 } 01027 01028 /** 01029 * @brief Retrieve the length of the stop bits 01030 * @rmtoll CR2 STOP LL_LPUART_GetStopBitsLength 01031 * @param LPUARTx LPUART Instance 01032 * @retval Returned value can be one of the following values: 01033 * @arg @ref LL_LPUART_STOPBITS_1 01034 * @arg @ref LL_LPUART_STOPBITS_2 01035 */ 01036 __STATIC_INLINE uint32_t LL_LPUART_GetStopBitsLength(USART_TypeDef *LPUARTx) 01037 { 01038 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_STOP)); 01039 } 01040 01041 /** 01042 * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) 01043 * @note Call of this function is equivalent to following function call sequence : 01044 * - Data Width configuration using @ref LL_LPUART_SetDataWidth() function 01045 * - Parity Control and mode configuration using @ref LL_LPUART_SetParity() function 01046 * - Stop bits configuration using @ref LL_LPUART_SetStopBitsLength() function 01047 * @rmtoll CR1 PS LL_LPUART_ConfigCharacter\n 01048 * CR1 PCE LL_LPUART_ConfigCharacter\n 01049 * CR1 M LL_LPUART_ConfigCharacter\n 01050 * CR2 STOP LL_LPUART_ConfigCharacter 01051 * @param LPUARTx LPUART Instance 01052 * @param DataWidth This parameter can be one of the following values: 01053 * @arg @ref LL_LPUART_DATAWIDTH_7B 01054 * @arg @ref LL_LPUART_DATAWIDTH_8B 01055 * @arg @ref LL_LPUART_DATAWIDTH_9B 01056 * @param Parity This parameter can be one of the following values: 01057 * @arg @ref LL_LPUART_PARITY_NONE 01058 * @arg @ref LL_LPUART_PARITY_EVEN 01059 * @arg @ref LL_LPUART_PARITY_ODD 01060 * @param StopBits This parameter can be one of the following values: 01061 * @arg @ref LL_LPUART_STOPBITS_1 01062 * @arg @ref LL_LPUART_STOPBITS_2 01063 * @retval None 01064 */ 01065 __STATIC_INLINE void LL_LPUART_ConfigCharacter(USART_TypeDef *LPUARTx, uint32_t DataWidth, uint32_t Parity, 01066 uint32_t StopBits) 01067 { 01068 MODIFY_REG(LPUARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); 01069 MODIFY_REG(LPUARTx->CR2, USART_CR2_STOP, StopBits); 01070 } 01071 01072 /** 01073 * @brief Configure TX/RX pins swapping setting. 01074 * @rmtoll CR2 SWAP LL_LPUART_SetTXRXSwap 01075 * @param LPUARTx LPUART Instance 01076 * @param SwapConfig This parameter can be one of the following values: 01077 * @arg @ref LL_LPUART_TXRX_STANDARD 01078 * @arg @ref LL_LPUART_TXRX_SWAPPED 01079 * @retval None 01080 */ 01081 __STATIC_INLINE void LL_LPUART_SetTXRXSwap(USART_TypeDef *LPUARTx, uint32_t SwapConfig) 01082 { 01083 MODIFY_REG(LPUARTx->CR2, USART_CR2_SWAP, SwapConfig); 01084 } 01085 01086 /** 01087 * @brief Retrieve TX/RX pins swapping configuration. 01088 * @rmtoll CR2 SWAP LL_LPUART_GetTXRXSwap 01089 * @param LPUARTx LPUART Instance 01090 * @retval Returned value can be one of the following values: 01091 * @arg @ref LL_LPUART_TXRX_STANDARD 01092 * @arg @ref LL_LPUART_TXRX_SWAPPED 01093 */ 01094 __STATIC_INLINE uint32_t LL_LPUART_GetTXRXSwap(USART_TypeDef *LPUARTx) 01095 { 01096 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_SWAP)); 01097 } 01098 01099 /** 01100 * @brief Configure RX pin active level logic 01101 * @rmtoll CR2 RXINV LL_LPUART_SetRXPinLevel 01102 * @param LPUARTx LPUART Instance 01103 * @param PinInvMethod This parameter can be one of the following values: 01104 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD 01105 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED 01106 * @retval None 01107 */ 01108 __STATIC_INLINE void LL_LPUART_SetRXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) 01109 { 01110 MODIFY_REG(LPUARTx->CR2, USART_CR2_RXINV, PinInvMethod); 01111 } 01112 01113 /** 01114 * @brief Retrieve RX pin active level logic configuration 01115 * @rmtoll CR2 RXINV LL_LPUART_GetRXPinLevel 01116 * @param LPUARTx LPUART Instance 01117 * @retval Returned value can be one of the following values: 01118 * @arg @ref LL_LPUART_RXPIN_LEVEL_STANDARD 01119 * @arg @ref LL_LPUART_RXPIN_LEVEL_INVERTED 01120 */ 01121 __STATIC_INLINE uint32_t LL_LPUART_GetRXPinLevel(USART_TypeDef *LPUARTx) 01122 { 01123 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_RXINV)); 01124 } 01125 01126 /** 01127 * @brief Configure TX pin active level logic 01128 * @rmtoll CR2 TXINV LL_LPUART_SetTXPinLevel 01129 * @param LPUARTx LPUART Instance 01130 * @param PinInvMethod This parameter can be one of the following values: 01131 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD 01132 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED 01133 * @retval None 01134 */ 01135 __STATIC_INLINE void LL_LPUART_SetTXPinLevel(USART_TypeDef *LPUARTx, uint32_t PinInvMethod) 01136 { 01137 MODIFY_REG(LPUARTx->CR2, USART_CR2_TXINV, PinInvMethod); 01138 } 01139 01140 /** 01141 * @brief Retrieve TX pin active level logic configuration 01142 * @rmtoll CR2 TXINV LL_LPUART_GetTXPinLevel 01143 * @param LPUARTx LPUART Instance 01144 * @retval Returned value can be one of the following values: 01145 * @arg @ref LL_LPUART_TXPIN_LEVEL_STANDARD 01146 * @arg @ref LL_LPUART_TXPIN_LEVEL_INVERTED 01147 */ 01148 __STATIC_INLINE uint32_t LL_LPUART_GetTXPinLevel(USART_TypeDef *LPUARTx) 01149 { 01150 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_TXINV)); 01151 } 01152 01153 /** 01154 * @brief Configure Binary data logic. 01155 * 01156 * @note Allow to define how Logical data from the data register are send/received : 01157 * either in positive/direct logic (1=H, 0=L) or in negative/inverse logic (1=L, 0=H) 01158 * @rmtoll CR2 DATAINV LL_LPUART_SetBinaryDataLogic 01159 * @param LPUARTx LPUART Instance 01160 * @param DataLogic This parameter can be one of the following values: 01161 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE 01162 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE 01163 * @retval None 01164 */ 01165 __STATIC_INLINE void LL_LPUART_SetBinaryDataLogic(USART_TypeDef *LPUARTx, uint32_t DataLogic) 01166 { 01167 MODIFY_REG(LPUARTx->CR2, USART_CR2_DATAINV, DataLogic); 01168 } 01169 01170 /** 01171 * @brief Retrieve Binary data configuration 01172 * @rmtoll CR2 DATAINV LL_LPUART_GetBinaryDataLogic 01173 * @param LPUARTx LPUART Instance 01174 * @retval Returned value can be one of the following values: 01175 * @arg @ref LL_LPUART_BINARY_LOGIC_POSITIVE 01176 * @arg @ref LL_LPUART_BINARY_LOGIC_NEGATIVE 01177 */ 01178 __STATIC_INLINE uint32_t LL_LPUART_GetBinaryDataLogic(USART_TypeDef *LPUARTx) 01179 { 01180 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_DATAINV)); 01181 } 01182 01183 /** 01184 * @brief Configure transfer bit order (either Less or Most Significant Bit First) 01185 * @note MSB First means data is transmitted/received with the MSB first, following the start bit. 01186 * LSB First means data is transmitted/received with data bit 0 first, following the start bit. 01187 * @rmtoll CR2 MSBFIRST LL_LPUART_SetTransferBitOrder 01188 * @param LPUARTx LPUART Instance 01189 * @param BitOrder This parameter can be one of the following values: 01190 * @arg @ref LL_LPUART_BITORDER_LSBFIRST 01191 * @arg @ref LL_LPUART_BITORDER_MSBFIRST 01192 * @retval None 01193 */ 01194 __STATIC_INLINE void LL_LPUART_SetTransferBitOrder(USART_TypeDef *LPUARTx, uint32_t BitOrder) 01195 { 01196 MODIFY_REG(LPUARTx->CR2, USART_CR2_MSBFIRST, BitOrder); 01197 } 01198 01199 /** 01200 * @brief Return transfer bit order (either Less or Most Significant Bit First) 01201 * @note MSB First means data is transmitted/received with the MSB first, following the start bit. 01202 * LSB First means data is transmitted/received with data bit 0 first, following the start bit. 01203 * @rmtoll CR2 MSBFIRST LL_LPUART_GetTransferBitOrder 01204 * @param LPUARTx LPUART Instance 01205 * @retval Returned value can be one of the following values: 01206 * @arg @ref LL_LPUART_BITORDER_LSBFIRST 01207 * @arg @ref LL_LPUART_BITORDER_MSBFIRST 01208 */ 01209 __STATIC_INLINE uint32_t LL_LPUART_GetTransferBitOrder(USART_TypeDef *LPUARTx) 01210 { 01211 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_MSBFIRST)); 01212 } 01213 01214 /** 01215 * @brief Set Address of the LPUART node. 01216 * @note This is used in multiprocessor communication during Mute mode or Stop mode, 01217 * for wake up with address mark detection. 01218 * @note 4bits address node is used when 4-bit Address Detection is selected in ADDM7. 01219 * (b7-b4 should be set to 0) 01220 * 8bits address node is used when 7-bit Address Detection is selected in ADDM7. 01221 * (This is used in multiprocessor communication during Mute mode or Stop mode, 01222 * for wake up with 7-bit address mark detection. 01223 * The MSB of the character sent by the transmitter should be equal to 1. 01224 * It may also be used for character detection during normal reception, 01225 * Mute mode inactive (for example, end of block detection in ModBus protocol). 01226 * In this case, the whole received character (8-bit) is compared to the ADD[7:0] 01227 * value and CMF flag is set on match) 01228 * @rmtoll CR2 ADD LL_LPUART_ConfigNodeAddress\n 01229 * CR2 ADDM7 LL_LPUART_ConfigNodeAddress 01230 * @param LPUARTx LPUART Instance 01231 * @param AddressLen This parameter can be one of the following values: 01232 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B 01233 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B 01234 * @param NodeAddress 4 or 7 bit Address of the LPUART node. 01235 * @retval None 01236 */ 01237 __STATIC_INLINE void LL_LPUART_ConfigNodeAddress(USART_TypeDef *LPUARTx, uint32_t AddressLen, uint32_t NodeAddress) 01238 { 01239 MODIFY_REG(LPUARTx->CR2, USART_CR2_ADD | USART_CR2_ADDM7, 01240 (uint32_t)(AddressLen | (NodeAddress << USART_CR2_ADD_Pos))); 01241 } 01242 01243 /** 01244 * @brief Return 8 bit Address of the LPUART node as set in ADD field of CR2. 01245 * @note If 4-bit Address Detection is selected in ADDM7, 01246 * only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) 01247 * If 7-bit Address Detection is selected in ADDM7, 01248 * only 8bits (b7-b0) of returned value are relevant (b31-b8 are not relevant) 01249 * @rmtoll CR2 ADD LL_LPUART_GetNodeAddress 01250 * @param LPUARTx LPUART Instance 01251 * @retval Address of the LPUART node (Value between Min_Data=0 and Max_Data=255) 01252 */ 01253 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddress(USART_TypeDef *LPUARTx) 01254 { 01255 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADD) >> USART_CR2_ADD_Pos); 01256 } 01257 01258 /** 01259 * @brief Return Length of Node Address used in Address Detection mode (7-bit or 4-bit) 01260 * @rmtoll CR2 ADDM7 LL_LPUART_GetNodeAddressLen 01261 * @param LPUARTx LPUART Instance 01262 * @retval Returned value can be one of the following values: 01263 * @arg @ref LL_LPUART_ADDRESS_DETECT_4B 01264 * @arg @ref LL_LPUART_ADDRESS_DETECT_7B 01265 */ 01266 __STATIC_INLINE uint32_t LL_LPUART_GetNodeAddressLen(USART_TypeDef *LPUARTx) 01267 { 01268 return (uint32_t)(READ_BIT(LPUARTx->CR2, USART_CR2_ADDM7)); 01269 } 01270 01271 /** 01272 * @brief Enable RTS HW Flow Control 01273 * @rmtoll CR3 RTSE LL_LPUART_EnableRTSHWFlowCtrl 01274 * @param LPUARTx LPUART Instance 01275 * @retval None 01276 */ 01277 __STATIC_INLINE void LL_LPUART_EnableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) 01278 { 01279 SET_BIT(LPUARTx->CR3, USART_CR3_RTSE); 01280 } 01281 01282 /** 01283 * @brief Disable RTS HW Flow Control 01284 * @rmtoll CR3 RTSE LL_LPUART_DisableRTSHWFlowCtrl 01285 * @param LPUARTx LPUART Instance 01286 * @retval None 01287 */ 01288 __STATIC_INLINE void LL_LPUART_DisableRTSHWFlowCtrl(USART_TypeDef *LPUARTx) 01289 { 01290 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RTSE); 01291 } 01292 01293 /** 01294 * @brief Enable CTS HW Flow Control 01295 * @rmtoll CR3 CTSE LL_LPUART_EnableCTSHWFlowCtrl 01296 * @param LPUARTx LPUART Instance 01297 * @retval None 01298 */ 01299 __STATIC_INLINE void LL_LPUART_EnableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) 01300 { 01301 SET_BIT(LPUARTx->CR3, USART_CR3_CTSE); 01302 } 01303 01304 /** 01305 * @brief Disable CTS HW Flow Control 01306 * @rmtoll CR3 CTSE LL_LPUART_DisableCTSHWFlowCtrl 01307 * @param LPUARTx LPUART Instance 01308 * @retval None 01309 */ 01310 __STATIC_INLINE void LL_LPUART_DisableCTSHWFlowCtrl(USART_TypeDef *LPUARTx) 01311 { 01312 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSE); 01313 } 01314 01315 /** 01316 * @brief Configure HW Flow Control mode (both CTS and RTS) 01317 * @rmtoll CR3 RTSE LL_LPUART_SetHWFlowCtrl\n 01318 * CR3 CTSE LL_LPUART_SetHWFlowCtrl 01319 * @param LPUARTx LPUART Instance 01320 * @param HardwareFlowControl This parameter can be one of the following values: 01321 * @arg @ref LL_LPUART_HWCONTROL_NONE 01322 * @arg @ref LL_LPUART_HWCONTROL_RTS 01323 * @arg @ref LL_LPUART_HWCONTROL_CTS 01324 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS 01325 * @retval None 01326 */ 01327 __STATIC_INLINE void LL_LPUART_SetHWFlowCtrl(USART_TypeDef *LPUARTx, uint32_t HardwareFlowControl) 01328 { 01329 MODIFY_REG(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); 01330 } 01331 01332 /** 01333 * @brief Return HW Flow Control configuration (both CTS and RTS) 01334 * @rmtoll CR3 RTSE LL_LPUART_GetHWFlowCtrl\n 01335 * CR3 CTSE LL_LPUART_GetHWFlowCtrl 01336 * @param LPUARTx LPUART Instance 01337 * @retval Returned value can be one of the following values: 01338 * @arg @ref LL_LPUART_HWCONTROL_NONE 01339 * @arg @ref LL_LPUART_HWCONTROL_RTS 01340 * @arg @ref LL_LPUART_HWCONTROL_CTS 01341 * @arg @ref LL_LPUART_HWCONTROL_RTS_CTS 01342 */ 01343 __STATIC_INLINE uint32_t LL_LPUART_GetHWFlowCtrl(USART_TypeDef *LPUARTx) 01344 { 01345 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); 01346 } 01347 01348 /** 01349 * @brief Enable Overrun detection 01350 * @rmtoll CR3 OVRDIS LL_LPUART_EnableOverrunDetect 01351 * @param LPUARTx LPUART Instance 01352 * @retval None 01353 */ 01354 __STATIC_INLINE void LL_LPUART_EnableOverrunDetect(USART_TypeDef *LPUARTx) 01355 { 01356 CLEAR_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); 01357 } 01358 01359 /** 01360 * @brief Disable Overrun detection 01361 * @rmtoll CR3 OVRDIS LL_LPUART_DisableOverrunDetect 01362 * @param LPUARTx LPUART Instance 01363 * @retval None 01364 */ 01365 __STATIC_INLINE void LL_LPUART_DisableOverrunDetect(USART_TypeDef *LPUARTx) 01366 { 01367 SET_BIT(LPUARTx->CR3, USART_CR3_OVRDIS); 01368 } 01369 01370 /** 01371 * @brief Indicate if Overrun detection is enabled 01372 * @rmtoll CR3 OVRDIS LL_LPUART_IsEnabledOverrunDetect 01373 * @param LPUARTx LPUART Instance 01374 * @retval State of bit (1 or 0). 01375 */ 01376 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledOverrunDetect(USART_TypeDef *LPUARTx) 01377 { 01378 return (READ_BIT(LPUARTx->CR3, USART_CR3_OVRDIS) != USART_CR3_OVRDIS); 01379 } 01380 01381 /** 01382 * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) 01383 * @rmtoll CR3 WUS LL_LPUART_SetWKUPType 01384 * @param LPUARTx LPUART Instance 01385 * @param Type This parameter can be one of the following values: 01386 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS 01387 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT 01388 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE 01389 * @retval None 01390 */ 01391 __STATIC_INLINE void LL_LPUART_SetWKUPType(USART_TypeDef *LPUARTx, uint32_t Type) 01392 { 01393 MODIFY_REG(LPUARTx->CR3, USART_CR3_WUS, Type); 01394 } 01395 01396 /** 01397 * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) 01398 * @rmtoll CR3 WUS LL_LPUART_GetWKUPType 01399 * @param LPUARTx LPUART Instance 01400 * @retval Returned value can be one of the following values: 01401 * @arg @ref LL_LPUART_WAKEUP_ON_ADDRESS 01402 * @arg @ref LL_LPUART_WAKEUP_ON_STARTBIT 01403 * @arg @ref LL_LPUART_WAKEUP_ON_RXNE 01404 */ 01405 __STATIC_INLINE uint32_t LL_LPUART_GetWKUPType(USART_TypeDef *LPUARTx) 01406 { 01407 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_WUS)); 01408 } 01409 01410 /** 01411 * @brief Configure LPUART BRR register for achieving expected Baud Rate value. 01412 * 01413 * @note Compute and set LPUARTDIV value in BRR Register (full BRR content) 01414 * according to used Peripheral Clock and expected Baud Rate values 01415 * @note Peripheral clock and Baud Rate values provided as function parameters should be valid 01416 * (Baud rate value != 0). 01417 * @note Provided that LPUARTx_BRR must be > = 0x300 and LPUART_BRR is 20-bit, 01418 * a care should be taken when generating high baud rates using high PeriphClk 01419 * values. PeriphClk must be in the range [3 x BaudRate, 4096 x BaudRate]. 01420 * @rmtoll BRR BRR LL_LPUART_SetBaudRate 01421 * @param LPUARTx LPUART Instance 01422 * @param PeriphClk Peripheral Clock 01423 @if USART_PRESC_PRESCALER 01424 * @param PrescalerValue This parameter can be one of the following values: 01425 * @arg @ref LL_LPUART_PRESCALER_DIV1 01426 * @arg @ref LL_LPUART_PRESCALER_DIV2 01427 * @arg @ref LL_LPUART_PRESCALER_DIV4 01428 * @arg @ref LL_LPUART_PRESCALER_DIV6 01429 * @arg @ref LL_LPUART_PRESCALER_DIV8 01430 * @arg @ref LL_LPUART_PRESCALER_DIV10 01431 * @arg @ref LL_LPUART_PRESCALER_DIV12 01432 * @arg @ref LL_LPUART_PRESCALER_DIV16 01433 * @arg @ref LL_LPUART_PRESCALER_DIV32 01434 * @arg @ref LL_LPUART_PRESCALER_DIV64 01435 * @arg @ref LL_LPUART_PRESCALER_DIV128 01436 * @arg @ref LL_LPUART_PRESCALER_DIV256 01437 @endif 01438 * @param BaudRate Baud Rate 01439 * @retval None 01440 */ 01441 #if defined(USART_PRESC_PRESCALER) 01442 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue, uint32_t BaudRate) 01443 #else 01444 __STATIC_INLINE void LL_LPUART_SetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t BaudRate) 01445 #endif 01446 { 01447 #if defined(USART_PRESC_PRESCALER) 01448 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, (uint16_t)PrescalerValue, BaudRate); 01449 #else 01450 LPUARTx->BRR = __LL_LPUART_DIV(PeriphClk, BaudRate); 01451 #endif 01452 } 01453 01454 /** 01455 * @brief Return current Baud Rate value, according to LPUARTDIV present in BRR register 01456 * (full BRR content), and to used Peripheral Clock values 01457 * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. 01458 * @rmtoll BRR BRR LL_LPUART_GetBaudRate 01459 * @param LPUARTx LPUART Instance 01460 * @param PeriphClk Peripheral Clock 01461 @if USART_PRESC_PRESCALER 01462 * @param PrescalerValue This parameter can be one of the following values: 01463 * @arg @ref LL_LPUART_PRESCALER_DIV1 01464 * @arg @ref LL_LPUART_PRESCALER_DIV2 01465 * @arg @ref LL_LPUART_PRESCALER_DIV4 01466 * @arg @ref LL_LPUART_PRESCALER_DIV6 01467 * @arg @ref LL_LPUART_PRESCALER_DIV8 01468 * @arg @ref LL_LPUART_PRESCALER_DIV10 01469 * @arg @ref LL_LPUART_PRESCALER_DIV12 01470 * @arg @ref LL_LPUART_PRESCALER_DIV16 01471 * @arg @ref LL_LPUART_PRESCALER_DIV32 01472 * @arg @ref LL_LPUART_PRESCALER_DIV64 01473 * @arg @ref LL_LPUART_PRESCALER_DIV128 01474 * @arg @ref LL_LPUART_PRESCALER_DIV256 01475 @endif 01476 * @retval Baud Rate 01477 */ 01478 #if defined(USART_PRESC_PRESCALER) 01479 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk, uint32_t PrescalerValue) 01480 #else 01481 __STATIC_INLINE uint32_t LL_LPUART_GetBaudRate(USART_TypeDef *LPUARTx, uint32_t PeriphClk) 01482 #endif 01483 { 01484 register uint32_t lpuartdiv = 0x0U; 01485 register uint32_t brrresult = 0x0U; 01486 #if defined(USART_PRESC_PRESCALER) 01487 register uint32_t periphclkpresc = (uint32_t)(PeriphClk / (LPUART_PRESCALER_TAB[(uint16_t)PrescalerValue])); 01488 #endif 01489 01490 lpuartdiv = LPUARTx->BRR & LPUART_BRR_MASK; 01491 01492 if (lpuartdiv >= LPUART_BRR_MIN_VALUE) 01493 { 01494 #if defined(USART_PRESC_PRESCALER) 01495 brrresult = (uint32_t)(((uint64_t)(periphclkpresc) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); 01496 #else 01497 brrresult = (uint32_t)(((uint64_t)(PeriphClk) * LPUART_LPUARTDIV_FREQ_MUL) / lpuartdiv); 01498 #endif 01499 } 01500 01501 return (brrresult); 01502 } 01503 01504 /** 01505 * @} 01506 */ 01507 01508 /** @defgroup LPUART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature 01509 * @{ 01510 */ 01511 01512 /** 01513 * @brief Enable Single Wire Half-Duplex mode 01514 * @rmtoll CR3 HDSEL LL_LPUART_EnableHalfDuplex 01515 * @param LPUARTx LPUART Instance 01516 * @retval None 01517 */ 01518 __STATIC_INLINE void LL_LPUART_EnableHalfDuplex(USART_TypeDef *LPUARTx) 01519 { 01520 SET_BIT(LPUARTx->CR3, USART_CR3_HDSEL); 01521 } 01522 01523 /** 01524 * @brief Disable Single Wire Half-Duplex mode 01525 * @rmtoll CR3 HDSEL LL_LPUART_DisableHalfDuplex 01526 * @param LPUARTx LPUART Instance 01527 * @retval None 01528 */ 01529 __STATIC_INLINE void LL_LPUART_DisableHalfDuplex(USART_TypeDef *LPUARTx) 01530 { 01531 CLEAR_BIT(LPUARTx->CR3, USART_CR3_HDSEL); 01532 } 01533 01534 /** 01535 * @brief Indicate if Single Wire Half-Duplex mode is enabled 01536 * @rmtoll CR3 HDSEL LL_LPUART_IsEnabledHalfDuplex 01537 * @param LPUARTx LPUART Instance 01538 * @retval State of bit (1 or 0). 01539 */ 01540 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledHalfDuplex(USART_TypeDef *LPUARTx) 01541 { 01542 return (READ_BIT(LPUARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); 01543 } 01544 01545 /** 01546 * @} 01547 */ 01548 01549 /** @defgroup LPUART_LL_EF_Configuration_DE Configuration functions related to Driver Enable feature 01550 * @{ 01551 */ 01552 01553 /** 01554 * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). 01555 * @rmtoll CR1 DEDT LL_LPUART_SetDEDeassertionTime 01556 * @param LPUARTx LPUART Instance 01557 * @param Time Value between Min_Data=0 and Max_Data=31 01558 * @retval None 01559 */ 01560 __STATIC_INLINE void LL_LPUART_SetDEDeassertionTime(USART_TypeDef *LPUARTx, uint32_t Time) 01561 { 01562 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEDT, Time << USART_CR1_DEDT_Pos); 01563 } 01564 01565 /** 01566 * @brief Return DEDT (Driver Enable De-Assertion Time) 01567 * @rmtoll CR1 DEDT LL_LPUART_GetDEDeassertionTime 01568 * @param LPUARTx LPUART Instance 01569 * @retval Time value expressed on 5 bits ([4:0] bits) : c 01570 */ 01571 __STATIC_INLINE uint32_t LL_LPUART_GetDEDeassertionTime(USART_TypeDef *LPUARTx) 01572 { 01573 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEDT) >> USART_CR1_DEDT_Pos); 01574 } 01575 01576 /** 01577 * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). 01578 * @rmtoll CR1 DEAT LL_LPUART_SetDEAssertionTime 01579 * @param LPUARTx LPUART Instance 01580 * @param Time Value between Min_Data=0 and Max_Data=31 01581 * @retval None 01582 */ 01583 __STATIC_INLINE void LL_LPUART_SetDEAssertionTime(USART_TypeDef *LPUARTx, uint32_t Time) 01584 { 01585 MODIFY_REG(LPUARTx->CR1, USART_CR1_DEAT, Time << USART_CR1_DEAT_Pos); 01586 } 01587 01588 /** 01589 * @brief Return DEAT (Driver Enable Assertion Time) 01590 * @rmtoll CR1 DEAT LL_LPUART_GetDEAssertionTime 01591 * @param LPUARTx LPUART Instance 01592 * @retval Time value expressed on 5 bits ([4:0] bits) : Time Value between Min_Data=0 and Max_Data=31 01593 */ 01594 __STATIC_INLINE uint32_t LL_LPUART_GetDEAssertionTime(USART_TypeDef *LPUARTx) 01595 { 01596 return (uint32_t)(READ_BIT(LPUARTx->CR1, USART_CR1_DEAT) >> USART_CR1_DEAT_Pos); 01597 } 01598 01599 /** 01600 * @brief Enable Driver Enable (DE) Mode 01601 * @rmtoll CR3 DEM LL_LPUART_EnableDEMode 01602 * @param LPUARTx LPUART Instance 01603 * @retval None 01604 */ 01605 __STATIC_INLINE void LL_LPUART_EnableDEMode(USART_TypeDef *LPUARTx) 01606 { 01607 SET_BIT(LPUARTx->CR3, USART_CR3_DEM); 01608 } 01609 01610 /** 01611 * @brief Disable Driver Enable (DE) Mode 01612 * @rmtoll CR3 DEM LL_LPUART_DisableDEMode 01613 * @param LPUARTx LPUART Instance 01614 * @retval None 01615 */ 01616 __STATIC_INLINE void LL_LPUART_DisableDEMode(USART_TypeDef *LPUARTx) 01617 { 01618 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DEM); 01619 } 01620 01621 /** 01622 * @brief Indicate if Driver Enable (DE) Mode is enabled 01623 * @rmtoll CR3 DEM LL_LPUART_IsEnabledDEMode 01624 * @param LPUARTx LPUART Instance 01625 * @retval State of bit (1 or 0). 01626 */ 01627 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDEMode(USART_TypeDef *LPUARTx) 01628 { 01629 return (READ_BIT(LPUARTx->CR3, USART_CR3_DEM) == (USART_CR3_DEM)); 01630 } 01631 01632 /** 01633 * @brief Select Driver Enable Polarity 01634 * @rmtoll CR3 DEP LL_LPUART_SetDESignalPolarity 01635 * @param LPUARTx LPUART Instance 01636 * @param Polarity This parameter can be one of the following values: 01637 * @arg @ref LL_LPUART_DE_POLARITY_HIGH 01638 * @arg @ref LL_LPUART_DE_POLARITY_LOW 01639 * @retval None 01640 */ 01641 __STATIC_INLINE void LL_LPUART_SetDESignalPolarity(USART_TypeDef *LPUARTx, uint32_t Polarity) 01642 { 01643 MODIFY_REG(LPUARTx->CR3, USART_CR3_DEP, Polarity); 01644 } 01645 01646 /** 01647 * @brief Return Driver Enable Polarity 01648 * @rmtoll CR3 DEP LL_LPUART_GetDESignalPolarity 01649 * @param LPUARTx LPUART Instance 01650 * @retval Returned value can be one of the following values: 01651 * @arg @ref LL_LPUART_DE_POLARITY_HIGH 01652 * @arg @ref LL_LPUART_DE_POLARITY_LOW 01653 */ 01654 __STATIC_INLINE uint32_t LL_LPUART_GetDESignalPolarity(USART_TypeDef *LPUARTx) 01655 { 01656 return (uint32_t)(READ_BIT(LPUARTx->CR3, USART_CR3_DEP)); 01657 } 01658 01659 /** 01660 * @} 01661 */ 01662 01663 /** @defgroup LPUART_LL_EF_FLAG_Management FLAG_Management 01664 * @{ 01665 */ 01666 01667 /** 01668 * @brief Check if the LPUART Parity Error Flag is set or not 01669 * @rmtoll ISR PE LL_LPUART_IsActiveFlag_PE 01670 * @param LPUARTx LPUART Instance 01671 * @retval State of bit (1 or 0). 01672 */ 01673 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_PE(USART_TypeDef *LPUARTx) 01674 { 01675 return (READ_BIT(LPUARTx->ISR, USART_ISR_PE) == (USART_ISR_PE)); 01676 } 01677 01678 /** 01679 * @brief Check if the LPUART Framing Error Flag is set or not 01680 * @rmtoll ISR FE LL_LPUART_IsActiveFlag_FE 01681 * @param LPUARTx LPUART Instance 01682 * @retval State of bit (1 or 0). 01683 */ 01684 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_FE(USART_TypeDef *LPUARTx) 01685 { 01686 return (READ_BIT(LPUARTx->ISR, USART_ISR_FE) == (USART_ISR_FE)); 01687 } 01688 01689 /** 01690 * @brief Check if the LPUART Noise error detected Flag is set or not 01691 * @rmtoll ISR NE LL_LPUART_IsActiveFlag_NE 01692 * @param LPUARTx LPUART Instance 01693 * @retval State of bit (1 or 0). 01694 */ 01695 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_NE(USART_TypeDef *LPUARTx) 01696 { 01697 return (READ_BIT(LPUARTx->ISR, USART_ISR_NE) == (USART_ISR_NE)); 01698 } 01699 01700 /** 01701 * @brief Check if the LPUART OverRun Error Flag is set or not 01702 * @rmtoll ISR ORE LL_LPUART_IsActiveFlag_ORE 01703 * @param LPUARTx LPUART Instance 01704 * @retval State of bit (1 or 0). 01705 */ 01706 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_ORE(USART_TypeDef *LPUARTx) 01707 { 01708 return (READ_BIT(LPUARTx->ISR, USART_ISR_ORE) == (USART_ISR_ORE)); 01709 } 01710 01711 /** 01712 * @brief Check if the LPUART IDLE line detected Flag is set or not 01713 * @rmtoll ISR IDLE LL_LPUART_IsActiveFlag_IDLE 01714 * @param LPUARTx LPUART Instance 01715 * @retval State of bit (1 or 0). 01716 */ 01717 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(USART_TypeDef *LPUARTx) 01718 { 01719 return (READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)); 01720 } 01721 01722 #if defined(USART_CR1_FIFOEN) 01723 /* Legacy define */ 01724 #define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE 01725 01726 /** 01727 * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not 01728 * @rmtoll ISR RXNE_RXFNE LL_LPUART_IsActiveFlag_RXNE_RXFNE 01729 * @param LPUARTx LPUART Instance 01730 * @retval State of bit (1 or 0). 01731 */ 01732 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE_RXFNE(USART_TypeDef *LPUARTx) 01733 { 01734 return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE_RXFNE) == (USART_ISR_RXNE_RXFNE)); 01735 } 01736 #else 01737 01738 /** 01739 * @brief Check if the LPUART Read Data Register Not Empty Flag is set or not 01740 * @rmtoll ISR RXNE LL_LPUART_IsActiveFlag_RXNE 01741 * @param LPUARTx LPUART Instance 01742 * @retval State of bit (1 or 0). 01743 */ 01744 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXNE(USART_TypeDef *LPUARTx) 01745 { 01746 return (READ_BIT(LPUARTx->ISR, USART_ISR_RXNE) == (USART_ISR_RXNE)); 01747 } 01748 #endif 01749 01750 /** 01751 * @brief Check if the LPUART Transmission Complete Flag is set or not 01752 * @rmtoll ISR TC LL_LPUART_IsActiveFlag_TC 01753 * @param LPUARTx LPUART Instance 01754 * @retval State of bit (1 or 0). 01755 */ 01756 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(USART_TypeDef *LPUARTx) 01757 { 01758 return (READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)); 01759 } 01760 01761 #if defined(USART_CR1_FIFOEN) 01762 /* Legacy define */ 01763 #define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF 01764 01765 /** 01766 * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not 01767 * @rmtoll ISR TXE_TXFNF LL_LPUART_IsActiveFlag_TXE_TXFNF 01768 * @param LPUARTx LPUART Instance 01769 * @retval State of bit (1 or 0). 01770 */ 01771 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE_TXFNF(USART_TypeDef *LPUARTx) 01772 { 01773 return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE_TXFNF) == (USART_ISR_TXE_TXFNF)); 01774 } 01775 #else 01776 01777 /** 01778 * @brief Check if the LPUART Transmit Data Register Empty Flag is set or not 01779 * @rmtoll ISR TXE LL_LPUART_IsActiveFlag_TXE 01780 * @param LPUARTx LPUART Instance 01781 * @retval State of bit (1 or 0). 01782 */ 01783 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXE(USART_TypeDef *LPUARTx) 01784 { 01785 return (READ_BIT(LPUARTx->ISR, USART_ISR_TXE) == (USART_ISR_TXE)); 01786 } 01787 #endif 01788 01789 /** 01790 * @brief Check if the LPUART CTS interrupt Flag is set or not 01791 * @rmtoll ISR CTSIF LL_LPUART_IsActiveFlag_nCTS 01792 * @param LPUARTx LPUART Instance 01793 * @retval State of bit (1 or 0). 01794 */ 01795 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_nCTS(USART_TypeDef *LPUARTx) 01796 { 01797 return (READ_BIT(LPUARTx->ISR, USART_ISR_CTSIF) == (USART_ISR_CTSIF)); 01798 } 01799 01800 /** 01801 * @brief Check if the LPUART CTS Flag is set or not 01802 * @rmtoll ISR CTS LL_LPUART_IsActiveFlag_CTS 01803 * @param LPUARTx LPUART Instance 01804 * @retval State of bit (1 or 0). 01805 */ 01806 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CTS(USART_TypeDef *LPUARTx) 01807 { 01808 return (READ_BIT(LPUARTx->ISR, USART_ISR_CTS) == (USART_ISR_CTS)); 01809 } 01810 01811 /** 01812 * @brief Check if the LPUART Busy Flag is set or not 01813 * @rmtoll ISR BUSY LL_LPUART_IsActiveFlag_BUSY 01814 * @param LPUARTx LPUART Instance 01815 * @retval State of bit (1 or 0). 01816 */ 01817 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_BUSY(USART_TypeDef *LPUARTx) 01818 { 01819 return (READ_BIT(LPUARTx->ISR, USART_ISR_BUSY) == (USART_ISR_BUSY)); 01820 } 01821 01822 /** 01823 * @brief Check if the LPUART Character Match Flag is set or not 01824 * @rmtoll ISR CMF LL_LPUART_IsActiveFlag_CM 01825 * @param LPUARTx LPUART Instance 01826 * @retval State of bit (1 or 0). 01827 */ 01828 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_CM(USART_TypeDef *LPUARTx) 01829 { 01830 return (READ_BIT(LPUARTx->ISR, USART_ISR_CMF) == (USART_ISR_CMF)); 01831 } 01832 01833 /** 01834 * @brief Check if the LPUART Send Break Flag is set or not 01835 * @rmtoll ISR SBKF LL_LPUART_IsActiveFlag_SBK 01836 * @param LPUARTx LPUART Instance 01837 * @retval State of bit (1 or 0). 01838 */ 01839 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_SBK(USART_TypeDef *LPUARTx) 01840 { 01841 return (READ_BIT(LPUARTx->ISR, USART_ISR_SBKF) == (USART_ISR_SBKF)); 01842 } 01843 01844 /** 01845 * @brief Check if the LPUART Receive Wake Up from mute mode Flag is set or not 01846 * @rmtoll ISR RWU LL_LPUART_IsActiveFlag_RWU 01847 * @param LPUARTx LPUART Instance 01848 * @retval State of bit (1 or 0). 01849 */ 01850 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RWU(USART_TypeDef *LPUARTx) 01851 { 01852 return (READ_BIT(LPUARTx->ISR, USART_ISR_RWU) == (USART_ISR_RWU)); 01853 } 01854 01855 /** 01856 * @brief Check if the LPUART Wake Up from stop mode Flag is set or not 01857 * @rmtoll ISR WUF LL_LPUART_IsActiveFlag_WKUP 01858 * @param LPUARTx LPUART Instance 01859 * @retval State of bit (1 or 0). 01860 */ 01861 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_WKUP(USART_TypeDef *LPUARTx) 01862 { 01863 return (READ_BIT(LPUARTx->ISR, USART_ISR_WUF) == (USART_ISR_WUF)); 01864 } 01865 01866 /** 01867 * @brief Check if the LPUART Transmit Enable Acknowledge Flag is set or not 01868 * @rmtoll ISR TEACK LL_LPUART_IsActiveFlag_TEACK 01869 * @param LPUARTx LPUART Instance 01870 * @retval State of bit (1 or 0). 01871 */ 01872 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TEACK(USART_TypeDef *LPUARTx) 01873 { 01874 return (READ_BIT(LPUARTx->ISR, USART_ISR_TEACK) == (USART_ISR_TEACK)); 01875 } 01876 01877 /** 01878 * @brief Check if the LPUART Receive Enable Acknowledge Flag is set or not 01879 * @rmtoll ISR REACK LL_LPUART_IsActiveFlag_REACK 01880 * @param LPUARTx LPUART Instance 01881 * @retval State of bit (1 or 0). 01882 */ 01883 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_REACK(USART_TypeDef *LPUARTx) 01884 { 01885 return (READ_BIT(LPUARTx->ISR, USART_ISR_REACK) == (USART_ISR_REACK)); 01886 } 01887 01888 #if defined(USART_CR1_FIFOEN) 01889 /** 01890 * @brief Check if the LPUART TX FIFO Empty Flag is set or not 01891 * @rmtoll ISR TXFE LL_LPUART_IsActiveFlag_TXFE 01892 * @param LPUARTx LPUART Instance 01893 * @retval State of bit (1 or 0). 01894 */ 01895 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFE(USART_TypeDef *LPUARTx) 01896 { 01897 return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFE) == (USART_ISR_TXFE)); 01898 } 01899 01900 /** 01901 * @brief Check if the LPUART RX FIFO Full Flag is set or not 01902 * @rmtoll ISR RXFF LL_LPUART_IsActiveFlag_RXFF 01903 * @param LPUARTx LPUART Instance 01904 * @retval State of bit (1 or 0). 01905 */ 01906 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFF(USART_TypeDef *LPUARTx) 01907 { 01908 return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFF) == (USART_ISR_RXFF)); 01909 } 01910 01911 /** 01912 * @brief Check if the LPUART TX FIFO Threshold Flag is set or not 01913 * @rmtoll ISR TXFT LL_LPUART_IsActiveFlag_TXFT 01914 * @param LPUARTx LPUART Instance 01915 * @retval State of bit (1 or 0). 01916 */ 01917 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TXFT(USART_TypeDef *LPUARTx) 01918 { 01919 return (READ_BIT(LPUARTx->ISR, USART_ISR_TXFT) == (USART_ISR_TXFT)); 01920 } 01921 01922 /** 01923 * @brief Check if the LPUART RX FIFO Threshold Flag is set or not 01924 * @rmtoll ISR RXFT LL_LPUART_IsActiveFlag_RXFT 01925 * @param LPUARTx LPUART Instance 01926 * @retval State of bit (1 or 0). 01927 */ 01928 __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_RXFT(USART_TypeDef *LPUARTx) 01929 { 01930 return (READ_BIT(LPUARTx->ISR, USART_ISR_RXFT) == (USART_ISR_RXFT)); 01931 } 01932 #endif 01933 01934 /** 01935 * @brief Clear Parity Error Flag 01936 * @rmtoll ICR PECF LL_LPUART_ClearFlag_PE 01937 * @param LPUARTx LPUART Instance 01938 * @retval None 01939 */ 01940 __STATIC_INLINE void LL_LPUART_ClearFlag_PE(USART_TypeDef *LPUARTx) 01941 { 01942 WRITE_REG(LPUARTx->ICR, USART_ICR_PECF); 01943 } 01944 01945 /** 01946 * @brief Clear Framing Error Flag 01947 * @rmtoll ICR FECF LL_LPUART_ClearFlag_FE 01948 * @param LPUARTx LPUART Instance 01949 * @retval None 01950 */ 01951 __STATIC_INLINE void LL_LPUART_ClearFlag_FE(USART_TypeDef *LPUARTx) 01952 { 01953 WRITE_REG(LPUARTx->ICR, USART_ICR_FECF); 01954 } 01955 01956 /** 01957 * @brief Clear Noise detected Flag 01958 * @rmtoll ICR NECF LL_LPUART_ClearFlag_NE 01959 * @param LPUARTx LPUART Instance 01960 * @retval None 01961 */ 01962 __STATIC_INLINE void LL_LPUART_ClearFlag_NE(USART_TypeDef *LPUARTx) 01963 { 01964 WRITE_REG(LPUARTx->ICR, USART_ICR_NECF); 01965 } 01966 01967 /** 01968 * @brief Clear OverRun Error Flag 01969 * @rmtoll ICR ORECF LL_LPUART_ClearFlag_ORE 01970 * @param LPUARTx LPUART Instance 01971 * @retval None 01972 */ 01973 __STATIC_INLINE void LL_LPUART_ClearFlag_ORE(USART_TypeDef *LPUARTx) 01974 { 01975 WRITE_REG(LPUARTx->ICR, USART_ICR_ORECF); 01976 } 01977 01978 /** 01979 * @brief Clear IDLE line detected Flag 01980 * @rmtoll ICR IDLECF LL_LPUART_ClearFlag_IDLE 01981 * @param LPUARTx LPUART Instance 01982 * @retval None 01983 */ 01984 __STATIC_INLINE void LL_LPUART_ClearFlag_IDLE(USART_TypeDef *LPUARTx) 01985 { 01986 WRITE_REG(LPUARTx->ICR, USART_ICR_IDLECF); 01987 } 01988 01989 #if defined(USART_CR1_FIFOEN) 01990 /** 01991 * @brief Clear TX FIFO Empty Flag 01992 * @rmtoll ICR TXFECF LL_LPUART_ClearFlag_TXFE 01993 * @param LPUARTx LPUART Instance 01994 * @retval None 01995 */ 01996 __STATIC_INLINE void LL_LPUART_ClearFlag_TXFE(USART_TypeDef *LPUARTx) 01997 { 01998 WRITE_REG(LPUARTx->ICR, USART_ICR_TXFECF); 01999 } 02000 #endif 02001 02002 /** 02003 * @brief Clear Transmission Complete Flag 02004 * @rmtoll ICR TCCF LL_LPUART_ClearFlag_TC 02005 * @param LPUARTx LPUART Instance 02006 * @retval None 02007 */ 02008 __STATIC_INLINE void LL_LPUART_ClearFlag_TC(USART_TypeDef *LPUARTx) 02009 { 02010 WRITE_REG(LPUARTx->ICR, USART_ICR_TCCF); 02011 } 02012 02013 /** 02014 * @brief Clear CTS Interrupt Flag 02015 * @rmtoll ICR CTSCF LL_LPUART_ClearFlag_nCTS 02016 * @param LPUARTx LPUART Instance 02017 * @retval None 02018 */ 02019 __STATIC_INLINE void LL_LPUART_ClearFlag_nCTS(USART_TypeDef *LPUARTx) 02020 { 02021 WRITE_REG(LPUARTx->ICR, USART_ICR_CTSCF); 02022 } 02023 02024 /** 02025 * @brief Clear Character Match Flag 02026 * @rmtoll ICR CMCF LL_LPUART_ClearFlag_CM 02027 * @param LPUARTx LPUART Instance 02028 * @retval None 02029 */ 02030 __STATIC_INLINE void LL_LPUART_ClearFlag_CM(USART_TypeDef *LPUARTx) 02031 { 02032 WRITE_REG(LPUARTx->ICR, USART_ICR_CMCF); 02033 } 02034 02035 /** 02036 * @brief Clear Wake Up from stop mode Flag 02037 * @rmtoll ICR WUCF LL_LPUART_ClearFlag_WKUP 02038 * @param LPUARTx LPUART Instance 02039 * @retval None 02040 */ 02041 __STATIC_INLINE void LL_LPUART_ClearFlag_WKUP(USART_TypeDef *LPUARTx) 02042 { 02043 WRITE_REG(LPUARTx->ICR, USART_ICR_WUCF); 02044 } 02045 02046 /** 02047 * @} 02048 */ 02049 02050 /** @defgroup LPUART_LL_EF_IT_Management IT_Management 02051 * @{ 02052 */ 02053 02054 /** 02055 * @brief Enable IDLE Interrupt 02056 * @rmtoll CR1 IDLEIE LL_LPUART_EnableIT_IDLE 02057 * @param LPUARTx LPUART Instance 02058 * @retval None 02059 */ 02060 __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) 02061 { 02062 SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); 02063 } 02064 02065 #if defined(USART_CR1_FIFOEN) 02066 /* Legacy define */ 02067 #define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE 02068 02069 /** 02070 * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt 02071 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_EnableIT_RXNE_RXFNE 02072 * @param LPUARTx LPUART Instance 02073 * @retval None 02074 */ 02075 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) 02076 { 02077 SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); 02078 } 02079 #else 02080 02081 /** 02082 * @brief Enable RX Not Empty Interrupt 02083 * @rmtoll CR1 RXNEIE LL_LPUART_EnableIT_RXNE 02084 * @param LPUARTx LPUART Instance 02085 * @retval None 02086 */ 02087 __STATIC_INLINE void LL_LPUART_EnableIT_RXNE(USART_TypeDef *LPUARTx) 02088 { 02089 SET_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); 02090 } 02091 #endif 02092 02093 /** 02094 * @brief Enable Transmission Complete Interrupt 02095 * @rmtoll CR1 TCIE LL_LPUART_EnableIT_TC 02096 * @param LPUARTx LPUART Instance 02097 * @retval None 02098 */ 02099 __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) 02100 { 02101 SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); 02102 } 02103 02104 #if defined(USART_CR1_FIFOEN) 02105 /* Legacy define */ 02106 #define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF 02107 02108 /** 02109 * @brief Enable TX Empty and TX FIFO Not Full Interrupt 02110 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_EnableIT_TXE_TXFNF 02111 * @param LPUARTx LPUART Instance 02112 * @retval None 02113 */ 02114 __STATIC_INLINE void LL_LPUART_EnableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) 02115 { 02116 SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); 02117 } 02118 #else 02119 02120 /** 02121 * @brief Enable TX Empty Interrupt 02122 * @rmtoll CR1 TXEIE LL_LPUART_EnableIT_TXE 02123 * @param LPUARTx LPUART Instance 02124 * @retval None 02125 */ 02126 __STATIC_INLINE void LL_LPUART_EnableIT_TXE(USART_TypeDef *LPUARTx) 02127 { 02128 SET_BIT(LPUARTx->CR1, USART_CR1_TXEIE); 02129 } 02130 #endif 02131 02132 /** 02133 * @brief Enable Parity Error Interrupt 02134 * @rmtoll CR1 PEIE LL_LPUART_EnableIT_PE 02135 * @param LPUARTx LPUART Instance 02136 * @retval None 02137 */ 02138 __STATIC_INLINE void LL_LPUART_EnableIT_PE(USART_TypeDef *LPUARTx) 02139 { 02140 SET_BIT(LPUARTx->CR1, USART_CR1_PEIE); 02141 } 02142 02143 /** 02144 * @brief Enable Character Match Interrupt 02145 * @rmtoll CR1 CMIE LL_LPUART_EnableIT_CM 02146 * @param LPUARTx LPUART Instance 02147 * @retval None 02148 */ 02149 __STATIC_INLINE void LL_LPUART_EnableIT_CM(USART_TypeDef *LPUARTx) 02150 { 02151 SET_BIT(LPUARTx->CR1, USART_CR1_CMIE); 02152 } 02153 02154 #if defined(USART_CR1_FIFOEN) 02155 /** 02156 * @brief Enable TX FIFO Empty Interrupt 02157 * @rmtoll CR1 TXFEIE LL_LPUART_EnableIT_TXFE 02158 * @param LPUARTx LPUART Instance 02159 * @retval None 02160 */ 02161 __STATIC_INLINE void LL_LPUART_EnableIT_TXFE(USART_TypeDef *LPUARTx) 02162 { 02163 SET_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); 02164 } 02165 02166 /** 02167 * @brief Enable RX FIFO Full Interrupt 02168 * @rmtoll CR1 RXFFIE LL_LPUART_EnableIT_RXFF 02169 * @param LPUARTx LPUART Instance 02170 * @retval None 02171 */ 02172 __STATIC_INLINE void LL_LPUART_EnableIT_RXFF(USART_TypeDef *LPUARTx) 02173 { 02174 SET_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); 02175 } 02176 #endif 02177 02178 /** 02179 * @brief Enable Error Interrupt 02180 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing 02181 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). 02182 * - 0: Interrupt is inhibited 02183 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. 02184 * @rmtoll CR3 EIE LL_LPUART_EnableIT_ERROR 02185 * @param LPUARTx LPUART Instance 02186 * @retval None 02187 */ 02188 __STATIC_INLINE void LL_LPUART_EnableIT_ERROR(USART_TypeDef *LPUARTx) 02189 { 02190 SET_BIT(LPUARTx->CR3, USART_CR3_EIE); 02191 } 02192 02193 /** 02194 * @brief Enable CTS Interrupt 02195 * @rmtoll CR3 CTSIE LL_LPUART_EnableIT_CTS 02196 * @param LPUARTx LPUART Instance 02197 * @retval None 02198 */ 02199 __STATIC_INLINE void LL_LPUART_EnableIT_CTS(USART_TypeDef *LPUARTx) 02200 { 02201 SET_BIT(LPUARTx->CR3, USART_CR3_CTSIE); 02202 } 02203 02204 /** 02205 * @brief Enable Wake Up from Stop Mode Interrupt 02206 * @rmtoll CR3 WUFIE LL_LPUART_EnableIT_WKUP 02207 * @param LPUARTx LPUART Instance 02208 * @retval None 02209 */ 02210 __STATIC_INLINE void LL_LPUART_EnableIT_WKUP(USART_TypeDef *LPUARTx) 02211 { 02212 SET_BIT(LPUARTx->CR3, USART_CR3_WUFIE); 02213 } 02214 02215 #if defined(USART_CR1_FIFOEN) 02216 /** 02217 * @brief Enable TX FIFO Threshold Interrupt 02218 * @rmtoll CR3 TXFTIE LL_LPUART_EnableIT_TXFT 02219 * @param LPUARTx LPUART Instance 02220 * @retval None 02221 */ 02222 __STATIC_INLINE void LL_LPUART_EnableIT_TXFT(USART_TypeDef *LPUARTx) 02223 { 02224 SET_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); 02225 } 02226 02227 /** 02228 * @brief Enable RX FIFO Threshold Interrupt 02229 * @rmtoll CR3 RXFTIE LL_LPUART_EnableIT_RXFT 02230 * @param LPUARTx LPUART Instance 02231 * @retval None 02232 */ 02233 __STATIC_INLINE void LL_LPUART_EnableIT_RXFT(USART_TypeDef *LPUARTx) 02234 { 02235 SET_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); 02236 } 02237 #endif 02238 02239 /** 02240 * @brief Disable IDLE Interrupt 02241 * @rmtoll CR1 IDLEIE LL_LPUART_DisableIT_IDLE 02242 * @param LPUARTx LPUART Instance 02243 * @retval None 02244 */ 02245 __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) 02246 { 02247 CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); 02248 } 02249 02250 #if defined(USART_CR1_FIFOEN) 02251 /* Legacy define */ 02252 #define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE 02253 02254 /** 02255 * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt 02256 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_DisableIT_RXNE_RXFNE 02257 * @param LPUARTx LPUART Instance 02258 * @retval None 02259 */ 02260 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) 02261 { 02262 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE); 02263 } 02264 #else 02265 02266 /** 02267 * @brief Disable RX Not Empty Interrupt 02268 * @rmtoll CR1 RXNEIE LL_LPUART_DisableIT_RXNE 02269 * @param LPUARTx LPUART Instance 02270 * @retval None 02271 */ 02272 __STATIC_INLINE void LL_LPUART_DisableIT_RXNE(USART_TypeDef *LPUARTx) 02273 { 02274 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXNEIE); 02275 } 02276 #endif 02277 02278 /** 02279 * @brief Disable Transmission Complete Interrupt 02280 * @rmtoll CR1 TCIE LL_LPUART_DisableIT_TC 02281 * @param LPUARTx LPUART Instance 02282 * @retval None 02283 */ 02284 __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) 02285 { 02286 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); 02287 } 02288 02289 #if defined(USART_CR1_FIFOEN) 02290 /* Legacy define */ 02291 #define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF 02292 02293 /** 02294 * @brief Disable TX Empty and TX FIFO Not Full Interrupt 02295 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_DisableIT_TXE_TXFNF 02296 * @param LPUARTx LPUART Instance 02297 * @retval None 02298 */ 02299 __STATIC_INLINE void LL_LPUART_DisableIT_TXE_TXFNF(USART_TypeDef *LPUARTx) 02300 { 02301 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE); 02302 } 02303 #else 02304 02305 /** 02306 * @brief Disable TX Empty Interrupt 02307 * @rmtoll CR1 TXEIE LL_LPUART_DisableIT_TXE 02308 * @param LPUARTx LPUART Instance 02309 * @retval None 02310 */ 02311 __STATIC_INLINE void LL_LPUART_DisableIT_TXE(USART_TypeDef *LPUARTx) 02312 { 02313 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXEIE); 02314 } 02315 #endif 02316 02317 /** 02318 * @brief Disable Parity Error Interrupt 02319 * @rmtoll CR1 PEIE LL_LPUART_DisableIT_PE 02320 * @param LPUARTx LPUART Instance 02321 * @retval None 02322 */ 02323 __STATIC_INLINE void LL_LPUART_DisableIT_PE(USART_TypeDef *LPUARTx) 02324 { 02325 CLEAR_BIT(LPUARTx->CR1, USART_CR1_PEIE); 02326 } 02327 02328 /** 02329 * @brief Disable Character Match Interrupt 02330 * @rmtoll CR1 CMIE LL_LPUART_DisableIT_CM 02331 * @param LPUARTx LPUART Instance 02332 * @retval None 02333 */ 02334 __STATIC_INLINE void LL_LPUART_DisableIT_CM(USART_TypeDef *LPUARTx) 02335 { 02336 CLEAR_BIT(LPUARTx->CR1, USART_CR1_CMIE); 02337 } 02338 02339 #if defined(USART_CR1_FIFOEN) 02340 /** 02341 * @brief Disable TX FIFO Empty Interrupt 02342 * @rmtoll CR1 TXFEIE LL_LPUART_DisableIT_TXFE 02343 * @param LPUARTx LPUART Instance 02344 * @retval None 02345 */ 02346 __STATIC_INLINE void LL_LPUART_DisableIT_TXFE(USART_TypeDef *LPUARTx) 02347 { 02348 CLEAR_BIT(LPUARTx->CR1, USART_CR1_TXFEIE); 02349 } 02350 02351 /** 02352 * @brief Disable RX FIFO Full Interrupt 02353 * @rmtoll CR1 RXFFIE LL_LPUART_DisableIT_RXFF 02354 * @param LPUARTx LPUART Instance 02355 * @retval None 02356 */ 02357 __STATIC_INLINE void LL_LPUART_DisableIT_RXFF(USART_TypeDef *LPUARTx) 02358 { 02359 CLEAR_BIT(LPUARTx->CR1, USART_CR1_RXFFIE); 02360 } 02361 #endif 02362 02363 /** 02364 * @brief Disable Error Interrupt 02365 * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing 02366 * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register). 02367 * - 0: Interrupt is inhibited 02368 * - 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the LPUARTx_ISR register. 02369 * @rmtoll CR3 EIE LL_LPUART_DisableIT_ERROR 02370 * @param LPUARTx LPUART Instance 02371 * @retval None 02372 */ 02373 __STATIC_INLINE void LL_LPUART_DisableIT_ERROR(USART_TypeDef *LPUARTx) 02374 { 02375 CLEAR_BIT(LPUARTx->CR3, USART_CR3_EIE); 02376 } 02377 02378 /** 02379 * @brief Disable CTS Interrupt 02380 * @rmtoll CR3 CTSIE LL_LPUART_DisableIT_CTS 02381 * @param LPUARTx LPUART Instance 02382 * @retval None 02383 */ 02384 __STATIC_INLINE void LL_LPUART_DisableIT_CTS(USART_TypeDef *LPUARTx) 02385 { 02386 CLEAR_BIT(LPUARTx->CR3, USART_CR3_CTSIE); 02387 } 02388 02389 /** 02390 * @brief Disable Wake Up from Stop Mode Interrupt 02391 * @rmtoll CR3 WUFIE LL_LPUART_DisableIT_WKUP 02392 * @param LPUARTx LPUART Instance 02393 * @retval None 02394 */ 02395 __STATIC_INLINE void LL_LPUART_DisableIT_WKUP(USART_TypeDef *LPUARTx) 02396 { 02397 CLEAR_BIT(LPUARTx->CR3, USART_CR3_WUFIE); 02398 } 02399 02400 #if defined(USART_CR1_FIFOEN) 02401 /** 02402 * @brief Disable TX FIFO Threshold Interrupt 02403 * @rmtoll CR3 TXFTIE LL_LPUART_DisableIT_TXFT 02404 * @param LPUARTx LPUART Instance 02405 * @retval None 02406 */ 02407 __STATIC_INLINE void LL_LPUART_DisableIT_TXFT(USART_TypeDef *LPUARTx) 02408 { 02409 CLEAR_BIT(LPUARTx->CR3, USART_CR3_TXFTIE); 02410 } 02411 02412 /** 02413 * @brief Disable RX FIFO Threshold Interrupt 02414 * @rmtoll CR3 RXFTIE LL_LPUART_DisableIT_RXFT 02415 * @param LPUARTx LPUART Instance 02416 * @retval None 02417 */ 02418 __STATIC_INLINE void LL_LPUART_DisableIT_RXFT(USART_TypeDef *LPUARTx) 02419 { 02420 CLEAR_BIT(LPUARTx->CR3, USART_CR3_RXFTIE); 02421 } 02422 #endif 02423 02424 /** 02425 * @brief Check if the LPUART IDLE Interrupt source is enabled or disabled. 02426 * @rmtoll CR1 IDLEIE LL_LPUART_IsEnabledIT_IDLE 02427 * @param LPUARTx LPUART Instance 02428 * @retval State of bit (1 or 0). 02429 */ 02430 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(USART_TypeDef *LPUARTx) 02431 { 02432 return (READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); 02433 } 02434 02435 #if defined(USART_CR1_FIFOEN) 02436 /* Legacy define */ 02437 #define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE 02438 02439 /** 02440 * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. 02441 * @rmtoll CR1 RXNEIE_RXFNEIE LL_LPUART_IsEnabledIT_RXNE_RXFNE 02442 * @param LPUARTx LPUART Instance 02443 * @retval State of bit (1 or 0). 02444 */ 02445 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE_RXFNE(USART_TypeDef *LPUARTx) 02446 { 02447 return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE_RXFNEIE) == (USART_CR1_RXNEIE_RXFNEIE)); 02448 } 02449 #else 02450 02451 /** 02452 * @brief Check if the LPUART RX Not Empty Interrupt is enabled or disabled. 02453 * @rmtoll CR1 RXNEIE LL_LPUART_IsEnabledIT_RXNE 02454 * @param LPUARTx LPUART Instance 02455 * @retval State of bit (1 or 0). 02456 */ 02457 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXNE(USART_TypeDef *LPUARTx) 02458 { 02459 return (READ_BIT(LPUARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); 02460 } 02461 #endif 02462 02463 /** 02464 * @brief Check if the LPUART Transmission Complete Interrupt is enabled or disabled. 02465 * @rmtoll CR1 TCIE LL_LPUART_IsEnabledIT_TC 02466 * @param LPUARTx LPUART Instance 02467 * @retval State of bit (1 or 0). 02468 */ 02469 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(USART_TypeDef *LPUARTx) 02470 { 02471 return (READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); 02472 } 02473 02474 #if defined(USART_CR1_FIFOEN) 02475 /* Legacy define */ 02476 #define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF 02477 02478 /** 02479 * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled 02480 * @rmtoll CR1 TXEIE_TXFNFIE LL_LPUART_IsEnabledIT_TXE_TXFNF 02481 * @param LPUARTx LPUART Instance 02482 * @retval State of bit (1 or 0). 02483 */ 02484 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE_TXFNF(USART_TypeDef *LPUARTx) 02485 { 02486 return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE_TXFNFIE) == (USART_CR1_TXEIE_TXFNFIE)); 02487 } 02488 #else 02489 02490 /** 02491 * @brief Check if the LPUART TX Empty Interrupt is enabled or disabled. 02492 * @rmtoll CR1 TXEIE LL_LPUART_IsEnabledIT_TXE 02493 * @param LPUARTx LPUART Instance 02494 * @retval State of bit (1 or 0). 02495 */ 02496 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXE(USART_TypeDef *LPUARTx) 02497 { 02498 return (READ_BIT(LPUARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); 02499 } 02500 #endif 02501 02502 /** 02503 * @brief Check if the LPUART Parity Error Interrupt is enabled or disabled. 02504 * @rmtoll CR1 PEIE LL_LPUART_IsEnabledIT_PE 02505 * @param LPUARTx LPUART Instance 02506 * @retval State of bit (1 or 0). 02507 */ 02508 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_PE(USART_TypeDef *LPUARTx) 02509 { 02510 return (READ_BIT(LPUARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); 02511 } 02512 02513 /** 02514 * @brief Check if the LPUART Character Match Interrupt is enabled or disabled. 02515 * @rmtoll CR1 CMIE LL_LPUART_IsEnabledIT_CM 02516 * @param LPUARTx LPUART Instance 02517 * @retval State of bit (1 or 0). 02518 */ 02519 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CM(USART_TypeDef *LPUARTx) 02520 { 02521 return (READ_BIT(LPUARTx->CR1, USART_CR1_CMIE) == (USART_CR1_CMIE)); 02522 } 02523 02524 #if defined(USART_CR1_FIFOEN) 02525 /** 02526 * @brief Check if the LPUART TX FIFO Empty Interrupt is enabled or disabled 02527 * @rmtoll CR1 TXFEIE LL_LPUART_IsEnabledIT_TXFE 02528 * @param LPUARTx LPUART Instance 02529 * @retval State of bit (1 or 0). 02530 */ 02531 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFE(USART_TypeDef *LPUARTx) 02532 { 02533 return (READ_BIT(LPUARTx->CR1, USART_CR1_TXFEIE) == (USART_CR1_TXFEIE)); 02534 } 02535 02536 /** 02537 * @brief Check if the LPUART RX FIFO Full Interrupt is enabled or disabled 02538 * @rmtoll CR1 RXFFIE LL_LPUART_IsEnabledIT_RXFF 02539 * @param LPUARTx LPUART Instance 02540 * @retval State of bit (1 or 0). 02541 */ 02542 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFF(USART_TypeDef *LPUARTx) 02543 { 02544 return (READ_BIT(LPUARTx->CR1, USART_CR1_RXFFIE) == (USART_CR1_RXFFIE)); 02545 } 02546 #endif 02547 02548 /** 02549 * @brief Check if the LPUART Error Interrupt is enabled or disabled. 02550 * @rmtoll CR3 EIE LL_LPUART_IsEnabledIT_ERROR 02551 * @param LPUARTx LPUART Instance 02552 * @retval State of bit (1 or 0). 02553 */ 02554 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_ERROR(USART_TypeDef *LPUARTx) 02555 { 02556 return (READ_BIT(LPUARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); 02557 } 02558 02559 /** 02560 * @brief Check if the LPUART CTS Interrupt is enabled or disabled. 02561 * @rmtoll CR3 CTSIE LL_LPUART_IsEnabledIT_CTS 02562 * @param LPUARTx LPUART Instance 02563 * @retval State of bit (1 or 0). 02564 */ 02565 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_CTS(USART_TypeDef *LPUARTx) 02566 { 02567 return (READ_BIT(LPUARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); 02568 } 02569 02570 /** 02571 * @brief Check if the LPUART Wake Up from Stop Mode Interrupt is enabled or disabled. 02572 * @rmtoll CR3 WUFIE LL_LPUART_IsEnabledIT_WKUP 02573 * @param LPUARTx LPUART Instance 02574 * @retval State of bit (1 or 0). 02575 */ 02576 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_WKUP(USART_TypeDef *LPUARTx) 02577 { 02578 return (READ_BIT(LPUARTx->CR3, USART_CR3_WUFIE) == (USART_CR3_WUFIE)); 02579 } 02580 02581 #if defined(USART_CR1_FIFOEN) 02582 /** 02583 * @brief Check if LPUART TX FIFO Threshold Interrupt is enabled or disabled 02584 * @rmtoll CR3 TXFTIE LL_LPUART_IsEnabledIT_TXFT 02585 * @param LPUARTx LPUART Instance 02586 * @retval State of bit (1 or 0). 02587 */ 02588 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TXFT(USART_TypeDef *LPUARTx) 02589 { 02590 return (READ_BIT(LPUARTx->CR3, USART_CR3_TXFTIE) == (USART_CR3_TXFTIE)); 02591 } 02592 02593 /** 02594 * @brief Check if LPUART RX FIFO Threshold Interrupt is enabled or disabled 02595 * @rmtoll CR3 RXFTIE LL_LPUART_IsEnabledIT_RXFT 02596 * @param LPUARTx LPUART Instance 02597 * @retval State of bit (1 or 0). 02598 */ 02599 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_RXFT(USART_TypeDef *LPUARTx) 02600 { 02601 return (READ_BIT(LPUARTx->CR3, USART_CR3_RXFTIE) == (USART_CR3_RXFTIE)); 02602 } 02603 #endif 02604 02605 /** 02606 * @} 02607 */ 02608 02609 /** @defgroup LPUART_LL_EF_DMA_Management DMA_Management 02610 * @{ 02611 */ 02612 02613 /** 02614 * @brief Enable DMA Mode for reception 02615 * @rmtoll CR3 DMAR LL_LPUART_EnableDMAReq_RX 02616 * @param LPUARTx LPUART Instance 02617 * @retval None 02618 */ 02619 __STATIC_INLINE void LL_LPUART_EnableDMAReq_RX(USART_TypeDef *LPUARTx) 02620 { 02621 SET_BIT(LPUARTx->CR3, USART_CR3_DMAR); 02622 } 02623 02624 /** 02625 * @brief Disable DMA Mode for reception 02626 * @rmtoll CR3 DMAR LL_LPUART_DisableDMAReq_RX 02627 * @param LPUARTx LPUART Instance 02628 * @retval None 02629 */ 02630 __STATIC_INLINE void LL_LPUART_DisableDMAReq_RX(USART_TypeDef *LPUARTx) 02631 { 02632 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAR); 02633 } 02634 02635 /** 02636 * @brief Check if DMA Mode is enabled for reception 02637 * @rmtoll CR3 DMAR LL_LPUART_IsEnabledDMAReq_RX 02638 * @param LPUARTx LPUART Instance 02639 * @retval State of bit (1 or 0). 02640 */ 02641 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_RX(USART_TypeDef *LPUARTx) 02642 { 02643 return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); 02644 } 02645 02646 /** 02647 * @brief Enable DMA Mode for transmission 02648 * @rmtoll CR3 DMAT LL_LPUART_EnableDMAReq_TX 02649 * @param LPUARTx LPUART Instance 02650 * @retval None 02651 */ 02652 __STATIC_INLINE void LL_LPUART_EnableDMAReq_TX(USART_TypeDef *LPUARTx) 02653 { 02654 SET_BIT(LPUARTx->CR3, USART_CR3_DMAT); 02655 } 02656 02657 /** 02658 * @brief Disable DMA Mode for transmission 02659 * @rmtoll CR3 DMAT LL_LPUART_DisableDMAReq_TX 02660 * @param LPUARTx LPUART Instance 02661 * @retval None 02662 */ 02663 __STATIC_INLINE void LL_LPUART_DisableDMAReq_TX(USART_TypeDef *LPUARTx) 02664 { 02665 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DMAT); 02666 } 02667 02668 /** 02669 * @brief Check if DMA Mode is enabled for transmission 02670 * @rmtoll CR3 DMAT LL_LPUART_IsEnabledDMAReq_TX 02671 * @param LPUARTx LPUART Instance 02672 * @retval State of bit (1 or 0). 02673 */ 02674 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMAReq_TX(USART_TypeDef *LPUARTx) 02675 { 02676 return (READ_BIT(LPUARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); 02677 } 02678 02679 /** 02680 * @brief Enable DMA Disabling on Reception Error 02681 * @rmtoll CR3 DDRE LL_LPUART_EnableDMADeactOnRxErr 02682 * @param LPUARTx LPUART Instance 02683 * @retval None 02684 */ 02685 __STATIC_INLINE void LL_LPUART_EnableDMADeactOnRxErr(USART_TypeDef *LPUARTx) 02686 { 02687 SET_BIT(LPUARTx->CR3, USART_CR3_DDRE); 02688 } 02689 02690 /** 02691 * @brief Disable DMA Disabling on Reception Error 02692 * @rmtoll CR3 DDRE LL_LPUART_DisableDMADeactOnRxErr 02693 * @param LPUARTx LPUART Instance 02694 * @retval None 02695 */ 02696 __STATIC_INLINE void LL_LPUART_DisableDMADeactOnRxErr(USART_TypeDef *LPUARTx) 02697 { 02698 CLEAR_BIT(LPUARTx->CR3, USART_CR3_DDRE); 02699 } 02700 02701 /** 02702 * @brief Indicate if DMA Disabling on Reception Error is disabled 02703 * @rmtoll CR3 DDRE LL_LPUART_IsEnabledDMADeactOnRxErr 02704 * @param LPUARTx LPUART Instance 02705 * @retval State of bit (1 or 0). 02706 */ 02707 __STATIC_INLINE uint32_t LL_LPUART_IsEnabledDMADeactOnRxErr(USART_TypeDef *LPUARTx) 02708 { 02709 return (READ_BIT(LPUARTx->CR3, USART_CR3_DDRE) == (USART_CR3_DDRE)); 02710 } 02711 02712 /** 02713 * @brief Get the LPUART data register address used for DMA transfer 02714 * @rmtoll RDR RDR LL_LPUART_DMA_GetRegAddr\n 02715 * @rmtoll TDR TDR LL_LPUART_DMA_GetRegAddr 02716 * @param LPUARTx LPUART Instance 02717 * @param Direction This parameter can be one of the following values: 02718 * @arg @ref LL_LPUART_DMA_REG_DATA_TRANSMIT 02719 * @arg @ref LL_LPUART_DMA_REG_DATA_RECEIVE 02720 * @retval Address of data register 02721 */ 02722 __STATIC_INLINE uint32_t LL_LPUART_DMA_GetRegAddr(USART_TypeDef *LPUARTx, uint32_t Direction) 02723 { 02724 register uint32_t data_reg_addr = 0U; 02725 02726 if (Direction == LL_LPUART_DMA_REG_DATA_TRANSMIT) 02727 { 02728 /* return address of TDR register */ 02729 data_reg_addr = (uint32_t) & (LPUARTx->TDR); 02730 } 02731 else 02732 { 02733 /* return address of RDR register */ 02734 data_reg_addr = (uint32_t) & (LPUARTx->RDR); 02735 } 02736 02737 return data_reg_addr; 02738 } 02739 02740 /** 02741 * @} 02742 */ 02743 02744 /** @defgroup LPUART_LL_EF_Data_Management Data_Management 02745 * @{ 02746 */ 02747 02748 /** 02749 * @brief Read Receiver Data register (Receive Data value, 8 bits) 02750 * @rmtoll RDR RDR LL_LPUART_ReceiveData8 02751 * @param LPUARTx LPUART Instance 02752 * @retval Time Value between Min_Data=0x00 and Max_Data=0xFF 02753 */ 02754 __STATIC_INLINE uint8_t LL_LPUART_ReceiveData8(USART_TypeDef *LPUARTx) 02755 { 02756 return (uint8_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); 02757 } 02758 02759 /** 02760 * @brief Read Receiver Data register (Receive Data value, 9 bits) 02761 * @rmtoll RDR RDR LL_LPUART_ReceiveData9 02762 * @param LPUARTx LPUART Instance 02763 * @retval Time Value between Min_Data=0x00 and Max_Data=0x1FF 02764 */ 02765 __STATIC_INLINE uint16_t LL_LPUART_ReceiveData9(USART_TypeDef *LPUARTx) 02766 { 02767 return (uint16_t)(READ_BIT(LPUARTx->RDR, USART_RDR_RDR)); 02768 } 02769 02770 /** 02771 * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) 02772 * @rmtoll TDR TDR LL_LPUART_TransmitData8 02773 * @param LPUARTx LPUART Instance 02774 * @param Value between Min_Data=0x00 and Max_Data=0xFF 02775 * @retval None 02776 */ 02777 __STATIC_INLINE void LL_LPUART_TransmitData8(USART_TypeDef *LPUARTx, uint8_t Value) 02778 { 02779 LPUARTx->TDR = Value; 02780 } 02781 02782 /** 02783 * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) 02784 * @rmtoll TDR TDR LL_LPUART_TransmitData9 02785 * @param LPUARTx LPUART Instance 02786 * @param Value between Min_Data=0x00 and Max_Data=0x1FF 02787 * @retval None 02788 */ 02789 __STATIC_INLINE void LL_LPUART_TransmitData9(USART_TypeDef *LPUARTx, uint16_t Value) 02790 { 02791 LPUARTx->TDR = Value & 0x1FFU; 02792 } 02793 02794 /** 02795 * @} 02796 */ 02797 02798 /** @defgroup LPUART_LL_EF_Execution Execution 02799 * @{ 02800 */ 02801 02802 /** 02803 * @brief Request Break sending 02804 * @rmtoll RQR SBKRQ LL_LPUART_RequestBreakSending 02805 * @param LPUARTx LPUART Instance 02806 * @retval None 02807 */ 02808 __STATIC_INLINE void LL_LPUART_RequestBreakSending(USART_TypeDef *LPUARTx) 02809 { 02810 SET_BIT(LPUARTx->RQR, USART_RQR_SBKRQ); 02811 } 02812 02813 /** 02814 * @brief Put LPUART in mute mode and set the RWU flag 02815 * @rmtoll RQR MMRQ LL_LPUART_RequestEnterMuteMode 02816 * @param LPUARTx LPUART Instance 02817 * @retval None 02818 */ 02819 __STATIC_INLINE void LL_LPUART_RequestEnterMuteMode(USART_TypeDef *LPUARTx) 02820 { 02821 SET_BIT(LPUARTx->RQR, USART_RQR_MMRQ); 02822 } 02823 02824 /** 02825 @if USART_CR1_FIFOEN 02826 * @brief Request a Receive Data and FIFO flush 02827 * @note Allows to discard the received data without reading them, and avoid an overrun 02828 * condition. 02829 @else 02830 * @brief Request a Receive Data flush 02831 @endif 02832 * @rmtoll RQR RXFRQ LL_LPUART_RequestRxDataFlush 02833 * @param LPUARTx LPUART Instance 02834 * @retval None 02835 */ 02836 __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) 02837 { 02838 SET_BIT(LPUARTx->RQR, USART_RQR_RXFRQ); 02839 } 02840 02841 /** 02842 * @} 02843 */ 02844 02845 #if defined(USE_FULL_LL_DRIVER) 02846 /** @defgroup LPUART_LL_EF_Init Initialization and de-initialization functions 02847 * @{ 02848 */ 02849 ErrorStatus LL_LPUART_DeInit(USART_TypeDef *LPUARTx); 02850 ErrorStatus LL_LPUART_Init(USART_TypeDef *LPUARTx, LL_LPUART_InitTypeDef *LPUART_InitStruct); 02851 void LL_LPUART_StructInit(LL_LPUART_InitTypeDef *LPUART_InitStruct); 02852 /** 02853 * @} 02854 */ 02855 #endif /* USE_FULL_LL_DRIVER */ 02856 02857 /** 02858 * @} 02859 */ 02860 02861 /** 02862 * @} 02863 */ 02864 02865 #endif /* LPUART1 */ 02866 02867 /** 02868 * @} 02869 */ 02870 02871 #ifdef __cplusplus 02872 } 02873 #endif 02874 02875 #endif /* __STM32L4xx_LL_LPUART_H */ 02876 02877 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/