STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_dma.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_DMA_H 00038 #define __STM32L4xx_LL_DMA_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 #if defined(DMAMUX1) 00047 #include "stm32l4xx_ll_dmamux.h" 00048 #endif /* DMAMUX1 */ 00049 00050 /** @addtogroup STM32L4xx_LL_Driver 00051 * @{ 00052 */ 00053 00054 #if defined (DMA1) || defined (DMA2) 00055 00056 /** @defgroup DMA_LL DMA 00057 * @{ 00058 */ 00059 00060 /* Private types -------------------------------------------------------------*/ 00061 /* Private variables ---------------------------------------------------------*/ 00062 /** @defgroup DMA_LL_Private_Variables DMA Private Variables 00063 * @{ 00064 */ 00065 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ 00066 static const uint8_t CHANNEL_OFFSET_TAB[] = 00067 { 00068 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), 00069 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), 00070 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), 00071 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE), 00072 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE), 00073 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE), 00074 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE) 00075 }; 00076 /** 00077 * @} 00078 */ 00079 00080 /* Private constants ---------------------------------------------------------*/ 00081 #if defined(DMAMUX1) 00082 #else 00083 /** @defgroup DMA_LL_Private_Constants DMA Private Constants 00084 * @{ 00085 */ 00086 /* Define used to get CSELR register offset */ 00087 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE) 00088 00089 /* Defines used for the bit position in the register and perform offsets */ 00090 #define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U)) 00091 /** 00092 * @} 00093 */ 00094 #endif /* DMAMUX1 */ 00095 00096 /* Private macros ------------------------------------------------------------*/ 00097 #if defined(DMAMUX1) 00098 /** @defgroup DMA_LL_Private_Macros DMA Private Macros 00099 * @{ 00100 */ 00101 /** 00102 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel 00103 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. 00104 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. 00105 * @param __DMA_INSTANCE__ DMAx 00106 * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). 00107 */ 00108 #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ 00109 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) 00110 00111 /** 00112 * @} 00113 */ 00114 #else 00115 #if defined(USE_FULL_LL_DRIVER) 00116 /** @defgroup DMA_LL_Private_Macros DMA Private Macros 00117 * @{ 00118 */ 00119 /** 00120 * @} 00121 */ 00122 #endif /*USE_FULL_LL_DRIVER*/ 00123 #endif /* DMAMUX1 */ 00124 00125 /* Exported types ------------------------------------------------------------*/ 00126 #if defined(USE_FULL_LL_DRIVER) 00127 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 00128 * @{ 00129 */ 00130 typedef struct 00131 { 00132 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 00133 or as Source base address in case of memory to memory transfer direction. 00134 00135 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00136 00137 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 00138 or as Destination base address in case of memory to memory transfer direction. 00139 00140 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00141 00142 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00143 from memory to memory or from peripheral to memory. 00144 This parameter can be a value of @ref DMA_LL_EC_DIRECTION 00145 00146 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ 00147 00148 uint32_t Mode; /*!< Specifies the normal or circular operation mode. 00149 This parameter can be a value of @ref DMA_LL_EC_MODE 00150 @note: The circular buffer mode cannot be used if the memory to memory 00151 data transfer direction is configured on the selected Channel 00152 00153 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ 00154 00155 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction 00156 is incremented or not. 00157 This parameter can be a value of @ref DMA_LL_EC_PERIPH 00158 00159 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ 00160 00161 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction 00162 is incremented or not. 00163 This parameter can be a value of @ref DMA_LL_EC_MEMORY 00164 00165 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ 00166 00167 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) 00168 in case of memory to memory transfer direction. 00169 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 00170 00171 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ 00172 00173 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) 00174 in case of memory to memory transfer direction. 00175 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 00176 00177 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ 00178 00179 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 00180 The data unit is equal to the source buffer configuration set in PeripheralSize 00181 or MemorySize parameters depending in the transfer direction. 00182 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF 00183 00184 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ 00185 #if defined(DMAMUX1) 00186 00187 uint32_t PeriphRequest; /*!< Specifies the peripheral request. 00188 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST 00189 00190 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ 00191 #else 00192 00193 uint32_t PeriphRequest; /*!< Specifies the peripheral request. 00194 This parameter can be a value of @ref DMA_LL_EC_REQUEST 00195 00196 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */ 00197 #endif /* DMAMUX1 */ 00198 00199 uint32_t Priority; /*!< Specifies the channel priority level. 00200 This parameter can be a value of @ref DMA_LL_EC_PRIORITY 00201 00202 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ 00203 00204 } LL_DMA_InitTypeDef; 00205 /** 00206 * @} 00207 */ 00208 #endif /*USE_FULL_LL_DRIVER*/ 00209 00210 /* Exported constants --------------------------------------------------------*/ 00211 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 00212 * @{ 00213 */ 00214 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines 00215 * @brief Flags defines which can be used with LL_DMA_WriteReg function 00216 * @{ 00217 */ 00218 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ 00219 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ 00220 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ 00221 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ 00222 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ 00223 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ 00224 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ 00225 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ 00226 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ 00227 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ 00228 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ 00229 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ 00230 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */ 00231 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */ 00232 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */ 00233 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */ 00234 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */ 00235 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */ 00236 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */ 00237 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */ 00238 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */ 00239 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */ 00240 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */ 00241 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */ 00242 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */ 00243 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */ 00244 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */ 00245 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */ 00246 /** 00247 * @} 00248 */ 00249 00250 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines 00251 * @brief Flags defines which can be used with LL_DMA_ReadReg function 00252 * @{ 00253 */ 00254 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ 00255 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ 00256 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ 00257 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ 00258 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ 00259 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ 00260 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ 00261 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ 00262 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ 00263 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ 00264 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ 00265 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ 00266 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */ 00267 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */ 00268 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */ 00269 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */ 00270 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */ 00271 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */ 00272 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */ 00273 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */ 00274 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */ 00275 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */ 00276 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */ 00277 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */ 00278 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */ 00279 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */ 00280 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */ 00281 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */ 00282 /** 00283 * @} 00284 */ 00285 00286 /** @defgroup DMA_LL_EC_IT IT Defines 00287 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions 00288 * @{ 00289 */ 00290 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ 00291 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ 00292 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ 00293 /** 00294 * @} 00295 */ 00296 00297 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 00298 * @{ 00299 */ 00300 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ 00301 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ 00302 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ 00303 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */ 00304 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */ 00305 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */ 00306 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */ 00307 #if defined(USE_FULL_LL_DRIVER) 00308 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */ 00309 #endif /*USE_FULL_LL_DRIVER*/ 00310 /** 00311 * @} 00312 */ 00313 00314 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction 00315 * @{ 00316 */ 00317 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 00318 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ 00319 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ 00320 /** 00321 * @} 00322 */ 00323 00324 /** @defgroup DMA_LL_EC_MODE Transfer mode 00325 * @{ 00326 */ 00327 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ 00328 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ 00329 /** 00330 * @} 00331 */ 00332 00333 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode 00334 * @{ 00335 */ 00336 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ 00337 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ 00338 /** 00339 * @} 00340 */ 00341 00342 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode 00343 * @{ 00344 */ 00345 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ 00346 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ 00347 /** 00348 * @} 00349 */ 00350 00351 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment 00352 * @{ 00353 */ 00354 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 00355 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 00356 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 00357 /** 00358 * @} 00359 */ 00360 00361 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment 00362 * @{ 00363 */ 00364 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 00365 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 00366 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ 00367 /** 00368 * @} 00369 */ 00370 00371 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level 00372 * @{ 00373 */ 00374 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 00375 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ 00376 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ 00377 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ 00378 /** 00379 * @} 00380 */ 00381 00382 #if defined(DMAMUX1) 00383 /** @defgroup DMAMUX_LL_EC_REQUEST Transfer request 00384 * @{ 00385 */ 00386 #define LL_DMAMUX_REQUEST_MEM2MEM 0U /*!< Memory to memory transfer */ 00387 #define LL_DMAMUX_REQUEST_GENERATOR0 1U /*!< DMAMUX request generator 0 */ 00388 #define LL_DMAMUX_REQUEST_GENERATOR1 2U /*!< DMAMUX request generator 1 */ 00389 #define LL_DMAMUX_REQUEST_GENERATOR2 3U /*!< DMAMUX request generator 2 */ 00390 #define LL_DMAMUX_REQUEST_GENERATOR3 4U /*!< DMAMUX request generator 3 */ 00391 #define LL_DMAMUX_REQUEST_ADC1 5U /*!< DMAMUX ADC1 request */ 00392 #define LL_DMAMUX_REQUEST_DAC1_CH1 6U /*!< DMAMUX DAC1 CH1 request */ 00393 #define LL_DMAMUX_REQUEST_DAC1_CH2 7U /*!< DMAMUX DAC1 CH2 request */ 00394 #define LL_DMAMUX_REQUEST_TIM6_UP 8U /*!< DMAMUX TIM6 UP request */ 00395 #define LL_DMAMUX_REQUEST_TIM7_UP 9U /*!< DMAMUX TIM7 UP request */ 00396 #define LL_DMAMUX_REQUEST_SPI1_RX 10U /*!< DMAMUX SPI1 RX request */ 00397 #define LL_DMAMUX_REQUEST_SPI1_TX 11U /*!< DMAMUX SPI1 TX request */ 00398 #define LL_DMAMUX_REQUEST_SPI2_RX 12U /*!< DMAMUX SPI2 RX request */ 00399 #define LL_DMAMUX_REQUEST_SPI2_TX 13U /*!< DMAMUX SPI2 TX request */ 00400 #define LL_DMAMUX_REQUEST_SPI3_RX 14U /*!< DMAMUX SPI3 RX request */ 00401 #define LL_DMAMUX_REQUEST_SPI3_TX 15U /*!< DMAMUX SPI3 TX request */ 00402 #define LL_DMAMUX_REQUEST_I2C1_RX 16U /*!< DMAMUX I2C1 RX request */ 00403 #define LL_DMAMUX_REQUEST_I2C1_TX 17U /*!< DMAMUX I2C1 TX request */ 00404 #define LL_DMAMUX_REQUEST_I2C2_RX 18U /*!< DMAMUX I2C2 RX request */ 00405 #define LL_DMAMUX_REQUEST_I2C2_TX 19U /*!< DMAMUX I2C2 TX request */ 00406 #define LL_DMAMUX_REQUEST_I2C3_RX 20U /*!< DMAMUX I2C3 RX request */ 00407 #define LL_DMAMUX_REQUEST_I2C3_TX 21U /*!< DMAMUX I2C3 TX request */ 00408 #define LL_DMAMUX_REQUEST_I2C4_RX 22U /*!< DMAMUX I2C4 RX request */ 00409 #define LL_DMAMUX_REQUEST_I2C4_TX 23U /*!< DMAMUX I2C4 TX request */ 00410 #define LL_DMAMUX_REQUEST_USART1_RX 24U /*!< DMAMUX USART1 RX request */ 00411 #define LL_DMAMUX_REQUEST_USART1_TX 25U /*!< DMAMUX USART1 TX request */ 00412 #define LL_DMAMUX_REQUEST_USART2_RX 26U /*!< DMAMUX USART2 RX request */ 00413 #define LL_DMAMUX_REQUEST_USART2_TX 27U /*!< DMAMUX USART2 TX request */ 00414 #define LL_DMAMUX_REQUEST_USART3_RX 28U /*!< DMAMUX USART3 RX request */ 00415 #define LL_DMAMUX_REQUEST_USART3_TX 29U /*!< DMAMUX USART3 TX request */ 00416 #define LL_DMAMUX_REQUEST_UART4_RX 30U /*!< DMAMUX UART4 RX request */ 00417 #define LL_DMAMUX_REQUEST_UART4_TX 31U /*!< DMAMUX UART4 TX request */ 00418 #define LL_DMAMUX_REQUEST_UART5_RX 32U /*!< DMAMUX UART5 RX request */ 00419 #define LL_DMAMUX_REQUEST_UART5_TX 33U /*!< DMAMUX UART5 TX request */ 00420 #define LL_DMAMUX_REQUEST_LPUART1_RX 34U /*!< DMAMUX LPUART1 RX request */ 00421 #define LL_DMAMUX_REQUEST_LPUART1_TX 35U /*!< DMAMUX LPUART1 TX request */ 00422 #define LL_DMAMUX_REQUEST_SAI1_A 36U /*!< DMAMUX SAI1 A request */ 00423 #define LL_DMAMUX_REQUEST_SAI1_B 37U /*!< DMAMUX SAI1 B request */ 00424 #define LL_DMAMUX_REQUEST_SAI2_A 38U /*!< DMAMUX SAI2 A request */ 00425 #define LL_DMAMUX_REQUEST_SAI2_B 39U /*!< DMAMUX SAI2 B request */ 00426 #define LL_DMAMUX_REQUEST_OSPI1 40U /*!< DMAMUX OCTOSPI1 request */ 00427 #define LL_DMAMUX_REQUEST_OSPI2 41U /*!< DMAMUX OCTOSPI2 request */ 00428 #define LL_DMAMUX_REQUEST_TIM1_CH1 42U /*!< DMAMUX TIM1 CH1 request */ 00429 #define LL_DMAMUX_REQUEST_TIM1_CH2 43U /*!< DMAMUX TIM1 CH2 request */ 00430 #define LL_DMAMUX_REQUEST_TIM1_CH3 44U /*!< DMAMUX TIM1 CH3 request */ 00431 #define LL_DMAMUX_REQUEST_TIM1_CH4 45U /*!< DMAMUX TIM1 CH4 request */ 00432 #define LL_DMAMUX_REQUEST_TIM1_UP 46U /*!< DMAMUX TIM1 UP request */ 00433 #define LL_DMAMUX_REQUEST_TIM1_TRIG 47U /*!< DMAMUX TIM1 TRIG request */ 00434 #define LL_DMAMUX_REQUEST_TIM1_COM 48U /*!< DMAMUX TIM1 COM request */ 00435 #define LL_DMAMUX_REQUEST_TIM8_CH1 49U /*!< DMAMUX TIM8 CH1 request */ 00436 #define LL_DMAMUX_REQUEST_TIM8_CH2 50U /*!< DMAMUX TIM8 CH2 request */ 00437 #define LL_DMAMUX_REQUEST_TIM8_CH3 51U /*!< DMAMUX TIM8 CH3 request */ 00438 #define LL_DMAMUX_REQUEST_TIM8_CH4 52U /*!< DMAMUX TIM8 CH4 request */ 00439 #define LL_DMAMUX_REQUEST_TIM8_UP 53U /*!< DMAMUX TIM8 UP request */ 00440 #define LL_DMAMUX_REQUEST_TIM8_TRIG 54U /*!< DMAMUX TIM8 TRIG request */ 00441 #define LL_DMAMUX_REQUEST_TIM8_COM 55U /*!< DMAMUX TIM8 COM request */ 00442 #define LL_DMAMUX_REQUEST_TIM2_CH1 56U /*!< DMAMUX TIM2 CH1 request */ 00443 #define LL_DMAMUX_REQUEST_TIM2_CH2 57U /*!< DMAMUX TIM2 CH2 request */ 00444 #define LL_DMAMUX_REQUEST_TIM2_CH3 58U /*!< DMAMUX TIM2 CH3 request */ 00445 #define LL_DMAMUX_REQUEST_TIM2_CH4 59U /*!< DMAMUX TIM2 CH4 request */ 00446 #define LL_DMAMUX_REQUEST_TIM2_UP 60U /*!< DMAMUX TIM2 UP request */ 00447 #define LL_DMAMUX_REQUEST_TIM3_CH1 61U /*!< DMAMUX TIM3 CH1 request */ 00448 #define LL_DMAMUX_REQUEST_TIM3_CH2 62U /*!< DMAMUX TIM3 CH2 request */ 00449 #define LL_DMAMUX_REQUEST_TIM3_CH3 63U /*!< DMAMUX TIM3 CH3 request */ 00450 #define LL_DMAMUX_REQUEST_TIM3_CH4 64U /*!< DMAMUX TIM3 CH4 request */ 00451 #define LL_DMAMUX_REQUEST_TIM3_UP 65U /*!< DMAMUX TIM3 UP request */ 00452 #define LL_DMAMUX_REQUEST_TIM3_TRIG 66U /*!< DMAMUX TIM3 TRIG request */ 00453 #define LL_DMAMUX_REQUEST_TIM4_CH1 67U /*!< DMAMUX TIM4 CH1 request */ 00454 #define LL_DMAMUX_REQUEST_TIM4_CH2 68U /*!< DMAMUX TIM4 CH2 request */ 00455 #define LL_DMAMUX_REQUEST_TIM4_CH3 69U /*!< DMAMUX TIM4 CH3 request */ 00456 #define LL_DMAMUX_REQUEST_TIM4_CH4 70U /*!< DMAMUX TIM4 CH4 request */ 00457 #define LL_DMAMUX_REQUEST_TIM4_UP 71U /*!< DMAMUX TIM4 UP request */ 00458 #define LL_DMAMUX_REQUEST_TIM5_CH1 72U /*!< DMAMUX TIM5 CH1 request */ 00459 #define LL_DMAMUX_REQUEST_TIM5_CH2 73U /*!< DMAMUX TIM5 CH2 request */ 00460 #define LL_DMAMUX_REQUEST_TIM5_CH3 74U /*!< DMAMUX TIM5 CH3 request */ 00461 #define LL_DMAMUX_REQUEST_TIM5_CH4 75U /*!< DMAMUX TIM5 CH4 request */ 00462 #define LL_DMAMUX_REQUEST_TIM5_UP 76U /*!< DMAMUX TIM5 UP request */ 00463 #define LL_DMAMUX_REQUEST_TIM5_TRIG 77U /*!< DMAMUX TIM5 TRIG request */ 00464 #define LL_DMAMUX_REQUEST_TIM15_CH1 78U /*!< DMAMUX TIM15 CH1 request */ 00465 #define LL_DMAMUX_REQUEST_TIM15_UP 79U /*!< DMAMUX TIM15 UP request */ 00466 #define LL_DMAMUX_REQUEST_TIM15_TRIG 80U /*!< DMAMUX TIM15 TRIG request */ 00467 #define LL_DMAMUX_REQUEST_TIM15_COM 81U /*!< DMAMUX TIM15 COM request */ 00468 #define LL_DMAMUX_REQUEST_TIM16_CH1 82U /*!< DMAMUX TIM16 CH1 request */ 00469 #define LL_DMAMUX_REQUEST_TIM16_UP 83U /*!< DMAMUX TIM16 UP request */ 00470 #define LL_DMAMUX_REQUEST_TIM17_CH1 84U /*!< DMAMUX TIM17 CH1 request */ 00471 #define LL_DMAMUX_REQUEST_TIM17_UP 85U /*!< DMAMUX TIM17 UP request */ 00472 #define LL_DMAMUX_REQUEST_DFSDM1_FLT0 86U /*!< DMAMUX DFSDM1_FLT0 request */ 00473 #define LL_DMAMUX_REQUEST_DFSDM1_FLT1 87U /*!< DMAMUX DFSDM1_FLT1 request */ 00474 #define LL_DMAMUX_REQUEST_DFSDM1_FLT2 88U /*!< DMAMUX DFSDM1_FLT2 request */ 00475 #define LL_DMAMUX_REQUEST_DFSDM1_FLT3 89U /*!< DMAMUX DFSDM1_FLT3 request */ 00476 #define LL_DMAMUX_REQUEST_DCMI 90U /*!< DMAMUX DCMI request */ 00477 #define LL_DMAMUX_REQUEST_AES_IN 91U /*!< DMAMUX AES_IN request */ 00478 #define LL_DMAMUX_REQUEST_AES_OUT 92U /*!< DMAMUX AES_OUT request */ 00479 #define LL_DMAMUX_REQUEST_HASH_IN 93U /*!< DMAMUX HASH_IN request */ 00480 /** 00481 * @} 00482 */ 00483 #else 00484 /** @defgroup DMA_LL_EC_REQUEST Transfer peripheral request 00485 * @{ 00486 */ 00487 #define LL_DMA_REQUEST_0 0x00000000U /*!< DMA peripheral request 0 */ 00488 #define LL_DMA_REQUEST_1 0x00000001U /*!< DMA peripheral request 1 */ 00489 #define LL_DMA_REQUEST_2 0x00000002U /*!< DMA peripheral request 2 */ 00490 #define LL_DMA_REQUEST_3 0x00000003U /*!< DMA peripheral request 3 */ 00491 #define LL_DMA_REQUEST_4 0x00000004U /*!< DMA peripheral request 4 */ 00492 #define LL_DMA_REQUEST_5 0x00000005U /*!< DMA peripheral request 5 */ 00493 #define LL_DMA_REQUEST_6 0x00000006U /*!< DMA peripheral request 6 */ 00494 #define LL_DMA_REQUEST_7 0x00000007U /*!< DMA peripheral request 7 */ 00495 /** 00496 * @} 00497 */ 00498 #endif /* DMAMUX1 */ 00499 00500 /** 00501 * @} 00502 */ 00503 00504 /* Exported macro ------------------------------------------------------------*/ 00505 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 00506 * @{ 00507 */ 00508 00509 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 00510 * @{ 00511 */ 00512 /** 00513 * @brief Write a value in DMA register 00514 * @param __INSTANCE__ DMA Instance 00515 * @param __REG__ Register to be written 00516 * @param __VALUE__ Value to be written in the register 00517 * @retval None 00518 */ 00519 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00520 00521 /** 00522 * @brief Read a value in DMA register 00523 * @param __INSTANCE__ DMA Instance 00524 * @param __REG__ Register to be read 00525 * @retval Register value 00526 */ 00527 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00528 /** 00529 * @} 00530 */ 00531 00532 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely 00533 * @{ 00534 */ 00535 /** 00536 * @brief Convert DMAx_Channely into DMAx 00537 * @param __CHANNEL_INSTANCE__ DMAx_Channely 00538 * @retval DMAx 00539 */ 00540 #if defined(DMA2) 00541 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ 00542 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) 00543 #else 00544 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) 00545 #endif 00546 00547 /** 00548 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y 00549 * @param __CHANNEL_INSTANCE__ DMAx_Channely 00550 * @retval LL_DMA_CHANNEL_y 00551 */ 00552 #if defined (DMA2) 00553 #if defined (DMA2_Channel6) && defined (DMA2_Channel7) 00554 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 00555 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00556 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00557 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00558 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00559 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00560 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00561 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00562 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00563 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00564 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00565 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 00566 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ 00567 LL_DMA_CHANNEL_7) 00568 #else 00569 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 00570 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00571 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00572 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00573 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00574 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00575 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00576 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00577 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00578 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00579 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00580 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 00581 LL_DMA_CHANNEL_7) 00582 #endif 00583 #else 00584 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ 00585 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ 00586 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ 00587 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ 00588 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ 00589 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ 00590 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ 00591 LL_DMA_CHANNEL_7) 00592 #endif 00593 00594 /** 00595 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely 00596 * @param __DMA_INSTANCE__ DMAx 00597 * @param __CHANNEL__ LL_DMA_CHANNEL_y 00598 * @retval DMAx_Channely 00599 */ 00600 #if defined (DMA2) 00601 #if defined (DMA2_Channel6) && defined (DMA2_Channel7) 00602 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ 00603 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ 00604 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ 00605 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ 00606 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ 00607 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ 00608 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ 00609 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ 00610 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ 00611 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ 00612 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ 00613 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ 00614 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ 00615 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ 00616 DMA2_Channel7) 00617 #else 00618 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ 00619 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ 00620 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ 00621 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ 00622 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ 00623 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ 00624 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ 00625 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ 00626 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ 00627 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ 00628 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ 00629 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ 00630 DMA1_Channel7) 00631 #endif 00632 #else 00633 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ 00634 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ 00635 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ 00636 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ 00637 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ 00638 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ 00639 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ 00640 DMA1_Channel7) 00641 #endif 00642 00643 /** 00644 * @} 00645 */ 00646 00647 /** 00648 * @} 00649 */ 00650 00651 /* Exported functions --------------------------------------------------------*/ 00652 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 00653 * @{ 00654 */ 00655 00656 /** @defgroup DMA_LL_EF_Configuration Configuration 00657 * @{ 00658 */ 00659 /** 00660 * @brief Enable DMA channel. 00661 * @rmtoll CCR EN LL_DMA_EnableChannel 00662 * @param DMAx DMAx Instance 00663 * @param Channel This parameter can be one of the following values: 00664 * @arg @ref LL_DMA_CHANNEL_1 00665 * @arg @ref LL_DMA_CHANNEL_2 00666 * @arg @ref LL_DMA_CHANNEL_3 00667 * @arg @ref LL_DMA_CHANNEL_4 00668 * @arg @ref LL_DMA_CHANNEL_5 00669 * @arg @ref LL_DMA_CHANNEL_6 00670 * @arg @ref LL_DMA_CHANNEL_7 00671 * @retval None 00672 */ 00673 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) 00674 { 00675 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); 00676 } 00677 00678 /** 00679 * @brief Disable DMA channel. 00680 * @rmtoll CCR EN LL_DMA_DisableChannel 00681 * @param DMAx DMAx Instance 00682 * @param Channel This parameter can be one of the following values: 00683 * @arg @ref LL_DMA_CHANNEL_1 00684 * @arg @ref LL_DMA_CHANNEL_2 00685 * @arg @ref LL_DMA_CHANNEL_3 00686 * @arg @ref LL_DMA_CHANNEL_4 00687 * @arg @ref LL_DMA_CHANNEL_5 00688 * @arg @ref LL_DMA_CHANNEL_6 00689 * @arg @ref LL_DMA_CHANNEL_7 00690 * @retval None 00691 */ 00692 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) 00693 { 00694 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); 00695 } 00696 00697 /** 00698 * @brief Check if DMA channel is enabled or disabled. 00699 * @rmtoll CCR EN LL_DMA_IsEnabledChannel 00700 * @param DMAx DMAx Instance 00701 * @param Channel This parameter can be one of the following values: 00702 * @arg @ref LL_DMA_CHANNEL_1 00703 * @arg @ref LL_DMA_CHANNEL_2 00704 * @arg @ref LL_DMA_CHANNEL_3 00705 * @arg @ref LL_DMA_CHANNEL_4 00706 * @arg @ref LL_DMA_CHANNEL_5 00707 * @arg @ref LL_DMA_CHANNEL_6 00708 * @arg @ref LL_DMA_CHANNEL_7 00709 * @retval State of bit (1 or 0). 00710 */ 00711 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) 00712 { 00713 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00714 DMA_CCR_EN) == (DMA_CCR_EN)); 00715 } 00716 00717 /** 00718 * @brief Configure all parameters link to DMA transfer. 00719 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n 00720 * CCR MEM2MEM LL_DMA_ConfigTransfer\n 00721 * CCR CIRC LL_DMA_ConfigTransfer\n 00722 * CCR PINC LL_DMA_ConfigTransfer\n 00723 * CCR MINC LL_DMA_ConfigTransfer\n 00724 * CCR PSIZE LL_DMA_ConfigTransfer\n 00725 * CCR MSIZE LL_DMA_ConfigTransfer\n 00726 * CCR PL LL_DMA_ConfigTransfer 00727 * @param DMAx DMAx Instance 00728 * @param Channel This parameter can be one of the following values: 00729 * @arg @ref LL_DMA_CHANNEL_1 00730 * @arg @ref LL_DMA_CHANNEL_2 00731 * @arg @ref LL_DMA_CHANNEL_3 00732 * @arg @ref LL_DMA_CHANNEL_4 00733 * @arg @ref LL_DMA_CHANNEL_5 00734 * @arg @ref LL_DMA_CHANNEL_6 00735 * @arg @ref LL_DMA_CHANNEL_7 00736 * @param Configuration This parameter must be a combination of all the following values: 00737 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00738 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR 00739 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 00740 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 00741 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD 00742 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD 00743 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH 00744 * @retval None 00745 */ 00746 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) 00747 { 00748 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00749 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, 00750 Configuration); 00751 } 00752 00753 /** 00754 * @brief Set Data transfer direction (read from peripheral or from memory). 00755 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n 00756 * CCR MEM2MEM LL_DMA_SetDataTransferDirection 00757 * @param DMAx DMAx Instance 00758 * @param Channel This parameter can be one of the following values: 00759 * @arg @ref LL_DMA_CHANNEL_1 00760 * @arg @ref LL_DMA_CHANNEL_2 00761 * @arg @ref LL_DMA_CHANNEL_3 00762 * @arg @ref LL_DMA_CHANNEL_4 00763 * @arg @ref LL_DMA_CHANNEL_5 00764 * @arg @ref LL_DMA_CHANNEL_6 00765 * @arg @ref LL_DMA_CHANNEL_7 00766 * @param Direction This parameter can be one of the following values: 00767 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00768 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00769 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00770 * @retval None 00771 */ 00772 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) 00773 { 00774 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00775 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); 00776 } 00777 00778 /** 00779 * @brief Get Data transfer direction (read from peripheral or from memory). 00780 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n 00781 * CCR MEM2MEM LL_DMA_GetDataTransferDirection 00782 * @param DMAx DMAx Instance 00783 * @param Channel This parameter can be one of the following values: 00784 * @arg @ref LL_DMA_CHANNEL_1 00785 * @arg @ref LL_DMA_CHANNEL_2 00786 * @arg @ref LL_DMA_CHANNEL_3 00787 * @arg @ref LL_DMA_CHANNEL_4 00788 * @arg @ref LL_DMA_CHANNEL_5 00789 * @arg @ref LL_DMA_CHANNEL_6 00790 * @arg @ref LL_DMA_CHANNEL_7 00791 * @retval Returned value can be one of the following values: 00792 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00793 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00794 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00795 */ 00796 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) 00797 { 00798 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00799 DMA_CCR_DIR | DMA_CCR_MEM2MEM)); 00800 } 00801 00802 /** 00803 * @brief Set DMA mode circular or normal. 00804 * @note The circular buffer mode cannot be used if the memory-to-memory 00805 * data transfer is configured on the selected Channel. 00806 * @rmtoll CCR CIRC LL_DMA_SetMode 00807 * @param DMAx DMAx Instance 00808 * @param Channel This parameter can be one of the following values: 00809 * @arg @ref LL_DMA_CHANNEL_1 00810 * @arg @ref LL_DMA_CHANNEL_2 00811 * @arg @ref LL_DMA_CHANNEL_3 00812 * @arg @ref LL_DMA_CHANNEL_4 00813 * @arg @ref LL_DMA_CHANNEL_5 00814 * @arg @ref LL_DMA_CHANNEL_6 00815 * @arg @ref LL_DMA_CHANNEL_7 00816 * @param Mode This parameter can be one of the following values: 00817 * @arg @ref LL_DMA_MODE_NORMAL 00818 * @arg @ref LL_DMA_MODE_CIRCULAR 00819 * @retval None 00820 */ 00821 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) 00822 { 00823 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, 00824 Mode); 00825 } 00826 00827 /** 00828 * @brief Get DMA mode circular or normal. 00829 * @rmtoll CCR CIRC LL_DMA_GetMode 00830 * @param DMAx DMAx Instance 00831 * @param Channel This parameter can be one of the following values: 00832 * @arg @ref LL_DMA_CHANNEL_1 00833 * @arg @ref LL_DMA_CHANNEL_2 00834 * @arg @ref LL_DMA_CHANNEL_3 00835 * @arg @ref LL_DMA_CHANNEL_4 00836 * @arg @ref LL_DMA_CHANNEL_5 00837 * @arg @ref LL_DMA_CHANNEL_6 00838 * @arg @ref LL_DMA_CHANNEL_7 00839 * @retval Returned value can be one of the following values: 00840 * @arg @ref LL_DMA_MODE_NORMAL 00841 * @arg @ref LL_DMA_MODE_CIRCULAR 00842 */ 00843 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) 00844 { 00845 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00846 DMA_CCR_CIRC)); 00847 } 00848 00849 /** 00850 * @brief Set Peripheral increment mode. 00851 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode 00852 * @param DMAx DMAx Instance 00853 * @param Channel This parameter can be one of the following values: 00854 * @arg @ref LL_DMA_CHANNEL_1 00855 * @arg @ref LL_DMA_CHANNEL_2 00856 * @arg @ref LL_DMA_CHANNEL_3 00857 * @arg @ref LL_DMA_CHANNEL_4 00858 * @arg @ref LL_DMA_CHANNEL_5 00859 * @arg @ref LL_DMA_CHANNEL_6 00860 * @arg @ref LL_DMA_CHANNEL_7 00861 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: 00862 * @arg @ref LL_DMA_PERIPH_INCREMENT 00863 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00864 * @retval None 00865 */ 00866 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) 00867 { 00868 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, 00869 PeriphOrM2MSrcIncMode); 00870 } 00871 00872 /** 00873 * @brief Get Peripheral increment mode. 00874 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode 00875 * @param DMAx DMAx Instance 00876 * @param Channel This parameter can be one of the following values: 00877 * @arg @ref LL_DMA_CHANNEL_1 00878 * @arg @ref LL_DMA_CHANNEL_2 00879 * @arg @ref LL_DMA_CHANNEL_3 00880 * @arg @ref LL_DMA_CHANNEL_4 00881 * @arg @ref LL_DMA_CHANNEL_5 00882 * @arg @ref LL_DMA_CHANNEL_6 00883 * @arg @ref LL_DMA_CHANNEL_7 00884 * @retval Returned value can be one of the following values: 00885 * @arg @ref LL_DMA_PERIPH_INCREMENT 00886 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00887 */ 00888 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) 00889 { 00890 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00891 DMA_CCR_PINC)); 00892 } 00893 00894 /** 00895 * @brief Set Memory increment mode. 00896 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode 00897 * @param DMAx DMAx Instance 00898 * @param Channel This parameter can be one of the following values: 00899 * @arg @ref LL_DMA_CHANNEL_1 00900 * @arg @ref LL_DMA_CHANNEL_2 00901 * @arg @ref LL_DMA_CHANNEL_3 00902 * @arg @ref LL_DMA_CHANNEL_4 00903 * @arg @ref LL_DMA_CHANNEL_5 00904 * @arg @ref LL_DMA_CHANNEL_6 00905 * @arg @ref LL_DMA_CHANNEL_7 00906 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: 00907 * @arg @ref LL_DMA_MEMORY_INCREMENT 00908 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00909 * @retval None 00910 */ 00911 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) 00912 { 00913 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, 00914 MemoryOrM2MDstIncMode); 00915 } 00916 00917 /** 00918 * @brief Get Memory increment mode. 00919 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode 00920 * @param DMAx DMAx Instance 00921 * @param Channel This parameter can be one of the following values: 00922 * @arg @ref LL_DMA_CHANNEL_1 00923 * @arg @ref LL_DMA_CHANNEL_2 00924 * @arg @ref LL_DMA_CHANNEL_3 00925 * @arg @ref LL_DMA_CHANNEL_4 00926 * @arg @ref LL_DMA_CHANNEL_5 00927 * @arg @ref LL_DMA_CHANNEL_6 00928 * @arg @ref LL_DMA_CHANNEL_7 00929 * @retval Returned value can be one of the following values: 00930 * @arg @ref LL_DMA_MEMORY_INCREMENT 00931 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00932 */ 00933 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) 00934 { 00935 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00936 DMA_CCR_MINC)); 00937 } 00938 00939 /** 00940 * @brief Set Peripheral size. 00941 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize 00942 * @param DMAx DMAx Instance 00943 * @param Channel This parameter can be one of the following values: 00944 * @arg @ref LL_DMA_CHANNEL_1 00945 * @arg @ref LL_DMA_CHANNEL_2 00946 * @arg @ref LL_DMA_CHANNEL_3 00947 * @arg @ref LL_DMA_CHANNEL_4 00948 * @arg @ref LL_DMA_CHANNEL_5 00949 * @arg @ref LL_DMA_CHANNEL_6 00950 * @arg @ref LL_DMA_CHANNEL_7 00951 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: 00952 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00953 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00954 * @arg @ref LL_DMA_PDATAALIGN_WORD 00955 * @retval None 00956 */ 00957 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) 00958 { 00959 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, 00960 PeriphOrM2MSrcDataSize); 00961 } 00962 00963 /** 00964 * @brief Get Peripheral size. 00965 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize 00966 * @param DMAx DMAx Instance 00967 * @param Channel This parameter can be one of the following values: 00968 * @arg @ref LL_DMA_CHANNEL_1 00969 * @arg @ref LL_DMA_CHANNEL_2 00970 * @arg @ref LL_DMA_CHANNEL_3 00971 * @arg @ref LL_DMA_CHANNEL_4 00972 * @arg @ref LL_DMA_CHANNEL_5 00973 * @arg @ref LL_DMA_CHANNEL_6 00974 * @arg @ref LL_DMA_CHANNEL_7 00975 * @retval Returned value can be one of the following values: 00976 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00977 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00978 * @arg @ref LL_DMA_PDATAALIGN_WORD 00979 */ 00980 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) 00981 { 00982 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 00983 DMA_CCR_PSIZE)); 00984 } 00985 00986 /** 00987 * @brief Set Memory size. 00988 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize 00989 * @param DMAx DMAx Instance 00990 * @param Channel This parameter can be one of the following values: 00991 * @arg @ref LL_DMA_CHANNEL_1 00992 * @arg @ref LL_DMA_CHANNEL_2 00993 * @arg @ref LL_DMA_CHANNEL_3 00994 * @arg @ref LL_DMA_CHANNEL_4 00995 * @arg @ref LL_DMA_CHANNEL_5 00996 * @arg @ref LL_DMA_CHANNEL_6 00997 * @arg @ref LL_DMA_CHANNEL_7 00998 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: 00999 * @arg @ref LL_DMA_MDATAALIGN_BYTE 01000 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 01001 * @arg @ref LL_DMA_MDATAALIGN_WORD 01002 * @retval None 01003 */ 01004 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) 01005 { 01006 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, 01007 MemoryOrM2MDstDataSize); 01008 } 01009 01010 /** 01011 * @brief Get Memory size. 01012 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize 01013 * @param DMAx DMAx Instance 01014 * @param Channel This parameter can be one of the following values: 01015 * @arg @ref LL_DMA_CHANNEL_1 01016 * @arg @ref LL_DMA_CHANNEL_2 01017 * @arg @ref LL_DMA_CHANNEL_3 01018 * @arg @ref LL_DMA_CHANNEL_4 01019 * @arg @ref LL_DMA_CHANNEL_5 01020 * @arg @ref LL_DMA_CHANNEL_6 01021 * @arg @ref LL_DMA_CHANNEL_7 01022 * @retval Returned value can be one of the following values: 01023 * @arg @ref LL_DMA_MDATAALIGN_BYTE 01024 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 01025 * @arg @ref LL_DMA_MDATAALIGN_WORD 01026 */ 01027 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) 01028 { 01029 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 01030 DMA_CCR_MSIZE)); 01031 } 01032 01033 /** 01034 * @brief Set Channel priority level. 01035 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel 01036 * @param DMAx DMAx Instance 01037 * @param Channel This parameter can be one of the following values: 01038 * @arg @ref LL_DMA_CHANNEL_1 01039 * @arg @ref LL_DMA_CHANNEL_2 01040 * @arg @ref LL_DMA_CHANNEL_3 01041 * @arg @ref LL_DMA_CHANNEL_4 01042 * @arg @ref LL_DMA_CHANNEL_5 01043 * @arg @ref LL_DMA_CHANNEL_6 01044 * @arg @ref LL_DMA_CHANNEL_7 01045 * @param Priority This parameter can be one of the following values: 01046 * @arg @ref LL_DMA_PRIORITY_LOW 01047 * @arg @ref LL_DMA_PRIORITY_MEDIUM 01048 * @arg @ref LL_DMA_PRIORITY_HIGH 01049 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 01050 * @retval None 01051 */ 01052 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) 01053 { 01054 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, 01055 Priority); 01056 } 01057 01058 /** 01059 * @brief Get Channel priority level. 01060 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel 01061 * @param DMAx DMAx Instance 01062 * @param Channel This parameter can be one of the following values: 01063 * @arg @ref LL_DMA_CHANNEL_1 01064 * @arg @ref LL_DMA_CHANNEL_2 01065 * @arg @ref LL_DMA_CHANNEL_3 01066 * @arg @ref LL_DMA_CHANNEL_4 01067 * @arg @ref LL_DMA_CHANNEL_5 01068 * @arg @ref LL_DMA_CHANNEL_6 01069 * @arg @ref LL_DMA_CHANNEL_7 01070 * @retval Returned value can be one of the following values: 01071 * @arg @ref LL_DMA_PRIORITY_LOW 01072 * @arg @ref LL_DMA_PRIORITY_MEDIUM 01073 * @arg @ref LL_DMA_PRIORITY_HIGH 01074 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 01075 */ 01076 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) 01077 { 01078 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 01079 DMA_CCR_PL)); 01080 } 01081 01082 /** 01083 * @brief Set Number of data to transfer. 01084 * @note This action has no effect if 01085 * channel is enabled. 01086 * @rmtoll CNDTR NDT LL_DMA_SetDataLength 01087 * @param DMAx DMAx Instance 01088 * @param Channel This parameter can be one of the following values: 01089 * @arg @ref LL_DMA_CHANNEL_1 01090 * @arg @ref LL_DMA_CHANNEL_2 01091 * @arg @ref LL_DMA_CHANNEL_3 01092 * @arg @ref LL_DMA_CHANNEL_4 01093 * @arg @ref LL_DMA_CHANNEL_5 01094 * @arg @ref LL_DMA_CHANNEL_6 01095 * @arg @ref LL_DMA_CHANNEL_7 01096 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF 01097 * @retval None 01098 */ 01099 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) 01100 { 01101 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, 01102 DMA_CNDTR_NDT, NbData); 01103 } 01104 01105 /** 01106 * @brief Get Number of data to transfer. 01107 * @note Once the channel is enabled, the return value indicate the 01108 * remaining bytes to be transmitted. 01109 * @rmtoll CNDTR NDT LL_DMA_GetDataLength 01110 * @param DMAx DMAx Instance 01111 * @param Channel This parameter can be one of the following values: 01112 * @arg @ref LL_DMA_CHANNEL_1 01113 * @arg @ref LL_DMA_CHANNEL_2 01114 * @arg @ref LL_DMA_CHANNEL_3 01115 * @arg @ref LL_DMA_CHANNEL_4 01116 * @arg @ref LL_DMA_CHANNEL_5 01117 * @arg @ref LL_DMA_CHANNEL_6 01118 * @arg @ref LL_DMA_CHANNEL_7 01119 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01120 */ 01121 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) 01122 { 01123 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, 01124 DMA_CNDTR_NDT)); 01125 } 01126 01127 /** 01128 * @brief Configure the Source and Destination addresses. 01129 * @note This API must not be called when the DMA channel is enabled. 01130 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). 01131 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n 01132 * CMAR MA LL_DMA_ConfigAddresses 01133 * @param DMAx DMAx Instance 01134 * @param Channel This parameter can be one of the following values: 01135 * @arg @ref LL_DMA_CHANNEL_1 01136 * @arg @ref LL_DMA_CHANNEL_2 01137 * @arg @ref LL_DMA_CHANNEL_3 01138 * @arg @ref LL_DMA_CHANNEL_4 01139 * @arg @ref LL_DMA_CHANNEL_5 01140 * @arg @ref LL_DMA_CHANNEL_6 01141 * @arg @ref LL_DMA_CHANNEL_7 01142 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01143 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01144 * @param Direction This parameter can be one of the following values: 01145 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 01146 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 01147 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 01148 * @retval None 01149 */ 01150 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, 01151 uint32_t DstAddress, uint32_t Direction) 01152 { 01153 /* Direction Memory to Periph */ 01154 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 01155 { 01156 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); 01157 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); 01158 } 01159 /* Direction Periph to Memory and Memory to Memory */ 01160 else 01161 { 01162 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); 01163 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); 01164 } 01165 } 01166 01167 /** 01168 * @brief Set the Memory address. 01169 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01170 * @note This API must not be called when the DMA channel is enabled. 01171 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress 01172 * @param DMAx DMAx Instance 01173 * @param Channel This parameter can be one of the following values: 01174 * @arg @ref LL_DMA_CHANNEL_1 01175 * @arg @ref LL_DMA_CHANNEL_2 01176 * @arg @ref LL_DMA_CHANNEL_3 01177 * @arg @ref LL_DMA_CHANNEL_4 01178 * @arg @ref LL_DMA_CHANNEL_5 01179 * @arg @ref LL_DMA_CHANNEL_6 01180 * @arg @ref LL_DMA_CHANNEL_7 01181 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01182 * @retval None 01183 */ 01184 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) 01185 { 01186 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); 01187 } 01188 01189 /** 01190 * @brief Set the Peripheral address. 01191 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01192 * @note This API must not be called when the DMA channel is enabled. 01193 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress 01194 * @param DMAx DMAx Instance 01195 * @param Channel This parameter can be one of the following values: 01196 * @arg @ref LL_DMA_CHANNEL_1 01197 * @arg @ref LL_DMA_CHANNEL_2 01198 * @arg @ref LL_DMA_CHANNEL_3 01199 * @arg @ref LL_DMA_CHANNEL_4 01200 * @arg @ref LL_DMA_CHANNEL_5 01201 * @arg @ref LL_DMA_CHANNEL_6 01202 * @arg @ref LL_DMA_CHANNEL_7 01203 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01204 * @retval None 01205 */ 01206 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) 01207 { 01208 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); 01209 } 01210 01211 /** 01212 * @brief Get Memory address. 01213 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01214 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress 01215 * @param DMAx DMAx Instance 01216 * @param Channel This parameter can be one of the following values: 01217 * @arg @ref LL_DMA_CHANNEL_1 01218 * @arg @ref LL_DMA_CHANNEL_2 01219 * @arg @ref LL_DMA_CHANNEL_3 01220 * @arg @ref LL_DMA_CHANNEL_4 01221 * @arg @ref LL_DMA_CHANNEL_5 01222 * @arg @ref LL_DMA_CHANNEL_6 01223 * @arg @ref LL_DMA_CHANNEL_7 01224 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01225 */ 01226 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) 01227 { 01228 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); 01229 } 01230 01231 /** 01232 * @brief Get Peripheral address. 01233 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01234 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress 01235 * @param DMAx DMAx Instance 01236 * @param Channel This parameter can be one of the following values: 01237 * @arg @ref LL_DMA_CHANNEL_1 01238 * @arg @ref LL_DMA_CHANNEL_2 01239 * @arg @ref LL_DMA_CHANNEL_3 01240 * @arg @ref LL_DMA_CHANNEL_4 01241 * @arg @ref LL_DMA_CHANNEL_5 01242 * @arg @ref LL_DMA_CHANNEL_6 01243 * @arg @ref LL_DMA_CHANNEL_7 01244 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01245 */ 01246 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) 01247 { 01248 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); 01249 } 01250 01251 /** 01252 * @brief Set the Memory to Memory Source address. 01253 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01254 * @note This API must not be called when the DMA channel is enabled. 01255 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress 01256 * @param DMAx DMAx Instance 01257 * @param Channel This parameter can be one of the following values: 01258 * @arg @ref LL_DMA_CHANNEL_1 01259 * @arg @ref LL_DMA_CHANNEL_2 01260 * @arg @ref LL_DMA_CHANNEL_3 01261 * @arg @ref LL_DMA_CHANNEL_4 01262 * @arg @ref LL_DMA_CHANNEL_5 01263 * @arg @ref LL_DMA_CHANNEL_6 01264 * @arg @ref LL_DMA_CHANNEL_7 01265 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01266 * @retval None 01267 */ 01268 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) 01269 { 01270 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); 01271 } 01272 01273 /** 01274 * @brief Set the Memory to Memory Destination address. 01275 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01276 * @note This API must not be called when the DMA channel is enabled. 01277 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress 01278 * @param DMAx DMAx Instance 01279 * @param Channel This parameter can be one of the following values: 01280 * @arg @ref LL_DMA_CHANNEL_1 01281 * @arg @ref LL_DMA_CHANNEL_2 01282 * @arg @ref LL_DMA_CHANNEL_3 01283 * @arg @ref LL_DMA_CHANNEL_4 01284 * @arg @ref LL_DMA_CHANNEL_5 01285 * @arg @ref LL_DMA_CHANNEL_6 01286 * @arg @ref LL_DMA_CHANNEL_7 01287 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01288 * @retval None 01289 */ 01290 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) 01291 { 01292 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); 01293 } 01294 01295 /** 01296 * @brief Get the Memory to Memory Source address. 01297 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01298 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress 01299 * @param DMAx DMAx Instance 01300 * @param Channel This parameter can be one of the following values: 01301 * @arg @ref LL_DMA_CHANNEL_1 01302 * @arg @ref LL_DMA_CHANNEL_2 01303 * @arg @ref LL_DMA_CHANNEL_3 01304 * @arg @ref LL_DMA_CHANNEL_4 01305 * @arg @ref LL_DMA_CHANNEL_5 01306 * @arg @ref LL_DMA_CHANNEL_6 01307 * @arg @ref LL_DMA_CHANNEL_7 01308 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01309 */ 01310 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) 01311 { 01312 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); 01313 } 01314 01315 /** 01316 * @brief Get the Memory to Memory Destination address. 01317 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01318 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress 01319 * @param DMAx DMAx Instance 01320 * @param Channel This parameter can be one of the following values: 01321 * @arg @ref LL_DMA_CHANNEL_1 01322 * @arg @ref LL_DMA_CHANNEL_2 01323 * @arg @ref LL_DMA_CHANNEL_3 01324 * @arg @ref LL_DMA_CHANNEL_4 01325 * @arg @ref LL_DMA_CHANNEL_5 01326 * @arg @ref LL_DMA_CHANNEL_6 01327 * @arg @ref LL_DMA_CHANNEL_7 01328 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF 01329 */ 01330 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) 01331 { 01332 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); 01333 } 01334 01335 #if defined(DMAMUX1) 01336 /** 01337 * @brief Set DMA request for DMA Channels on DMAMUX Channel x. 01338 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. 01339 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. 01340 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest 01341 * @param DMAx DMAx Instance 01342 * @param Channel This parameter can be one of the following values: 01343 * @arg @ref LL_DMA_CHANNEL_1 01344 * @arg @ref LL_DMA_CHANNEL_2 01345 * @arg @ref LL_DMA_CHANNEL_3 01346 * @arg @ref LL_DMA_CHANNEL_4 01347 * @arg @ref LL_DMA_CHANNEL_5 01348 * @arg @ref LL_DMA_CHANNEL_6 01349 * @arg @ref LL_DMA_CHANNEL_7 01350 * @param Request This parameter can be one of the following values: 01351 * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM 01352 * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 01353 * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 01354 * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 01355 * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 01356 * @arg @ref LL_DMAMUX_REQUEST_ADC1 01357 * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 01358 * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 01359 * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP 01360 * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP 01361 * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX 01362 * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX 01363 * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX 01364 * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX 01365 * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX 01366 * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX 01367 * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX 01368 * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX 01369 * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX 01370 * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX 01371 * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX 01372 * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX 01373 * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX 01374 * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX 01375 * @arg @ref LL_DMAMUX_REQUEST_USART1_RX 01376 * @arg @ref LL_DMAMUX_REQUEST_USART1_TX 01377 * @arg @ref LL_DMAMUX_REQUEST_USART2_RX 01378 * @arg @ref LL_DMAMUX_REQUEST_USART2_TX 01379 * @arg @ref LL_DMAMUX_REQUEST_USART3_RX 01380 * @arg @ref LL_DMAMUX_REQUEST_USART3_TX 01381 * @arg @ref LL_DMAMUX_REQUEST_UART4_RX 01382 * @arg @ref LL_DMAMUX_REQUEST_UART4_TX 01383 * @arg @ref LL_DMAMUX_REQUEST_UART5_RX 01384 * @arg @ref LL_DMAMUX_REQUEST_UART5_TX 01385 * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX 01386 * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX 01387 * @arg @ref LL_DMAMUX_REQUEST_SAI1_A 01388 * @arg @ref LL_DMAMUX_REQUEST_SAI1_B 01389 * @arg @ref LL_DMAMUX_REQUEST_SAI2_A 01390 * @arg @ref LL_DMAMUX_REQUEST_SAI2_B 01391 * @arg @ref LL_DMAMUX_REQUEST_OSPI1 01392 * @arg @ref LL_DMAMUX_REQUEST_OSPI2 01393 * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 01394 * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 01395 * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 01396 * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 01397 * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP 01398 * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG 01399 * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM 01400 * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 01401 * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 01402 * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 01403 * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 01404 * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP 01405 * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG 01406 * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM 01407 * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 01408 * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 01409 * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 01410 * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 01411 * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP 01412 * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 01413 * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 01414 * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 01415 * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 01416 * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP 01417 * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG 01418 * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 01419 * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 01420 * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 01421 * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 01422 * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP 01423 * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 01424 * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 01425 * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 01426 * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 01427 * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP 01428 * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG 01429 * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 01430 * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP 01431 * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG 01432 * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM 01433 * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 01434 * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP 01435 * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 01436 * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP 01437 * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 01438 * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 01439 * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 01440 * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 01441 * @arg @ref LL_DMAMUX_REQUEST_DCMI 01442 * @arg @ref LL_DMAMUX_REQUEST_AES_IN 01443 * @arg @ref LL_DMAMUX_REQUEST_AES_OUT 01444 * @arg @ref LL_DMAMUX_REQUEST_HASH_IN 01445 * @retval None 01446 */ 01447 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) 01448 { 01449 MODIFY_REG(((DMAMUX_Channel_TypeDef*)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); 01450 } 01451 01452 /** 01453 * @brief Get DMA request for DMA Channels on DMAMUX Channel x. 01454 * @note DMAMUX channel 0 to 6 are mapped to DMA1 channel 1 to 7. 01455 * DMAMUX channel 7 to 13 are mapped to DMA2 channel 1 to 7. 01456 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest 01457 * @param DMAx DMAx Instance 01458 * @param Channel This parameter can be one of the following values: 01459 * @arg @ref LL_DMA_CHANNEL_1 01460 * @arg @ref LL_DMA_CHANNEL_2 01461 * @arg @ref LL_DMA_CHANNEL_3 01462 * @arg @ref LL_DMA_CHANNEL_4 01463 * @arg @ref LL_DMA_CHANNEL_5 01464 * @arg @ref LL_DMA_CHANNEL_6 01465 * @arg @ref LL_DMA_CHANNEL_7 01466 * @retval Returned value can be one of the following values: 01467 * @arg @ref LL_DMAMUX_REQUEST_MEM2MEM 01468 * @arg @ref LL_DMAMUX_REQUEST_GENERATOR0 01469 * @arg @ref LL_DMAMUX_REQUEST_GENERATOR1 01470 * @arg @ref LL_DMAMUX_REQUEST_GENERATOR2 01471 * @arg @ref LL_DMAMUX_REQUEST_GENERATOR3 01472 * @arg @ref LL_DMAMUX_REQUEST_ADC1 01473 * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH1 01474 * @arg @ref LL_DMAMUX_REQUEST_DAC1_CH2 01475 * @arg @ref LL_DMAMUX_REQUEST_TIM6_UP 01476 * @arg @ref LL_DMAMUX_REQUEST_TIM7_UP 01477 * @arg @ref LL_DMAMUX_REQUEST_SPI1_RX 01478 * @arg @ref LL_DMAMUX_REQUEST_SPI1_TX 01479 * @arg @ref LL_DMAMUX_REQUEST_SPI2_RX 01480 * @arg @ref LL_DMAMUX_REQUEST_SPI2_TX 01481 * @arg @ref LL_DMAMUX_REQUEST_SPI3_RX 01482 * @arg @ref LL_DMAMUX_REQUEST_SPI3_TX 01483 * @arg @ref LL_DMAMUX_REQUEST_I2C1_RX 01484 * @arg @ref LL_DMAMUX_REQUEST_I2C1_TX 01485 * @arg @ref LL_DMAMUX_REQUEST_I2C2_RX 01486 * @arg @ref LL_DMAMUX_REQUEST_I2C2_TX 01487 * @arg @ref LL_DMAMUX_REQUEST_I2C3_RX 01488 * @arg @ref LL_DMAMUX_REQUEST_I2C3_TX 01489 * @arg @ref LL_DMAMUX_REQUEST_I2C4_RX 01490 * @arg @ref LL_DMAMUX_REQUEST_I2C4_TX 01491 * @arg @ref LL_DMAMUX_REQUEST_USART1_RX 01492 * @arg @ref LL_DMAMUX_REQUEST_USART1_TX 01493 * @arg @ref LL_DMAMUX_REQUEST_USART2_RX 01494 * @arg @ref LL_DMAMUX_REQUEST_USART2_TX 01495 * @arg @ref LL_DMAMUX_REQUEST_USART3_RX 01496 * @arg @ref LL_DMAMUX_REQUEST_USART3_TX 01497 * @arg @ref LL_DMAMUX_REQUEST_UART4_RX 01498 * @arg @ref LL_DMAMUX_REQUEST_UART4_TX 01499 * @arg @ref LL_DMAMUX_REQUEST_UART5_RX 01500 * @arg @ref LL_DMAMUX_REQUEST_UART5_TX 01501 * @arg @ref LL_DMAMUX_REQUEST_LPUART1_RX 01502 * @arg @ref LL_DMAMUX_REQUEST_LPUART1_TX 01503 * @arg @ref LL_DMAMUX_REQUEST_SAI1_A 01504 * @arg @ref LL_DMAMUX_REQUEST_SAI1_B 01505 * @arg @ref LL_DMAMUX_REQUEST_SAI2_A 01506 * @arg @ref LL_DMAMUX_REQUEST_SAI2_B 01507 * @arg @ref LL_DMAMUX_REQUEST_OSPI1 01508 * @arg @ref LL_DMAMUX_REQUEST_OSPI2 01509 * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH1 01510 * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH2 01511 * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH3 01512 * @arg @ref LL_DMAMUX_REQUEST_TIM1_CH4 01513 * @arg @ref LL_DMAMUX_REQUEST_TIM1_UP 01514 * @arg @ref LL_DMAMUX_REQUEST_TIM1_TRIG 01515 * @arg @ref LL_DMAMUX_REQUEST_TIM1_COM 01516 * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH1 01517 * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH2 01518 * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH3 01519 * @arg @ref LL_DMAMUX_REQUEST_TIM8_CH4 01520 * @arg @ref LL_DMAMUX_REQUEST_TIM8_UP 01521 * @arg @ref LL_DMAMUX_REQUEST_TIM8_TRIG 01522 * @arg @ref LL_DMAMUX_REQUEST_TIM8_COM 01523 * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH1 01524 * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH2 01525 * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH3 01526 * @arg @ref LL_DMAMUX_REQUEST_TIM2_CH4 01527 * @arg @ref LL_DMAMUX_REQUEST_TIM2_UP 01528 * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH1 01529 * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH2 01530 * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH3 01531 * @arg @ref LL_DMAMUX_REQUEST_TIM3_CH4 01532 * @arg @ref LL_DMAMUX_REQUEST_TIM3_UP 01533 * @arg @ref LL_DMAMUX_REQUEST_TIM3_TRIG 01534 * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH1 01535 * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH2 01536 * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH3 01537 * @arg @ref LL_DMAMUX_REQUEST_TIM4_CH4 01538 * @arg @ref LL_DMAMUX_REQUEST_TIM4_UP 01539 * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH1 01540 * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH2 01541 * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH3 01542 * @arg @ref LL_DMAMUX_REQUEST_TIM5_CH4 01543 * @arg @ref LL_DMAMUX_REQUEST_TIM5_UP 01544 * @arg @ref LL_DMAMUX_REQUEST_TIM5_TRIG 01545 * @arg @ref LL_DMAMUX_REQUEST_TIM15_CH1 01546 * @arg @ref LL_DMAMUX_REQUEST_TIM15_UP 01547 * @arg @ref LL_DMAMUX_REQUEST_TIM15_TRIG 01548 * @arg @ref LL_DMAMUX_REQUEST_TIM15_COM 01549 * @arg @ref LL_DMAMUX_REQUEST_TIM16_CH1 01550 * @arg @ref LL_DMAMUX_REQUEST_TIM16_UP 01551 * @arg @ref LL_DMAMUX_REQUEST_TIM17_CH1 01552 * @arg @ref LL_DMAMUX_REQUEST_TIM17_UP 01553 * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT0 01554 * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT1 01555 * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT2 01556 * @arg @ref LL_DMAMUX_REQUEST_DFSDM1_FLT3 01557 * @arg @ref LL_DMAMUX_REQUEST_DCMI 01558 * @arg @ref LL_DMAMUX_REQUEST_AES_IN 01559 * @arg @ref LL_DMAMUX_REQUEST_AES_OUT 01560 * @arg @ref LL_DMAMUX_REQUEST_HASH_IN 01561 */ 01562 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) 01563 { 01564 return (READ_BIT(((DMAMUX_Channel_TypeDef*)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE*(Channel-1U)) + (uint32_t)(DMAMUX_CCR_SIZE*__LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID)); 01565 } 01566 #else 01567 /** 01568 * @brief Set DMA request for DMA instance on Channel x. 01569 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection. 01570 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n 01571 * CSELR C2S LL_DMA_SetPeriphRequest\n 01572 * CSELR C3S LL_DMA_SetPeriphRequest\n 01573 * CSELR C4S LL_DMA_SetPeriphRequest\n 01574 * CSELR C5S LL_DMA_SetPeriphRequest\n 01575 * CSELR C6S LL_DMA_SetPeriphRequest\n 01576 * CSELR C7S LL_DMA_SetPeriphRequest 01577 * @param DMAx DMAx Instance 01578 * @param Channel This parameter can be one of the following values: 01579 * @arg @ref LL_DMA_CHANNEL_1 01580 * @arg @ref LL_DMA_CHANNEL_2 01581 * @arg @ref LL_DMA_CHANNEL_3 01582 * @arg @ref LL_DMA_CHANNEL_4 01583 * @arg @ref LL_DMA_CHANNEL_5 01584 * @arg @ref LL_DMA_CHANNEL_6 01585 * @arg @ref LL_DMA_CHANNEL_7 01586 * @param PeriphRequest This parameter can be one of the following values: 01587 * @arg @ref LL_DMA_REQUEST_0 01588 * @arg @ref LL_DMA_REQUEST_1 01589 * @arg @ref LL_DMA_REQUEST_2 01590 * @arg @ref LL_DMA_REQUEST_3 01591 * @arg @ref LL_DMA_REQUEST_4 01592 * @arg @ref LL_DMA_REQUEST_5 01593 * @arg @ref LL_DMA_REQUEST_6 01594 * @arg @ref LL_DMA_REQUEST_7 01595 * @retval None 01596 */ 01597 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest) 01598 { 01599 MODIFY_REG(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, 01600 DMA_CSELR_C1S << ((Channel - 1U) * 4U), PeriphRequest << DMA_POSITION_CSELR_CXS); 01601 } 01602 01603 /** 01604 * @brief Get DMA request for DMA instance on Channel x. 01605 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n 01606 * CSELR C2S LL_DMA_GetPeriphRequest\n 01607 * CSELR C3S LL_DMA_GetPeriphRequest\n 01608 * CSELR C4S LL_DMA_GetPeriphRequest\n 01609 * CSELR C5S LL_DMA_GetPeriphRequest\n 01610 * CSELR C6S LL_DMA_GetPeriphRequest\n 01611 * CSELR C7S LL_DMA_GetPeriphRequest 01612 * @param DMAx DMAx Instance 01613 * @param Channel This parameter can be one of the following values: 01614 * @arg @ref LL_DMA_CHANNEL_1 01615 * @arg @ref LL_DMA_CHANNEL_2 01616 * @arg @ref LL_DMA_CHANNEL_3 01617 * @arg @ref LL_DMA_CHANNEL_4 01618 * @arg @ref LL_DMA_CHANNEL_5 01619 * @arg @ref LL_DMA_CHANNEL_6 01620 * @arg @ref LL_DMA_CHANNEL_7 01621 * @retval Returned value can be one of the following values: 01622 * @arg @ref LL_DMA_REQUEST_0 01623 * @arg @ref LL_DMA_REQUEST_1 01624 * @arg @ref LL_DMA_REQUEST_2 01625 * @arg @ref LL_DMA_REQUEST_3 01626 * @arg @ref LL_DMA_REQUEST_4 01627 * @arg @ref LL_DMA_REQUEST_5 01628 * @arg @ref LL_DMA_REQUEST_6 01629 * @arg @ref LL_DMA_REQUEST_7 01630 */ 01631 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) 01632 { 01633 return (READ_BIT(((DMA_Request_TypeDef *)((uint32_t)((uint32_t)DMAx + DMA_CSELR_OFFSET)))->CSELR, 01634 DMA_CSELR_C1S << ((Channel - 1U) * 4U)) >> DMA_POSITION_CSELR_CXS); 01635 } 01636 #endif /* DMAMUX1 */ 01637 01638 /** 01639 * @} 01640 */ 01641 01642 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 01643 * @{ 01644 */ 01645 01646 /** 01647 * @brief Get Channel 1 global interrupt flag. 01648 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 01649 * @param DMAx DMAx Instance 01650 * @retval State of bit (1 or 0). 01651 */ 01652 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) 01653 { 01654 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); 01655 } 01656 01657 /** 01658 * @brief Get Channel 2 global interrupt flag. 01659 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 01660 * @param DMAx DMAx Instance 01661 * @retval State of bit (1 or 0). 01662 */ 01663 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) 01664 { 01665 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); 01666 } 01667 01668 /** 01669 * @brief Get Channel 3 global interrupt flag. 01670 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 01671 * @param DMAx DMAx Instance 01672 * @retval State of bit (1 or 0). 01673 */ 01674 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) 01675 { 01676 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); 01677 } 01678 01679 /** 01680 * @brief Get Channel 4 global interrupt flag. 01681 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4 01682 * @param DMAx DMAx Instance 01683 * @retval State of bit (1 or 0). 01684 */ 01685 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) 01686 { 01687 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)); 01688 } 01689 01690 /** 01691 * @brief Get Channel 5 global interrupt flag. 01692 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5 01693 * @param DMAx DMAx Instance 01694 * @retval State of bit (1 or 0). 01695 */ 01696 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) 01697 { 01698 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)); 01699 } 01700 01701 /** 01702 * @brief Get Channel 6 global interrupt flag. 01703 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6 01704 * @param DMAx DMAx Instance 01705 * @retval State of bit (1 or 0). 01706 */ 01707 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) 01708 { 01709 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)); 01710 } 01711 01712 /** 01713 * @brief Get Channel 7 global interrupt flag. 01714 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7 01715 * @param DMAx DMAx Instance 01716 * @retval State of bit (1 or 0). 01717 */ 01718 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) 01719 { 01720 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)); 01721 } 01722 01723 /** 01724 * @brief Get Channel 1 transfer complete flag. 01725 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 01726 * @param DMAx DMAx Instance 01727 * @retval State of bit (1 or 0). 01728 */ 01729 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 01730 { 01731 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); 01732 } 01733 01734 /** 01735 * @brief Get Channel 2 transfer complete flag. 01736 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 01737 * @param DMAx DMAx Instance 01738 * @retval State of bit (1 or 0). 01739 */ 01740 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 01741 { 01742 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); 01743 } 01744 01745 /** 01746 * @brief Get Channel 3 transfer complete flag. 01747 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 01748 * @param DMAx DMAx Instance 01749 * @retval State of bit (1 or 0). 01750 */ 01751 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 01752 { 01753 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); 01754 } 01755 01756 /** 01757 * @brief Get Channel 4 transfer complete flag. 01758 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4 01759 * @param DMAx DMAx Instance 01760 * @retval State of bit (1 or 0). 01761 */ 01762 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 01763 { 01764 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)); 01765 } 01766 01767 /** 01768 * @brief Get Channel 5 transfer complete flag. 01769 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5 01770 * @param DMAx DMAx Instance 01771 * @retval State of bit (1 or 0). 01772 */ 01773 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 01774 { 01775 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)); 01776 } 01777 01778 /** 01779 * @brief Get Channel 6 transfer complete flag. 01780 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6 01781 * @param DMAx DMAx Instance 01782 * @retval State of bit (1 or 0). 01783 */ 01784 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 01785 { 01786 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)); 01787 } 01788 01789 /** 01790 * @brief Get Channel 7 transfer complete flag. 01791 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7 01792 * @param DMAx DMAx Instance 01793 * @retval State of bit (1 or 0). 01794 */ 01795 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 01796 { 01797 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)); 01798 } 01799 01800 /** 01801 * @brief Get Channel 1 half transfer flag. 01802 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 01803 * @param DMAx DMAx Instance 01804 * @retval State of bit (1 or 0). 01805 */ 01806 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 01807 { 01808 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); 01809 } 01810 01811 /** 01812 * @brief Get Channel 2 half transfer flag. 01813 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 01814 * @param DMAx DMAx Instance 01815 * @retval State of bit (1 or 0). 01816 */ 01817 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 01818 { 01819 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); 01820 } 01821 01822 /** 01823 * @brief Get Channel 3 half transfer flag. 01824 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 01825 * @param DMAx DMAx Instance 01826 * @retval State of bit (1 or 0). 01827 */ 01828 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 01829 { 01830 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); 01831 } 01832 01833 /** 01834 * @brief Get Channel 4 half transfer flag. 01835 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4 01836 * @param DMAx DMAx Instance 01837 * @retval State of bit (1 or 0). 01838 */ 01839 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 01840 { 01841 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)); 01842 } 01843 01844 /** 01845 * @brief Get Channel 5 half transfer flag. 01846 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5 01847 * @param DMAx DMAx Instance 01848 * @retval State of bit (1 or 0). 01849 */ 01850 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 01851 { 01852 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)); 01853 } 01854 01855 /** 01856 * @brief Get Channel 6 half transfer flag. 01857 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6 01858 * @param DMAx DMAx Instance 01859 * @retval State of bit (1 or 0). 01860 */ 01861 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 01862 { 01863 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)); 01864 } 01865 01866 /** 01867 * @brief Get Channel 7 half transfer flag. 01868 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7 01869 * @param DMAx DMAx Instance 01870 * @retval State of bit (1 or 0). 01871 */ 01872 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 01873 { 01874 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)); 01875 } 01876 01877 /** 01878 * @brief Get Channel 1 transfer error flag. 01879 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 01880 * @param DMAx DMAx Instance 01881 * @retval State of bit (1 or 0). 01882 */ 01883 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 01884 { 01885 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); 01886 } 01887 01888 /** 01889 * @brief Get Channel 2 transfer error flag. 01890 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 01891 * @param DMAx DMAx Instance 01892 * @retval State of bit (1 or 0). 01893 */ 01894 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 01895 { 01896 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); 01897 } 01898 01899 /** 01900 * @brief Get Channel 3 transfer error flag. 01901 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 01902 * @param DMAx DMAx Instance 01903 * @retval State of bit (1 or 0). 01904 */ 01905 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 01906 { 01907 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); 01908 } 01909 01910 /** 01911 * @brief Get Channel 4 transfer error flag. 01912 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4 01913 * @param DMAx DMAx Instance 01914 * @retval State of bit (1 or 0). 01915 */ 01916 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 01917 { 01918 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)); 01919 } 01920 01921 /** 01922 * @brief Get Channel 5 transfer error flag. 01923 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5 01924 * @param DMAx DMAx Instance 01925 * @retval State of bit (1 or 0). 01926 */ 01927 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 01928 { 01929 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)); 01930 } 01931 01932 /** 01933 * @brief Get Channel 6 transfer error flag. 01934 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6 01935 * @param DMAx DMAx Instance 01936 * @retval State of bit (1 or 0). 01937 */ 01938 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 01939 { 01940 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)); 01941 } 01942 01943 /** 01944 * @brief Get Channel 7 transfer error flag. 01945 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7 01946 * @param DMAx DMAx Instance 01947 * @retval State of bit (1 or 0). 01948 */ 01949 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 01950 { 01951 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)); 01952 } 01953 01954 /** 01955 * @brief Clear Channel 1 global interrupt flag. 01956 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 01957 * @param DMAx DMAx Instance 01958 * @retval None 01959 */ 01960 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) 01961 { 01962 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); 01963 } 01964 01965 /** 01966 * @brief Clear Channel 2 global interrupt flag. 01967 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 01968 * @param DMAx DMAx Instance 01969 * @retval None 01970 */ 01971 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) 01972 { 01973 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); 01974 } 01975 01976 /** 01977 * @brief Clear Channel 3 global interrupt flag. 01978 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 01979 * @param DMAx DMAx Instance 01980 * @retval None 01981 */ 01982 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) 01983 { 01984 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); 01985 } 01986 01987 /** 01988 * @brief Clear Channel 4 global interrupt flag. 01989 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4 01990 * @param DMAx DMAx Instance 01991 * @retval None 01992 */ 01993 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx) 01994 { 01995 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4); 01996 } 01997 01998 /** 01999 * @brief Clear Channel 5 global interrupt flag. 02000 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5 02001 * @param DMAx DMAx Instance 02002 * @retval None 02003 */ 02004 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx) 02005 { 02006 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5); 02007 } 02008 02009 /** 02010 * @brief Clear Channel 6 global interrupt flag. 02011 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6 02012 * @param DMAx DMAx Instance 02013 * @retval None 02014 */ 02015 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx) 02016 { 02017 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6); 02018 } 02019 02020 /** 02021 * @brief Clear Channel 7 global interrupt flag. 02022 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7 02023 * @param DMAx DMAx Instance 02024 * @retval None 02025 */ 02026 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx) 02027 { 02028 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7); 02029 } 02030 02031 /** 02032 * @brief Clear Channel 1 transfer complete flag. 02033 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 02034 * @param DMAx DMAx Instance 02035 * @retval None 02036 */ 02037 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 02038 { 02039 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); 02040 } 02041 02042 /** 02043 * @brief Clear Channel 2 transfer complete flag. 02044 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 02045 * @param DMAx DMAx Instance 02046 * @retval None 02047 */ 02048 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 02049 { 02050 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); 02051 } 02052 02053 /** 02054 * @brief Clear Channel 3 transfer complete flag. 02055 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 02056 * @param DMAx DMAx Instance 02057 * @retval None 02058 */ 02059 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 02060 { 02061 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); 02062 } 02063 02064 /** 02065 * @brief Clear Channel 4 transfer complete flag. 02066 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4 02067 * @param DMAx DMAx Instance 02068 * @retval None 02069 */ 02070 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 02071 { 02072 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4); 02073 } 02074 02075 /** 02076 * @brief Clear Channel 5 transfer complete flag. 02077 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5 02078 * @param DMAx DMAx Instance 02079 * @retval None 02080 */ 02081 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 02082 { 02083 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5); 02084 } 02085 02086 /** 02087 * @brief Clear Channel 6 transfer complete flag. 02088 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6 02089 * @param DMAx DMAx Instance 02090 * @retval None 02091 */ 02092 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 02093 { 02094 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6); 02095 } 02096 02097 /** 02098 * @brief Clear Channel 7 transfer complete flag. 02099 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7 02100 * @param DMAx DMAx Instance 02101 * @retval None 02102 */ 02103 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 02104 { 02105 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7); 02106 } 02107 02108 /** 02109 * @brief Clear Channel 1 half transfer flag. 02110 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 02111 * @param DMAx DMAx Instance 02112 * @retval None 02113 */ 02114 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 02115 { 02116 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); 02117 } 02118 02119 /** 02120 * @brief Clear Channel 2 half transfer flag. 02121 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 02122 * @param DMAx DMAx Instance 02123 * @retval None 02124 */ 02125 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 02126 { 02127 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); 02128 } 02129 02130 /** 02131 * @brief Clear Channel 3 half transfer flag. 02132 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 02133 * @param DMAx DMAx Instance 02134 * @retval None 02135 */ 02136 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 02137 { 02138 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); 02139 } 02140 02141 /** 02142 * @brief Clear Channel 4 half transfer flag. 02143 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4 02144 * @param DMAx DMAx Instance 02145 * @retval None 02146 */ 02147 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 02148 { 02149 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4); 02150 } 02151 02152 /** 02153 * @brief Clear Channel 5 half transfer flag. 02154 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5 02155 * @param DMAx DMAx Instance 02156 * @retval None 02157 */ 02158 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 02159 { 02160 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5); 02161 } 02162 02163 /** 02164 * @brief Clear Channel 6 half transfer flag. 02165 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6 02166 * @param DMAx DMAx Instance 02167 * @retval None 02168 */ 02169 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 02170 { 02171 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6); 02172 } 02173 02174 /** 02175 * @brief Clear Channel 7 half transfer flag. 02176 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7 02177 * @param DMAx DMAx Instance 02178 * @retval None 02179 */ 02180 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 02181 { 02182 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7); 02183 } 02184 02185 /** 02186 * @brief Clear Channel 1 transfer error flag. 02187 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 02188 * @param DMAx DMAx Instance 02189 * @retval None 02190 */ 02191 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 02192 { 02193 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); 02194 } 02195 02196 /** 02197 * @brief Clear Channel 2 transfer error flag. 02198 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 02199 * @param DMAx DMAx Instance 02200 * @retval None 02201 */ 02202 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 02203 { 02204 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); 02205 } 02206 02207 /** 02208 * @brief Clear Channel 3 transfer error flag. 02209 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 02210 * @param DMAx DMAx Instance 02211 * @retval None 02212 */ 02213 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 02214 { 02215 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); 02216 } 02217 02218 /** 02219 * @brief Clear Channel 4 transfer error flag. 02220 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4 02221 * @param DMAx DMAx Instance 02222 * @retval None 02223 */ 02224 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 02225 { 02226 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4); 02227 } 02228 02229 /** 02230 * @brief Clear Channel 5 transfer error flag. 02231 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5 02232 * @param DMAx DMAx Instance 02233 * @retval None 02234 */ 02235 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 02236 { 02237 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5); 02238 } 02239 02240 /** 02241 * @brief Clear Channel 6 transfer error flag. 02242 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6 02243 * @param DMAx DMAx Instance 02244 * @retval None 02245 */ 02246 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 02247 { 02248 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6); 02249 } 02250 02251 /** 02252 * @brief Clear Channel 7 transfer error flag. 02253 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7 02254 * @param DMAx DMAx Instance 02255 * @retval None 02256 */ 02257 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 02258 { 02259 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7); 02260 } 02261 02262 /** 02263 * @} 02264 */ 02265 02266 /** @defgroup DMA_LL_EF_IT_Management IT_Management 02267 * @{ 02268 */ 02269 /** 02270 * @brief Enable Transfer complete interrupt. 02271 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC 02272 * @param DMAx DMAx Instance 02273 * @param Channel This parameter can be one of the following values: 02274 * @arg @ref LL_DMA_CHANNEL_1 02275 * @arg @ref LL_DMA_CHANNEL_2 02276 * @arg @ref LL_DMA_CHANNEL_3 02277 * @arg @ref LL_DMA_CHANNEL_4 02278 * @arg @ref LL_DMA_CHANNEL_5 02279 * @arg @ref LL_DMA_CHANNEL_6 02280 * @arg @ref LL_DMA_CHANNEL_7 02281 * @retval None 02282 */ 02283 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 02284 { 02285 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); 02286 } 02287 02288 /** 02289 * @brief Enable Half transfer interrupt. 02290 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT 02291 * @param DMAx DMAx Instance 02292 * @param Channel This parameter can be one of the following values: 02293 * @arg @ref LL_DMA_CHANNEL_1 02294 * @arg @ref LL_DMA_CHANNEL_2 02295 * @arg @ref LL_DMA_CHANNEL_3 02296 * @arg @ref LL_DMA_CHANNEL_4 02297 * @arg @ref LL_DMA_CHANNEL_5 02298 * @arg @ref LL_DMA_CHANNEL_6 02299 * @arg @ref LL_DMA_CHANNEL_7 02300 * @retval None 02301 */ 02302 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 02303 { 02304 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); 02305 } 02306 02307 /** 02308 * @brief Enable Transfer error interrupt. 02309 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE 02310 * @param DMAx DMAx Instance 02311 * @param Channel This parameter can be one of the following values: 02312 * @arg @ref LL_DMA_CHANNEL_1 02313 * @arg @ref LL_DMA_CHANNEL_2 02314 * @arg @ref LL_DMA_CHANNEL_3 02315 * @arg @ref LL_DMA_CHANNEL_4 02316 * @arg @ref LL_DMA_CHANNEL_5 02317 * @arg @ref LL_DMA_CHANNEL_6 02318 * @arg @ref LL_DMA_CHANNEL_7 02319 * @retval None 02320 */ 02321 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 02322 { 02323 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); 02324 } 02325 02326 /** 02327 * @brief Disable Transfer complete interrupt. 02328 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC 02329 * @param DMAx DMAx Instance 02330 * @param Channel This parameter can be one of the following values: 02331 * @arg @ref LL_DMA_CHANNEL_1 02332 * @arg @ref LL_DMA_CHANNEL_2 02333 * @arg @ref LL_DMA_CHANNEL_3 02334 * @arg @ref LL_DMA_CHANNEL_4 02335 * @arg @ref LL_DMA_CHANNEL_5 02336 * @arg @ref LL_DMA_CHANNEL_6 02337 * @arg @ref LL_DMA_CHANNEL_7 02338 * @retval None 02339 */ 02340 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 02341 { 02342 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); 02343 } 02344 02345 /** 02346 * @brief Disable Half transfer interrupt. 02347 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT 02348 * @param DMAx DMAx Instance 02349 * @param Channel This parameter can be one of the following values: 02350 * @arg @ref LL_DMA_CHANNEL_1 02351 * @arg @ref LL_DMA_CHANNEL_2 02352 * @arg @ref LL_DMA_CHANNEL_3 02353 * @arg @ref LL_DMA_CHANNEL_4 02354 * @arg @ref LL_DMA_CHANNEL_5 02355 * @arg @ref LL_DMA_CHANNEL_6 02356 * @arg @ref LL_DMA_CHANNEL_7 02357 * @retval None 02358 */ 02359 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 02360 { 02361 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); 02362 } 02363 02364 /** 02365 * @brief Disable Transfer error interrupt. 02366 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE 02367 * @param DMAx DMAx Instance 02368 * @param Channel This parameter can be one of the following values: 02369 * @arg @ref LL_DMA_CHANNEL_1 02370 * @arg @ref LL_DMA_CHANNEL_2 02371 * @arg @ref LL_DMA_CHANNEL_3 02372 * @arg @ref LL_DMA_CHANNEL_4 02373 * @arg @ref LL_DMA_CHANNEL_5 02374 * @arg @ref LL_DMA_CHANNEL_6 02375 * @arg @ref LL_DMA_CHANNEL_7 02376 * @retval None 02377 */ 02378 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 02379 { 02380 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); 02381 } 02382 02383 /** 02384 * @brief Check if Transfer complete Interrupt is enabled. 02385 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC 02386 * @param DMAx DMAx Instance 02387 * @param Channel This parameter can be one of the following values: 02388 * @arg @ref LL_DMA_CHANNEL_1 02389 * @arg @ref LL_DMA_CHANNEL_2 02390 * @arg @ref LL_DMA_CHANNEL_3 02391 * @arg @ref LL_DMA_CHANNEL_4 02392 * @arg @ref LL_DMA_CHANNEL_5 02393 * @arg @ref LL_DMA_CHANNEL_6 02394 * @arg @ref LL_DMA_CHANNEL_7 02395 * @retval State of bit (1 or 0). 02396 */ 02397 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) 02398 { 02399 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 02400 DMA_CCR_TCIE) == (DMA_CCR_TCIE)); 02401 } 02402 02403 /** 02404 * @brief Check if Half transfer Interrupt is enabled. 02405 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT 02406 * @param DMAx DMAx Instance 02407 * @param Channel This parameter can be one of the following values: 02408 * @arg @ref LL_DMA_CHANNEL_1 02409 * @arg @ref LL_DMA_CHANNEL_2 02410 * @arg @ref LL_DMA_CHANNEL_3 02411 * @arg @ref LL_DMA_CHANNEL_4 02412 * @arg @ref LL_DMA_CHANNEL_5 02413 * @arg @ref LL_DMA_CHANNEL_6 02414 * @arg @ref LL_DMA_CHANNEL_7 02415 * @retval State of bit (1 or 0). 02416 */ 02417 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) 02418 { 02419 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 02420 DMA_CCR_HTIE) == (DMA_CCR_HTIE)); 02421 } 02422 02423 /** 02424 * @brief Check if Transfer error Interrupt is enabled. 02425 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE 02426 * @param DMAx DMAx Instance 02427 * @param Channel This parameter can be one of the following values: 02428 * @arg @ref LL_DMA_CHANNEL_1 02429 * @arg @ref LL_DMA_CHANNEL_2 02430 * @arg @ref LL_DMA_CHANNEL_3 02431 * @arg @ref LL_DMA_CHANNEL_4 02432 * @arg @ref LL_DMA_CHANNEL_5 02433 * @arg @ref LL_DMA_CHANNEL_6 02434 * @arg @ref LL_DMA_CHANNEL_7 02435 * @retval State of bit (1 or 0). 02436 */ 02437 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) 02438 { 02439 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, 02440 DMA_CCR_TEIE) == (DMA_CCR_TEIE)); 02441 } 02442 02443 /** 02444 * @} 02445 */ 02446 02447 #if defined(USE_FULL_LL_DRIVER) 02448 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions 02449 * @{ 02450 */ 02451 02452 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); 02453 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); 02454 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); 02455 02456 /** 02457 * @} 02458 */ 02459 #endif /* USE_FULL_LL_DRIVER */ 02460 02461 /** 02462 * @} 02463 */ 02464 02465 /** 02466 * @} 02467 */ 02468 02469 #endif /* DMA1 || DMA2 */ 02470 02471 /** 02472 * @} 02473 */ 02474 02475 #ifdef __cplusplus 02476 } 02477 #endif 02478 02479 #endif /* __STM32L4xx_LL_DMA_H */ 02480 02481 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/