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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_dac.h 00004 * @author MCD Application Team 00005 * @brief Header file of DAC LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_DAC_H 00038 #define __STM32L4xx_LL_DAC_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (DAC1) 00052 00053 /** @defgroup DAC_LL DAC 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 00060 /* Private constants ---------------------------------------------------------*/ 00061 /** @defgroup DAC_LL_Private_Constants DAC Private Constants 00062 * @{ 00063 */ 00064 00065 /* Internal masks for DAC channels definition */ 00066 /* To select into literal LL_DAC_CHANNEL_x the relevant bits for: */ 00067 /* - channel bits position into registers CR, MCR, CCR, SHHR, SHRR */ 00068 /* - channel bits position into register SWTRIG */ 00069 /* - channel register offset of data holding register DHRx */ 00070 /* - channel register offset of data output register DORx */ 00071 /* - channel register offset of sample-and-hold sample time register SHSRx */ 00072 00073 #define DAC_CR_CH1_BITOFFSET 0U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 1 */ 00074 #define DAC_CR_CH2_BITOFFSET 16U /* Position of channel bits into registers CR, MCR, CCR, SHHR, SHRR of channel 2 */ 00075 #define DAC_CR_CHX_BITOFFSET_MASK (DAC_CR_CH1_BITOFFSET | DAC_CR_CH2_BITOFFSET) 00076 00077 #define DAC_SWTR_CH1 (DAC_SWTRIGR_SWTRIG1) /* Channel bit into register SWTRIGR of channel 1. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ 00078 #if defined(DAC_CHANNEL2_SUPPORT) 00079 #define DAC_SWTR_CH2 (DAC_SWTRIGR_SWTRIG2) /* Channel bit into register SWTRIGR of channel 2. This bit is into area of LL_DAC_CR_CHx_BITOFFSET but excluded by mask DAC_CR_CHX_BITOFFSET_MASK (done to be enable to trig SW start of both DAC channels simultaneously). */ 00080 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1 | DAC_SWTR_CH2) 00081 #else 00082 #define DAC_SWTR_CHX_MASK (DAC_SWTR_CH1) 00083 #endif /* DAC_CHANNEL2_SUPPORT */ 00084 00085 #define DAC_REG_DHR12R1_REGOFFSET 0x00000000U /* Register DHR12Rx channel 1 taken as reference */ 00086 #define DAC_REG_DHR12L1_REGOFFSET 0x00100000U /* Register offset of DHR12Lx channel 1 versus DHR12Rx channel 1 (shifted left of 20 bits) */ 00087 #define DAC_REG_DHR8R1_REGOFFSET 0x02000000U /* Register offset of DHR8Rx channel 1 versus DHR12Rx channel 1 (shifted left of 24 bits) */ 00088 #if defined(DAC_CHANNEL2_SUPPORT) 00089 #define DAC_REG_DHR12R2_REGOFFSET 0x00030000U /* Register offset of DHR12Rx channel 2 versus DHR12Rx channel 1 (shifted left of 16 bits) */ 00090 #define DAC_REG_DHR12L2_REGOFFSET 0x00400000U /* Register offset of DHR12Lx channel 2 versus DHR12Rx channel 1 (shifted left of 20 bits) */ 00091 #define DAC_REG_DHR8R2_REGOFFSET 0x05000000U /* Register offset of DHR8Rx channel 2 versus DHR12Rx channel 1 (shifted left of 24 bits) */ 00092 #endif /* DAC_CHANNEL2_SUPPORT */ 00093 #define DAC_REG_DHR12RX_REGOFFSET_MASK 0x000F0000U 00094 #define DAC_REG_DHR12LX_REGOFFSET_MASK 0x00F00000U 00095 #define DAC_REG_DHR8RX_REGOFFSET_MASK 0x0F000000U 00096 #define DAC_REG_DHRX_REGOFFSET_MASK (DAC_REG_DHR12RX_REGOFFSET_MASK | DAC_REG_DHR12LX_REGOFFSET_MASK | DAC_REG_DHR8RX_REGOFFSET_MASK) 00097 00098 #define DAC_REG_DOR1_REGOFFSET 0x00000000U /* Register DORx channel 1 taken as reference */ 00099 #if defined(DAC_CHANNEL2_SUPPORT) 00100 #define DAC_REG_DOR2_REGOFFSET 0x10000000U /* Register offset of DORx channel 1 versus DORx channel 2 (shifted left of 28 bits) */ 00101 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET | DAC_REG_DOR2_REGOFFSET) 00102 #else 00103 #define DAC_REG_DORX_REGOFFSET_MASK (DAC_REG_DOR1_REGOFFSET) 00104 #endif /* DAC_CHANNEL2_SUPPORT */ 00105 00106 #define DAC_REG_SHSR1_REGOFFSET 0x00000000U /* Register SHSRx channel 1 taken as reference */ 00107 #if defined(DAC_CHANNEL2_SUPPORT) 00108 #define DAC_REG_SHSR2_REGOFFSET 0x00001000U /* Register offset of SHSRx channel 1 versus SHSRx channel 2 (shifted left of 12 bits) */ 00109 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET | DAC_REG_SHSR2_REGOFFSET) 00110 #else 00111 #define DAC_REG_SHSRX_REGOFFSET_MASK (DAC_REG_SHSR1_REGOFFSET) 00112 #endif /* DAC_CHANNEL2_SUPPORT */ 00113 00114 /* DAC registers bits positions */ 00115 #if defined(DAC_CHANNEL2_SUPPORT) 00116 #define DAC_DHR12RD_DACC2DHR_BITOFFSET_POS 16U /* Value equivalent to POSITION_VAL(DAC_DHR12RD_DACC2DHR) */ 00117 #define DAC_DHR12LD_DACC2DHR_BITOFFSET_POS 20U /* Value equivalent to POSITION_VAL(DAC_DHR12LD_DACC2DHR) */ 00118 #define DAC_DHR8RD_DACC2DHR_BITOFFSET_POS 8U /* Value equivalent to POSITION_VAL(DAC_DHR8RD_DACC2DHR) */ 00119 #endif /* DAC_CHANNEL2_SUPPORT */ 00120 00121 /* Miscellaneous data */ 00122 #define DAC_DIGITAL_SCALE_12BITS 4095U /* Full-scale digital value with a resolution of 12 bits (voltage range determined by analog voltage references Vref+ and Vref-, refer to reference manual) */ 00123 00124 /** 00125 * @} 00126 */ 00127 00128 00129 /* Private macros ------------------------------------------------------------*/ 00130 /** @defgroup DAC_LL_Private_Macros DAC Private Macros 00131 * @{ 00132 */ 00133 00134 /** 00135 * @brief Driver macro reserved for internal use: isolate bits with the 00136 * selected mask and shift them to the register LSB 00137 * (shift mask on register position bit 0). 00138 * @param __BITS__ Bits in register 32 bits 00139 * @param __MASK__ Mask in register 32 bits 00140 * @retval Bits in register 32 bits 00141 */ 00142 #define __DAC_MASK_SHIFT(__BITS__, __MASK__) \ 00143 (((__BITS__) & (__MASK__)) >> POSITION_VAL((__MASK__))) 00144 00145 /** 00146 * @brief Driver macro reserved for internal use: set a pointer to 00147 * a register from a register basis from which an offset 00148 * is applied. 00149 * @param __REG__ Register basis from which the offset is applied. 00150 * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). 00151 * @retval Pointer to register address 00152 */ 00153 #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ 00154 ((uint32_t *)((uint32_t) ((uint32_t)(&(__REG__)) + ((__REG_OFFFSET__) << 2U)))) 00155 00156 /** 00157 * @} 00158 */ 00159 00160 00161 /* Exported types ------------------------------------------------------------*/ 00162 #if defined(USE_FULL_LL_DRIVER) 00163 /** @defgroup DAC_LL_ES_INIT DAC Exported Init structure 00164 * @{ 00165 */ 00166 00167 /** 00168 * @brief Structure definition of some features of DAC instance. 00169 */ 00170 typedef struct 00171 { 00172 uint32_t TriggerSource; /*!< Set the conversion trigger source for the selected DAC channel: internal (SW start) or from external IP (timer event, external interrupt line). 00173 This parameter can be a value of @ref DAC_LL_EC_TRIGGER_SOURCE 00174 00175 This feature can be modified afterwards using unitary function @ref LL_DAC_SetTriggerSource(). */ 00176 00177 uint32_t WaveAutoGeneration; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00178 This parameter can be a value of @ref DAC_LL_EC_WAVE_AUTO_GENERATION_MODE 00179 00180 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveAutoGeneration(). */ 00181 00182 uint32_t WaveAutoGenerationConfig; /*!< Set the waveform automatic generation mode for the selected DAC channel. 00183 If waveform automatic generation mode is set to noise, this parameter can be a value of @ref DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS 00184 If waveform automatic generation mode is set to triangle, this parameter can be a value of @ref DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE 00185 @note If waveform automatic generation mode is disabled, this parameter is discarded. 00186 00187 This feature can be modified afterwards using unitary function @ref LL_DAC_SetWaveNoiseLFSR() or @ref LL_DAC_SetWaveTriangleAmplitude(), depending on the wave automatic generation selected. */ 00188 00189 uint32_t OutputBuffer; /*!< Set the output buffer for the selected DAC channel. 00190 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_BUFFER 00191 00192 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputBuffer(). */ 00193 00194 uint32_t OutputConnection; /*!< Set the output connection for the selected DAC channel. 00195 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_CONNECTION 00196 00197 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputConnection(). */ 00198 00199 uint32_t OutputMode; /*!< Set the output mode normal or sample-and-hold for the selected DAC channel. 00200 This parameter can be a value of @ref DAC_LL_EC_OUTPUT_MODE 00201 00202 This feature can be modified afterwards using unitary function @ref LL_DAC_SetOutputMode(). */ 00203 00204 } LL_DAC_InitTypeDef; 00205 00206 /** 00207 * @} 00208 */ 00209 #endif /* USE_FULL_LL_DRIVER */ 00210 00211 /* Exported constants --------------------------------------------------------*/ 00212 /** @defgroup DAC_LL_Exported_Constants DAC Exported Constants 00213 * @{ 00214 */ 00215 00216 /** @defgroup DAC_LL_EC_GET_FLAG DAC flags 00217 * @brief Flags defines which can be used with LL_DAC_ReadReg function 00218 * @{ 00219 */ 00220 /* DAC channel 1 flags */ 00221 #define LL_DAC_FLAG_DMAUDR1 (DAC_SR_DMAUDR1) /*!< DAC channel 1 flag DMA underrun */ 00222 #define LL_DAC_FLAG_CAL1 (DAC_SR_CAL_FLAG1) /*!< DAC channel 1 flag offset calibration status */ 00223 #define LL_DAC_FLAG_BWST1 (DAC_SR_BWST1) /*!< DAC channel 1 flag busy writing sample time */ 00224 00225 #if defined(DAC_CHANNEL2_SUPPORT) 00226 /* DAC channel 2 flags */ 00227 #define LL_DAC_FLAG_DMAUDR2 (DAC_SR_DMAUDR2) /*!< DAC channel 2 flag DMA underrun */ 00228 #define LL_DAC_FLAG_CAL2 (DAC_SR_CAL_FLAG2) /*!< DAC channel 2 flag offset calibration status */ 00229 #define LL_DAC_FLAG_BWST2 (DAC_SR_BWST2) /*!< DAC channel 2 flag busy writing sample time */ 00230 #endif /* DAC_CHANNEL2_SUPPORT */ 00231 /** 00232 * @} 00233 */ 00234 00235 /** @defgroup DAC_LL_EC_IT DAC interruptions 00236 * @brief IT defines which can be used with LL_DAC_ReadReg and LL_DAC_WriteReg functions 00237 * @{ 00238 */ 00239 #define LL_DAC_IT_DMAUDRIE1 (DAC_CR_DMAUDRIE1) /*!< DAC channel 1 interruption DMA underrun */ 00240 #if defined(DAC_CHANNEL2_SUPPORT) 00241 #define LL_DAC_IT_DMAUDRIE2 (DAC_CR_DMAUDRIE2) /*!< DAC channel 2 interruption DMA underrun */ 00242 #endif /* DAC_CHANNEL2_SUPPORT */ 00243 /** 00244 * @} 00245 */ 00246 00247 /** @defgroup DAC_LL_EC_CHANNEL DAC channels 00248 * @{ 00249 */ 00250 #define LL_DAC_CHANNEL_1 (DAC_REG_SHSR1_REGOFFSET | DAC_REG_DOR1_REGOFFSET | DAC_REG_DHR12R1_REGOFFSET | DAC_REG_DHR12L1_REGOFFSET | DAC_REG_DHR8R1_REGOFFSET | DAC_CR_CH1_BITOFFSET | DAC_SWTR_CH1) /*!< DAC channel 1 */ 00251 #if defined(DAC_CHANNEL2_SUPPORT) 00252 #define LL_DAC_CHANNEL_2 (DAC_REG_SHSR2_REGOFFSET | DAC_REG_DOR2_REGOFFSET | DAC_REG_DHR12R2_REGOFFSET | DAC_REG_DHR12L2_REGOFFSET | DAC_REG_DHR8R2_REGOFFSET | DAC_CR_CH2_BITOFFSET | DAC_SWTR_CH2) /*!< DAC channel 2 */ 00253 #endif /* DAC_CHANNEL2_SUPPORT */ 00254 /** 00255 * @} 00256 */ 00257 00258 /** @defgroup DAC_LL_EC_OPERATING_MODE DAC operating mode 00259 * @{ 00260 */ 00261 #define LL_DAC_MODE_NORMAL_OPERATION 0x00000000U /*!< DAC channel in mode normal operation */ 00262 #define LL_DAC_MODE_CALIBRATION (DAC_CR_CEN1) /*!< DAC channel in mode calibration */ 00263 /** 00264 * @} 00265 */ 00266 00267 /** @defgroup DAC_LL_EC_TRIGGER_SOURCE DAC trigger source 00268 * @{ 00269 */ 00270 #if defined (DAC_CR_TSEL1_3) 00271 #define LL_DAC_TRIG_EXT_TIM1_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM1 TRGO. */ 00272 #define LL_DAC_TRIG_EXT_TIM2_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ 00273 #define LL_DAC_TRIG_EXT_TIM4_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ 00274 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ 00275 #define LL_DAC_TRIG_EXT_TIM6_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ 00276 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ 00277 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ 00278 #define LL_DAC_TRIG_EXT_TIM15_TRGO (DAC_CR_TSEL1_3 ) /*!< DAC channel conversion trigger from external IP: TIM15 TRGO. */ 00279 #define LL_DAC_TRIG_EXT_LPTIM1_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: LPTIM1 OUT TRGO. */ 00280 #define LL_DAC_TRIG_EXT_LPTIM2_OUT_TRGO (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: LPTIM2 OUT TRGO. */ 00281 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_3 | DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ 00282 #define LL_DAC_TRIG_SOFTWARE 0x00000000U /*!< DAC channel conversion trigger internal (SW start) */ 00283 #else 00284 #define LL_DAC_TRIG_SOFTWARE (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger internal (SW start) */ 00285 #define LL_DAC_TRIG_EXT_TIM2_TRGO (DAC_CR_TSEL1_2 ) /*!< DAC channel conversion trigger from external IP: TIM2 TRGO. */ 00286 #define LL_DAC_TRIG_EXT_TIM4_TRGO (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM4 TRGO. */ 00287 #define LL_DAC_TRIG_EXT_TIM5_TRGO ( DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM5 TRGO. */ 00288 #define LL_DAC_TRIG_EXT_TIM6_TRGO 0x00000000U /*!< DAC channel conversion trigger from external IP: TIM6 TRGO. */ 00289 #define LL_DAC_TRIG_EXT_TIM7_TRGO ( DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: TIM7 TRGO. */ 00290 #define LL_DAC_TRIG_EXT_TIM8_TRGO ( DAC_CR_TSEL1_0) /*!< DAC channel conversion trigger from external IP: TIM8 TRGO. */ 00291 #define LL_DAC_TRIG_EXT_EXTI_LINE9 (DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1 ) /*!< DAC channel conversion trigger from external IP: external interrupt line 9. */ 00292 #endif 00293 00294 /** 00295 * @} 00296 */ 00297 00298 /** @defgroup DAC_LL_EC_WAVE_AUTO_GENERATION_MODE DAC waveform automatic generation mode 00299 * @{ 00300 */ 00301 #define LL_DAC_WAVE_AUTO_GENERATION_NONE 0x00000000U /*!< DAC channel wave auto generation mode disabled. */ 00302 #define LL_DAC_WAVE_AUTO_GENERATION_NOISE (DAC_CR_WAVE1_0) /*!< DAC channel wave auto generation mode enabled, set generated noise waveform. */ 00303 #define LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE (DAC_CR_WAVE1_1) /*!< DAC channel wave auto generation mode enabled, set generated triangle waveform. */ 00304 /** 00305 * @} 00306 */ 00307 00308 /** @defgroup DAC_LL_EC_WAVE_NOISE_LFSR_UNMASK_BITS DAC wave generation - Noise LFSR unmask bits 00309 * @{ 00310 */ 00311 #define LL_DAC_NOISE_LFSR_UNMASK_BIT0 0x00000000U /*!< Noise wave generation, unmask LFSR bit0, for the selected DAC channel */ 00312 #define LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 ( DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[1:0], for the selected DAC channel */ 00313 #define LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 ( DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[2:0], for the selected DAC channel */ 00314 #define LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[3:0], for the selected DAC channel */ 00315 #define LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 ( DAC_CR_MAMP1_2 ) /*!< Noise wave generation, unmask LFSR bits[4:0], for the selected DAC channel */ 00316 #define LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[5:0], for the selected DAC channel */ 00317 #define LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[6:0], for the selected DAC channel */ 00318 #define LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[7:0], for the selected DAC channel */ 00319 #define LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 (DAC_CR_MAMP1_3 ) /*!< Noise wave generation, unmask LFSR bits[8:0], for the selected DAC channel */ 00320 #define LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[9:0], for the selected DAC channel */ 00321 #define LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Noise wave generation, unmask LFSR bits[10:0], for the selected DAC channel */ 00322 #define LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Noise wave generation, unmask LFSR bits[11:0], for the selected DAC channel */ 00323 /** 00324 * @} 00325 */ 00326 00327 /** @defgroup DAC_LL_EC_WAVE_TRIANGLE_AMPLITUDE DAC wave generation - Triangle amplitude 00328 * @{ 00329 */ 00330 #define LL_DAC_TRIANGLE_AMPLITUDE_1 0x00000000U /*!< Triangle wave generation, amplitude of 1 LSB of DAC output range, for the selected DAC channel */ 00331 #define LL_DAC_TRIANGLE_AMPLITUDE_3 ( DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 3 LSB of DAC output range, for the selected DAC channel */ 00332 #define LL_DAC_TRIANGLE_AMPLITUDE_7 ( DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 7 LSB of DAC output range, for the selected DAC channel */ 00333 #define LL_DAC_TRIANGLE_AMPLITUDE_15 ( DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 15 LSB of DAC output range, for the selected DAC channel */ 00334 #define LL_DAC_TRIANGLE_AMPLITUDE_31 ( DAC_CR_MAMP1_2 ) /*!< Triangle wave generation, amplitude of 31 LSB of DAC output range, for the selected DAC channel */ 00335 #define LL_DAC_TRIANGLE_AMPLITUDE_63 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 63 LSB of DAC output range, for the selected DAC channel */ 00336 #define LL_DAC_TRIANGLE_AMPLITUDE_127 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 127 LSB of DAC output range, for the selected DAC channel */ 00337 #define LL_DAC_TRIANGLE_AMPLITUDE_255 ( DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 255 LSB of DAC output range, for the selected DAC channel */ 00338 #define LL_DAC_TRIANGLE_AMPLITUDE_511 (DAC_CR_MAMP1_3 ) /*!< Triangle wave generation, amplitude of 512 LSB of DAC output range, for the selected DAC channel */ 00339 #define LL_DAC_TRIANGLE_AMPLITUDE_1023 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 1023 LSB of DAC output range, for the selected DAC channel */ 00340 #define LL_DAC_TRIANGLE_AMPLITUDE_2047 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 ) /*!< Triangle wave generation, amplitude of 2047 LSB of DAC output range, for the selected DAC channel */ 00341 #define LL_DAC_TRIANGLE_AMPLITUDE_4095 (DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Triangle wave generation, amplitude of 4095 LSB of DAC output range, for the selected DAC channel */ 00342 /** 00343 * @} 00344 */ 00345 00346 /** @defgroup DAC_LL_EC_OUTPUT_MODE DAC channel output mode 00347 * @{ 00348 */ 00349 #define LL_DAC_OUTPUT_MODE_NORMAL 0x00000000U /*!< The selected DAC channel output is on mode normal. */ 00350 #define LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD (DAC_MCR_MODE1_2) /*!< The selected DAC channel output is on mode sample-and-hold. Mode sample-and-hold requires an external capacitor, refer to description of function @ref LL_DAC_ConfigOutput() or @ref LL_DAC_SetOutputMode(). */ 00351 /** 00352 * @} 00353 */ 00354 00355 /** @defgroup DAC_LL_EC_OUTPUT_BUFFER DAC channel output buffer 00356 * @{ 00357 */ 00358 #define LL_DAC_OUTPUT_BUFFER_ENABLE 0x00000000U /*!< The selected DAC channel output is buffered: higher drive current capability, but also higher current consumption */ 00359 #define LL_DAC_OUTPUT_BUFFER_DISABLE (DAC_MCR_MODE1_1) /*!< The selected DAC channel output is not buffered: lower drive current capability, but also lower current consumption */ 00360 /** 00361 * @} 00362 */ 00363 00364 /** @defgroup DAC_LL_EC_OUTPUT_CONNECTION DAC channel output connection 00365 * @{ 00366 */ 00367 #define LL_DAC_OUTPUT_CONNECT_GPIO 0x00000000U /*!< The selected DAC channel output is connected to external pin */ 00368 #define LL_DAC_OUTPUT_CONNECT_INTERNAL (DAC_MCR_MODE1_0) /*!< The selected DAC channel output is connected to on-chip peripherals via internal paths. On this STM32 serie, output connection depends on output mode (normal or sample and hold) and output buffer state. Refer to comments of function @ref LL_DAC_SetOutputConnection(). */ 00369 /** 00370 * @} 00371 */ 00372 00373 /** @defgroup DAC_LL_EC_LEGACY DAC literals legacy naming 00374 * @{ 00375 */ 00376 #define LL_DAC_TRIGGER_SOFTWARE (LL_DAC_TRIG_SOFTWARE) 00377 #define LL_DAC_TRIGGER_TIM2_TRGO (LL_DAC_TRIG_EXT_TIM2_TRGO) 00378 #define LL_DAC_TRIGGER_TIM4_TRGO (LL_DAC_TRIG_EXT_TIM4_TRGO) 00379 #define LL_DAC_TRIGGER_TIM5_TRGO (LL_DAC_TRIG_EXT_TIM5_TRGO) 00380 #define LL_DAC_TRIGGER_TIM6_TRGO (LL_DAC_TRIG_EXT_TIM6_TRGO) 00381 #define LL_DAC_TRIGGER_TIM7_TRGO (LL_DAC_TRIG_EXT_TIM7_TRGO) 00382 #define LL_DAC_TRIGGER_TIM8_TRGO (LL_DAC_TRIG_EXT_TIM8_TRGO) 00383 #define LL_DAC_TRIGGER_EXT_IT9 (LL_DAC_TRIG_EXT_EXTI_LINE9) 00384 00385 #define LL_DAC_WAVEGENERATION_NONE (LL_DAC_WAVE_AUTO_GENERATION_NONE) 00386 #define LL_DAC_WAVEGENERATION_NOISE (LL_DAC_WAVE_AUTO_GENERATION_NOISE) 00387 #define LL_DAC_WAVEGENERATION_TRIANGLE (LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE) 00388 00389 #define LL_DAC_CONNECT_GPIO (LL_DAC_OUTPUT_CONNECT_GPIO) 00390 #define LL_DAC_CONNECT_INTERNAL (LL_DAC_OUTPUT_CONNECT_INTERNAL) 00391 /** 00392 * @} 00393 */ 00394 00395 /** @defgroup DAC_LL_EC_RESOLUTION DAC channel output resolution 00396 * @{ 00397 */ 00398 #define LL_DAC_RESOLUTION_12B 0x00000000U /*!< DAC channel resolution 12 bits */ 00399 #define LL_DAC_RESOLUTION_8B 0x00000002U /*!< DAC channel resolution 8 bits */ 00400 /** 00401 * @} 00402 */ 00403 00404 /** @defgroup DAC_LL_EC_REGISTERS DAC registers compliant with specific purpose 00405 * @{ 00406 */ 00407 /* List of DAC registers intended to be used (most commonly) with */ 00408 /* DMA transfer. */ 00409 /* Refer to function @ref LL_DAC_DMA_GetRegAddr(). */ 00410 #define LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED DAC_REG_DHR12RX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits right aligned */ 00411 #define LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED DAC_REG_DHR12LX_REGOFFSET_MASK /*!< DAC channel data holding register 12 bits left aligned */ 00412 #define LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED DAC_REG_DHR8RX_REGOFFSET_MASK /*!< DAC channel data holding register 8 bits right aligned */ 00413 /** 00414 * @} 00415 */ 00416 00417 /** @defgroup DAC_LL_EC_HW_DELAYS Definitions of DAC hardware constraints delays 00418 * @note Only DAC IP HW delays are defined in DAC LL driver driver, 00419 * not timeout values. 00420 * For details on delays values, refer to descriptions in source code 00421 * above each literal definition. 00422 * @{ 00423 */ 00424 00425 /* Delay for DAC channel voltage settling time from DAC channel startup */ 00426 /* (transition from disable to enable). */ 00427 /* Note: DAC channel startup time depends on board application environment: */ 00428 /* impedance connected to DAC channel output. */ 00429 /* The delay below is specified under conditions: */ 00430 /* - voltage maximum transition (lowest to highest value) */ 00431 /* - until voltage reaches final value +-1LSB */ 00432 /* - DAC channel output buffer enabled */ 00433 /* - load impedance of 5kOhm (min), 50pF (max) */ 00434 /* Literal set to maximum value (refer to device datasheet, */ 00435 /* parameter "tWAKEUP"). */ 00436 /* Unit: us */ 00437 #define LL_DAC_DELAY_STARTUP_VOLTAGE_SETTLING_US 8U /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ 00438 00439 00440 /* Delay for DAC channel voltage settling time. */ 00441 /* Note: DAC channel startup time depends on board application environment: */ 00442 /* impedance connected to DAC channel output. */ 00443 /* The delay below is specified under conditions: */ 00444 /* - voltage maximum transition (lowest to highest value) */ 00445 /* - until voltage reaches final value +-1LSB */ 00446 /* - DAC channel output buffer enabled */ 00447 /* - load impedance of 5kOhm min, 50pF max */ 00448 /* Literal set to maximum value (refer to device datasheet, */ 00449 /* parameter "tSETTLING"). */ 00450 /* Unit: us */ 00451 #define LL_DAC_DELAY_VOLTAGE_SETTLING_US 2U /*!< Delay for DAC channel voltage settling time */ 00452 00453 /** 00454 * @} 00455 */ 00456 00457 /** 00458 * @} 00459 */ 00460 00461 /* Exported macro ------------------------------------------------------------*/ 00462 /** @defgroup DAC_LL_Exported_Macros DAC Exported Macros 00463 * @{ 00464 */ 00465 00466 /** @defgroup DAC_LL_EM_WRITE_READ Common write and read registers macros 00467 * @{ 00468 */ 00469 00470 /** 00471 * @brief Write a value in DAC register 00472 * @param __INSTANCE__ DAC Instance 00473 * @param __REG__ Register to be written 00474 * @param __VALUE__ Value to be written in the register 00475 * @retval None 00476 */ 00477 #define LL_DAC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00478 00479 /** 00480 * @brief Read a value in DAC register 00481 * @param __INSTANCE__ DAC Instance 00482 * @param __REG__ Register to be read 00483 * @retval Register value 00484 */ 00485 #define LL_DAC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00486 00487 /** 00488 * @} 00489 */ 00490 00491 /** @defgroup DAC_LL_EM_HELPER_MACRO DAC helper macro 00492 * @{ 00493 */ 00494 00495 /** 00496 * @brief Helper macro to get DAC channel number in decimal format 00497 * from literals LL_DAC_CHANNEL_x. 00498 * Example: 00499 * __LL_DAC_CHANNEL_TO_DECIMAL_NB(LL_DAC_CHANNEL_1) 00500 * will return decimal number "1". 00501 * @note The input can be a value from functions where a channel 00502 * number is returned. 00503 * @param __CHANNEL__ This parameter can be one of the following values: 00504 * @arg @ref LL_DAC_CHANNEL_1 00505 * @arg @ref LL_DAC_CHANNEL_2 (1) 00506 * 00507 * (1) On this STM32 serie, parameter not available on all devices. 00508 * Refer to device datasheet for channels availability. 00509 * @retval 1...2 (value "2" depending on DAC channel 2 availability) 00510 */ 00511 #define __LL_DAC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ 00512 ((__CHANNEL__) & DAC_SWTR_CHX_MASK) 00513 00514 /** 00515 * @brief Helper macro to get DAC channel in literal format LL_DAC_CHANNEL_x 00516 * from number in decimal format. 00517 * Example: 00518 * __LL_DAC_DECIMAL_NB_TO_CHANNEL(1) 00519 * will return a data equivalent to "LL_DAC_CHANNEL_1". 00520 * @note If the input parameter does not correspond to a DAC channel, 00521 * this macro returns value '0'. 00522 * @param __DECIMAL_NB__ 1...2 (value "2" depending on DAC channel 2 availability) 00523 * @retval Returned value can be one of the following values: 00524 * @arg @ref LL_DAC_CHANNEL_1 00525 * @arg @ref LL_DAC_CHANNEL_2 (1) 00526 * 00527 * (1) On this STM32 serie, parameter not available on all devices. 00528 * Refer to device datasheet for channels availability. 00529 */ 00530 #if defined(DAC_CHANNEL2_SUPPORT) 00531 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 00532 (((__DECIMAL_NB__) == 1U) \ 00533 ? ( \ 00534 LL_DAC_CHANNEL_1 \ 00535 ) \ 00536 : \ 00537 (((__DECIMAL_NB__) == 2U) \ 00538 ? ( \ 00539 LL_DAC_CHANNEL_2 \ 00540 ) \ 00541 : \ 00542 ( \ 00543 0 \ 00544 ) \ 00545 ) \ 00546 ) 00547 #else 00548 #define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ 00549 (((__DECIMAL_NB__) == 1U) \ 00550 ? ( \ 00551 LL_DAC_CHANNEL_1 \ 00552 ) \ 00553 : \ 00554 ( \ 00555 0 \ 00556 ) \ 00557 ) 00558 #endif /* DAC_CHANNEL2_SUPPORT */ 00559 00560 /** 00561 * @brief Helper macro to define the DAC conversion data full-scale digital 00562 * value corresponding to the selected DAC resolution. 00563 * @note DAC conversion data full-scale corresponds to voltage range 00564 * determined by analog voltage references Vref+ and Vref- 00565 * (refer to reference manual). 00566 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00567 * @arg @ref LL_DAC_RESOLUTION_12B 00568 * @arg @ref LL_DAC_RESOLUTION_8B 00569 * @retval ADC conversion data equivalent voltage value (unit: mVolt) 00570 */ 00571 #define __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00572 ((0x00000FFFU) >> ((__DAC_RESOLUTION__) << 1U)) 00573 00574 /** 00575 * @brief Helper macro to calculate the DAC conversion data (unit: digital 00576 * value) corresponding to a voltage (unit: mVolt). 00577 * @note This helper macro is intended to provide input data in voltage 00578 * rather than digital value, 00579 * to be used with LL DAC functions such as 00580 * @ref LL_DAC_ConvertData12RightAligned(). 00581 * @note Analog reference voltage (Vref+) must be either known from 00582 * user board environment or can be calculated using ADC measurement 00583 * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). 00584 * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) 00585 * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel 00586 * (unit: mVolt). 00587 * @param __DAC_RESOLUTION__ This parameter can be one of the following values: 00588 * @arg @ref LL_DAC_RESOLUTION_12B 00589 * @arg @ref LL_DAC_RESOLUTION_8B 00590 * @retval DAC conversion data (unit: digital value) 00591 */ 00592 #define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ 00593 __DAC_VOLTAGE__,\ 00594 __DAC_RESOLUTION__) \ 00595 ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ 00596 / (__VREFANALOG_VOLTAGE__) \ 00597 ) 00598 00599 /** 00600 * @} 00601 */ 00602 00603 /** 00604 * @} 00605 */ 00606 00607 00608 /* Exported functions --------------------------------------------------------*/ 00609 /** @defgroup DAC_LL_Exported_Functions DAC Exported Functions 00610 * @{ 00611 */ 00612 /** @defgroup DAC_LL_EF_Configuration Configuration of DAC channels 00613 * @{ 00614 */ 00615 00616 /** 00617 * @brief Set the operating mode for the selected DAC channel: 00618 * calibration or normal operating mode. 00619 * @rmtoll CR CEN1 LL_DAC_SetMode\n 00620 * CR CEN2 LL_DAC_SetMode 00621 * @param DACx DAC instance 00622 * @param DAC_Channel This parameter can be one of the following values: 00623 * @arg @ref LL_DAC_CHANNEL_1 00624 * 00625 * @arg @ref LL_DAC_CHANNEL_2 (1) 00626 * (1) On this STM32 serie, parameter not available on all devices. 00627 * Refer to device datasheet for channels availability. 00628 * @param ChannelMode This parameter can be one of the following values: 00629 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION 00630 * @arg @ref LL_DAC_MODE_CALIBRATION 00631 * @retval None 00632 */ 00633 __STATIC_INLINE void LL_DAC_SetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t ChannelMode) 00634 { 00635 MODIFY_REG(DACx->CR, 00636 DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00637 ChannelMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00638 } 00639 00640 /** 00641 * @brief Get the operating mode for the selected DAC channel: 00642 * calibration or normal operating mode. 00643 * @rmtoll CR CEN1 LL_DAC_GetMode\n 00644 * CR CEN2 LL_DAC_GetMode 00645 * @param DACx DAC instance 00646 * @param DAC_Channel This parameter can be one of the following values: 00647 * @arg @ref LL_DAC_CHANNEL_1 00648 * @arg @ref LL_DAC_CHANNEL_2 (1) 00649 * 00650 * (1) On this STM32 serie, parameter not available on all devices. 00651 * Refer to device datasheet for channels availability. 00652 * @retval Returned value can be one of the following values: 00653 * @arg @ref LL_DAC_MODE_NORMAL_OPERATION 00654 * @arg @ref LL_DAC_MODE_CALIBRATION 00655 */ 00656 __STATIC_INLINE uint32_t LL_DAC_GetMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00657 { 00658 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_CEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00659 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00660 ); 00661 } 00662 00663 /** 00664 * @brief Set the offset trimming value for the selected DAC channel. 00665 * Trimming has an impact when output buffer is enabled 00666 * and is intended to replace factory calibration default values. 00667 * @rmtoll CCR OTRIM1 LL_DAC_SetTrimmingValue\n 00668 * CCR OTRIM2 LL_DAC_SetTrimmingValue 00669 * @param DACx DAC instance 00670 * @param DAC_Channel This parameter can be one of the following values: 00671 * @arg @ref LL_DAC_CHANNEL_1 00672 * @arg @ref LL_DAC_CHANNEL_2 (1) 00673 * 00674 * (1) On this STM32 serie, parameter not available on all devices. 00675 * Refer to device datasheet for channels availability. 00676 * @param TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F 00677 * @retval None 00678 */ 00679 __STATIC_INLINE void LL_DAC_SetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TrimmingValue) 00680 { 00681 MODIFY_REG(DACx->CCR, 00682 DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00683 TrimmingValue << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00684 } 00685 00686 /** 00687 * @brief Get the offset trimming value for the selected DAC channel. 00688 * Trimming has an impact when output buffer is enabled 00689 * and is intended to replace factory calibration default values. 00690 * @rmtoll CCR OTRIM1 LL_DAC_GetTrimmingValue\n 00691 * CCR OTRIM2 LL_DAC_GetTrimmingValue 00692 * @param DACx DAC instance 00693 * @param DAC_Channel This parameter can be one of the following values: 00694 * @arg @ref LL_DAC_CHANNEL_1 00695 * @arg @ref LL_DAC_CHANNEL_2 (1) 00696 * 00697 * (1) On this STM32 serie, parameter not available on all devices. 00698 * Refer to device datasheet for channels availability. 00699 * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F 00700 */ 00701 __STATIC_INLINE uint32_t LL_DAC_GetTrimmingValue(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00702 { 00703 return (uint32_t)(READ_BIT(DACx->CCR, DAC_CCR_OTRIM1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00704 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00705 ); 00706 } 00707 00708 /** 00709 * @brief Set the conversion trigger source for the selected DAC channel. 00710 * @note For conversion trigger source to be effective, DAC trigger 00711 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00712 * @note To set conversion trigger source, DAC channel must be disabled. 00713 * Otherwise, the setting is discarded. 00714 * @note Availability of parameters of trigger sources from timer 00715 * depends on timers availability on the selected device. 00716 * @rmtoll CR TSEL1 LL_DAC_SetTriggerSource\n 00717 * CR TSEL2 LL_DAC_SetTriggerSource 00718 * @param DACx DAC instance 00719 * @param DAC_Channel This parameter can be one of the following values: 00720 * @arg @ref LL_DAC_CHANNEL_1 00721 * @arg @ref LL_DAC_CHANNEL_2 (1) 00722 * 00723 * (1) On this STM32 serie, parameter not available on all devices. 00724 * Refer to device datasheet for channels availability. 00725 * @param TriggerSource This parameter can be one of the following values: 00726 * @arg @ref LL_DAC_TRIG_SOFTWARE 00727 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00728 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00729 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00730 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00731 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00732 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 00733 * @arg @ref LL_DAC_TRIG_EXT_EXTI_LINE9 00734 * @retval None 00735 */ 00736 __STATIC_INLINE void LL_DAC_SetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriggerSource) 00737 { 00738 MODIFY_REG(DACx->CR, 00739 DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00740 TriggerSource << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00741 } 00742 00743 /** 00744 * @brief Get the conversion trigger source for the selected DAC channel. 00745 * @note For conversion trigger source to be effective, DAC trigger 00746 * must be enabled using function @ref LL_DAC_EnableTrigger(). 00747 * @note Availability of parameters of trigger sources from timer 00748 * depends on timers availability on the selected device. 00749 * @rmtoll CR TSEL1 LL_DAC_GetTriggerSource\n 00750 * CR TSEL2 LL_DAC_GetTriggerSource 00751 * @param DACx DAC instance 00752 * @param DAC_Channel This parameter can be one of the following values: 00753 * @arg @ref LL_DAC_CHANNEL_1 00754 * @arg @ref LL_DAC_CHANNEL_2 (1) 00755 * 00756 * (1) On this STM32 serie, parameter not available on all devices. 00757 * Refer to device datasheet for channels availability. 00758 * @retval Returned value can be one of the following values: 00759 * @arg @ref LL_DAC_TRIG_SOFTWARE 00760 * @arg @ref LL_DAC_TRIG_EXT_TIM2_TRGO 00761 * @arg @ref LL_DAC_TRIG_EXT_TIM4_TRGO 00762 * @arg @ref LL_DAC_TRIG_EXT_TIM5_TRGO 00763 * @arg @ref LL_DAC_TRIG_EXT_TIM6_TRGO 00764 * @arg @ref LL_DAC_TRIG_EXT_TIM7_TRGO 00765 * @arg @ref LL_DAC_TRIG_EXT_TIM8_TRGO 00766 * @arg @ref LL_DAC_TRIGGER_EXT_IT9 00767 */ 00768 __STATIC_INLINE uint32_t LL_DAC_GetTriggerSource(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00769 { 00770 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_TSEL1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00771 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00772 ); 00773 } 00774 00775 /** 00776 * @brief Set the waveform automatic generation mode 00777 * for the selected DAC channel. 00778 * @rmtoll CR WAVE1 LL_DAC_SetWaveAutoGeneration\n 00779 * CR WAVE2 LL_DAC_SetWaveAutoGeneration 00780 * @param DACx DAC instance 00781 * @param DAC_Channel This parameter can be one of the following values: 00782 * @arg @ref LL_DAC_CHANNEL_1 00783 * @arg @ref LL_DAC_CHANNEL_2 (1) 00784 * 00785 * (1) On this STM32 serie, parameter not available on all devices. 00786 * Refer to device datasheet for channels availability. 00787 * @param WaveAutoGeneration This parameter can be one of the following values: 00788 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00789 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00790 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00791 * @retval None 00792 */ 00793 __STATIC_INLINE void LL_DAC_SetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveAutoGeneration) 00794 { 00795 MODIFY_REG(DACx->CR, 00796 DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00797 WaveAutoGeneration << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00798 } 00799 00800 /** 00801 * @brief Get the waveform automatic generation mode 00802 * for the selected DAC channel. 00803 * @rmtoll CR WAVE1 LL_DAC_GetWaveAutoGeneration\n 00804 * CR WAVE2 LL_DAC_GetWaveAutoGeneration 00805 * @param DACx DAC instance 00806 * @param DAC_Channel This parameter can be one of the following values: 00807 * @arg @ref LL_DAC_CHANNEL_1 00808 * @arg @ref LL_DAC_CHANNEL_2 (1) 00809 * 00810 * (1) On this STM32 serie, parameter not available on all devices. 00811 * Refer to device datasheet for channels availability. 00812 * @retval Returned value can be one of the following values: 00813 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NONE 00814 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_NOISE 00815 * @arg @ref LL_DAC_WAVE_AUTO_GENERATION_TRIANGLE 00816 */ 00817 __STATIC_INLINE uint32_t LL_DAC_GetWaveAutoGeneration(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00818 { 00819 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_WAVE1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00820 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00821 ); 00822 } 00823 00824 /** 00825 * @brief Set the noise waveform generation for the selected DAC channel: 00826 * Noise mode and parameters LFSR (linear feedback shift register). 00827 * @note For wave generation to be effective, DAC channel 00828 * wave generation mode must be enabled using 00829 * function @ref LL_DAC_SetWaveAutoGeneration(). 00830 * @note This setting can be set when the selected DAC channel is disabled 00831 * (otherwise, the setting operation is ignored). 00832 * @rmtoll CR MAMP1 LL_DAC_SetWaveNoiseLFSR\n 00833 * CR MAMP2 LL_DAC_SetWaveNoiseLFSR 00834 * @param DACx DAC instance 00835 * @param DAC_Channel This parameter can be one of the following values: 00836 * @arg @ref LL_DAC_CHANNEL_1 00837 * @arg @ref LL_DAC_CHANNEL_2 (1) 00838 * 00839 * (1) On this STM32 serie, parameter not available on all devices. 00840 * Refer to device datasheet for channels availability. 00841 * @param NoiseLFSRMask This parameter can be one of the following values: 00842 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00843 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00844 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00845 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00846 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00847 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00848 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00849 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00850 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00851 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00852 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00853 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00854 * @retval None 00855 */ 00856 __STATIC_INLINE void LL_DAC_SetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t NoiseLFSRMask) 00857 { 00858 MODIFY_REG(DACx->CR, 00859 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00860 NoiseLFSRMask << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00861 } 00862 00863 /** 00864 * @brief Get the noise waveform generation for the selected DAC channel: 00865 * Noise mode and parameters LFSR (linear feedback shift register). 00866 * @rmtoll CR MAMP1 LL_DAC_GetWaveNoiseLFSR\n 00867 * CR MAMP2 LL_DAC_GetWaveNoiseLFSR 00868 * @param DACx DAC instance 00869 * @param DAC_Channel This parameter can be one of the following values: 00870 * @arg @ref LL_DAC_CHANNEL_1 00871 * @arg @ref LL_DAC_CHANNEL_2 (1) 00872 * 00873 * (1) On this STM32 serie, parameter not available on all devices. 00874 * Refer to device datasheet for channels availability. 00875 * @retval Returned value can be one of the following values: 00876 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BIT0 00877 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS1_0 00878 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS2_0 00879 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS3_0 00880 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS4_0 00881 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS5_0 00882 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS6_0 00883 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS7_0 00884 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS8_0 00885 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS9_0 00886 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS10_0 00887 * @arg @ref LL_DAC_NOISE_LFSR_UNMASK_BITS11_0 00888 */ 00889 __STATIC_INLINE uint32_t LL_DAC_GetWaveNoiseLFSR(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00890 { 00891 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00892 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00893 ); 00894 } 00895 00896 /** 00897 * @brief Set the triangle waveform generation for the selected DAC channel: 00898 * triangle mode and amplitude. 00899 * @note For wave generation to be effective, DAC channel 00900 * wave generation mode must be enabled using 00901 * function @ref LL_DAC_SetWaveAutoGeneration(). 00902 * @note This setting can be set when the selected DAC channel is disabled 00903 * (otherwise, the setting operation is ignored). 00904 * @rmtoll CR MAMP1 LL_DAC_SetWaveTriangleAmplitude\n 00905 * CR MAMP2 LL_DAC_SetWaveTriangleAmplitude 00906 * @param DACx DAC instance 00907 * @param DAC_Channel This parameter can be one of the following values: 00908 * @arg @ref LL_DAC_CHANNEL_1 00909 * @arg @ref LL_DAC_CHANNEL_2 (1) 00910 * 00911 * (1) On this STM32 serie, parameter not available on all devices. 00912 * Refer to device datasheet for channels availability. 00913 * @param TriangleAmplitude This parameter can be one of the following values: 00914 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00915 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00916 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00917 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00918 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00919 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00920 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00921 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00922 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00923 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00924 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00925 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00926 * @retval None 00927 */ 00928 __STATIC_INLINE void LL_DAC_SetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t TriangleAmplitude) 00929 { 00930 MODIFY_REG(DACx->CR, 00931 DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 00932 TriangleAmplitude << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 00933 } 00934 00935 /** 00936 * @brief Get the triangle waveform generation for the selected DAC channel: 00937 * triangle mode and amplitude. 00938 * @rmtoll CR MAMP1 LL_DAC_GetWaveTriangleAmplitude\n 00939 * CR MAMP2 LL_DAC_GetWaveTriangleAmplitude 00940 * @param DACx DAC instance 00941 * @param DAC_Channel This parameter can be one of the following values: 00942 * @arg @ref LL_DAC_CHANNEL_1 00943 * @arg @ref LL_DAC_CHANNEL_2 (1) 00944 * 00945 * (1) On this STM32 serie, parameter not available on all devices. 00946 * Refer to device datasheet for channels availability. 00947 * @retval Returned value can be one of the following values: 00948 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1 00949 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_3 00950 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_7 00951 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_15 00952 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_31 00953 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_63 00954 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_127 00955 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_255 00956 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_511 00957 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_1023 00958 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_2047 00959 * @arg @ref LL_DAC_TRIANGLE_AMPLITUDE_4095 00960 */ 00961 __STATIC_INLINE uint32_t LL_DAC_GetWaveTriangleAmplitude(DAC_TypeDef *DACx, uint32_t DAC_Channel) 00962 { 00963 return (uint32_t)(READ_BIT(DACx->CR, DAC_CR_MAMP1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 00964 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 00965 ); 00966 } 00967 00968 /** 00969 * @brief Set the output for the selected DAC channel. 00970 * @note This function set several features: 00971 * - mode normal or sample-and-hold 00972 * - buffer 00973 * - connection to GPIO or internal path. 00974 * These features can also be set individually using 00975 * dedicated functions: 00976 * - @ref LL_DAC_SetOutputBuffer() 00977 * - @ref LL_DAC_SetOutputMode() 00978 * - @ref LL_DAC_SetOutputConnection() 00979 * @note On this STM32 serie, output connection depends on output mode 00980 * (normal or sample and hold) and output buffer state. 00981 * - if output connection is set to internal path and output buffer 00982 * is enabled (whatever output mode): 00983 * output connection is also connected to GPIO pin 00984 * (both connections to GPIO pin and internal path). 00985 * - if output connection is set to GPIO pin, output buffer 00986 * is disabled, output mode set to sample and hold: 00987 * output connection is also connected to internal path 00988 * (both connections to GPIO pin and internal path). 00989 * @note Mode sample-and-hold requires an external capacitor 00990 * to be connected between DAC channel output and ground. 00991 * Capacitor value depends on load on DAC channel output and 00992 * sample-and-hold timings configured. 00993 * As indication, capacitor typical value is 100nF 00994 * (refer to device datasheet, parameter "CSH"). 00995 * @rmtoll CR MODE1 LL_DAC_ConfigOutput\n 00996 * CR MODE2 LL_DAC_ConfigOutput 00997 * @param DACx DAC instance 00998 * @param DAC_Channel This parameter can be one of the following values: 00999 * @arg @ref LL_DAC_CHANNEL_1 01000 * @arg @ref LL_DAC_CHANNEL_2 (1) 01001 * 01002 * (1) On this STM32 serie, parameter not available on all devices. 01003 * Refer to device datasheet for channels availability. 01004 * @param OutputMode This parameter can be one of the following values: 01005 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 01006 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 01007 * @param OutputBuffer This parameter can be one of the following values: 01008 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 01009 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 01010 * @param OutputConnection This parameter can be one of the following values: 01011 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 01012 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 01013 * @retval None 01014 */ 01015 __STATIC_INLINE void LL_DAC_ConfigOutput(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode, uint32_t OutputBuffer, uint32_t OutputConnection) 01016 { 01017 MODIFY_REG(DACx->MCR, 01018 (DAC_MCR_MODE1_2 | DAC_MCR_MODE1_1 | DAC_MCR_MODE1_0) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01019 (OutputMode | OutputBuffer | OutputConnection) << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01020 } 01021 01022 /** 01023 * @brief Set the output mode normal or sample-and-hold 01024 * for the selected DAC channel. 01025 * @note Mode sample-and-hold requires an external capacitor 01026 * to be connected between DAC channel output and ground. 01027 * Capacitor value depends on load on DAC channel output and 01028 * sample-and-hold timings configured. 01029 * As indication, capacitor typical value is 100nF 01030 * (refer to device datasheet, parameter "CSH"). 01031 * @rmtoll CR MODE1 LL_DAC_SetOutputMode\n 01032 * CR MODE2 LL_DAC_SetOutputMode 01033 * @param DACx DAC instance 01034 * @param DAC_Channel This parameter can be one of the following values: 01035 * @arg @ref LL_DAC_CHANNEL_1 01036 * @arg @ref LL_DAC_CHANNEL_2 (1) 01037 * 01038 * (1) On this STM32 serie, parameter not available on all devices. 01039 * Refer to device datasheet for channels availability. 01040 * @param OutputMode This parameter can be one of the following values: 01041 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 01042 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 01043 * @retval None 01044 */ 01045 __STATIC_INLINE void LL_DAC_SetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputMode) 01046 { 01047 MODIFY_REG(DACx->MCR, 01048 DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01049 OutputMode << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01050 } 01051 01052 /** 01053 * @brief Get the output mode normal or sample-and-hold for the selected DAC channel. 01054 * @rmtoll CR MODE1 LL_DAC_GetOutputMode\n 01055 * CR MODE2 LL_DAC_GetOutputMode 01056 * @param DACx DAC instance 01057 * @param DAC_Channel This parameter can be one of the following values: 01058 * @arg @ref LL_DAC_CHANNEL_1 01059 * @arg @ref LL_DAC_CHANNEL_2 (1) 01060 * 01061 * (1) On this STM32 serie, parameter not available on all devices. 01062 * Refer to device datasheet for channels availability. 01063 * @retval Returned value can be one of the following values: 01064 * @arg @ref LL_DAC_OUTPUT_MODE_NORMAL 01065 * @arg @ref LL_DAC_OUTPUT_MODE_SAMPLE_AND_HOLD 01066 */ 01067 __STATIC_INLINE uint32_t LL_DAC_GetOutputMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01068 { 01069 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_2 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01070 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01071 ); 01072 } 01073 01074 /** 01075 * @brief Set the output buffer for the selected DAC channel. 01076 * @note On this STM32 serie, when buffer is enabled, its offset can be 01077 * trimmed: factory calibration default values can be 01078 * replaced by user trimming values, using function 01079 * @ref LL_DAC_SetTrimmingValue(). 01080 * @rmtoll CR MODE1 LL_DAC_SetOutputBuffer\n 01081 * CR MODE2 LL_DAC_SetOutputBuffer 01082 * @param DACx DAC instance 01083 * @param DAC_Channel This parameter can be one of the following values: 01084 * @arg @ref LL_DAC_CHANNEL_1 01085 * @arg @ref LL_DAC_CHANNEL_2 (1) 01086 * 01087 * (1) On this STM32 serie, parameter not available on all devices. 01088 * Refer to device datasheet for channels availability. 01089 * @param OutputBuffer This parameter can be one of the following values: 01090 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 01091 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 01092 * @retval None 01093 */ 01094 __STATIC_INLINE void LL_DAC_SetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputBuffer) 01095 { 01096 MODIFY_REG(DACx->MCR, 01097 DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01098 OutputBuffer << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01099 } 01100 01101 /** 01102 * @brief Get the output buffer state for the selected DAC channel. 01103 * @rmtoll CR MODE1 LL_DAC_GetOutputBuffer\n 01104 * CR MODE2 LL_DAC_GetOutputBuffer 01105 * @param DACx DAC instance 01106 * @param DAC_Channel This parameter can be one of the following values: 01107 * @arg @ref LL_DAC_CHANNEL_1 01108 * @arg @ref LL_DAC_CHANNEL_2 (1) 01109 * 01110 * (1) On this STM32 serie, parameter not available on all devices. 01111 * Refer to device datasheet for channels availability. 01112 * @retval Returned value can be one of the following values: 01113 * @arg @ref LL_DAC_OUTPUT_BUFFER_ENABLE 01114 * @arg @ref LL_DAC_OUTPUT_BUFFER_DISABLE 01115 */ 01116 __STATIC_INLINE uint32_t LL_DAC_GetOutputBuffer(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01117 { 01118 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01119 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01120 ); 01121 } 01122 01123 /** 01124 * @brief Set the output connection for the selected DAC channel. 01125 * @note On this STM32 serie, output connection depends on output mode (normal or 01126 * sample and hold) and output buffer state. 01127 * - if output connection is set to internal path and output buffer 01128 * is enabled (whatever output mode): 01129 * output connection is also connected to GPIO pin 01130 * (both connections to GPIO pin and internal path). 01131 * - if output connection is set to GPIO pin, output buffer 01132 * is disabled, output mode set to sample and hold: 01133 * output connection is also connected to internal path 01134 * (both connections to GPIO pin and internal path). 01135 * @rmtoll CR MODE1 LL_DAC_SetOutputConnection\n 01136 * CR MODE2 LL_DAC_SetOutputConnection 01137 * @param DACx DAC instance 01138 * @param DAC_Channel This parameter can be one of the following values: 01139 * @arg @ref LL_DAC_CHANNEL_1 01140 * @arg @ref LL_DAC_CHANNEL_2 (1) 01141 * 01142 * (1) On this STM32 serie, parameter not available on all devices. 01143 * Refer to device datasheet for channels availability. 01144 * @param OutputConnection This parameter can be one of the following values: 01145 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 01146 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 01147 * @retval None 01148 */ 01149 __STATIC_INLINE void LL_DAC_SetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t OutputConnection) 01150 { 01151 MODIFY_REG(DACx->MCR, 01152 DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01153 OutputConnection << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01154 } 01155 01156 /** 01157 * @brief Get the output connection for the selected DAC channel. 01158 * @note On this STM32 serie, output connection depends on output mode (normal or 01159 * sample and hold) and output buffer state. 01160 * - if output connection is set to internal path and output buffer 01161 * is enabled (whatever output mode): 01162 * output connection is also connected to GPIO pin 01163 * (both connections to GPIO pin and internal path). 01164 * - if output connection is set to GPIO pin, output buffer 01165 * is disabled, output mode set to sample and hold: 01166 * output connection is also connected to internal path 01167 * (both connections to GPIO pin and internal path). 01168 * @rmtoll CR MODE1 LL_DAC_GetOutputConnection\n 01169 * CR MODE2 LL_DAC_GetOutputConnection 01170 * @param DACx DAC instance 01171 * @param DAC_Channel This parameter can be one of the following values: 01172 * @arg @ref LL_DAC_CHANNEL_1 01173 * @arg @ref LL_DAC_CHANNEL_2 (1) 01174 * 01175 * (1) On this STM32 serie, parameter not available on all devices. 01176 * Refer to device datasheet for channels availability. 01177 * @retval Returned value can be one of the following values: 01178 * @arg @ref LL_DAC_OUTPUT_CONNECT_GPIO 01179 * @arg @ref LL_DAC_OUTPUT_CONNECT_INTERNAL 01180 */ 01181 __STATIC_INLINE uint32_t LL_DAC_GetOutputConnection(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01182 { 01183 return (uint32_t)(READ_BIT(DACx->MCR, DAC_MCR_MODE1_0 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01184 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01185 ); 01186 } 01187 01188 /** 01189 * @brief Set the sample-and-hold timing for the selected DAC channel: 01190 * sample time 01191 * @note Sample time must be set when DAC channel is disabled 01192 * or during DAC operation when DAC channel flag BWSTx is reset, 01193 * otherwise the setting is ignored. 01194 * Check BWSTx flag state using function "LL_DAC_IsActiveFlag_BWSTx()". 01195 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_SetSampleAndHoldSampleTime\n 01196 * SHSR2 TSAMPLE2 LL_DAC_SetSampleAndHoldSampleTime 01197 * @param DACx DAC instance 01198 * @param DAC_Channel This parameter can be one of the following values: 01199 * @arg @ref LL_DAC_CHANNEL_1 01200 * @arg @ref LL_DAC_CHANNEL_2 (1) 01201 * 01202 * (1) On this STM32 serie, parameter not available on all devices. 01203 * Refer to device datasheet for channels availability. 01204 * @param SampleTime Value between Min_Data=0x000 and Max_Data=0x3FF 01205 * @retval None 01206 */ 01207 __STATIC_INLINE void LL_DAC_SetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t SampleTime) 01208 { 01209 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK)); 01210 01211 MODIFY_REG(*preg, 01212 DAC_SHSR1_TSAMPLE1, 01213 SampleTime); 01214 } 01215 01216 /** 01217 * @brief Get the sample-and-hold timing for the selected DAC channel: 01218 * sample time 01219 * @rmtoll SHSR1 TSAMPLE1 LL_DAC_GetSampleAndHoldSampleTime\n 01220 * SHSR2 TSAMPLE2 LL_DAC_GetSampleAndHoldSampleTime 01221 * @param DACx DAC instance 01222 * @param DAC_Channel This parameter can be one of the following values: 01223 * @arg @ref LL_DAC_CHANNEL_1 01224 * @arg @ref LL_DAC_CHANNEL_2 (1) 01225 * 01226 * (1) On this STM32 serie, parameter not available on all devices. 01227 * Refer to device datasheet for channels availability. 01228 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 01229 */ 01230 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldSampleTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01231 { 01232 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->SHSR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_SHSRX_REGOFFSET_MASK)); 01233 01234 return (uint32_t) READ_BIT(*preg, DAC_SHSR1_TSAMPLE1); 01235 } 01236 01237 /** 01238 * @brief Set the sample-and-hold timing for the selected DAC channel: 01239 * hold time 01240 * @rmtoll SHHR THOLD1 LL_DAC_SetSampleAndHoldHoldTime\n 01241 * SHHR THOLD2 LL_DAC_SetSampleAndHoldHoldTime 01242 * @param DACx DAC instance 01243 * @param DAC_Channel This parameter can be one of the following values: 01244 * @arg @ref LL_DAC_CHANNEL_1 01245 * @arg @ref LL_DAC_CHANNEL_2 (1) 01246 * 01247 * (1) On this STM32 serie, parameter not available on all devices. 01248 * Refer to device datasheet for channels availability. 01249 * @param HoldTime Value between Min_Data=0x000 and Max_Data=0x3FF 01250 * @retval None 01251 */ 01252 __STATIC_INLINE void LL_DAC_SetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t HoldTime) 01253 { 01254 MODIFY_REG(DACx->SHHR, 01255 DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01256 HoldTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01257 } 01258 01259 /** 01260 * @brief Get the sample-and-hold timing for the selected DAC channel: 01261 * hold time 01262 * @rmtoll SHHR THOLD1 LL_DAC_GetSampleAndHoldHoldTime\n 01263 * SHHR THOLD2 LL_DAC_GetSampleAndHoldHoldTime 01264 * @param DACx DAC instance 01265 * @param DAC_Channel This parameter can be one of the following values: 01266 * @arg @ref LL_DAC_CHANNEL_1 01267 * @arg @ref LL_DAC_CHANNEL_2 (1) 01268 * 01269 * (1) On this STM32 serie, parameter not available on all devices. 01270 * Refer to device datasheet for channels availability. 01271 * @retval Value between Min_Data=0x000 and Max_Data=0x3FF 01272 */ 01273 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldHoldTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01274 { 01275 return (uint32_t)(READ_BIT(DACx->SHHR, DAC_SHHR_THOLD1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01276 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01277 ); 01278 } 01279 01280 /** 01281 * @brief Set the sample-and-hold timing for the selected DAC channel: 01282 * refresh time 01283 * @rmtoll SHRR TREFRESH1 LL_DAC_SetSampleAndHoldRefreshTime\n 01284 * SHRR TREFRESH2 LL_DAC_SetSampleAndHoldRefreshTime 01285 * @param DACx DAC instance 01286 * @param DAC_Channel This parameter can be one of the following values: 01287 * @arg @ref LL_DAC_CHANNEL_1 01288 * @arg @ref LL_DAC_CHANNEL_2 (1) 01289 * 01290 * (1) On this STM32 serie, parameter not available on all devices. 01291 * Refer to device datasheet for channels availability. 01292 * @param RefreshTime Value between Min_Data=0x00 and Max_Data=0xFF 01293 * @retval None 01294 */ 01295 __STATIC_INLINE void LL_DAC_SetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t RefreshTime) 01296 { 01297 MODIFY_REG(DACx->SHRR, 01298 DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK), 01299 RefreshTime << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01300 } 01301 01302 /** 01303 * @brief Get the sample-and-hold timing for the selected DAC channel: 01304 * refresh time 01305 * @rmtoll SHRR TREFRESH1 LL_DAC_GetSampleAndHoldRefreshTime\n 01306 * SHRR TREFRESH2 LL_DAC_GetSampleAndHoldRefreshTime 01307 * @param DACx DAC instance 01308 * @param DAC_Channel This parameter can be one of the following values: 01309 * @arg @ref LL_DAC_CHANNEL_1 01310 * @arg @ref LL_DAC_CHANNEL_2 (1) 01311 * 01312 * (1) On this STM32 serie, parameter not available on all devices. 01313 * Refer to device datasheet for channels availability. 01314 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 01315 */ 01316 __STATIC_INLINE uint32_t LL_DAC_GetSampleAndHoldRefreshTime(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01317 { 01318 return (uint32_t)(READ_BIT(DACx->SHRR, DAC_SHRR_TREFRESH1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01319 >> (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK) 01320 ); 01321 } 01322 01323 /** 01324 * @} 01325 */ 01326 01327 /** @defgroup DAC_LL_EF_Configuration_Legacy_Functions DAC configuration, legacy functions name 01328 * @{ 01329 */ 01330 /* Old functions name kept for legacy purpose, to be replaced by the */ 01331 /* current functions name. */ 01332 __STATIC_INLINE void LL_DAC_SetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t WaveMode) 01333 { 01334 LL_DAC_SetWaveAutoGeneration(DACx, DAC_Channel, WaveMode); 01335 } 01336 __STATIC_INLINE uint32_t LL_DAC_GetWaveMode(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01337 { 01338 return LL_DAC_GetWaveAutoGeneration(DACx, DAC_Channel); 01339 } 01340 01341 /** 01342 * @} 01343 */ 01344 01345 /** @defgroup DAC_LL_EF_DMA_Management DMA Management 01346 * @{ 01347 */ 01348 01349 /** 01350 * @brief Enable DAC DMA transfer request of the selected channel. 01351 * @note To configure DMA source address (peripheral address), 01352 * use function @ref LL_DAC_DMA_GetRegAddr(). 01353 * @rmtoll CR DMAEN1 LL_DAC_EnableDMAReq\n 01354 * CR DMAEN2 LL_DAC_EnableDMAReq 01355 * @param DACx DAC instance 01356 * @param DAC_Channel This parameter can be one of the following values: 01357 * @arg @ref LL_DAC_CHANNEL_1 01358 * @arg @ref LL_DAC_CHANNEL_2 (1) 01359 * 01360 * (1) On this STM32 serie, parameter not available on all devices. 01361 * Refer to device datasheet for channels availability. 01362 * @retval None 01363 */ 01364 __STATIC_INLINE void LL_DAC_EnableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01365 { 01366 SET_BIT(DACx->CR, 01367 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01368 } 01369 01370 /** 01371 * @brief Disable DAC DMA transfer request of the selected channel. 01372 * @note To configure DMA source address (peripheral address), 01373 * use function @ref LL_DAC_DMA_GetRegAddr(). 01374 * @rmtoll CR DMAEN1 LL_DAC_DisableDMAReq\n 01375 * CR DMAEN2 LL_DAC_DisableDMAReq 01376 * @param DACx DAC instance 01377 * @param DAC_Channel This parameter can be one of the following values: 01378 * @arg @ref LL_DAC_CHANNEL_1 01379 * @arg @ref LL_DAC_CHANNEL_2 (1) 01380 * 01381 * (1) On this STM32 serie, parameter not available on all devices. 01382 * Refer to device datasheet for channels availability. 01383 * @retval None 01384 */ 01385 __STATIC_INLINE void LL_DAC_DisableDMAReq(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01386 { 01387 CLEAR_BIT(DACx->CR, 01388 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01389 } 01390 01391 /** 01392 * @brief Get DAC DMA transfer request state of the selected channel. 01393 * (0: DAC DMA transfer request is disabled, 1: DAC DMA transfer request is enabled) 01394 * @rmtoll CR DMAEN1 LL_DAC_IsDMAReqEnabled\n 01395 * CR DMAEN2 LL_DAC_IsDMAReqEnabled 01396 * @param DACx DAC instance 01397 * @param DAC_Channel This parameter can be one of the following values: 01398 * @arg @ref LL_DAC_CHANNEL_1 01399 * @arg @ref LL_DAC_CHANNEL_2 (1) 01400 * 01401 * (1) On this STM32 serie, parameter not available on all devices. 01402 * Refer to device datasheet for channels availability. 01403 * @retval State of bit (1 or 0). 01404 */ 01405 __STATIC_INLINE uint32_t LL_DAC_IsDMAReqEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01406 { 01407 return (READ_BIT(DACx->CR, 01408 DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01409 == (DAC_CR_DMAEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); 01410 } 01411 01412 /** 01413 * @brief Function to help to configure DMA transfer to DAC: retrieve the 01414 * DAC register address from DAC instance and a list of DAC registers 01415 * intended to be used (most commonly) with DMA transfer. 01416 * @note These DAC registers are data holding registers: 01417 * when DAC conversion is requested, DAC generates a DMA transfer 01418 * request to have data available in DAC data holding registers. 01419 * @note This macro is intended to be used with LL DMA driver, refer to 01420 * function "LL_DMA_ConfigAddresses()". 01421 * Example: 01422 * LL_DMA_ConfigAddresses(DMA1, 01423 * LL_DMA_CHANNEL_1, 01424 * (uint32_t)&< array or variable >, 01425 * LL_DAC_DMA_GetRegAddr(DAC1, LL_DAC_CHANNEL_1, LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED), 01426 * LL_DMA_DIRECTION_MEMORY_TO_PERIPH); 01427 * @rmtoll DHR12R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 01428 * DHR12L1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 01429 * DHR8R1 DACC1DHR LL_DAC_DMA_GetRegAddr\n 01430 * DHR12R2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 01431 * DHR12L2 DACC2DHR LL_DAC_DMA_GetRegAddr\n 01432 * DHR8R2 DACC2DHR LL_DAC_DMA_GetRegAddr 01433 * @param DACx DAC instance 01434 * @param DAC_Channel This parameter can be one of the following values: 01435 * @arg @ref LL_DAC_CHANNEL_1 01436 * @arg @ref LL_DAC_CHANNEL_2 (1) 01437 * 01438 * (1) On this STM32 serie, parameter not available on all devices. 01439 * Refer to device datasheet for channels availability. 01440 * @param Register This parameter can be one of the following values: 01441 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_RIGHT_ALIGNED 01442 * @arg @ref LL_DAC_DMA_REG_DATA_12BITS_LEFT_ALIGNED 01443 * @arg @ref LL_DAC_DMA_REG_DATA_8BITS_RIGHT_ALIGNED 01444 * @retval DAC register address 01445 */ 01446 __STATIC_INLINE uint32_t LL_DAC_DMA_GetRegAddr(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Register) 01447 { 01448 /* Retrieve address of register DHR12Rx, DHR12Lx or DHR8Rx depending on */ 01449 /* DAC channel selected. */ 01450 return ((uint32_t)(__DAC_PTR_REG_OFFSET((DACx)->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, Register)))); 01451 } 01452 /** 01453 * @} 01454 */ 01455 01456 /** @defgroup DAC_LL_EF_Operation Operation on DAC channels 01457 * @{ 01458 */ 01459 01460 /** 01461 * @brief Enable DAC selected channel. 01462 * @rmtoll CR EN1 LL_DAC_Enable\n 01463 * CR EN2 LL_DAC_Enable 01464 * @note After enable from off state, DAC channel requires a delay 01465 * for output voltage to reach accuracy +/- 1 LSB. 01466 * Refer to device datasheet, parameter "tWAKEUP". 01467 * @param DACx DAC instance 01468 * @param DAC_Channel This parameter can be one of the following values: 01469 * @arg @ref LL_DAC_CHANNEL_1 01470 * @arg @ref LL_DAC_CHANNEL_2 (1) 01471 * 01472 * (1) On this STM32 serie, parameter not available on all devices. 01473 * Refer to device datasheet for channels availability. 01474 * @retval None 01475 */ 01476 __STATIC_INLINE void LL_DAC_Enable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01477 { 01478 SET_BIT(DACx->CR, 01479 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01480 } 01481 01482 /** 01483 * @brief Disable DAC selected channel. 01484 * @rmtoll CR EN1 LL_DAC_Disable\n 01485 * CR EN2 LL_DAC_Disable 01486 * @param DACx DAC instance 01487 * @param DAC_Channel This parameter can be one of the following values: 01488 * @arg @ref LL_DAC_CHANNEL_1 01489 * @arg @ref LL_DAC_CHANNEL_2 (1) 01490 * 01491 * (1) On this STM32 serie, parameter not available on all devices. 01492 * Refer to device datasheet for channels availability. 01493 * @retval None 01494 */ 01495 __STATIC_INLINE void LL_DAC_Disable(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01496 { 01497 CLEAR_BIT(DACx->CR, 01498 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01499 } 01500 01501 /** 01502 * @brief Get DAC enable state of the selected channel. 01503 * (0: DAC channel is disabled, 1: DAC channel is enabled) 01504 * @rmtoll CR EN1 LL_DAC_IsEnabled\n 01505 * CR EN2 LL_DAC_IsEnabled 01506 * @param DACx DAC instance 01507 * @param DAC_Channel This parameter can be one of the following values: 01508 * @arg @ref LL_DAC_CHANNEL_1 01509 * @arg @ref LL_DAC_CHANNEL_2 (1) 01510 * 01511 * (1) On this STM32 serie, parameter not available on all devices. 01512 * Refer to device datasheet for channels availability. 01513 * @retval State of bit (1 or 0). 01514 */ 01515 __STATIC_INLINE uint32_t LL_DAC_IsEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01516 { 01517 return (READ_BIT(DACx->CR, 01518 DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01519 == (DAC_CR_EN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); 01520 } 01521 01522 /** 01523 * @brief Enable DAC trigger of the selected channel. 01524 * @note - If DAC trigger is disabled, DAC conversion is performed 01525 * automatically once the data holding register is updated, 01526 * using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01527 * @ref LL_DAC_ConvertData12RightAligned(), ... 01528 * - If DAC trigger is enabled, DAC conversion is performed 01529 * only when a hardware of software trigger event is occurring. 01530 * Select trigger source using 01531 * function @ref LL_DAC_SetTriggerSource(). 01532 * @rmtoll CR TEN1 LL_DAC_EnableTrigger\n 01533 * CR TEN2 LL_DAC_EnableTrigger 01534 * @param DACx DAC instance 01535 * @param DAC_Channel This parameter can be one of the following values: 01536 * @arg @ref LL_DAC_CHANNEL_1 01537 * @arg @ref LL_DAC_CHANNEL_2 (1) 01538 * 01539 * (1) On this STM32 serie, parameter not available on all devices. 01540 * Refer to device datasheet for channels availability. 01541 * @retval None 01542 */ 01543 __STATIC_INLINE void LL_DAC_EnableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01544 { 01545 SET_BIT(DACx->CR, 01546 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01547 } 01548 01549 /** 01550 * @brief Disable DAC trigger of the selected channel. 01551 * @rmtoll CR TEN1 LL_DAC_DisableTrigger\n 01552 * CR TEN2 LL_DAC_DisableTrigger 01553 * @param DACx DAC instance 01554 * @param DAC_Channel This parameter can be one of the following values: 01555 * @arg @ref LL_DAC_CHANNEL_1 01556 * @arg @ref LL_DAC_CHANNEL_2 (1) 01557 * 01558 * (1) On this STM32 serie, parameter not available on all devices. 01559 * Refer to device datasheet for channels availability. 01560 * @retval None 01561 */ 01562 __STATIC_INLINE void LL_DAC_DisableTrigger(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01563 { 01564 CLEAR_BIT(DACx->CR, 01565 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)); 01566 } 01567 01568 /** 01569 * @brief Get DAC trigger state of the selected channel. 01570 * (0: DAC trigger is disabled, 1: DAC trigger is enabled) 01571 * @rmtoll CR TEN1 LL_DAC_IsTriggerEnabled\n 01572 * CR TEN2 LL_DAC_IsTriggerEnabled 01573 * @param DACx DAC instance 01574 * @param DAC_Channel This parameter can be one of the following values: 01575 * @arg @ref LL_DAC_CHANNEL_1 01576 * @arg @ref LL_DAC_CHANNEL_2 (1) 01577 * 01578 * (1) On this STM32 serie, parameter not available on all devices. 01579 * Refer to device datasheet for channels availability. 01580 * @retval State of bit (1 or 0). 01581 */ 01582 __STATIC_INLINE uint32_t LL_DAC_IsTriggerEnabled(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01583 { 01584 return (READ_BIT(DACx->CR, 01585 DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK)) 01586 == (DAC_CR_TEN1 << (DAC_Channel & DAC_CR_CHX_BITOFFSET_MASK))); 01587 } 01588 01589 /** 01590 * @brief Trig DAC conversion by software for the selected DAC channel. 01591 * @note Preliminarily, DAC trigger must be set to software trigger 01592 * using function @ref LL_DAC_SetTriggerSource() 01593 * with parameter "LL_DAC_TRIGGER_SOFTWARE". 01594 * and DAC trigger must be enabled using 01595 * function @ref LL_DAC_EnableTrigger(). 01596 * @note For devices featuring DAC with 2 channels: this function 01597 * can perform a SW start of both DAC channels simultaneously. 01598 * Two channels can be selected as parameter. 01599 * Example: (LL_DAC_CHANNEL_1 | LL_DAC_CHANNEL_2) 01600 * @rmtoll SWTRIGR SWTRIG1 LL_DAC_TrigSWConversion\n 01601 * SWTRIGR SWTRIG2 LL_DAC_TrigSWConversion 01602 * @param DACx DAC instance 01603 * @param DAC_Channel This parameter can a combination of the following values: 01604 * @arg @ref LL_DAC_CHANNEL_1 01605 * @arg @ref LL_DAC_CHANNEL_2 (1) 01606 * 01607 * (1) On this STM32 serie, parameter not available on all devices. 01608 * Refer to device datasheet for channels availability. 01609 * @retval None 01610 */ 01611 __STATIC_INLINE void LL_DAC_TrigSWConversion(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01612 { 01613 SET_BIT(DACx->SWTRIGR, 01614 (DAC_Channel & DAC_SWTR_CHX_MASK)); 01615 } 01616 01617 /** 01618 * @brief Set the data to be loaded in the data holding register 01619 * in format 12 bits left alignment (LSB aligned on bit 0), 01620 * for the selected DAC channel. 01621 * @rmtoll DHR12R1 DACC1DHR LL_DAC_ConvertData12RightAligned\n 01622 * DHR12R2 DACC2DHR LL_DAC_ConvertData12RightAligned 01623 * @param DACx DAC instance 01624 * @param DAC_Channel This parameter can be one of the following values: 01625 * @arg @ref LL_DAC_CHANNEL_1 01626 * @arg @ref LL_DAC_CHANNEL_2 (1) 01627 * 01628 * (1) On this STM32 serie, parameter not available on all devices. 01629 * Refer to device datasheet for channels availability. 01630 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01631 * @retval None 01632 */ 01633 __STATIC_INLINE void LL_DAC_ConvertData12RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01634 { 01635 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12RX_REGOFFSET_MASK)); 01636 01637 MODIFY_REG(*preg, 01638 DAC_DHR12R1_DACC1DHR, 01639 Data); 01640 } 01641 01642 /** 01643 * @brief Set the data to be loaded in the data holding register 01644 * in format 12 bits left alignment (MSB aligned on bit 15), 01645 * for the selected DAC channel. 01646 * @rmtoll DHR12L1 DACC1DHR LL_DAC_ConvertData12LeftAligned\n 01647 * DHR12L2 DACC2DHR LL_DAC_ConvertData12LeftAligned 01648 * @param DACx DAC instance 01649 * @param DAC_Channel This parameter can be one of the following values: 01650 * @arg @ref LL_DAC_CHANNEL_1 01651 * @arg @ref LL_DAC_CHANNEL_2 (1) 01652 * 01653 * (1) On this STM32 serie, parameter not available on all devices. 01654 * Refer to device datasheet for channels availability. 01655 * @param Data Value between Min_Data=0x000 and Max_Data=0xFFF 01656 * @retval None 01657 */ 01658 __STATIC_INLINE void LL_DAC_ConvertData12LeftAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01659 { 01660 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR12LX_REGOFFSET_MASK)); 01661 01662 MODIFY_REG(*preg, 01663 DAC_DHR12L1_DACC1DHR, 01664 Data); 01665 } 01666 01667 /** 01668 * @brief Set the data to be loaded in the data holding register 01669 * in format 8 bits left alignment (LSB aligned on bit 0), 01670 * for the selected DAC channel. 01671 * @rmtoll DHR8R1 DACC1DHR LL_DAC_ConvertData8RightAligned\n 01672 * DHR8R2 DACC2DHR LL_DAC_ConvertData8RightAligned 01673 * @param DACx DAC instance 01674 * @param DAC_Channel This parameter can be one of the following values: 01675 * @arg @ref LL_DAC_CHANNEL_1 01676 * @arg @ref LL_DAC_CHANNEL_2 (1) 01677 * 01678 * (1) On this STM32 serie, parameter not available on all devices. 01679 * Refer to device datasheet for channels availability. 01680 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF 01681 * @retval None 01682 */ 01683 __STATIC_INLINE void LL_DAC_ConvertData8RightAligned(DAC_TypeDef *DACx, uint32_t DAC_Channel, uint32_t Data) 01684 { 01685 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DHR12R1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DHR8RX_REGOFFSET_MASK)); 01686 01687 MODIFY_REG(*preg, 01688 DAC_DHR8R1_DACC1DHR, 01689 Data); 01690 } 01691 01692 #if defined(DAC_CHANNEL2_SUPPORT) 01693 /** 01694 * @brief Set the data to be loaded in the data holding register 01695 * in format 12 bits left alignment (LSB aligned on bit 0), 01696 * for both DAC channels. 01697 * @rmtoll DHR12RD DACC1DHR LL_DAC_ConvertDualData12RightAligned\n 01698 * DHR12RD DACC2DHR LL_DAC_ConvertDualData12RightAligned 01699 * @param DACx DAC instance 01700 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01701 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01702 * @retval None 01703 */ 01704 __STATIC_INLINE void LL_DAC_ConvertDualData12RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) 01705 { 01706 MODIFY_REG(DACx->DHR12RD, 01707 (DAC_DHR12RD_DACC2DHR | DAC_DHR12RD_DACC1DHR), 01708 ((DataChannel2 << DAC_DHR12RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01709 } 01710 01711 /** 01712 * @brief Set the data to be loaded in the data holding register 01713 * in format 12 bits left alignment (MSB aligned on bit 15), 01714 * for both DAC channels. 01715 * @rmtoll DHR12LD DACC1DHR LL_DAC_ConvertDualData12LeftAligned\n 01716 * DHR12LD DACC2DHR LL_DAC_ConvertDualData12LeftAligned 01717 * @param DACx DAC instance 01718 * @param DataChannel1 Value between Min_Data=0x000 and Max_Data=0xFFF 01719 * @param DataChannel2 Value between Min_Data=0x000 and Max_Data=0xFFF 01720 * @retval None 01721 */ 01722 __STATIC_INLINE void LL_DAC_ConvertDualData12LeftAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) 01723 { 01724 /* Note: Data of DAC channel 2 shift value subtracted of 4 because */ 01725 /* data on 16 bits and DAC channel 2 bits field is on the 12 MSB, */ 01726 /* the 4 LSB must be taken into account for the shift value. */ 01727 MODIFY_REG(DACx->DHR12LD, 01728 (DAC_DHR12LD_DACC2DHR | DAC_DHR12LD_DACC1DHR), 01729 ((DataChannel2 << (DAC_DHR12LD_DACC2DHR_BITOFFSET_POS - 4U)) | DataChannel1)); 01730 } 01731 01732 /** 01733 * @brief Set the data to be loaded in the data holding register 01734 * in format 8 bits left alignment (LSB aligned on bit 0), 01735 * for both DAC channels. 01736 * @rmtoll DHR8RD DACC1DHR LL_DAC_ConvertDualData8RightAligned\n 01737 * DHR8RD DACC2DHR LL_DAC_ConvertDualData8RightAligned 01738 * @param DACx DAC instance 01739 * @param DataChannel1 Value between Min_Data=0x00 and Max_Data=0xFF 01740 * @param DataChannel2 Value between Min_Data=0x00 and Max_Data=0xFF 01741 * @retval None 01742 */ 01743 __STATIC_INLINE void LL_DAC_ConvertDualData8RightAligned(DAC_TypeDef *DACx, uint32_t DataChannel1, uint32_t DataChannel2) 01744 { 01745 MODIFY_REG(DACx->DHR8RD, 01746 (DAC_DHR8RD_DACC2DHR | DAC_DHR8RD_DACC1DHR), 01747 ((DataChannel2 << DAC_DHR8RD_DACC2DHR_BITOFFSET_POS) | DataChannel1)); 01748 } 01749 01750 #endif /* DAC_CHANNEL2_SUPPORT */ 01751 /** 01752 * @brief Retrieve output data currently generated for the selected DAC channel. 01753 * @note Whatever alignment and resolution settings 01754 * (using functions "LL_DAC_ConvertData{8; 12}{Right; Left} Aligned()": 01755 * @ref LL_DAC_ConvertData12RightAligned(), ...), 01756 * output data format is 12 bits right aligned (LSB aligned on bit 0). 01757 * @rmtoll DOR1 DACC1DOR LL_DAC_RetrieveOutputData\n 01758 * DOR2 DACC2DOR LL_DAC_RetrieveOutputData 01759 * @param DACx DAC instance 01760 * @param DAC_Channel This parameter can be one of the following values: 01761 * @arg @ref LL_DAC_CHANNEL_1 01762 * @arg @ref LL_DAC_CHANNEL_2 (1) 01763 * 01764 * (1) On this STM32 serie, parameter not available on all devices. 01765 * Refer to device datasheet for channels availability. 01766 * @retval Value between Min_Data=0x000 and Max_Data=0xFFF 01767 */ 01768 __STATIC_INLINE uint32_t LL_DAC_RetrieveOutputData(DAC_TypeDef *DACx, uint32_t DAC_Channel) 01769 { 01770 register uint32_t *preg = __DAC_PTR_REG_OFFSET(DACx->DOR1, __DAC_MASK_SHIFT(DAC_Channel, DAC_REG_DORX_REGOFFSET_MASK)); 01771 01772 return (uint16_t) READ_BIT(*preg, DAC_DOR1_DACC1DOR); 01773 } 01774 01775 /** 01776 * @} 01777 */ 01778 01779 /** @defgroup DAC_LL_EF_FLAG_Management FLAG Management 01780 * @{ 01781 */ 01782 /** 01783 * @brief Get DAC calibration offset flag for DAC channel 1 01784 * @rmtoll SR CAL_FLAG1 LL_DAC_IsActiveFlag_CAL1 01785 * @param DACx DAC instance 01786 * @retval State of bit (1 or 0). 01787 */ 01788 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL1(DAC_TypeDef *DACx) 01789 { 01790 return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL1) == (LL_DAC_FLAG_CAL1)); 01791 } 01792 01793 #if defined(DAC_CHANNEL2_SUPPORT) 01794 /** 01795 * @brief Get DAC calibration offset flag for DAC channel 2 01796 * @rmtoll SR CAL_FLAG2 LL_DAC_IsActiveFlag_CAL2 01797 * @param DACx DAC instance 01798 * @retval State of bit (1 or 0). 01799 */ 01800 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_CAL2(DAC_TypeDef *DACx) 01801 { 01802 return (READ_BIT(DACx->SR, LL_DAC_FLAG_CAL2) == (LL_DAC_FLAG_CAL2)); 01803 } 01804 01805 #endif /* DAC_CHANNEL2_SUPPORT */ 01806 /** 01807 * @brief Get DAC busy writing sample time flag for DAC channel 1 01808 * @rmtoll SR BWST1 LL_DAC_IsActiveFlag_BWST1 01809 * @param DACx DAC instance 01810 * @retval State of bit (1 or 0). 01811 */ 01812 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST1(DAC_TypeDef *DACx) 01813 { 01814 return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST1) == (LL_DAC_FLAG_BWST1)); 01815 } 01816 01817 #if defined(DAC_CHANNEL2_SUPPORT) 01818 /** 01819 * @brief Get DAC busy writing sample time flag for DAC channel 2 01820 * @rmtoll SR BWST2 LL_DAC_IsActiveFlag_BWST2 01821 * @param DACx DAC instance 01822 * @retval State of bit (1 or 0). 01823 */ 01824 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_BWST2(DAC_TypeDef *DACx) 01825 { 01826 return (READ_BIT(DACx->SR, LL_DAC_FLAG_BWST2) == (LL_DAC_FLAG_BWST2)); 01827 } 01828 01829 #endif /* DAC_CHANNEL2_SUPPORT */ 01830 /** 01831 * @brief Get DAC underrun flag for DAC channel 1 01832 * @rmtoll SR DMAUDR1 LL_DAC_IsActiveFlag_DMAUDR1 01833 * @param DACx DAC instance 01834 * @retval State of bit (1 or 0). 01835 */ 01836 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR1(DAC_TypeDef *DACx) 01837 { 01838 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR1) == (LL_DAC_FLAG_DMAUDR1)); 01839 } 01840 01841 #if defined(DAC_CHANNEL2_SUPPORT) 01842 /** 01843 * @brief Get DAC underrun flag for DAC channel 2 01844 * @rmtoll SR DMAUDR2 LL_DAC_IsActiveFlag_DMAUDR2 01845 * @param DACx DAC instance 01846 * @retval State of bit (1 or 0). 01847 */ 01848 __STATIC_INLINE uint32_t LL_DAC_IsActiveFlag_DMAUDR2(DAC_TypeDef *DACx) 01849 { 01850 return (READ_BIT(DACx->SR, LL_DAC_FLAG_DMAUDR2) == (LL_DAC_FLAG_DMAUDR2)); 01851 } 01852 #endif /* DAC_CHANNEL2_SUPPORT */ 01853 01854 /** 01855 * @brief Clear DAC underrun flag for DAC channel 1 01856 * @rmtoll SR DMAUDR1 LL_DAC_ClearFlag_DMAUDR1 01857 * @param DACx DAC instance 01858 * @retval None 01859 */ 01860 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR1(DAC_TypeDef *DACx) 01861 { 01862 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR1); 01863 } 01864 01865 #if defined(DAC_CHANNEL2_SUPPORT) 01866 /** 01867 * @brief Clear DAC underrun flag for DAC channel 2 01868 * @rmtoll SR DMAUDR2 LL_DAC_ClearFlag_DMAUDR2 01869 * @param DACx DAC instance 01870 * @retval None 01871 */ 01872 __STATIC_INLINE void LL_DAC_ClearFlag_DMAUDR2(DAC_TypeDef *DACx) 01873 { 01874 WRITE_REG(DACx->SR, LL_DAC_FLAG_DMAUDR2); 01875 } 01876 #endif /* DAC_CHANNEL2_SUPPORT */ 01877 01878 /** 01879 * @} 01880 */ 01881 01882 /** @defgroup DAC_LL_EF_IT_Management IT management 01883 * @{ 01884 */ 01885 01886 /** 01887 * @brief Enable DMA underrun interrupt for DAC channel 1 01888 * @rmtoll CR DMAUDRIE1 LL_DAC_EnableIT_DMAUDR1 01889 * @param DACx DAC instance 01890 * @retval None 01891 */ 01892 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR1(DAC_TypeDef *DACx) 01893 { 01894 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01895 } 01896 01897 #if defined(DAC_CHANNEL2_SUPPORT) 01898 /** 01899 * @brief Enable DMA underrun interrupt for DAC channel 2 01900 * @rmtoll CR DMAUDRIE2 LL_DAC_EnableIT_DMAUDR2 01901 * @param DACx DAC instance 01902 * @retval None 01903 */ 01904 __STATIC_INLINE void LL_DAC_EnableIT_DMAUDR2(DAC_TypeDef *DACx) 01905 { 01906 SET_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01907 } 01908 #endif /* DAC_CHANNEL2_SUPPORT */ 01909 01910 /** 01911 * @brief Disable DMA underrun interrupt for DAC channel 1 01912 * @rmtoll CR DMAUDRIE1 LL_DAC_DisableIT_DMAUDR1 01913 * @param DACx DAC instance 01914 * @retval None 01915 */ 01916 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR1(DAC_TypeDef *DACx) 01917 { 01918 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1); 01919 } 01920 01921 #if defined(DAC_CHANNEL2_SUPPORT) 01922 /** 01923 * @brief Disable DMA underrun interrupt for DAC channel 2 01924 * @rmtoll CR DMAUDRIE2 LL_DAC_DisableIT_DMAUDR2 01925 * @param DACx DAC instance 01926 * @retval None 01927 */ 01928 __STATIC_INLINE void LL_DAC_DisableIT_DMAUDR2(DAC_TypeDef *DACx) 01929 { 01930 CLEAR_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2); 01931 } 01932 #endif /* DAC_CHANNEL2_SUPPORT */ 01933 01934 /** 01935 * @brief Get DMA underrun interrupt for DAC channel 1 01936 * @rmtoll CR DMAUDRIE1 LL_DAC_IsEnabledIT_DMAUDR1 01937 * @param DACx DAC instance 01938 * @retval State of bit (1 or 0). 01939 */ 01940 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(DAC_TypeDef *DACx) 01941 { 01942 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE1) == (LL_DAC_IT_DMAUDRIE1)); 01943 } 01944 01945 #if defined(DAC_CHANNEL2_SUPPORT) 01946 /** 01947 * @brief Get DMA underrun interrupt for DAC channel 2 01948 * @rmtoll CR DMAUDRIE2 LL_DAC_IsEnabledIT_DMAUDR2 01949 * @param DACx DAC instance 01950 * @retval State of bit (1 or 0). 01951 */ 01952 __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR2(DAC_TypeDef *DACx) 01953 { 01954 return (READ_BIT(DACx->CR, LL_DAC_IT_DMAUDRIE2) == (LL_DAC_IT_DMAUDRIE2)); 01955 } 01956 #endif /* DAC_CHANNEL2_SUPPORT */ 01957 01958 /** 01959 * @} 01960 */ 01961 01962 #if defined(USE_FULL_LL_DRIVER) 01963 /** @defgroup DAC_LL_EF_Init Initialization and de-initialization functions 01964 * @{ 01965 */ 01966 01967 ErrorStatus LL_DAC_DeInit(DAC_TypeDef* DACx); 01968 ErrorStatus LL_DAC_Init(DAC_TypeDef* DACx, uint32_t DAC_Channel, LL_DAC_InitTypeDef* DAC_InitStruct); 01969 void LL_DAC_StructInit(LL_DAC_InitTypeDef* DAC_InitStruct); 01970 01971 /** 01972 * @} 01973 */ 01974 #endif /* USE_FULL_LL_DRIVER */ 01975 01976 /** 01977 * @} 01978 */ 01979 01980 /** 01981 * @} 01982 */ 01983 01984 #endif /* DAC1 */ 01985 01986 /** 01987 * @} 01988 */ 01989 01990 #ifdef __cplusplus 01991 } 01992 #endif 01993 01994 #endif /* __STM32L4xx_LL_DAC_H */ 01995 01996 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1