STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_crs.h 00004 * @author MCD Application Team 00005 * @brief Header file of CRS LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_LL_CRS_H 00038 #define __STM32L4xx_LL_CRS_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx.h" 00046 00047 /** @addtogroup STM32L4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined(CRS) 00052 00053 /** @defgroup CRS_LL CRS 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /* Private constants ---------------------------------------------------------*/ 00060 /* Private macros ------------------------------------------------------------*/ 00061 00062 /* Exported types ------------------------------------------------------------*/ 00063 /* Exported constants --------------------------------------------------------*/ 00064 /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants 00065 * @{ 00066 */ 00067 00068 /** @defgroup CRS_LL_EC_GET_FLAG Get Flags Defines 00069 * @brief Flags defines which can be used with LL_CRS_ReadReg function 00070 * @{ 00071 */ 00072 #define LL_CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF 00073 #define LL_CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF 00074 #define LL_CRS_ISR_ERRF CRS_ISR_ERRF 00075 #define LL_CRS_ISR_ESYNCF CRS_ISR_ESYNCF 00076 #define LL_CRS_ISR_SYNCERR CRS_ISR_SYNCERR 00077 #define LL_CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS 00078 #define LL_CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF 00079 /** 00080 * @} 00081 */ 00082 00083 /** @defgroup CRS_LL_EC_IT IT Defines 00084 * @brief IT defines which can be used with LL_CRS_ReadReg and LL_CRS_WriteReg functions 00085 * @{ 00086 */ 00087 #define LL_CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE 00088 #define LL_CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE 00089 #define LL_CRS_CR_ERRIE CRS_CR_ERRIE 00090 #define LL_CRS_CR_ESYNCIE CRS_CR_ESYNCIE 00091 /** 00092 * @} 00093 */ 00094 00095 /** @defgroup CRS_LL_EC_SYNC_DIV Synchronization Signal Divider 00096 * @{ 00097 */ 00098 #define LL_CRS_SYNC_DIV_1 ((uint32_t)0x00U) /*!< Synchro Signal not divided (default) */ 00099 #define LL_CRS_SYNC_DIV_2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */ 00100 #define LL_CRS_SYNC_DIV_4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */ 00101 #define LL_CRS_SYNC_DIV_8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */ 00102 #define LL_CRS_SYNC_DIV_16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */ 00103 #define LL_CRS_SYNC_DIV_32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */ 00104 #define LL_CRS_SYNC_DIV_64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */ 00105 #define LL_CRS_SYNC_DIV_128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */ 00106 /** 00107 * @} 00108 */ 00109 00110 /** @defgroup CRS_LL_EC_SYNC_SOURCE Synchronization Signal Source 00111 * @{ 00112 */ 00113 #define LL_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00U) /*!< Synchro Signal soucre GPIO */ 00114 #define LL_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */ 00115 #define LL_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/ 00116 /** 00117 * @} 00118 */ 00119 00120 /** @defgroup CRS_LL_EC_SYNC_POLARITY Synchronization Signal Polarity 00121 * @{ 00122 */ 00123 #define LL_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00U) /*!< Synchro Active on rising edge (default) */ 00124 #define LL_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */ 00125 /** 00126 * @} 00127 */ 00128 00129 /** @defgroup CRS_LL_EC_FREQERRORDIR Frequency Error Direction 00130 * @{ 00131 */ 00132 #define LL_CRS_FREQ_ERROR_DIR_UP ((uint32_t)0x00U) /*!< Upcounting direction, the actual frequency is above the target */ 00133 #define LL_CRS_FREQ_ERROR_DIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */ 00134 /** 00135 * @} 00136 */ 00137 00138 /** @defgroup CRS_LL_EC_DEFAULTVALUES Default Values 00139 * @{ 00140 */ 00141 /** 00142 * @brief Reset value of the RELOAD field 00143 * @note The reset value of the RELOAD field corresponds to a target frequency of 48 MHz 00144 * and a synchronization signal frequency of 1 kHz (SOF signal from USB) 00145 */ 00146 #define LL_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7FU) 00147 00148 /** 00149 * @brief Reset value of Frequency error limit. 00150 */ 00151 #define LL_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22U) 00152 00153 /** 00154 * @brief Reset value of the HSI48 Calibration field 00155 * @note The default value is 32, which corresponds to the middle of the trimming interval. 00156 * The trimming step is around 67 kHz between two consecutive TRIM steps. 00157 * A higher TRIM value corresponds to a higher output frequency 00158 */ 00159 #define LL_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20U) 00160 /** 00161 * @} 00162 */ 00163 00164 /** 00165 * @} 00166 */ 00167 00168 /* Exported macro ------------------------------------------------------------*/ 00169 /** @defgroup CRS_LL_Exported_Macros CRS Exported Macros 00170 * @{ 00171 */ 00172 00173 /** @defgroup CRS_LL_EM_WRITE_READ Common Write and read registers Macros 00174 * @{ 00175 */ 00176 00177 /** 00178 * @brief Write a value in CRS register 00179 * @param __INSTANCE__ CRS Instance 00180 * @param __REG__ Register to be written 00181 * @param __VALUE__ Value to be written in the register 00182 * @retval None 00183 */ 00184 #define LL_CRS_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00185 00186 /** 00187 * @brief Read a value in CRS register 00188 * @param __INSTANCE__ CRS Instance 00189 * @param __REG__ Register to be read 00190 * @retval Register value 00191 */ 00192 #define LL_CRS_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00193 /** 00194 * @} 00195 */ 00196 00197 /** @defgroup CRS_LL_EM_Exported_Macros_Calculate_Reload Exported_Macros_Calculate_Reload 00198 * @{ 00199 */ 00200 00201 /** 00202 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies 00203 * @note The RELOAD value should be selected according to the ratio between 00204 * the target frequency and the frequency of the synchronization source after 00205 * prescaling. It is then decreased by one in order to reach the expected 00206 * synchronization on the zero value. The formula is the following: 00207 * RELOAD = (fTARGET / fSYNC) -1 00208 * @param __FTARGET__ Target frequency (value in Hz) 00209 * @param __FSYNC__ Synchronization signal frequency (value in Hz) 00210 * @retval Reload value (in Hz) 00211 */ 00212 #define __LL_CRS_CALC_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1U) 00213 00214 /** 00215 * @} 00216 */ 00217 00218 /** 00219 * @} 00220 */ 00221 00222 /* Exported functions --------------------------------------------------------*/ 00223 /** @defgroup CRS_LL_Exported_Functions CRS Exported Functions 00224 * @{ 00225 */ 00226 00227 /** @defgroup CRS_LL_EF_Configuration Configuration 00228 * @{ 00229 */ 00230 00231 /** 00232 * @brief Enable Frequency error counter 00233 * @note When this bit is set, the CRS_CFGR register is write-protected and cannot be modified 00234 * @rmtoll CR CEN LL_CRS_EnableFreqErrorCounter 00235 * @retval None 00236 */ 00237 __STATIC_INLINE void LL_CRS_EnableFreqErrorCounter(void) 00238 { 00239 SET_BIT(CRS->CR, CRS_CR_CEN); 00240 } 00241 00242 /** 00243 * @brief Disable Frequency error counter 00244 * @rmtoll CR CEN LL_CRS_DisableFreqErrorCounter 00245 * @retval None 00246 */ 00247 __STATIC_INLINE void LL_CRS_DisableFreqErrorCounter(void) 00248 { 00249 CLEAR_BIT(CRS->CR, CRS_CR_CEN); 00250 } 00251 00252 /** 00253 * @brief Check if Frequency error counter is enabled or not 00254 * @rmtoll CR CEN LL_CRS_IsEnabledFreqErrorCounter 00255 * @retval State of bit (1 or 0). 00256 */ 00257 __STATIC_INLINE uint32_t LL_CRS_IsEnabledFreqErrorCounter(void) 00258 { 00259 return (READ_BIT(CRS->CR, CRS_CR_CEN) == (CRS_CR_CEN)); 00260 } 00261 00262 /** 00263 * @brief Enable Automatic trimming counter 00264 * @rmtoll CR AUTOTRIMEN LL_CRS_EnableAutoTrimming 00265 * @retval None 00266 */ 00267 __STATIC_INLINE void LL_CRS_EnableAutoTrimming(void) 00268 { 00269 SET_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); 00270 } 00271 00272 /** 00273 * @brief Disable Automatic trimming counter 00274 * @rmtoll CR AUTOTRIMEN LL_CRS_DisableAutoTrimming 00275 * @retval None 00276 */ 00277 __STATIC_INLINE void LL_CRS_DisableAutoTrimming(void) 00278 { 00279 CLEAR_BIT(CRS->CR, CRS_CR_AUTOTRIMEN); 00280 } 00281 00282 /** 00283 * @brief Check if Automatic trimming is enabled or not 00284 * @rmtoll CR AUTOTRIMEN LL_CRS_IsEnabledAutoTrimming 00285 * @retval State of bit (1 or 0). 00286 */ 00287 __STATIC_INLINE uint32_t LL_CRS_IsEnabledAutoTrimming(void) 00288 { 00289 return (READ_BIT(CRS->CR, CRS_CR_AUTOTRIMEN) == (CRS_CR_AUTOTRIMEN)); 00290 } 00291 00292 /** 00293 * @brief Set HSI48 oscillator smooth trimming 00294 * @note When the AUTOTRIMEN bit is set, this field is controlled by hardware and is read-only 00295 * @rmtoll CR TRIM LL_CRS_SetHSI48SmoothTrimming 00296 * @param Value a number between Min_Data = 0 and Max_Data = 63 00297 * @note Default value can be set thanks to @ref LL_CRS_HSI48CALIBRATION_DEFAULT 00298 * @retval None 00299 */ 00300 __STATIC_INLINE void LL_CRS_SetHSI48SmoothTrimming(uint32_t Value) 00301 { 00302 MODIFY_REG(CRS->CR, CRS_CR_TRIM, Value << CRS_CR_TRIM_Pos); 00303 } 00304 00305 /** 00306 * @brief Get HSI48 oscillator smooth trimming 00307 * @rmtoll CR TRIM LL_CRS_GetHSI48SmoothTrimming 00308 * @retval a number between Min_Data = 0 and Max_Data = 63 00309 */ 00310 __STATIC_INLINE uint32_t LL_CRS_GetHSI48SmoothTrimming(void) 00311 { 00312 return (uint32_t)(READ_BIT(CRS->CR, CRS_CR_TRIM) >> CRS_CR_TRIM_Pos); 00313 } 00314 00315 /** 00316 * @brief Set counter reload value 00317 * @rmtoll CFGR RELOAD LL_CRS_SetReloadCounter 00318 * @param Value a number between Min_Data = 0 and Max_Data = 0xFFFF 00319 * @note Default value can be set thanks to @ref LL_CRS_RELOADVALUE_DEFAULT 00320 * Otherwise it can be calculated in using macro @ref __LL_CRS_CALC_CALCULATE_RELOADVALUE (_FTARGET_, _FSYNC_) 00321 * @retval None 00322 */ 00323 __STATIC_INLINE void LL_CRS_SetReloadCounter(uint32_t Value) 00324 { 00325 MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD, Value); 00326 } 00327 00328 /** 00329 * @brief Get counter reload value 00330 * @rmtoll CFGR RELOAD LL_CRS_GetReloadCounter 00331 * @retval a number between Min_Data = 0 and Max_Data = 0xFFFF 00332 */ 00333 __STATIC_INLINE uint32_t LL_CRS_GetReloadCounter(void) 00334 { 00335 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_RELOAD)); 00336 } 00337 00338 /** 00339 * @brief Set frequency error limit 00340 * @rmtoll CFGR FELIM LL_CRS_SetFreqErrorLimit 00341 * @param Value a number between Min_Data = 0 and Max_Data = 255 00342 * @note Default value can be set thanks to @ref LL_CRS_ERRORLIMIT_DEFAULT 00343 * @retval None 00344 */ 00345 __STATIC_INLINE void LL_CRS_SetFreqErrorLimit(uint32_t Value) 00346 { 00347 MODIFY_REG(CRS->CFGR, CRS_CFGR_FELIM, Value << CRS_CFGR_FELIM_Pos); 00348 } 00349 00350 /** 00351 * @brief Get frequency error limit 00352 * @rmtoll CFGR FELIM LL_CRS_GetFreqErrorLimit 00353 * @retval A number between Min_Data = 0 and Max_Data = 255 00354 */ 00355 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorLimit(void) 00356 { 00357 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_FELIM) >> CRS_CFGR_FELIM_Pos); 00358 } 00359 00360 /** 00361 * @brief Set division factor for SYNC signal 00362 * @rmtoll CFGR SYNCDIV LL_CRS_SetSyncDivider 00363 * @param Divider This parameter can be one of the following values: 00364 * @arg @ref LL_CRS_SYNC_DIV_1 00365 * @arg @ref LL_CRS_SYNC_DIV_2 00366 * @arg @ref LL_CRS_SYNC_DIV_4 00367 * @arg @ref LL_CRS_SYNC_DIV_8 00368 * @arg @ref LL_CRS_SYNC_DIV_16 00369 * @arg @ref LL_CRS_SYNC_DIV_32 00370 * @arg @ref LL_CRS_SYNC_DIV_64 00371 * @arg @ref LL_CRS_SYNC_DIV_128 00372 * @retval None 00373 */ 00374 __STATIC_INLINE void LL_CRS_SetSyncDivider(uint32_t Divider) 00375 { 00376 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCDIV, Divider); 00377 } 00378 00379 /** 00380 * @brief Get division factor for SYNC signal 00381 * @rmtoll CFGR SYNCDIV LL_CRS_GetSyncDivider 00382 * @retval Returned value can be one of the following values: 00383 * @arg @ref LL_CRS_SYNC_DIV_1 00384 * @arg @ref LL_CRS_SYNC_DIV_2 00385 * @arg @ref LL_CRS_SYNC_DIV_4 00386 * @arg @ref LL_CRS_SYNC_DIV_8 00387 * @arg @ref LL_CRS_SYNC_DIV_16 00388 * @arg @ref LL_CRS_SYNC_DIV_32 00389 * @arg @ref LL_CRS_SYNC_DIV_64 00390 * @arg @ref LL_CRS_SYNC_DIV_128 00391 */ 00392 __STATIC_INLINE uint32_t LL_CRS_GetSyncDivider(void) 00393 { 00394 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCDIV)); 00395 } 00396 00397 /** 00398 * @brief Set SYNC signal source 00399 * @rmtoll CFGR SYNCSRC LL_CRS_SetSyncSignalSource 00400 * @param Source This parameter can be one of the following values: 00401 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO 00402 * @arg @ref LL_CRS_SYNC_SOURCE_LSE 00403 * @arg @ref LL_CRS_SYNC_SOURCE_USB 00404 * @retval None 00405 */ 00406 __STATIC_INLINE void LL_CRS_SetSyncSignalSource(uint32_t Source) 00407 { 00408 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCSRC, Source); 00409 } 00410 00411 /** 00412 * @brief Get SYNC signal source 00413 * @rmtoll CFGR SYNCSRC LL_CRS_GetSyncSignalSource 00414 * @retval Returned value can be one of the following values: 00415 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO 00416 * @arg @ref LL_CRS_SYNC_SOURCE_LSE 00417 * @arg @ref LL_CRS_SYNC_SOURCE_USB 00418 */ 00419 __STATIC_INLINE uint32_t LL_CRS_GetSyncSignalSource(void) 00420 { 00421 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCSRC)); 00422 } 00423 00424 /** 00425 * @brief Set input polarity for the SYNC signal source 00426 * @rmtoll CFGR SYNCPOL LL_CRS_SetSyncPolarity 00427 * @param Polarity This parameter can be one of the following values: 00428 * @arg @ref LL_CRS_SYNC_POLARITY_RISING 00429 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING 00430 * @retval None 00431 */ 00432 __STATIC_INLINE void LL_CRS_SetSyncPolarity(uint32_t Polarity) 00433 { 00434 MODIFY_REG(CRS->CFGR, CRS_CFGR_SYNCPOL, Polarity); 00435 } 00436 00437 /** 00438 * @brief Get input polarity for the SYNC signal source 00439 * @rmtoll CFGR SYNCPOL LL_CRS_GetSyncPolarity 00440 * @retval Returned value can be one of the following values: 00441 * @arg @ref LL_CRS_SYNC_POLARITY_RISING 00442 * @arg @ref LL_CRS_SYNC_POLARITY_FALLING 00443 */ 00444 __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) 00445 { 00446 return (uint32_t)(READ_BIT(CRS->CFGR, CRS_CFGR_SYNCPOL)); 00447 } 00448 00449 /** 00450 * @brief Configure CRS for the synchronization 00451 * @rmtoll CR TRIM LL_CRS_ConfigSynchronization\n 00452 * CFGR RELOAD LL_CRS_ConfigSynchronization\n 00453 * CFGR FELIM LL_CRS_ConfigSynchronization\n 00454 * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n 00455 * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n 00456 * CFGR SYNCPOL LL_CRS_ConfigSynchronization 00457 * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 00458 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF 00459 * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 00460 * @param Settings This parameter can be a combination of the following values: 00461 * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 00462 * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 00463 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB 00464 * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING 00465 * @retval None 00466 */ 00467 __STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) 00468 { 00469 MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); 00470 MODIFY_REG(CRS->CFGR, 00471 CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, 00472 ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); 00473 } 00474 00475 /** 00476 * @} 00477 */ 00478 00479 /** @defgroup CRS_LL_EF_CRS_Management CRS_Management 00480 * @{ 00481 */ 00482 00483 /** 00484 * @brief Generate software SYNC event 00485 * @rmtoll CR SWSYNC LL_CRS_GenerateEvent_SWSYNC 00486 * @retval None 00487 */ 00488 __STATIC_INLINE void LL_CRS_GenerateEvent_SWSYNC(void) 00489 { 00490 SET_BIT(CRS->CR, CRS_CR_SWSYNC); 00491 } 00492 00493 /** 00494 * @brief Get the frequency error direction latched in the time of the last 00495 * SYNC event 00496 * @rmtoll ISR FEDIR LL_CRS_GetFreqErrorDirection 00497 * @retval Returned value can be one of the following values: 00498 * @arg @ref LL_CRS_FREQ_ERROR_DIR_UP 00499 * @arg @ref LL_CRS_FREQ_ERROR_DIR_DOWN 00500 */ 00501 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorDirection(void) 00502 { 00503 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FEDIR)); 00504 } 00505 00506 /** 00507 * @brief Get the frequency error counter value latched in the time of the last SYNC event 00508 * @rmtoll ISR FECAP LL_CRS_GetFreqErrorCapture 00509 * @retval A number between Min_Data = 0x0000 and Max_Data = 0xFFFF 00510 */ 00511 __STATIC_INLINE uint32_t LL_CRS_GetFreqErrorCapture(void) 00512 { 00513 return (uint32_t)(READ_BIT(CRS->ISR, CRS_ISR_FECAP) >> CRS_ISR_FECAP_Pos); 00514 } 00515 00516 /** 00517 * @} 00518 */ 00519 00520 /** @defgroup CRS_LL_EF_FLAG_Management FLAG_Management 00521 * @{ 00522 */ 00523 00524 /** 00525 * @brief Check if SYNC event OK signal occurred or not 00526 * @rmtoll ISR SYNCOKF LL_CRS_IsActiveFlag_SYNCOK 00527 * @retval State of bit (1 or 0). 00528 */ 00529 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCOK(void) 00530 { 00531 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCOKF) == (CRS_ISR_SYNCOKF)); 00532 } 00533 00534 /** 00535 * @brief Check if SYNC warning signal occurred or not 00536 * @rmtoll ISR SYNCWARNF LL_CRS_IsActiveFlag_SYNCWARN 00537 * @retval State of bit (1 or 0). 00538 */ 00539 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCWARN(void) 00540 { 00541 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCWARNF) == (CRS_ISR_SYNCWARNF)); 00542 } 00543 00544 /** 00545 * @brief Check if Synchronization or trimming error signal occurred or not 00546 * @rmtoll ISR ERRF LL_CRS_IsActiveFlag_ERR 00547 * @retval State of bit (1 or 0). 00548 */ 00549 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ERR(void) 00550 { 00551 return (READ_BIT(CRS->ISR, CRS_ISR_ERRF) == (CRS_ISR_ERRF)); 00552 } 00553 00554 /** 00555 * @brief Check if Expected SYNC signal occurred or not 00556 * @rmtoll ISR ESYNCF LL_CRS_IsActiveFlag_ESYNC 00557 * @retval State of bit (1 or 0). 00558 */ 00559 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_ESYNC(void) 00560 { 00561 return (READ_BIT(CRS->ISR, CRS_ISR_ESYNCF) == (CRS_ISR_ESYNCF)); 00562 } 00563 00564 /** 00565 * @brief Check if SYNC error signal occurred or not 00566 * @rmtoll ISR SYNCERR LL_CRS_IsActiveFlag_SYNCERR 00567 * @retval State of bit (1 or 0). 00568 */ 00569 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCERR(void) 00570 { 00571 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCERR) == (CRS_ISR_SYNCERR)); 00572 } 00573 00574 /** 00575 * @brief Check if SYNC missed error signal occurred or not 00576 * @rmtoll ISR SYNCMISS LL_CRS_IsActiveFlag_SYNCMISS 00577 * @retval State of bit (1 or 0). 00578 */ 00579 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_SYNCMISS(void) 00580 { 00581 return (READ_BIT(CRS->ISR, CRS_ISR_SYNCMISS) == (CRS_ISR_SYNCMISS)); 00582 } 00583 00584 /** 00585 * @brief Check if Trimming overflow or underflow occurred or not 00586 * @rmtoll ISR TRIMOVF LL_CRS_IsActiveFlag_TRIMOVF 00587 * @retval State of bit (1 or 0). 00588 */ 00589 __STATIC_INLINE uint32_t LL_CRS_IsActiveFlag_TRIMOVF(void) 00590 { 00591 return (READ_BIT(CRS->ISR, CRS_ISR_TRIMOVF) == (CRS_ISR_TRIMOVF)); 00592 } 00593 00594 /** 00595 * @brief Clear the SYNC event OK flag 00596 * @rmtoll ICR SYNCOKC LL_CRS_ClearFlag_SYNCOK 00597 * @retval None 00598 */ 00599 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCOK(void) 00600 { 00601 WRITE_REG(CRS->ICR, CRS_ICR_SYNCOKC); 00602 } 00603 00604 /** 00605 * @brief Clear the SYNC warning flag 00606 * @rmtoll ICR SYNCWARNC LL_CRS_ClearFlag_SYNCWARN 00607 * @retval None 00608 */ 00609 __STATIC_INLINE void LL_CRS_ClearFlag_SYNCWARN(void) 00610 { 00611 WRITE_REG(CRS->ICR, CRS_ICR_SYNCWARNC); 00612 } 00613 00614 /** 00615 * @brief Clear TRIMOVF, SYNCMISS and SYNCERR bits and consequently also 00616 * the ERR flag 00617 * @rmtoll ICR ERRC LL_CRS_ClearFlag_ERR 00618 * @retval None 00619 */ 00620 __STATIC_INLINE void LL_CRS_ClearFlag_ERR(void) 00621 { 00622 WRITE_REG(CRS->ICR, CRS_ICR_ERRC); 00623 } 00624 00625 /** 00626 * @brief Clear Expected SYNC flag 00627 * @rmtoll ICR ESYNCC LL_CRS_ClearFlag_ESYNC 00628 * @retval None 00629 */ 00630 __STATIC_INLINE void LL_CRS_ClearFlag_ESYNC(void) 00631 { 00632 WRITE_REG(CRS->ICR, CRS_ICR_ESYNCC); 00633 } 00634 00635 /** 00636 * @} 00637 */ 00638 00639 /** @defgroup CRS_LL_EF_IT_Management IT_Management 00640 * @{ 00641 */ 00642 00643 /** 00644 * @brief Enable SYNC event OK interrupt 00645 * @rmtoll CR SYNCOKIE LL_CRS_EnableIT_SYNCOK 00646 * @retval None 00647 */ 00648 __STATIC_INLINE void LL_CRS_EnableIT_SYNCOK(void) 00649 { 00650 SET_BIT(CRS->CR, CRS_CR_SYNCOKIE); 00651 } 00652 00653 /** 00654 * @brief Disable SYNC event OK interrupt 00655 * @rmtoll CR SYNCOKIE LL_CRS_DisableIT_SYNCOK 00656 * @retval None 00657 */ 00658 __STATIC_INLINE void LL_CRS_DisableIT_SYNCOK(void) 00659 { 00660 CLEAR_BIT(CRS->CR, CRS_CR_SYNCOKIE); 00661 } 00662 00663 /** 00664 * @brief Check if SYNC event OK interrupt is enabled or not 00665 * @rmtoll CR SYNCOKIE LL_CRS_IsEnabledIT_SYNCOK 00666 * @retval State of bit (1 or 0). 00667 */ 00668 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCOK(void) 00669 { 00670 return (READ_BIT(CRS->CR, CRS_CR_SYNCOKIE) == (CRS_CR_SYNCOKIE)); 00671 } 00672 00673 /** 00674 * @brief Enable SYNC warning interrupt 00675 * @rmtoll CR SYNCWARNIE LL_CRS_EnableIT_SYNCWARN 00676 * @retval None 00677 */ 00678 __STATIC_INLINE void LL_CRS_EnableIT_SYNCWARN(void) 00679 { 00680 SET_BIT(CRS->CR, CRS_CR_SYNCWARNIE); 00681 } 00682 00683 /** 00684 * @brief Disable SYNC warning interrupt 00685 * @rmtoll CR SYNCWARNIE LL_CRS_DisableIT_SYNCWARN 00686 * @retval None 00687 */ 00688 __STATIC_INLINE void LL_CRS_DisableIT_SYNCWARN(void) 00689 { 00690 CLEAR_BIT(CRS->CR, CRS_CR_SYNCWARNIE); 00691 } 00692 00693 /** 00694 * @brief Check if SYNC warning interrupt is enabled or not 00695 * @rmtoll CR SYNCWARNIE LL_CRS_IsEnabledIT_SYNCWARN 00696 * @retval State of bit (1 or 0). 00697 */ 00698 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_SYNCWARN(void) 00699 { 00700 return (READ_BIT(CRS->CR, CRS_CR_SYNCWARNIE) == (CRS_CR_SYNCWARNIE)); 00701 } 00702 00703 /** 00704 * @brief Enable Synchronization or trimming error interrupt 00705 * @rmtoll CR ERRIE LL_CRS_EnableIT_ERR 00706 * @retval None 00707 */ 00708 __STATIC_INLINE void LL_CRS_EnableIT_ERR(void) 00709 { 00710 SET_BIT(CRS->CR, CRS_CR_ERRIE); 00711 } 00712 00713 /** 00714 * @brief Disable Synchronization or trimming error interrupt 00715 * @rmtoll CR ERRIE LL_CRS_DisableIT_ERR 00716 * @retval None 00717 */ 00718 __STATIC_INLINE void LL_CRS_DisableIT_ERR(void) 00719 { 00720 CLEAR_BIT(CRS->CR, CRS_CR_ERRIE); 00721 } 00722 00723 /** 00724 * @brief Check if Synchronization or trimming error interrupt is enabled or not 00725 * @rmtoll CR ERRIE LL_CRS_IsEnabledIT_ERR 00726 * @retval State of bit (1 or 0). 00727 */ 00728 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ERR(void) 00729 { 00730 return (READ_BIT(CRS->CR, CRS_CR_ERRIE) == (CRS_CR_ERRIE)); 00731 } 00732 00733 /** 00734 * @brief Enable Expected SYNC interrupt 00735 * @rmtoll CR ESYNCIE LL_CRS_EnableIT_ESYNC 00736 * @retval None 00737 */ 00738 __STATIC_INLINE void LL_CRS_EnableIT_ESYNC(void) 00739 { 00740 SET_BIT(CRS->CR, CRS_CR_ESYNCIE); 00741 } 00742 00743 /** 00744 * @brief Disable Expected SYNC interrupt 00745 * @rmtoll CR ESYNCIE LL_CRS_DisableIT_ESYNC 00746 * @retval None 00747 */ 00748 __STATIC_INLINE void LL_CRS_DisableIT_ESYNC(void) 00749 { 00750 CLEAR_BIT(CRS->CR, CRS_CR_ESYNCIE); 00751 } 00752 00753 /** 00754 * @brief Check if Expected SYNC interrupt is enabled or not 00755 * @rmtoll CR ESYNCIE LL_CRS_IsEnabledIT_ESYNC 00756 * @retval State of bit (1 or 0). 00757 */ 00758 __STATIC_INLINE uint32_t LL_CRS_IsEnabledIT_ESYNC(void) 00759 { 00760 return (READ_BIT(CRS->CR, CRS_CR_ESYNCIE) == (CRS_CR_ESYNCIE)); 00761 } 00762 00763 /** 00764 * @} 00765 */ 00766 00767 #if defined(USE_FULL_LL_DRIVER) 00768 /** @defgroup CRS_LL_EF_Init Initialization and de-initialization functions 00769 * @{ 00770 */ 00771 00772 ErrorStatus LL_CRS_DeInit(void); 00773 00774 /** 00775 * @} 00776 */ 00777 #endif /* USE_FULL_LL_DRIVER */ 00778 00779 /** 00780 * @} 00781 */ 00782 00783 /** 00784 * @} 00785 */ 00786 00787 #endif /* defined(CRS) */ 00788 00789 /** 00790 * @} 00791 */ 00792 00793 #ifdef __cplusplus 00794 } 00795 #endif 00796 00797 #endif /* __STM32L4xx_LL_CRS_H */ 00798 00799 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/