STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_ll_cortex.h 00004 * @author MCD Application Team 00005 * @brief Header file of CORTEX LL module. 00006 @verbatim 00007 ============================================================================== 00008 ##### How to use this driver ##### 00009 ============================================================================== 00010 [..] 00011 The LL CORTEX driver contains a set of generic APIs that can be 00012 used by user: 00013 (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick 00014 functions 00015 (+) Low power mode configuration (SCB register of Cortex-MCU) 00016 (+) MPU API to configure and enable regions 00017 (+) API to access to MCU info (CPUID register) 00018 (+) API to enable fault handler (SHCSR accesses) 00019 00020 @endverbatim 00021 ****************************************************************************** 00022 * @attention 00023 * 00024 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00025 * 00026 * Redistribution and use in source and binary forms, with or without modification, 00027 * are permitted provided that the following conditions are met: 00028 * 1. Redistributions of source code must retain the above copyright notice, 00029 * this list of conditions and the following disclaimer. 00030 * 2. Redistributions in binary form must reproduce the above copyright notice, 00031 * this list of conditions and the following disclaimer in the documentation 00032 * and/or other materials provided with the distribution. 00033 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00034 * may be used to endorse or promote products derived from this software 00035 * without specific prior written permission. 00036 * 00037 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00038 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00039 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00040 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00041 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00042 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00043 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00044 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00045 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00046 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00047 * 00048 ****************************************************************************** 00049 */ 00050 00051 /* Define to prevent recursive inclusion -------------------------------------*/ 00052 #ifndef __STM32L4xx_LL_CORTEX_H 00053 #define __STM32L4xx_LL_CORTEX_H 00054 00055 #ifdef __cplusplus 00056 extern "C" { 00057 #endif 00058 00059 /* Includes ------------------------------------------------------------------*/ 00060 #include "stm32l4xx.h" 00061 00062 /** @addtogroup STM32L4xx_LL_Driver 00063 * @{ 00064 */ 00065 00066 /** @defgroup CORTEX_LL CORTEX 00067 * @{ 00068 */ 00069 00070 /* Private types -------------------------------------------------------------*/ 00071 /* Private variables ---------------------------------------------------------*/ 00072 00073 /* Private constants ---------------------------------------------------------*/ 00074 00075 /* Private macros ------------------------------------------------------------*/ 00076 00077 /* Exported types ------------------------------------------------------------*/ 00078 /* Exported constants --------------------------------------------------------*/ 00079 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants 00080 * @{ 00081 */ 00082 00083 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source 00084 * @{ 00085 */ 00086 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ 00087 #define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ 00088 /** 00089 * @} 00090 */ 00091 00092 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type 00093 * @{ 00094 */ 00095 #define LL_HANDLER_FAULT_USG SCB_SHCSR_USGFAULTENA_Msk /*!< Usage fault */ 00096 #define LL_HANDLER_FAULT_BUS SCB_SHCSR_BUSFAULTENA_Msk /*!< Bus fault */ 00097 #define LL_HANDLER_FAULT_MEM SCB_SHCSR_MEMFAULTENA_Msk /*!< Memory management fault */ 00098 /** 00099 * @} 00100 */ 00101 00102 #if __MPU_PRESENT 00103 00104 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control 00105 * @{ 00106 */ 00107 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0x00000000U /*!< Disable NMI and privileged SW access */ 00108 #define LL_MPU_CTRL_HARDFAULT_NMI MPU_CTRL_HFNMIENA_Msk /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */ 00109 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT MPU_CTRL_PRIVDEFENA_Msk /*!< Enable privileged software access to default memory map */ 00110 #define LL_MPU_CTRL_HFNMI_PRIVDEF (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */ 00111 /** 00112 * @} 00113 */ 00114 00115 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number 00116 * @{ 00117 */ 00118 #define LL_MPU_REGION_NUMBER0 0x00U /*!< REGION Number 0 */ 00119 #define LL_MPU_REGION_NUMBER1 0x01U /*!< REGION Number 1 */ 00120 #define LL_MPU_REGION_NUMBER2 0x02U /*!< REGION Number 2 */ 00121 #define LL_MPU_REGION_NUMBER3 0x03U /*!< REGION Number 3 */ 00122 #define LL_MPU_REGION_NUMBER4 0x04U /*!< REGION Number 4 */ 00123 #define LL_MPU_REGION_NUMBER5 0x05U /*!< REGION Number 5 */ 00124 #define LL_MPU_REGION_NUMBER6 0x06U /*!< REGION Number 6 */ 00125 #define LL_MPU_REGION_NUMBER7 0x07U /*!< REGION Number 7 */ 00126 /** 00127 * @} 00128 */ 00129 00130 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size 00131 * @{ 00132 */ 00133 #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ 00134 #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ 00135 #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ 00136 #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ 00137 #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ 00138 #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ 00139 #define LL_MPU_REGION_SIZE_2KB (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */ 00140 #define LL_MPU_REGION_SIZE_4KB (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */ 00141 #define LL_MPU_REGION_SIZE_8KB (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */ 00142 #define LL_MPU_REGION_SIZE_16KB (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */ 00143 #define LL_MPU_REGION_SIZE_32KB (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */ 00144 #define LL_MPU_REGION_SIZE_64KB (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */ 00145 #define LL_MPU_REGION_SIZE_128KB (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */ 00146 #define LL_MPU_REGION_SIZE_256KB (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */ 00147 #define LL_MPU_REGION_SIZE_512KB (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */ 00148 #define LL_MPU_REGION_SIZE_1MB (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */ 00149 #define LL_MPU_REGION_SIZE_2MB (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */ 00150 #define LL_MPU_REGION_SIZE_4MB (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */ 00151 #define LL_MPU_REGION_SIZE_8MB (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */ 00152 #define LL_MPU_REGION_SIZE_16MB (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */ 00153 #define LL_MPU_REGION_SIZE_32MB (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */ 00154 #define LL_MPU_REGION_SIZE_64MB (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */ 00155 #define LL_MPU_REGION_SIZE_128MB (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */ 00156 #define LL_MPU_REGION_SIZE_256MB (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */ 00157 #define LL_MPU_REGION_SIZE_512MB (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */ 00158 #define LL_MPU_REGION_SIZE_1GB (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */ 00159 #define LL_MPU_REGION_SIZE_2GB (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */ 00160 #define LL_MPU_REGION_SIZE_4GB (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */ 00161 /** 00162 * @} 00163 */ 00164 00165 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges 00166 * @{ 00167 */ 00168 #define LL_MPU_REGION_NO_ACCESS (0x00U << MPU_RASR_AP_Pos) /*!< No access*/ 00169 #define LL_MPU_REGION_PRIV_RW (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/ 00170 #define LL_MPU_REGION_PRIV_RW_URO (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */ 00171 #define LL_MPU_REGION_FULL_ACCESS (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */ 00172 #define LL_MPU_REGION_PRIV_RO (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/ 00173 #define LL_MPU_REGION_PRIV_RO_URO (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */ 00174 /** 00175 * @} 00176 */ 00177 00178 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level 00179 * @{ 00180 */ 00181 #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ 00182 #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ 00183 #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ 00184 #define LL_MPU_TEX_LEVEL4 (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */ 00185 /** 00186 * @} 00187 */ 00188 00189 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access 00190 * @{ 00191 */ 00192 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE 0x00U /*!< Instruction fetches enabled */ 00193 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE MPU_RASR_XN_Msk /*!< Instruction fetches disabled*/ 00194 /** 00195 * @} 00196 */ 00197 00198 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access 00199 * @{ 00200 */ 00201 #define LL_MPU_ACCESS_SHAREABLE MPU_RASR_S_Msk /*!< Shareable memory attribute */ 00202 #define LL_MPU_ACCESS_NOT_SHAREABLE 0x00U /*!< Not Shareable memory attribute */ 00203 /** 00204 * @} 00205 */ 00206 00207 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access 00208 * @{ 00209 */ 00210 #define LL_MPU_ACCESS_CACHEABLE MPU_RASR_C_Msk /*!< Cacheable memory attribute */ 00211 #define LL_MPU_ACCESS_NOT_CACHEABLE 0x00U /*!< Not Cacheable memory attribute */ 00212 /** 00213 * @} 00214 */ 00215 00216 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access 00217 * @{ 00218 */ 00219 #define LL_MPU_ACCESS_BUFFERABLE MPU_RASR_B_Msk /*!< Bufferable memory attribute */ 00220 #define LL_MPU_ACCESS_NOT_BUFFERABLE 0x00U /*!< Not Bufferable memory attribute */ 00221 /** 00222 * @} 00223 */ 00224 #endif /* __MPU_PRESENT */ 00225 /** 00226 * @} 00227 */ 00228 00229 /* Exported macro ------------------------------------------------------------*/ 00230 00231 /* Exported functions --------------------------------------------------------*/ 00232 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions 00233 * @{ 00234 */ 00235 00236 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK 00237 * @{ 00238 */ 00239 00240 /** 00241 * @brief This function checks if the Systick counter flag is active or not. 00242 * @note It can be used in timeout function on application side. 00243 * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag 00244 * @retval State of bit (1 or 0). 00245 */ 00246 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) 00247 { 00248 return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)); 00249 } 00250 00251 /** 00252 * @brief Configures the SysTick clock source 00253 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource 00254 * @param Source This parameter can be one of the following values: 00255 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 00256 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 00257 * @retval None 00258 */ 00259 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) 00260 { 00261 if (Source == LL_SYSTICK_CLKSOURCE_HCLK) 00262 { 00263 SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00264 } 00265 else 00266 { 00267 CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00268 } 00269 } 00270 00271 /** 00272 * @brief Get the SysTick clock source 00273 * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource 00274 * @retval Returned value can be one of the following values: 00275 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 00276 * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK 00277 */ 00278 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) 00279 { 00280 return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); 00281 } 00282 00283 /** 00284 * @brief Enable SysTick exception request 00285 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT 00286 * @retval None 00287 */ 00288 __STATIC_INLINE void LL_SYSTICK_EnableIT(void) 00289 { 00290 SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 00291 } 00292 00293 /** 00294 * @brief Disable SysTick exception request 00295 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT 00296 * @retval None 00297 */ 00298 __STATIC_INLINE void LL_SYSTICK_DisableIT(void) 00299 { 00300 CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); 00301 } 00302 00303 /** 00304 * @brief Checks if the SYSTICK interrupt is enabled or disabled. 00305 * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT 00306 * @retval State of bit (1 or 0). 00307 */ 00308 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) 00309 { 00310 return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)); 00311 } 00312 00313 /** 00314 * @} 00315 */ 00316 00317 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE 00318 * @{ 00319 */ 00320 00321 /** 00322 * @brief Processor uses sleep as its low power mode 00323 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep 00324 * @retval None 00325 */ 00326 __STATIC_INLINE void LL_LPM_EnableSleep(void) 00327 { 00328 /* Clear SLEEPDEEP bit of Cortex System Control Register */ 00329 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00330 } 00331 00332 /** 00333 * @brief Processor uses deep sleep as its low power mode 00334 * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep 00335 * @retval None 00336 */ 00337 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void) 00338 { 00339 /* Set SLEEPDEEP bit of Cortex System Control Register */ 00340 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 00341 } 00342 00343 /** 00344 * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. 00345 * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an 00346 * empty main application. 00347 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit 00348 * @retval None 00349 */ 00350 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) 00351 { 00352 /* Set SLEEPONEXIT bit of Cortex System Control Register */ 00353 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 00354 } 00355 00356 /** 00357 * @brief Do not sleep when returning to Thread mode. 00358 * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit 00359 * @retval None 00360 */ 00361 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) 00362 { 00363 /* Clear SLEEPONEXIT bit of Cortex System Control Register */ 00364 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); 00365 } 00366 00367 /** 00368 * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the 00369 * processor. 00370 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend 00371 * @retval None 00372 */ 00373 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void) 00374 { 00375 /* Set SEVEONPEND bit of Cortex System Control Register */ 00376 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 00377 } 00378 00379 /** 00380 * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are 00381 * excluded 00382 * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend 00383 * @retval None 00384 */ 00385 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void) 00386 { 00387 /* Clear SEVEONPEND bit of Cortex System Control Register */ 00388 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); 00389 } 00390 00391 /** 00392 * @} 00393 */ 00394 00395 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER 00396 * @{ 00397 */ 00398 00399 /** 00400 * @brief Enable a fault in System handler control register (SHCSR) 00401 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_EnableFault 00402 * @param Fault This parameter can be a combination of the following values: 00403 * @arg @ref LL_HANDLER_FAULT_USG 00404 * @arg @ref LL_HANDLER_FAULT_BUS 00405 * @arg @ref LL_HANDLER_FAULT_MEM 00406 * @retval None 00407 */ 00408 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault) 00409 { 00410 /* Enable the system handler fault */ 00411 SET_BIT(SCB->SHCSR, Fault); 00412 } 00413 00414 /** 00415 * @brief Disable a fault in System handler control register (SHCSR) 00416 * @rmtoll SCB_SHCSR MEMFAULTENA LL_HANDLER_DisableFault 00417 * @param Fault This parameter can be a combination of the following values: 00418 * @arg @ref LL_HANDLER_FAULT_USG 00419 * @arg @ref LL_HANDLER_FAULT_BUS 00420 * @arg @ref LL_HANDLER_FAULT_MEM 00421 * @retval None 00422 */ 00423 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault) 00424 { 00425 /* Disable the system handler fault */ 00426 CLEAR_BIT(SCB->SHCSR, Fault); 00427 } 00428 00429 /** 00430 * @} 00431 */ 00432 00433 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO 00434 * @{ 00435 */ 00436 00437 /** 00438 * @brief Get Implementer code 00439 * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer 00440 * @retval Value should be equal to 0x41 for ARM 00441 */ 00442 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) 00443 { 00444 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); 00445 } 00446 00447 /** 00448 * @brief Get Variant number (The r value in the rnpn product revision identifier) 00449 * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant 00450 * @retval Value between 0 and 255 (0x0: revision 0) 00451 */ 00452 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) 00453 { 00454 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); 00455 } 00456 00457 /** 00458 * @brief Get Constant number 00459 * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetConstant 00460 * @retval Value should be equal to 0xF for Cortex-M4 devices 00461 */ 00462 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void) 00463 { 00464 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); 00465 } 00466 00467 /** 00468 * @brief Get Part number 00469 * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo 00470 * @retval Value should be equal to 0xC24 for Cortex-M4 00471 */ 00472 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) 00473 { 00474 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); 00475 } 00476 00477 /** 00478 * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) 00479 * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision 00480 * @retval Value between 0 and 255 (0x1: patch 1) 00481 */ 00482 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) 00483 { 00484 return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); 00485 } 00486 00487 /** 00488 * @} 00489 */ 00490 00491 #if __MPU_PRESENT 00492 /** @defgroup CORTEX_LL_EF_MPU MPU 00493 * @{ 00494 */ 00495 00496 /** 00497 * @brief Enable MPU with input options 00498 * @rmtoll MPU_CTRL ENABLE LL_MPU_Enable 00499 * @param Options This parameter can be one of the following values: 00500 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 00501 * @arg @ref LL_MPU_CTRL_HARDFAULT_NMI 00502 * @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT 00503 * @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF 00504 * @retval None 00505 */ 00506 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options) 00507 { 00508 /* Enable the MPU*/ 00509 WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options)); 00510 /* Ensure MPU settings take effects */ 00511 __DSB(); 00512 /* Sequence instruction fetches using update settings */ 00513 __ISB(); 00514 } 00515 00516 /** 00517 * @brief Disable MPU 00518 * @rmtoll MPU_CTRL ENABLE LL_MPU_Disable 00519 * @retval None 00520 */ 00521 __STATIC_INLINE void LL_MPU_Disable(void) 00522 { 00523 /* Make sure outstanding transfers are done */ 00524 __DMB(); 00525 /* Disable MPU*/ 00526 WRITE_REG(MPU->CTRL, 0U); 00527 } 00528 00529 /** 00530 * @brief Check if MPU is enabled or not 00531 * @rmtoll MPU_CTRL ENABLE LL_MPU_IsEnabled 00532 * @retval State of bit (1 or 0). 00533 */ 00534 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void) 00535 { 00536 return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk)); 00537 } 00538 00539 /** 00540 * @brief Enable a MPU region 00541 * @rmtoll MPU_RASR ENABLE LL_MPU_EnableRegion 00542 * @param Region This parameter can be one of the following values: 00543 * @arg @ref LL_MPU_REGION_NUMBER0 00544 * @arg @ref LL_MPU_REGION_NUMBER1 00545 * @arg @ref LL_MPU_REGION_NUMBER2 00546 * @arg @ref LL_MPU_REGION_NUMBER3 00547 * @arg @ref LL_MPU_REGION_NUMBER4 00548 * @arg @ref LL_MPU_REGION_NUMBER5 00549 * @arg @ref LL_MPU_REGION_NUMBER6 00550 * @arg @ref LL_MPU_REGION_NUMBER7 00551 * @retval None 00552 */ 00553 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) 00554 { 00555 /* Set Region number */ 00556 WRITE_REG(MPU->RNR, Region); 00557 /* Enable the MPU region */ 00558 SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 00559 } 00560 00561 /** 00562 * @brief Configure and enable a region 00563 * @rmtoll MPU_RNR REGION LL_MPU_ConfigRegion\n 00564 * MPU_RBAR REGION LL_MPU_ConfigRegion\n 00565 * MPU_RBAR ADDR LL_MPU_ConfigRegion\n 00566 * MPU_RASR XN LL_MPU_ConfigRegion\n 00567 * MPU_RASR AP LL_MPU_ConfigRegion\n 00568 * MPU_RASR S LL_MPU_ConfigRegion\n 00569 * MPU_RASR C LL_MPU_ConfigRegion\n 00570 * MPU_RASR B LL_MPU_ConfigRegion\n 00571 * MPU_RASR SIZE LL_MPU_ConfigRegion 00572 * @param Region This parameter can be one of the following values: 00573 * @arg @ref LL_MPU_REGION_NUMBER0 00574 * @arg @ref LL_MPU_REGION_NUMBER1 00575 * @arg @ref LL_MPU_REGION_NUMBER2 00576 * @arg @ref LL_MPU_REGION_NUMBER3 00577 * @arg @ref LL_MPU_REGION_NUMBER4 00578 * @arg @ref LL_MPU_REGION_NUMBER5 00579 * @arg @ref LL_MPU_REGION_NUMBER6 00580 * @arg @ref LL_MPU_REGION_NUMBER7 00581 * @param Address Value of region base address 00582 * @param SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF 00583 * @param Attributes This parameter can be a combination of the following values: 00584 * @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B 00585 * or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB 00586 * or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB 00587 * or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB 00588 * or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB 00589 * or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB 00590 * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS 00591 * or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO 00592 * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4 00593 * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE 00594 * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE 00595 * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE 00596 * @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE 00597 * @retval None 00598 */ 00599 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes) 00600 { 00601 /* Set Region number */ 00602 WRITE_REG(MPU->RNR, Region); 00603 /* Set base address */ 00604 WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U)); 00605 /* Configure MPU */ 00606 WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos)); 00607 } 00608 00609 /** 00610 * @brief Disable a region 00611 * @rmtoll MPU_RNR REGION LL_MPU_DisableRegion\n 00612 * MPU_RASR ENABLE LL_MPU_DisableRegion 00613 * @param Region This parameter can be one of the following values: 00614 * @arg @ref LL_MPU_REGION_NUMBER0 00615 * @arg @ref LL_MPU_REGION_NUMBER1 00616 * @arg @ref LL_MPU_REGION_NUMBER2 00617 * @arg @ref LL_MPU_REGION_NUMBER3 00618 * @arg @ref LL_MPU_REGION_NUMBER4 00619 * @arg @ref LL_MPU_REGION_NUMBER5 00620 * @arg @ref LL_MPU_REGION_NUMBER6 00621 * @arg @ref LL_MPU_REGION_NUMBER7 00622 * @retval None 00623 */ 00624 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region) 00625 { 00626 /* Set Region number */ 00627 WRITE_REG(MPU->RNR, Region); 00628 /* Disable the MPU region */ 00629 CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk); 00630 } 00631 00632 /** 00633 * @} 00634 */ 00635 00636 #endif /* __MPU_PRESENT */ 00637 /** 00638 * @} 00639 */ 00640 00641 /** 00642 * @} 00643 */ 00644 00645 /** 00646 * @} 00647 */ 00648 00649 #ifdef __cplusplus 00650 } 00651 #endif 00652 00653 #endif /* __STM32L4xx_LL_CORTEX_H */ 00654 00655 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/