STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_sram.h 00004 * @author MCD Application Team 00005 * @brief Header file of SRAM HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_SRAM_H 00038 #define __STM32L4xx_HAL_SRAM_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 #if defined(FMC_BANK1) 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_ll_fmc.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 /** @addtogroup SRAM 00053 * @{ 00054 */ 00055 00056 /* Exported typedef ----------------------------------------------------------*/ 00057 00058 /** @defgroup SRAM_Exported_Types SRAM Exported Types 00059 * @{ 00060 */ 00061 /** 00062 * @brief HAL SRAM State structures definition 00063 */ 00064 typedef enum 00065 { 00066 HAL_SRAM_STATE_RESET = 0x00U, /*!< SRAM not yet initialized or disabled */ 00067 HAL_SRAM_STATE_READY = 0x01U, /*!< SRAM initialized and ready for use */ 00068 HAL_SRAM_STATE_BUSY = 0x02U, /*!< SRAM internal process is ongoing */ 00069 HAL_SRAM_STATE_ERROR = 0x03U, /*!< SRAM error state */ 00070 HAL_SRAM_STATE_PROTECTED = 0x04U /*!< SRAM peripheral NORSRAM device write protected */ 00071 }HAL_SRAM_StateTypeDef; 00072 00073 /** 00074 * @brief SRAM handle Structure definition 00075 */ 00076 typedef struct 00077 { 00078 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */ 00079 00080 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */ 00081 00082 FMC_NORSRAM_InitTypeDef Init; /*!< SRAM device control configuration parameters */ 00083 00084 HAL_LockTypeDef Lock; /*!< SRAM locking object */ 00085 00086 __IO HAL_SRAM_StateTypeDef State; /*!< SRAM device access state */ 00087 00088 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */ 00089 }SRAM_HandleTypeDef; 00090 00091 /** 00092 * @} 00093 */ 00094 00095 /* Exported constants --------------------------------------------------------*/ 00096 /* Exported macro ------------------------------------------------------------*/ 00097 00098 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros 00099 * @{ 00100 */ 00101 00102 /** @brief Reset SRAM handle state 00103 * @param __HANDLE__ SRAM handle 00104 * @retval None 00105 */ 00106 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET) 00107 00108 /** 00109 * @} 00110 */ 00111 00112 /* Exported functions --------------------------------------------------------*/ 00113 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions 00114 * @{ 00115 */ 00116 00117 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions 00118 * @{ 00119 */ 00120 00121 /* Initialization/de-initialization functions ********************************/ 00122 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming); 00123 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram); 00124 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram); 00125 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram); 00126 00127 /** 00128 * @} 00129 */ 00130 00131 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions 00132 * @{ 00133 */ 00134 00135 /* I/O operation functions ***************************************************/ 00136 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize); 00137 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize); 00138 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize); 00139 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize); 00140 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); 00141 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); 00142 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize); 00143 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize); 00144 00145 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma); 00146 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma); 00147 00148 /** 00149 * @} 00150 */ 00151 00152 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions 00153 * @{ 00154 */ 00155 00156 /* SRAM Control functions ****************************************************/ 00157 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram); 00158 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram); 00159 00160 /** 00161 * @} 00162 */ 00163 00164 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions 00165 * @{ 00166 */ 00167 00168 /* SRAM State functions ******************************************************/ 00169 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram); 00170 00171 /** 00172 * @} 00173 */ 00174 00175 /** 00176 * @} 00177 */ 00178 00179 /** 00180 * @} 00181 */ 00182 00183 /** 00184 * @} 00185 */ 00186 00187 #endif /* FMC_BANK1 */ 00188 00189 #ifdef __cplusplus 00190 } 00191 #endif 00192 00193 #endif /* __STM32L4xx_HAL_SRAM_H */ 00194 00195 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/