STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_sram.c 00004 * @author MCD Application Team 00005 * @brief SRAM HAL module driver. 00006 * This file provides a generic firmware to drive SRAM memories 00007 * mounted as external device. 00008 * 00009 @verbatim 00010 ============================================================================== 00011 ##### How to use this driver ##### 00012 ============================================================================== 00013 [..] 00014 This driver is a generic layered driver which contains a set of APIs used to 00015 control SRAM memories. It uses the FMC layer functions to interface 00016 with SRAM devices. 00017 The following sequence should be followed to configure the FMC to interface 00018 with SRAM/PSRAM memories: 00019 00020 (#) Declare a SRAM_HandleTypeDef handle structure, for example: 00021 SRAM_HandleTypeDef hsram; and: 00022 00023 (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed 00024 values of the structure member. 00025 00026 (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined 00027 base register instance for NOR or SRAM device 00028 00029 (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined 00030 base register instance for NOR or SRAM extended mode 00031 00032 (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended 00033 mode timings; for example: 00034 FMC_NORSRAM_TimingTypeDef Timing and FMC_NORSRAM_TimingTypeDef ExTiming; 00035 and fill its fields with the allowed values of the structure member. 00036 00037 (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function 00038 performs the following sequence: 00039 00040 (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit() 00041 (##) Control register configuration using the FMC NORSRAM interface function 00042 FMC_NORSRAM_Init() 00043 (##) Timing register configuration using the FMC NORSRAM interface function 00044 FMC_NORSRAM_Timing_Init() 00045 (##) Extended mode Timing register configuration using the FMC NORSRAM interface function 00046 FMC_NORSRAM_Extended_Timing_Init() 00047 (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE() 00048 00049 (#) At this stage you can perform read/write accesses from/to the memory connected 00050 to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the 00051 following APIs: 00052 (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access 00053 (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer 00054 00055 (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/ 00056 HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation 00057 00058 (#) You can continuously monitor the SRAM device HAL state by calling the function 00059 HAL_SRAM_GetState() 00060 00061 @endverbatim 00062 ****************************************************************************** 00063 * @attention 00064 * 00065 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00066 * 00067 * Redistribution and use in source and binary forms, with or without modification, 00068 * are permitted provided that the following conditions are met: 00069 * 1. Redistributions of source code must retain the above copyright notice, 00070 * this list of conditions and the following disclaimer. 00071 * 2. Redistributions in binary form must reproduce the above copyright notice, 00072 * this list of conditions and the following disclaimer in the documentation 00073 * and/or other materials provided with the distribution. 00074 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00075 * may be used to endorse or promote products derived from this software 00076 * without specific prior written permission. 00077 * 00078 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00079 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00080 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00081 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00082 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00083 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00084 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00085 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00086 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00087 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00088 * 00089 ****************************************************************************** 00090 */ 00091 00092 /* Includes ------------------------------------------------------------------*/ 00093 #include "stm32l4xx_hal.h" 00094 00095 #if defined(FMC_BANK1) 00096 00097 /** @addtogroup STM32L4xx_HAL_Driver 00098 * @{ 00099 */ 00100 00101 #ifdef HAL_SRAM_MODULE_ENABLED 00102 00103 /** @defgroup SRAM SRAM 00104 * @brief SRAM driver modules 00105 * @{ 00106 */ 00107 00108 /* Private typedef -----------------------------------------------------------*/ 00109 /* Private define ------------------------------------------------------------*/ 00110 /* Private macro -------------------------------------------------------------*/ 00111 /* Private variables ---------------------------------------------------------*/ 00112 /* Private function prototypes -----------------------------------------------*/ 00113 /* Exported functions --------------------------------------------------------*/ 00114 00115 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions 00116 * @{ 00117 */ 00118 00119 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions 00120 * @brief Initialization and Configuration functions. 00121 * 00122 @verbatim 00123 ============================================================================== 00124 ##### SRAM Initialization and de-initialization functions ##### 00125 ============================================================================== 00126 [..] This section provides functions allowing to initialize/de-initialize 00127 the SRAM memory. 00128 00129 @endverbatim 00130 * @{ 00131 */ 00132 00133 /** 00134 * @brief Perform the SRAM device initialization sequence 00135 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00136 * the configuration information for SRAM module. 00137 * @param Timing Pointer to SRAM control timing structure 00138 * @param ExtTiming Pointer to SRAM extended mode timing structure 00139 * @retval HAL status 00140 */ 00141 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming) 00142 { 00143 /* Check the SRAM handle parameter */ 00144 if(hsram == NULL) 00145 { 00146 return HAL_ERROR; 00147 } 00148 00149 if(hsram->State == HAL_SRAM_STATE_RESET) 00150 { 00151 /* Allocate lock resource and initialize it */ 00152 hsram->Lock = HAL_UNLOCKED; 00153 /* Initialize the low level hardware (MSP) */ 00154 HAL_SRAM_MspInit(hsram); 00155 } 00156 00157 /* Initialize SRAM control Interface */ 00158 FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init)); 00159 00160 /* Initialize SRAM timing Interface */ 00161 FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); 00162 00163 /* Initialize SRAM extended mode timing Interface */ 00164 FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank, hsram->Init.ExtendedMode); 00165 00166 /* Enable the NORSRAM device */ 00167 __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); 00168 00169 return HAL_OK; 00170 } 00171 00172 /** 00173 * @brief Perform the SRAM device de-initialization sequence. 00174 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00175 * the configuration information for SRAM module. 00176 * @retval HAL status 00177 */ 00178 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram) 00179 { 00180 /* De-Initialize the low level hardware (MSP) */ 00181 HAL_SRAM_MspDeInit(hsram); 00182 00183 /* Configure the SRAM registers with their reset values */ 00184 FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank); 00185 00186 hsram->State = HAL_SRAM_STATE_RESET; 00187 00188 /* Release Lock */ 00189 __HAL_UNLOCK(hsram); 00190 00191 return HAL_OK; 00192 } 00193 00194 /** 00195 * @brief Initialize the SRAM MSP. 00196 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00197 * the configuration information for SRAM module. 00198 * @retval None 00199 */ 00200 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram) 00201 { 00202 /* Prevent unused argument(s) compilation warning */ 00203 UNUSED(hsram); 00204 00205 /* NOTE : This function should not be modified, when the callback is needed, 00206 the HAL_SRAM_MspInit could be implemented in the user file 00207 */ 00208 } 00209 00210 /** 00211 * @brief DeInitialize the SRAM MSP. 00212 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00213 * the configuration information for SRAM module. 00214 * @retval None 00215 */ 00216 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram) 00217 { 00218 /* Prevent unused argument(s) compilation warning */ 00219 UNUSED(hsram); 00220 00221 /* NOTE : This function should not be modified, when the callback is needed, 00222 the HAL_SRAM_MspDeInit could be implemented in the user file 00223 */ 00224 } 00225 00226 /** 00227 * @brief DMA transfer complete callback. 00228 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains 00229 * the configuration information for SRAM module. 00230 * @retval None 00231 */ 00232 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma) 00233 { 00234 /* Prevent unused argument(s) compilation warning */ 00235 UNUSED(hdma); 00236 00237 /* NOTE : This function should not be modified, when the callback is needed, 00238 the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file 00239 */ 00240 } 00241 00242 /** 00243 * @brief DMA transfer complete error callback. 00244 * @param hdma pointer to a SRAM_HandleTypeDef structure that contains 00245 * the configuration information for SRAM module. 00246 * @retval None 00247 */ 00248 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma) 00249 { 00250 /* Prevent unused argument(s) compilation warning */ 00251 UNUSED(hdma); 00252 00253 /* NOTE : This function should not be modified, when the callback is needed, 00254 the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file 00255 */ 00256 } 00257 00258 /** 00259 * @} 00260 */ 00261 00262 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions 00263 * @brief Input Output and memory control functions 00264 * 00265 @verbatim 00266 ============================================================================== 00267 ##### SRAM Input and Output functions ##### 00268 ============================================================================== 00269 [..] 00270 This section provides functions allowing to use and control the SRAM memory 00271 00272 @endverbatim 00273 * @{ 00274 */ 00275 00276 /** 00277 * @brief Read 8-bit buffer from SRAM memory. 00278 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00279 * the configuration information for SRAM module. 00280 * @param pAddress Pointer to read start address 00281 * @param pDstBuffer Pointer to destination buffer 00282 * @param BufferSize Size of the buffer to read from memory 00283 * @retval HAL status 00284 */ 00285 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize) 00286 { 00287 __IO uint8_t * psramaddress = (uint8_t *)pAddress; 00288 00289 /* Process Locked */ 00290 __HAL_LOCK(hsram); 00291 00292 /* Update the SRAM controller state */ 00293 hsram->State = HAL_SRAM_STATE_BUSY; 00294 00295 /* Read data from memory */ 00296 for(; BufferSize != 0; BufferSize--) 00297 { 00298 *pDstBuffer = *(__IO uint8_t *)psramaddress; 00299 pDstBuffer++; 00300 psramaddress++; 00301 } 00302 00303 /* Update the SRAM controller state */ 00304 hsram->State = HAL_SRAM_STATE_READY; 00305 00306 /* Process unlocked */ 00307 __HAL_UNLOCK(hsram); 00308 00309 return HAL_OK; 00310 } 00311 00312 /** 00313 * @brief Write 8-bit buffer to SRAM memory. 00314 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00315 * the configuration information for SRAM module. 00316 * @param pAddress Pointer to write start address 00317 * @param pSrcBuffer Pointer to source buffer to write 00318 * @param BufferSize Size of the buffer to write to memory 00319 * @retval HAL status 00320 */ 00321 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize) 00322 { 00323 __IO uint8_t * psramaddress = (uint8_t *)pAddress; 00324 00325 /* Check the SRAM controller state */ 00326 if(hsram->State == HAL_SRAM_STATE_PROTECTED) 00327 { 00328 return HAL_ERROR; 00329 } 00330 00331 /* Process Locked */ 00332 __HAL_LOCK(hsram); 00333 00334 /* Update the SRAM controller state */ 00335 hsram->State = HAL_SRAM_STATE_BUSY; 00336 00337 /* Write data to memory */ 00338 for(; BufferSize != 0; BufferSize--) 00339 { 00340 *(__IO uint8_t *)psramaddress = *pSrcBuffer; 00341 pSrcBuffer++; 00342 psramaddress++; 00343 } 00344 00345 /* Update the SRAM controller state */ 00346 hsram->State = HAL_SRAM_STATE_READY; 00347 00348 /* Process unlocked */ 00349 __HAL_UNLOCK(hsram); 00350 00351 return HAL_OK; 00352 } 00353 00354 /** 00355 * @brief Read 16-bit buffer from SRAM memory. 00356 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00357 * the configuration information for SRAM module. 00358 * @param pAddress Pointer to read start address 00359 * @param pDstBuffer Pointer to destination buffer 00360 * @param BufferSize Size of the buffer to read from memory 00361 * @retval HAL status 00362 */ 00363 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize) 00364 { 00365 __IO uint16_t * psramaddress = (uint16_t *)pAddress; 00366 00367 /* Process Locked */ 00368 __HAL_LOCK(hsram); 00369 00370 /* Update the SRAM controller state */ 00371 hsram->State = HAL_SRAM_STATE_BUSY; 00372 00373 /* Read data from memory */ 00374 for(; BufferSize != 0; BufferSize--) 00375 { 00376 *pDstBuffer = *(__IO uint16_t *)psramaddress; 00377 pDstBuffer++; 00378 psramaddress++; 00379 } 00380 00381 /* Update the SRAM controller state */ 00382 hsram->State = HAL_SRAM_STATE_READY; 00383 00384 /* Process unlocked */ 00385 __HAL_UNLOCK(hsram); 00386 00387 return HAL_OK; 00388 } 00389 00390 /** 00391 * @brief Write 16-bit buffer to SRAM memory. 00392 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00393 * the configuration information for SRAM module. 00394 * @param pAddress Pointer to write start address 00395 * @param pSrcBuffer Pointer to source buffer to write 00396 * @param BufferSize Size of the buffer to write to memory 00397 * @retval HAL status 00398 */ 00399 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize) 00400 { 00401 __IO uint16_t * psramaddress = (uint16_t *)pAddress; 00402 00403 /* Check the SRAM controller state */ 00404 if(hsram->State == HAL_SRAM_STATE_PROTECTED) 00405 { 00406 return HAL_ERROR; 00407 } 00408 00409 /* Process Locked */ 00410 __HAL_LOCK(hsram); 00411 00412 /* Update the SRAM controller state */ 00413 hsram->State = HAL_SRAM_STATE_BUSY; 00414 00415 /* Write data to memory */ 00416 for(; BufferSize != 0; BufferSize--) 00417 { 00418 *(__IO uint16_t *)psramaddress = *pSrcBuffer; 00419 pSrcBuffer++; 00420 psramaddress++; 00421 } 00422 00423 /* Update the SRAM controller state */ 00424 hsram->State = HAL_SRAM_STATE_READY; 00425 00426 /* Process unlocked */ 00427 __HAL_UNLOCK(hsram); 00428 00429 return HAL_OK; 00430 } 00431 00432 /** 00433 * @brief Read 32-bit buffer from SRAM memory. 00434 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00435 * the configuration information for SRAM module. 00436 * @param pAddress Pointer to read start address 00437 * @param pDstBuffer Pointer to destination buffer 00438 * @param BufferSize Size of the buffer to read from memory 00439 * @retval HAL status 00440 */ 00441 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) 00442 { 00443 /* Process Locked */ 00444 __HAL_LOCK(hsram); 00445 00446 /* Update the SRAM controller state */ 00447 hsram->State = HAL_SRAM_STATE_BUSY; 00448 00449 /* Read data from memory */ 00450 for(; BufferSize != 0; BufferSize--) 00451 { 00452 *pDstBuffer = *(__IO uint32_t *)pAddress; 00453 pDstBuffer++; 00454 pAddress++; 00455 } 00456 00457 /* Update the SRAM controller state */ 00458 hsram->State = HAL_SRAM_STATE_READY; 00459 00460 /* Process unlocked */ 00461 __HAL_UNLOCK(hsram); 00462 00463 return HAL_OK; 00464 } 00465 00466 /** 00467 * @brief Write 32-bit buffer to SRAM memory. 00468 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00469 * the configuration information for SRAM module. 00470 * @param pAddress Pointer to write start address 00471 * @param pSrcBuffer Pointer to source buffer to write 00472 * @param BufferSize Size of the buffer to write to memory 00473 * @retval HAL status 00474 */ 00475 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) 00476 { 00477 /* Check the SRAM controller state */ 00478 if(hsram->State == HAL_SRAM_STATE_PROTECTED) 00479 { 00480 return HAL_ERROR; 00481 } 00482 00483 /* Process Locked */ 00484 __HAL_LOCK(hsram); 00485 00486 /* Update the SRAM controller state */ 00487 hsram->State = HAL_SRAM_STATE_BUSY; 00488 00489 /* Write data to memory */ 00490 for(; BufferSize != 0; BufferSize--) 00491 { 00492 *(__IO uint32_t *)pAddress = *pSrcBuffer; 00493 pSrcBuffer++; 00494 pAddress++; 00495 } 00496 00497 /* Update the SRAM controller state */ 00498 hsram->State = HAL_SRAM_STATE_READY; 00499 00500 /* Process unlocked */ 00501 __HAL_UNLOCK(hsram); 00502 00503 return HAL_OK; 00504 } 00505 00506 /** 00507 * @brief Read a Word data buffer from the SRAM memory using DMA transfer. 00508 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00509 * the configuration information for SRAM module. 00510 * @param pAddress Pointer to read start address 00511 * @param pDstBuffer Pointer to destination buffer 00512 * @param BufferSize Size of the buffer to read from memory 00513 * @retval HAL status 00514 */ 00515 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize) 00516 { 00517 /* Process Locked */ 00518 __HAL_LOCK(hsram); 00519 00520 /* Update the SRAM controller state */ 00521 hsram->State = HAL_SRAM_STATE_BUSY; 00522 00523 /* Configure DMA user callbacks */ 00524 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; 00525 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; 00526 00527 /* Enable the DMA Channel */ 00528 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize); 00529 00530 /* Update the SRAM controller state */ 00531 hsram->State = HAL_SRAM_STATE_READY; 00532 00533 /* Process unlocked */ 00534 __HAL_UNLOCK(hsram); 00535 00536 return HAL_OK; 00537 } 00538 00539 /** 00540 * @brief Write a Word data buffer to SRAM memory using DMA transfer. 00541 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00542 * the configuration information for SRAM module. 00543 * @param pAddress Pointer to write start address 00544 * @param pSrcBuffer Pointer to source buffer to write 00545 * @param BufferSize Size of the buffer to write to memory 00546 * @retval HAL status 00547 */ 00548 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize) 00549 { 00550 /* Check the SRAM controller state */ 00551 if(hsram->State == HAL_SRAM_STATE_PROTECTED) 00552 { 00553 return HAL_ERROR; 00554 } 00555 00556 /* Process Locked */ 00557 __HAL_LOCK(hsram); 00558 00559 /* Update the SRAM controller state */ 00560 hsram->State = HAL_SRAM_STATE_BUSY; 00561 00562 /* Configure DMA user callbacks */ 00563 hsram->hdma->XferCpltCallback = HAL_SRAM_DMA_XferCpltCallback; 00564 hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback; 00565 00566 /* Enable the DMA Channel */ 00567 HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize); 00568 00569 /* Update the SRAM controller state */ 00570 hsram->State = HAL_SRAM_STATE_READY; 00571 00572 /* Process unlocked */ 00573 __HAL_UNLOCK(hsram); 00574 00575 return HAL_OK; 00576 } 00577 00578 /** 00579 * @} 00580 */ 00581 00582 /** @defgroup SRAM_Exported_Functions_Group3 Control functions 00583 * @brief Control functions 00584 * 00585 @verbatim 00586 ============================================================================== 00587 ##### SRAM Control functions ##### 00588 ============================================================================== 00589 [..] 00590 This subsection provides a set of functions allowing to control dynamically 00591 the SRAM interface. 00592 00593 @endverbatim 00594 * @{ 00595 */ 00596 00597 /** 00598 * @brief Enable dynamically SRAM write operation. 00599 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00600 * the configuration information for SRAM module. 00601 * @retval HAL status 00602 */ 00603 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram) 00604 { 00605 /* Process Locked */ 00606 __HAL_LOCK(hsram); 00607 00608 /* Enable write operation */ 00609 FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); 00610 00611 /* Update the SRAM controller state */ 00612 hsram->State = HAL_SRAM_STATE_READY; 00613 00614 /* Process unlocked */ 00615 __HAL_UNLOCK(hsram); 00616 00617 return HAL_OK; 00618 } 00619 00620 /** 00621 * @brief Disable dynamically SRAM write operation. 00622 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00623 * the configuration information for SRAM module. 00624 * @retval HAL status 00625 */ 00626 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram) 00627 { 00628 /* Process Locked */ 00629 __HAL_LOCK(hsram); 00630 00631 /* Update the SRAM controller state */ 00632 hsram->State = HAL_SRAM_STATE_BUSY; 00633 00634 /* Disable write operation */ 00635 FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); 00636 00637 /* Update the SRAM controller state */ 00638 hsram->State = HAL_SRAM_STATE_PROTECTED; 00639 00640 /* Process unlocked */ 00641 __HAL_UNLOCK(hsram); 00642 00643 return HAL_OK; 00644 } 00645 00646 /** 00647 * @} 00648 */ 00649 00650 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions 00651 * @brief Peripheral State functions 00652 * 00653 @verbatim 00654 ============================================================================== 00655 ##### SRAM State functions ##### 00656 ============================================================================== 00657 [..] 00658 This subsection permits to get in run-time the status of the SRAM controller 00659 and the data flow. 00660 00661 @endverbatim 00662 * @{ 00663 */ 00664 00665 /** 00666 * @brief Return the SRAM controller state 00667 * @param hsram pointer to a SRAM_HandleTypeDef structure that contains 00668 * the configuration information for SRAM module. 00669 * @retval HAL state 00670 */ 00671 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram) 00672 { 00673 /* Return SRAM handle state */ 00674 return hsram->State; 00675 } 00676 00677 /** 00678 * @} 00679 */ 00680 00681 /** 00682 * @} 00683 */ 00684 00685 /** 00686 * @} 00687 */ 00688 00689 #endif /* HAL_SRAM_MODULE_ENABLED */ 00690 00691 /** 00692 * @} 00693 */ 00694 00695 #endif /* FMC_BANK1 */ 00696 00697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/