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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_spi.h 00004 * @author MCD Application Team 00005 * @brief Header file of SPI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_SPI_H 00038 #define __STM32L4xx_HAL_SPI_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /** @addtogroup STM32L4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @addtogroup SPI 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup SPI_Exported_Types SPI Exported Types 00057 * @{ 00058 */ 00059 00060 /** 00061 * @brief SPI Configuration Structure definition 00062 */ 00063 typedef struct 00064 { 00065 uint32_t Mode; /*!< Specifies the SPI operating mode. 00066 This parameter can be a value of @ref SPI_Mode */ 00067 00068 uint32_t Direction; /*!< Specifies the SPI bidirectional mode state. 00069 This parameter can be a value of @ref SPI_Direction */ 00070 00071 uint32_t DataSize; /*!< Specifies the SPI data size. 00072 This parameter can be a value of @ref SPI_Data_Size */ 00073 00074 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state. 00075 This parameter can be a value of @ref SPI_Clock_Polarity */ 00076 00077 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture. 00078 This parameter can be a value of @ref SPI_Clock_Phase */ 00079 00080 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by 00081 hardware (NSS pin) or by software using the SSI bit. 00082 This parameter can be a value of @ref SPI_Slave_Select_management */ 00083 00084 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be 00085 used to configure the transmit and receive SCK clock. 00086 This parameter can be a value of @ref SPI_BaudRate_Prescaler 00087 @note The communication clock is derived from the master 00088 clock. The slave clock does not need to be set. */ 00089 00090 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit. 00091 This parameter can be a value of @ref SPI_MSB_LSB_transmission */ 00092 00093 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not. 00094 This parameter can be a value of @ref SPI_TI_mode */ 00095 00096 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 00097 This parameter can be a value of @ref SPI_CRC_Calculation */ 00098 00099 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation. 00100 This parameter must be an odd number between Min_Data = 1 and Max_Data = 65535 */ 00101 00102 uint32_t CRCLength; /*!< Specifies the CRC Length used for the CRC calculation. 00103 CRC Length is only used with Data8 and Data16, not other data size 00104 This parameter can be a value of @ref SPI_CRC_length */ 00105 00106 uint32_t NSSPMode; /*!< Specifies whether the NSSP signal is enabled or not . 00107 This parameter can be a value of @ref SPI_NSSP_Mode 00108 This mode is activated by the NSSP bit in the SPIx_CR2 register and 00109 it takes effect only if the SPI interface is configured as Motorola SPI 00110 master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0, 00111 CPOL setting is ignored).. */ 00112 } SPI_InitTypeDef; 00113 00114 /** 00115 * @brief HAL SPI State structure definition 00116 */ 00117 typedef enum 00118 { 00119 HAL_SPI_STATE_RESET = 0x00U, /*!< Peripheral not Initialized */ 00120 HAL_SPI_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00121 HAL_SPI_STATE_BUSY = 0x02U, /*!< an internal process is ongoing */ 00122 HAL_SPI_STATE_BUSY_TX = 0x03U, /*!< Data Transmission process is ongoing */ 00123 HAL_SPI_STATE_BUSY_RX = 0x04U, /*!< Data Reception process is ongoing */ 00124 HAL_SPI_STATE_BUSY_TX_RX = 0x05U, /*!< Data Transmission and Reception process is ongoing */ 00125 HAL_SPI_STATE_ERROR = 0x06U, /*!< SPI error state */ 00126 HAL_SPI_STATE_ABORT = 0x07U /*!< SPI abort is ongoing */ 00127 } HAL_SPI_StateTypeDef; 00128 00129 /** 00130 * @brief SPI handle Structure definition 00131 */ 00132 typedef struct __SPI_HandleTypeDef 00133 { 00134 SPI_TypeDef *Instance; /*!< SPI registers base address */ 00135 00136 SPI_InitTypeDef Init; /*!< SPI communication parameters */ 00137 00138 uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ 00139 00140 uint16_t TxXferSize; /*!< SPI Tx Transfer size */ 00141 00142 __IO uint16_t TxXferCount; /*!< SPI Tx Transfer Counter */ 00143 00144 uint8_t *pRxBuffPtr; /*!< Pointer to SPI Rx transfer Buffer */ 00145 00146 uint16_t RxXferSize; /*!< SPI Rx Transfer size */ 00147 00148 __IO uint16_t RxXferCount; /*!< SPI Rx Transfer Counter */ 00149 00150 uint32_t CRCSize; /*!< SPI CRC size used for the transfer */ 00151 00152 void (*RxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Rx ISR */ 00153 00154 void (*TxISR)(struct __SPI_HandleTypeDef *hspi); /*!< function pointer on Tx ISR */ 00155 00156 DMA_HandleTypeDef *hdmatx; /*!< SPI Tx DMA Handle parameters */ 00157 00158 DMA_HandleTypeDef *hdmarx; /*!< SPI Rx DMA Handle parameters */ 00159 00160 HAL_LockTypeDef Lock; /*!< Locking object */ 00161 00162 __IO HAL_SPI_StateTypeDef State; /*!< SPI communication state */ 00163 00164 __IO uint32_t ErrorCode; /*!< SPI Error code */ 00165 00166 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 00167 void (* TxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Completed callback */ 00168 void (* RxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Completed callback */ 00169 void (* TxRxCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Completed callback */ 00170 void (* TxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Tx Half Completed callback */ 00171 void (* RxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Rx Half Completed callback */ 00172 void (* TxRxHalfCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI TxRx Half Completed callback */ 00173 void (* ErrorCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Error callback */ 00174 void (* AbortCpltCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Abort callback */ 00175 void (* MspInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp Init callback */ 00176 void (* MspDeInitCallback)(struct __SPI_HandleTypeDef *hspi); /*!< SPI Msp DeInit callback */ 00177 00178 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 00179 } SPI_HandleTypeDef; 00180 00181 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 00182 /** 00183 * @brief HAL SPI Callback ID enumeration definition 00184 */ 00185 typedef enum 00186 { 00187 HAL_SPI_TX_COMPLETE_CB_ID = 0x00U, /*!< SPI Tx Completed callback ID */ 00188 HAL_SPI_RX_COMPLETE_CB_ID = 0x01U, /*!< SPI Rx Completed callback ID */ 00189 HAL_SPI_TX_RX_COMPLETE_CB_ID = 0x02U, /*!< SPI TxRx Completed callback ID */ 00190 HAL_SPI_TX_HALF_COMPLETE_CB_ID = 0x03U, /*!< SPI Tx Half Completed callback ID */ 00191 HAL_SPI_RX_HALF_COMPLETE_CB_ID = 0x04U, /*!< SPI Rx Half Completed callback ID */ 00192 HAL_SPI_TX_RX_HALF_COMPLETE_CB_ID = 0x05U, /*!< SPI TxRx Half Completed callback ID */ 00193 HAL_SPI_ERROR_CB_ID = 0x06U, /*!< SPI Error callback ID */ 00194 HAL_SPI_ABORT_CB_ID = 0x07U, /*!< SPI Abort callback ID */ 00195 HAL_SPI_MSPINIT_CB_ID = 0x08U, /*!< SPI Msp Init callback ID */ 00196 HAL_SPI_MSPDEINIT_CB_ID = 0x09U /*!< SPI Msp DeInit callback ID */ 00197 00198 } HAL_SPI_CallbackIDTypeDef; 00199 00200 /** 00201 * @brief HAL SPI Callback pointer definition 00202 */ 00203 typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to an SPI callback function */ 00204 00205 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 00206 /** 00207 * @} 00208 */ 00209 00210 /* Exported constants --------------------------------------------------------*/ 00211 /** @defgroup SPI_Exported_Constants SPI Exported Constants 00212 * @{ 00213 */ 00214 00215 /** @defgroup SPI_Error_Code SPI Error Code 00216 * @{ 00217 */ 00218 #define HAL_SPI_ERROR_NONE (0x00000000U) /*!< No error */ 00219 #define HAL_SPI_ERROR_MODF (0x00000001U) /*!< MODF error */ 00220 #define HAL_SPI_ERROR_CRC (0x00000002U) /*!< CRC error */ 00221 #define HAL_SPI_ERROR_OVR (0x00000004U) /*!< OVR error */ 00222 #define HAL_SPI_ERROR_FRE (0x00000008U) /*!< FRE error */ 00223 #define HAL_SPI_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ 00224 #define HAL_SPI_ERROR_FLAG (0x00000020U) /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */ 00225 #define HAL_SPI_ERROR_ABORT (0x00000040U) /*!< Error during SPI Abort procedure */ 00226 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 00227 #define HAL_SPI_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ 00228 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 00229 /** 00230 * @} 00231 */ 00232 00233 /** @defgroup SPI_Mode SPI Mode 00234 * @{ 00235 */ 00236 #define SPI_MODE_SLAVE (0x00000000U) 00237 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) 00238 /** 00239 * @} 00240 */ 00241 00242 /** @defgroup SPI_Direction SPI Direction Mode 00243 * @{ 00244 */ 00245 #define SPI_DIRECTION_2LINES (0x00000000U) 00246 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY 00247 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE 00248 /** 00249 * @} 00250 */ 00251 00252 /** @defgroup SPI_Data_Size SPI Data Size 00253 * @{ 00254 */ 00255 #define SPI_DATASIZE_4BIT (0x00000300U) 00256 #define SPI_DATASIZE_5BIT (0x00000400U) 00257 #define SPI_DATASIZE_6BIT (0x00000500U) 00258 #define SPI_DATASIZE_7BIT (0x00000600U) 00259 #define SPI_DATASIZE_8BIT (0x00000700U) 00260 #define SPI_DATASIZE_9BIT (0x00000800U) 00261 #define SPI_DATASIZE_10BIT (0x00000900U) 00262 #define SPI_DATASIZE_11BIT (0x00000A00U) 00263 #define SPI_DATASIZE_12BIT (0x00000B00U) 00264 #define SPI_DATASIZE_13BIT (0x00000C00U) 00265 #define SPI_DATASIZE_14BIT (0x00000D00U) 00266 #define SPI_DATASIZE_15BIT (0x00000E00U) 00267 #define SPI_DATASIZE_16BIT (0x00000F00U) 00268 /** 00269 * @} 00270 */ 00271 00272 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity 00273 * @{ 00274 */ 00275 #define SPI_POLARITY_LOW (0x00000000U) 00276 #define SPI_POLARITY_HIGH SPI_CR1_CPOL 00277 /** 00278 * @} 00279 */ 00280 00281 /** @defgroup SPI_Clock_Phase SPI Clock Phase 00282 * @{ 00283 */ 00284 #define SPI_PHASE_1EDGE (0x00000000U) 00285 #define SPI_PHASE_2EDGE SPI_CR1_CPHA 00286 /** 00287 * @} 00288 */ 00289 00290 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management 00291 * @{ 00292 */ 00293 #define SPI_NSS_SOFT SPI_CR1_SSM 00294 #define SPI_NSS_HARD_INPUT (0x00000000U) 00295 #define SPI_NSS_HARD_OUTPUT (SPI_CR2_SSOE << 16U) 00296 /** 00297 * @} 00298 */ 00299 00300 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode 00301 * @{ 00302 */ 00303 #define SPI_NSS_PULSE_ENABLE SPI_CR2_NSSP 00304 #define SPI_NSS_PULSE_DISABLE (0x00000000U) 00305 /** 00306 * @} 00307 */ 00308 00309 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler 00310 * @{ 00311 */ 00312 #define SPI_BAUDRATEPRESCALER_2 (0x00000000U) 00313 #define SPI_BAUDRATEPRESCALER_4 (SPI_CR1_BR_0) 00314 #define SPI_BAUDRATEPRESCALER_8 (SPI_CR1_BR_1) 00315 #define SPI_BAUDRATEPRESCALER_16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) 00316 #define SPI_BAUDRATEPRESCALER_32 (SPI_CR1_BR_2) 00317 #define SPI_BAUDRATEPRESCALER_64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) 00318 #define SPI_BAUDRATEPRESCALER_128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) 00319 #define SPI_BAUDRATEPRESCALER_256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) 00320 /** 00321 * @} 00322 */ 00323 00324 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission 00325 * @{ 00326 */ 00327 #define SPI_FIRSTBIT_MSB (0x00000000U) 00328 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST 00329 /** 00330 * @} 00331 */ 00332 00333 /** @defgroup SPI_TI_mode SPI TI Mode 00334 * @{ 00335 */ 00336 #define SPI_TIMODE_DISABLE (0x00000000U) 00337 #define SPI_TIMODE_ENABLE SPI_CR2_FRF 00338 /** 00339 * @} 00340 */ 00341 00342 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation 00343 * @{ 00344 */ 00345 #define SPI_CRCCALCULATION_DISABLE (0x00000000U) 00346 #define SPI_CRCCALCULATION_ENABLE SPI_CR1_CRCEN 00347 /** 00348 * @} 00349 */ 00350 00351 /** @defgroup SPI_CRC_length SPI CRC Length 00352 * @{ 00353 * This parameter can be one of the following values: 00354 * SPI_CRC_LENGTH_DATASIZE: aligned with the data size 00355 * SPI_CRC_LENGTH_8BIT : CRC 8bit 00356 * SPI_CRC_LENGTH_16BIT : CRC 16bit 00357 */ 00358 #define SPI_CRC_LENGTH_DATASIZE (0x00000000U) 00359 #define SPI_CRC_LENGTH_8BIT (0x00000001U) 00360 #define SPI_CRC_LENGTH_16BIT (0x00000002U) 00361 /** 00362 * @} 00363 */ 00364 00365 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold 00366 * @{ 00367 * This parameter can be one of the following values: 00368 * SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF : 00369 * RXNE event is generated if the FIFO 00370 * level is greater or equal to 1/2(16-bits). 00371 * SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO 00372 * level is greater or equal to 1/4(8 bits). */ 00373 #define SPI_RXFIFO_THRESHOLD SPI_CR2_FRXTH 00374 #define SPI_RXFIFO_THRESHOLD_QF SPI_CR2_FRXTH 00375 #define SPI_RXFIFO_THRESHOLD_HF (0x00000000U) 00376 00377 /** 00378 * @} 00379 */ 00380 00381 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition 00382 * @{ 00383 */ 00384 #define SPI_IT_TXE SPI_CR2_TXEIE 00385 #define SPI_IT_RXNE SPI_CR2_RXNEIE 00386 #define SPI_IT_ERR SPI_CR2_ERRIE 00387 /** 00388 * @} 00389 */ 00390 00391 /** @defgroup SPI_Flags_definition SPI Flags Definition 00392 * @{ 00393 */ 00394 #define SPI_FLAG_RXNE SPI_SR_RXNE /* SPI status flag: Rx buffer not empty flag */ 00395 #define SPI_FLAG_TXE SPI_SR_TXE /* SPI status flag: Tx buffer empty flag */ 00396 #define SPI_FLAG_BSY SPI_SR_BSY /* SPI status flag: Busy flag */ 00397 #define SPI_FLAG_CRCERR SPI_SR_CRCERR /* SPI Error flag: CRC error flag */ 00398 #define SPI_FLAG_MODF SPI_SR_MODF /* SPI Error flag: Mode fault flag */ 00399 #define SPI_FLAG_OVR SPI_SR_OVR /* SPI Error flag: Overrun flag */ 00400 #define SPI_FLAG_FRE SPI_SR_FRE /* SPI Error flag: TI mode frame format error flag */ 00401 #define SPI_FLAG_FTLVL SPI_SR_FTLVL /* SPI fifo transmission level */ 00402 #define SPI_FLAG_FRLVL SPI_SR_FRLVL /* SPI fifo reception level */ 00403 /** 00404 * @} 00405 */ 00406 00407 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level 00408 * @{ 00409 */ 00410 #define SPI_FTLVL_EMPTY (0x00000000U) 00411 #define SPI_FTLVL_QUARTER_FULL (0x00000800U) 00412 #define SPI_FTLVL_HALF_FULL (0x00001000U) 00413 #define SPI_FTLVL_FULL (0x00001800U) 00414 00415 /** 00416 * @} 00417 */ 00418 00419 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level 00420 * @{ 00421 */ 00422 #define SPI_FRLVL_EMPTY (0x00000000U) 00423 #define SPI_FRLVL_QUARTER_FULL (0x00000200U) 00424 #define SPI_FRLVL_HALF_FULL (0x00000400U) 00425 #define SPI_FRLVL_FULL (0x00000600U) 00426 /** 00427 * @} 00428 */ 00429 00430 /** 00431 * @} 00432 */ 00433 00434 /* Exported macros -----------------------------------------------------------*/ 00435 /** @defgroup SPI_Exported_Macros SPI Exported Macros 00436 * @{ 00437 */ 00438 00439 /** @brief Reset SPI handle state. 00440 * @param __HANDLE__ specifies the SPI Handle. 00441 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00442 * @retval None 00443 */ 00444 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 00445 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00446 (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ 00447 (__HANDLE__)->MspInitCallback = NULL; \ 00448 (__HANDLE__)->MspDeInitCallback = NULL; \ 00449 } while(0) 00450 #else 00451 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) 00452 #endif 00453 00454 /** @brief Enable the specified SPI interrupts. 00455 * @param __HANDLE__ specifies the SPI Handle. 00456 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00457 * @param __INTERRUPT__ specifies the interrupt source to enable. 00458 * This parameter can be one of the following values: 00459 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 00460 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 00461 * @arg SPI_IT_ERR: Error interrupt enable 00462 * @retval None 00463 */ 00464 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) 00465 00466 /** @brief Disable the specified SPI interrupts. 00467 * @param __HANDLE__ specifies the SPI handle. 00468 * This parameter can be SPIx where x: 1, 2, or 3 to select the SPI peripheral. 00469 * @param __INTERRUPT__ specifies the interrupt source to disable. 00470 * This parameter can be one of the following values: 00471 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 00472 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 00473 * @arg SPI_IT_ERR: Error interrupt enable 00474 * @retval None 00475 */ 00476 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__)) 00477 00478 /** @brief Check whether the specified SPI interrupt source is enabled or not. 00479 * @param __HANDLE__ specifies the SPI Handle. 00480 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00481 * @param __INTERRUPT__ specifies the SPI interrupt source to check. 00482 * This parameter can be one of the following values: 00483 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable 00484 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable 00485 * @arg SPI_IT_ERR: Error interrupt enable 00486 * @retval The new state of __IT__ (TRUE or FALSE). 00487 */ 00488 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) 00489 00490 /** @brief Check whether the specified SPI flag is set or not. 00491 * @param __HANDLE__ specifies the SPI Handle. 00492 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00493 * @param __FLAG__ specifies the flag to check. 00494 * This parameter can be one of the following values: 00495 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag 00496 * @arg SPI_FLAG_TXE: Transmit buffer empty flag 00497 * @arg SPI_FLAG_CRCERR: CRC error flag 00498 * @arg SPI_FLAG_MODF: Mode fault flag 00499 * @arg SPI_FLAG_OVR: Overrun flag 00500 * @arg SPI_FLAG_BSY: Busy flag 00501 * @arg SPI_FLAG_FRE: Frame format error flag 00502 * @arg SPI_FLAG_FTLVL: SPI fifo transmission level 00503 * @arg SPI_FLAG_FRLVL: SPI fifo reception level 00504 * @retval The new state of __FLAG__ (TRUE or FALSE). 00505 */ 00506 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) 00507 00508 /** @brief Clear the SPI CRCERR pending flag. 00509 * @param __HANDLE__ specifies the SPI Handle. 00510 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00511 * @retval None 00512 */ 00513 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) 00514 00515 /** @brief Clear the SPI MODF pending flag. 00516 * @param __HANDLE__ specifies the SPI Handle. 00517 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00518 * @retval None 00519 */ 00520 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) \ 00521 do{ \ 00522 __IO uint32_t tmpreg_modf = 0x00U; \ 00523 tmpreg_modf = (__HANDLE__)->Instance->SR; \ 00524 CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE); \ 00525 UNUSED(tmpreg_modf); \ 00526 } while(0U) 00527 00528 /** @brief Clear the SPI OVR pending flag. 00529 * @param __HANDLE__ specifies the SPI Handle. 00530 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00531 * @retval None 00532 */ 00533 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) \ 00534 do{ \ 00535 __IO uint32_t tmpreg_ovr = 0x00U; \ 00536 tmpreg_ovr = (__HANDLE__)->Instance->DR; \ 00537 tmpreg_ovr = (__HANDLE__)->Instance->SR; \ 00538 UNUSED(tmpreg_ovr); \ 00539 } while(0U) 00540 00541 /** @brief Clear the SPI FRE pending flag. 00542 * @param __HANDLE__ specifies the SPI Handle. 00543 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00544 * @retval None 00545 */ 00546 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) \ 00547 do{ \ 00548 __IO uint32_t tmpreg_fre = 0x00U; \ 00549 tmpreg_fre = (__HANDLE__)->Instance->SR; \ 00550 UNUSED(tmpreg_fre); \ 00551 }while(0U) 00552 00553 /** @brief Enable the SPI peripheral. 00554 * @param __HANDLE__ specifies the SPI Handle. 00555 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00556 * @retval None 00557 */ 00558 #define __HAL_SPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) 00559 00560 /** @brief Disable the SPI peripheral. 00561 * @param __HANDLE__ specifies the SPI Handle. 00562 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00563 * @retval None 00564 */ 00565 #define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE) 00566 00567 /** 00568 * @} 00569 */ 00570 00571 /* Private macros ------------------------------------------------------------*/ 00572 /** @defgroup SPI_Private_Macros SPI Private Macros 00573 * @{ 00574 */ 00575 00576 /** @brief Set the SPI transmit-only mode. 00577 * @param __HANDLE__ specifies the SPI Handle. 00578 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00579 * @retval None 00580 */ 00581 #define SPI_1LINE_TX(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) 00582 00583 /** @brief Set the SPI receive-only mode. 00584 * @param __HANDLE__ specifies the SPI Handle. 00585 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00586 * @retval None 00587 */ 00588 #define SPI_1LINE_RX(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) 00589 00590 /** @brief Reset the CRC calculation of the SPI. 00591 * @param __HANDLE__ specifies the SPI Handle. 00592 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 00593 * @retval None 00594 */ 00595 #define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ 00596 SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) 00597 00598 /** @brief Checks if SPI Mode parameter is in allowed range. 00599 * @param __MODE__ specifies the SPI Mode. 00600 * This parameter can be a value of @ref SPI_Mode 00601 * @retval None 00602 */ 00603 #define IS_SPI_MODE(__MODE__) (((__MODE__) == SPI_MODE_SLAVE) || \ 00604 ((__MODE__) == SPI_MODE_MASTER)) 00605 00606 /** @brief Checks if SPI Direction Mode parameter is in allowed range. 00607 * @param __MODE__ specifies the SPI Direction Mode. 00608 * This parameter can be a value of @ref SPI_Direction 00609 * @retval None 00610 */ 00611 #define IS_SPI_DIRECTION(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ 00612 ((__MODE__) == SPI_DIRECTION_2LINES_RXONLY) || \ 00613 ((__MODE__) == SPI_DIRECTION_1LINE)) 00614 00615 /** @brief Checks if SPI Direction Mode parameter is 2 lines. 00616 * @param __MODE__ specifies the SPI Direction Mode. 00617 * @retval None 00618 */ 00619 #define IS_SPI_DIRECTION_2LINES(__MODE__) ((__MODE__) == SPI_DIRECTION_2LINES) 00620 00621 /** @brief Checks if SPI Direction Mode parameter is 1 or 2 lines. 00622 * @param __MODE__ specifies the SPI Direction Mode. 00623 * @retval None 00624 */ 00625 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(__MODE__) (((__MODE__) == SPI_DIRECTION_2LINES) || \ 00626 ((__MODE__) == SPI_DIRECTION_1LINE)) 00627 00628 /** @brief Checks if SPI Data Size parameter is in allowed range. 00629 * @param __DATASIZE__ specifies the SPI Data Size. 00630 * This parameter can be a value of @ref SPI_Data_Size 00631 * @retval None 00632 */ 00633 #define IS_SPI_DATASIZE(__DATASIZE__) (((__DATASIZE__) == SPI_DATASIZE_16BIT) || \ 00634 ((__DATASIZE__) == SPI_DATASIZE_15BIT) || \ 00635 ((__DATASIZE__) == SPI_DATASIZE_14BIT) || \ 00636 ((__DATASIZE__) == SPI_DATASIZE_13BIT) || \ 00637 ((__DATASIZE__) == SPI_DATASIZE_12BIT) || \ 00638 ((__DATASIZE__) == SPI_DATASIZE_11BIT) || \ 00639 ((__DATASIZE__) == SPI_DATASIZE_10BIT) || \ 00640 ((__DATASIZE__) == SPI_DATASIZE_9BIT) || \ 00641 ((__DATASIZE__) == SPI_DATASIZE_8BIT) || \ 00642 ((__DATASIZE__) == SPI_DATASIZE_7BIT) || \ 00643 ((__DATASIZE__) == SPI_DATASIZE_6BIT) || \ 00644 ((__DATASIZE__) == SPI_DATASIZE_5BIT) || \ 00645 ((__DATASIZE__) == SPI_DATASIZE_4BIT)) 00646 00647 /** @brief Checks if SPI Serial clock steady state parameter is in allowed range. 00648 * @param __CPOL__ specifies the SPI serial clock steady state. 00649 * This parameter can be a value of @ref SPI_Clock_Polarity 00650 * @retval None 00651 */ 00652 #define IS_SPI_CPOL(__CPOL__) (((__CPOL__) == SPI_POLARITY_LOW) || \ 00653 ((__CPOL__) == SPI_POLARITY_HIGH)) 00654 00655 /** @brief Checks if SPI Clock Phase parameter is in allowed range. 00656 * @param __CPHA__ specifies the SPI Clock Phase. 00657 * This parameter can be a value of @ref SPI_Clock_Phase 00658 * @retval None 00659 */ 00660 #define IS_SPI_CPHA(__CPHA__) (((__CPHA__) == SPI_PHASE_1EDGE) || \ 00661 ((__CPHA__) == SPI_PHASE_2EDGE)) 00662 00663 /** @brief Checks if SPI Slave Select parameter is in allowed range. 00664 * @param __NSS__ specifies the SPI Slave Slelect management parameter. 00665 * This parameter can be a value of @ref SPI_Slave_Select_management 00666 * @retval None 00667 */ 00668 #define IS_SPI_NSS(__NSS__) (((__NSS__) == SPI_NSS_SOFT) || \ 00669 ((__NSS__) == SPI_NSS_HARD_INPUT) || \ 00670 ((__NSS__) == SPI_NSS_HARD_OUTPUT)) 00671 00672 /** @brief Checks if SPI NSS Pulse parameter is in allowed range. 00673 * @param __NSSP__ specifies the SPI NSS Pulse Mode parameter. 00674 * This parameter can be a value of @ref SPI_NSSP_Mode 00675 * @retval None 00676 */ 00677 #define IS_SPI_NSSP(__NSSP__) (((__NSSP__) == SPI_NSS_PULSE_ENABLE) || \ 00678 ((__NSSP__) == SPI_NSS_PULSE_DISABLE)) 00679 00680 /** @brief Checks if SPI Baudrate prescaler parameter is in allowed range. 00681 * @param __PRESCALER__ specifies the SPI Baudrate prescaler. 00682 * This parameter can be a value of @ref SPI_BaudRate_Prescaler 00683 * @retval None 00684 */ 00685 #define IS_SPI_BAUDRATE_PRESCALER(__PRESCALER__) (((__PRESCALER__) == SPI_BAUDRATEPRESCALER_2) || \ 00686 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_4) || \ 00687 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_8) || \ 00688 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_16) || \ 00689 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_32) || \ 00690 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_64) || \ 00691 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_128) || \ 00692 ((__PRESCALER__) == SPI_BAUDRATEPRESCALER_256)) 00693 00694 /** @brief Checks if SPI MSB LSB transmission parameter is in allowed range. 00695 * @param __BIT__ specifies the SPI MSB LSB transmission (whether data transfer starts from MSB or LSB bit). 00696 * This parameter can be a value of @ref SPI_MSB_LSB_transmission 00697 * @retval None 00698 */ 00699 #define IS_SPI_FIRST_BIT(__BIT__) (((__BIT__) == SPI_FIRSTBIT_MSB) || \ 00700 ((__BIT__) == SPI_FIRSTBIT_LSB)) 00701 00702 /** @brief Checks if SPI TI mode parameter is in allowed range. 00703 * @param __MODE__ specifies the SPI TI mode. 00704 * This parameter can be a value of @ref SPI_TI_mode 00705 * @retval None 00706 */ 00707 #define IS_SPI_TIMODE(__MODE__) (((__MODE__) == SPI_TIMODE_DISABLE) || \ 00708 ((__MODE__) == SPI_TIMODE_ENABLE)) 00709 00710 /** @brief Checks if SPI CRC calculation enabled state is in allowed range. 00711 * @param __CALCULATION__ specifies the SPI CRC calculation enable state. 00712 * This parameter can be a value of @ref SPI_CRC_Calculation 00713 * @retval None 00714 */ 00715 #define IS_SPI_CRC_CALCULATION(__CALCULATION__) (((__CALCULATION__) == SPI_CRCCALCULATION_DISABLE) || \ 00716 ((__CALCULATION__) == SPI_CRCCALCULATION_ENABLE)) 00717 00718 /** @brief Checks if SPI CRC length is in allowed range. 00719 * @param __LENGTH__ specifies the SPI CRC length. 00720 * This parameter can be a value of @ref SPI_CRC_length 00721 * @retval None 00722 */ 00723 #define IS_SPI_CRC_LENGTH(__LENGTH__) (((__LENGTH__) == SPI_CRC_LENGTH_DATASIZE) ||\ 00724 ((__LENGTH__) == SPI_CRC_LENGTH_8BIT) || \ 00725 ((__LENGTH__) == SPI_CRC_LENGTH_16BIT)) 00726 00727 /** @brief Checks if SPI polynomial value to be used for the CRC calculation, is in allowed range. 00728 * @param __POLYNOMIAL__ specifies the SPI polynomial value to be used for the CRC calculation. 00729 * This parameter must be a number between Min_Data = 0 and Max_Data = 65535 00730 * @retval None 00731 */ 00732 #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && ((__POLYNOMIAL__) <= 0xFFFFU) && (((__POLYNOMIAL__)&0x1U) != 0U)) 00733 00734 /** @brief Checks if DMA handle is valid. 00735 * @param __HANDLE__ specifies a DMA Handle. 00736 * @retval None 00737 */ 00738 #define IS_SPI_DMA_HANDLE(__HANDLE__) ((__HANDLE__) != NULL) 00739 00740 /** 00741 * @} 00742 */ 00743 00744 /* Include SPI HAL Extended module */ 00745 #include "stm32l4xx_hal_spi_ex.h" 00746 00747 /* Exported functions --------------------------------------------------------*/ 00748 /** @addtogroup SPI_Exported_Functions 00749 * @{ 00750 */ 00751 00752 /** @addtogroup SPI_Exported_Functions_Group1 00753 * @{ 00754 */ 00755 /* Initialization/de-initialization functions ********************************/ 00756 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi); 00757 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi); 00758 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi); 00759 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi); 00760 00761 /* Callbacks Register/UnRegister functions ***********************************/ 00762 #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) 00763 HAL_StatusTypeDef HAL_SPI_RegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID, pSPI_CallbackTypeDef pCallback); 00764 HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_CallbackIDTypeDef CallbackID); 00765 #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ 00766 /** 00767 * @} 00768 */ 00769 00770 /** @addtogroup SPI_Exported_Functions_Group2 00771 * @{ 00772 */ 00773 /* I/O operation functions ***************************************************/ 00774 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); 00775 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); 00776 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, 00777 uint32_t Timeout); 00778 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 00779 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 00780 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, 00781 uint16_t Size); 00782 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 00783 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); 00784 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, 00785 uint16_t Size); 00786 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); 00787 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); 00788 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi); 00789 /* Transfer Abort functions */ 00790 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi); 00791 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi); 00792 00793 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi); 00794 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi); 00795 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi); 00796 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi); 00797 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi); 00798 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi); 00799 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi); 00800 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi); 00801 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); 00802 /** 00803 * @} 00804 */ 00805 00806 /** @addtogroup SPI_Exported_Functions_Group3 00807 * @{ 00808 */ 00809 /* Peripheral State and Error functions ***************************************/ 00810 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); 00811 uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); 00812 /** 00813 * @} 00814 */ 00815 00816 /** 00817 * @} 00818 */ 00819 00820 /** 00821 * @} 00822 */ 00823 00824 /** 00825 * @} 00826 */ 00827 00828 #ifdef __cplusplus 00829 } 00830 #endif 00831 00832 #endif /* __STM32L4xx_HAL_SPI_H */ 00833 00834 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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