STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_pwr_ex.c 00004 * @author MCD Application Team 00005 * @brief Extended PWR HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the Power Controller (PWR) peripheral: 00008 * + Extended Initialization and de-initialization functions 00009 * + Extended Peripheral Control functions 00010 * 00011 ****************************************************************************** 00012 * @attention 00013 * 00014 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00015 * 00016 * Redistribution and use in source and binary forms, with or without modification, 00017 * are permitted provided that the following conditions are met: 00018 * 1. Redistributions of source code must retain the above copyright notice, 00019 * this list of conditions and the following disclaimer. 00020 * 2. Redistributions in binary form must reproduce the above copyright notice, 00021 * this list of conditions and the following disclaimer in the documentation 00022 * and/or other materials provided with the distribution. 00023 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00024 * may be used to endorse or promote products derived from this software 00025 * without specific prior written permission. 00026 * 00027 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00028 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00029 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00030 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00031 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00032 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00033 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00034 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00035 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00036 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00037 * 00038 ****************************************************************************** 00039 */ 00040 00041 /* Includes ------------------------------------------------------------------*/ 00042 #include "stm32l4xx_hal.h" 00043 00044 /** @addtogroup STM32L4xx_HAL_Driver 00045 * @{ 00046 */ 00047 00048 /** @defgroup PWREx PWREx 00049 * @brief PWR Extended HAL module driver 00050 * @{ 00051 */ 00052 00053 #ifdef HAL_PWR_MODULE_ENABLED 00054 00055 /* Private typedef -----------------------------------------------------------*/ 00056 /* Private define ------------------------------------------------------------*/ 00057 00058 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) 00059 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ 00060 #elif defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 00061 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000000B) /* PH0/PH1/PH3 */ 00062 #elif defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) 00063 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x00000003) /* PH0/PH1 */ 00064 #elif defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00065 #define PWR_PORTH_AVAILABLE_PINS ((uint32_t)0x0000FFFF) /* PH0..PH15 */ 00066 #endif 00067 00068 #if defined (STM32L496xx) || defined (STM32L4A6xx) || defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined (STM32L4S9xx) 00069 #define PWR_PORTI_AVAILABLE_PINS ((uint32_t)0x00000FFF) /* PI0..PI11 */ 00070 #endif 00071 00072 /** @defgroup PWR_Extended_Private_Defines PWR Extended Private Defines 00073 * @{ 00074 */ 00075 00076 /** @defgroup PWREx_PVM_Mode_Mask PWR PVM Mode Mask 00077 * @{ 00078 */ 00079 #define PVM_MODE_IT ((uint32_t)0x00010000) /*!< Mask for interruption yielded by PVM threshold crossing */ 00080 #define PVM_MODE_EVT ((uint32_t)0x00020000) /*!< Mask for event yielded by PVM threshold crossing */ 00081 #define PVM_RISING_EDGE ((uint32_t)0x00000001) /*!< Mask for rising edge set as PVM trigger */ 00082 #define PVM_FALLING_EDGE ((uint32_t)0x00000002) /*!< Mask for falling edge set as PVM trigger */ 00083 /** 00084 * @} 00085 */ 00086 00087 /** @defgroup PWREx_TimeOut_Value PWR Extended Flag Setting Time Out Value 00088 * @{ 00089 */ 00090 #define PWR_FLAG_SETTING_DELAY_US 50 /*!< Time out value for REGLPF and VOSF flags setting */ 00091 /** 00092 * @} 00093 */ 00094 00095 00096 00097 /** 00098 * @} 00099 */ 00100 00101 00102 00103 /* Private macro -------------------------------------------------------------*/ 00104 /* Private variables ---------------------------------------------------------*/ 00105 /* Private function prototypes -----------------------------------------------*/ 00106 /* Exported functions --------------------------------------------------------*/ 00107 00108 /** @defgroup PWREx_Exported_Functions PWR Extended Exported Functions 00109 * @{ 00110 */ 00111 00112 /** @defgroup PWREx_Exported_Functions_Group1 Extended Peripheral Control functions 00113 * @brief Extended Peripheral Control functions 00114 * 00115 @verbatim 00116 =============================================================================== 00117 ##### Extended Peripheral Initialization and de-initialization functions ##### 00118 =============================================================================== 00119 [..] 00120 00121 @endverbatim 00122 * @{ 00123 */ 00124 00125 00126 /** 00127 * @brief Return Voltage Scaling Range. 00128 * @retval VOS bit field (PWR_REGULATOR_VOLTAGE_RANGE1 or PWR_REGULATOR_VOLTAGE_RANGE2 00129 * or PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when applicable) 00130 */ 00131 uint32_t HAL_PWREx_GetVoltageRange(void) 00132 { 00133 #if defined(PWR_CR5_R1MODE) 00134 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 00135 { 00136 return PWR_REGULATOR_VOLTAGE_SCALE2; 00137 } 00138 else if (READ_BIT(PWR->CR5, PWR_CR5_R1MODE) == PWR_CR5_R1MODE) 00139 { 00140 /* PWR_CR5_R1MODE bit set means that Range 1 Boost is disabled */ 00141 return PWR_REGULATOR_VOLTAGE_SCALE1; 00142 } 00143 else 00144 { 00145 return PWR_REGULATOR_VOLTAGE_SCALE1_BOOST; 00146 } 00147 #else 00148 return (PWR->CR1 & PWR_CR1_VOS); 00149 #endif 00150 } 00151 00152 00153 00154 /** 00155 * @brief Configure the main internal regulator output voltage. 00156 * @param VoltageScaling: specifies the regulator output voltage to achieve 00157 * a tradeoff between performance and power consumption. 00158 * This parameter can be one of the following values: 00159 @if STM32L4S9xx 00160 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1_BOOST when available, Regulator voltage output range 1 boost mode, 00161 * typical output voltage at 1.2 V, 00162 * system frequency up to 120 MHz. 00163 @endif 00164 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE1 Regulator voltage output range 1 mode, 00165 * typical output voltage at 1.2 V, 00166 * system frequency up to 80 MHz. 00167 * @arg @ref PWR_REGULATOR_VOLTAGE_SCALE2 Regulator voltage output range 2 mode, 00168 * typical output voltage at 1.0 V, 00169 * system frequency up to 26 MHz. 00170 * @note When moving from Range 1 to Range 2, the system frequency must be decreased to 00171 * a value below 26 MHz before calling HAL_PWREx_ControlVoltageScaling() API. 00172 * When moving from Range 2 to Range 1, the system frequency can be increased to 00173 * a value up to 80 MHz after calling HAL_PWREx_ControlVoltageScaling() API. For 00174 * some devices, the system frequency can be increased up to 120 MHz. 00175 * @note When moving from Range 2 to Range 1, the API waits for VOSF flag to be 00176 * cleared before returning the status. If the flag is not cleared within 00177 * 50 microseconds, HAL_TIMEOUT status is reported. 00178 * @retval HAL Status 00179 */ 00180 HAL_StatusTypeDef HAL_PWREx_ControlVoltageScaling(uint32_t VoltageScaling) 00181 { 00182 uint32_t wait_loop_index = 0; 00183 00184 assert_param(IS_PWR_VOLTAGE_SCALING_RANGE(VoltageScaling)); 00185 00186 #if defined(PWR_CR5_R1MODE) 00187 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1_BOOST) 00188 { 00189 /* If current range is range 2 */ 00190 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 00191 { 00192 /* Make sure Range 1 Boost is enabled */ 00193 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 00194 00195 /* Set Range 1 */ 00196 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 00197 00198 /* Wait until VOSF is cleared */ 00199 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); 00200 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) 00201 { 00202 wait_loop_index--; 00203 } 00204 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 00205 { 00206 return HAL_TIMEOUT; 00207 } 00208 } 00209 /* If current range is range 1 normal or boost mode */ 00210 else 00211 { 00212 /* Enable Range 1 Boost (no issue if bit already reset) */ 00213 CLEAR_BIT(PWR->CR5, PWR_CR5_R1MODE); 00214 } 00215 } 00216 else if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 00217 { 00218 /* If current range is range 2 */ 00219 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) == PWR_REGULATOR_VOLTAGE_SCALE2) 00220 { 00221 /* Make sure Range 1 Boost is disabled */ 00222 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 00223 00224 /* Set Range 1 */ 00225 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 00226 00227 /* Wait until VOSF is cleared */ 00228 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); 00229 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) 00230 { 00231 wait_loop_index--; 00232 } 00233 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 00234 { 00235 return HAL_TIMEOUT; 00236 } 00237 } 00238 /* If current range is range 1 normal or boost mode */ 00239 else 00240 { 00241 /* Disable Range 1 Boost (no issue if bit already set) */ 00242 SET_BIT(PWR->CR5, PWR_CR5_R1MODE); 00243 } 00244 } 00245 else 00246 { 00247 /* Set Range 2 */ 00248 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 00249 /* No need to wait for VOSF to be cleared for this transition */ 00250 /* PWR_CR5_R1MODE bit setting has no effect in Range 2 */ 00251 } 00252 00253 #else 00254 00255 /* If Set Range 1 */ 00256 if (VoltageScaling == PWR_REGULATOR_VOLTAGE_SCALE1) 00257 { 00258 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE1) 00259 { 00260 /* Set Range 1 */ 00261 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE1); 00262 00263 /* Wait until VOSF is cleared */ 00264 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); 00265 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF))) 00266 { 00267 wait_loop_index--; 00268 } 00269 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_VOSF)) 00270 { 00271 return HAL_TIMEOUT; 00272 } 00273 } 00274 } 00275 else 00276 { 00277 if (READ_BIT(PWR->CR1, PWR_CR1_VOS) != PWR_REGULATOR_VOLTAGE_SCALE2) 00278 { 00279 /* Set Range 2 */ 00280 MODIFY_REG(PWR->CR1, PWR_CR1_VOS, PWR_REGULATOR_VOLTAGE_SCALE2); 00281 /* No need to wait for VOSF to be cleared for this transition */ 00282 } 00283 } 00284 #endif 00285 00286 return HAL_OK; 00287 } 00288 00289 00290 /** 00291 * @brief Enable battery charging. 00292 * When VDD is present, charge the external battery on VBAT thru an internal resistor. 00293 * @param ResistorSelection: specifies the resistor impedance. 00294 * This parameter can be one of the following values: 00295 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_5 5 kOhms resistor 00296 * @arg @ref PWR_BATTERY_CHARGING_RESISTOR_1_5 1.5 kOhms resistor 00297 * @retval None 00298 */ 00299 void HAL_PWREx_EnableBatteryCharging(uint32_t ResistorSelection) 00300 { 00301 assert_param(IS_PWR_BATTERY_RESISTOR_SELECT(ResistorSelection)); 00302 00303 /* Specify resistor selection */ 00304 MODIFY_REG(PWR->CR4, PWR_CR4_VBRS, ResistorSelection); 00305 00306 /* Enable battery charging */ 00307 SET_BIT(PWR->CR4, PWR_CR4_VBE); 00308 } 00309 00310 00311 /** 00312 * @brief Disable battery charging. 00313 * @retval None 00314 */ 00315 void HAL_PWREx_DisableBatteryCharging(void) 00316 { 00317 CLEAR_BIT(PWR->CR4, PWR_CR4_VBE); 00318 } 00319 00320 00321 #if defined(PWR_CR2_USV) 00322 /** 00323 * @brief Enable VDDUSB supply. 00324 * @note Remove VDDUSB electrical and logical isolation, once VDDUSB supply is present. 00325 * @retval None 00326 */ 00327 void HAL_PWREx_EnableVddUSB(void) 00328 { 00329 SET_BIT(PWR->CR2, PWR_CR2_USV); 00330 } 00331 00332 00333 /** 00334 * @brief Disable VDDUSB supply. 00335 * @retval None 00336 */ 00337 void HAL_PWREx_DisableVddUSB(void) 00338 { 00339 CLEAR_BIT(PWR->CR2, PWR_CR2_USV); 00340 } 00341 #endif /* PWR_CR2_USV */ 00342 00343 #if defined(PWR_CR2_IOSV) 00344 /** 00345 * @brief Enable VDDIO2 supply. 00346 * @note Remove VDDIO2 electrical and logical isolation, once VDDIO2 supply is present. 00347 * @retval None 00348 */ 00349 void HAL_PWREx_EnableVddIO2(void) 00350 { 00351 SET_BIT(PWR->CR2, PWR_CR2_IOSV); 00352 } 00353 00354 00355 /** 00356 * @brief Disable VDDIO2 supply. 00357 * @retval None 00358 */ 00359 void HAL_PWREx_DisableVddIO2(void) 00360 { 00361 CLEAR_BIT(PWR->CR2, PWR_CR2_IOSV); 00362 } 00363 #endif /* PWR_CR2_IOSV */ 00364 00365 00366 /** 00367 * @brief Enable Internal Wake-up Line. 00368 * @retval None 00369 */ 00370 void HAL_PWREx_EnableInternalWakeUpLine(void) 00371 { 00372 SET_BIT(PWR->CR3, PWR_CR3_EIWF); 00373 } 00374 00375 00376 /** 00377 * @brief Disable Internal Wake-up Line. 00378 * @retval None 00379 */ 00380 void HAL_PWREx_DisableInternalWakeUpLine(void) 00381 { 00382 CLEAR_BIT(PWR->CR3, PWR_CR3_EIWF); 00383 } 00384 00385 00386 00387 /** 00388 * @brief Enable GPIO pull-up state in Standby and Shutdown modes. 00389 * @note Set the relevant PUy bits of PWR_PUCRx register to configure the I/O in 00390 * pull-up state in Standby and Shutdown modes. 00391 * @note This state is effective in Standby and Shutdown modes only if APC bit 00392 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. 00393 * @note The configuration is lost when exiting the Shutdown mode due to the 00394 * power-on reset, maintained when exiting the Standby mode. 00395 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding 00396 * PDy bit of PWR_PDCRx register is cleared unless it is reserved. 00397 * @note Even if a PUy bit to set is reserved, the other PUy bits entered as input 00398 * parameter at the same time are set. 00399 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H 00400 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. 00401 * @param GPIONumber: Specify the I/O pins numbers. 00402 * This parameter can be one of the following values: 00403 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less 00404 * I/O pins are available) or the logical OR of several of them to set 00405 * several bits for a given port in a single API call. 00406 * @retval HAL Status 00407 */ 00408 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00409 { 00410 assert_param(IS_PWR_GPIO(GPIO)); 00411 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00412 00413 switch (GPIO) 00414 { 00415 case PWR_GPIO_A: 00416 SET_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); 00417 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); 00418 break; 00419 case PWR_GPIO_B: 00420 SET_BIT(PWR->PUCRB, GPIONumber); 00421 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); 00422 break; 00423 case PWR_GPIO_C: 00424 SET_BIT(PWR->PUCRC, GPIONumber); 00425 CLEAR_BIT(PWR->PDCRC, GPIONumber); 00426 break; 00427 #if defined(GPIOD) 00428 case PWR_GPIO_D: 00429 SET_BIT(PWR->PUCRD, GPIONumber); 00430 CLEAR_BIT(PWR->PDCRD, GPIONumber); 00431 break; 00432 #endif 00433 #if defined(GPIOE) 00434 case PWR_GPIO_E: 00435 SET_BIT(PWR->PUCRE, GPIONumber); 00436 CLEAR_BIT(PWR->PDCRE, GPIONumber); 00437 break; 00438 #endif 00439 #if defined(GPIOF) 00440 case PWR_GPIO_F: 00441 SET_BIT(PWR->PUCRF, GPIONumber); 00442 CLEAR_BIT(PWR->PDCRF, GPIONumber); 00443 break; 00444 #endif 00445 #if defined(GPIOG) 00446 case PWR_GPIO_G: 00447 SET_BIT(PWR->PUCRG, GPIONumber); 00448 CLEAR_BIT(PWR->PDCRG, GPIONumber); 00449 break; 00450 #endif 00451 case PWR_GPIO_H: 00452 SET_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00453 #if defined (STM32L496xx) || defined (STM32L4A6xx) 00454 CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); 00455 #else 00456 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00457 #endif 00458 break; 00459 #if defined(GPIOI) 00460 case PWR_GPIO_I: 00461 SET_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); 00462 CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); 00463 break; 00464 #endif 00465 default: 00466 return HAL_ERROR; 00467 } 00468 00469 return HAL_OK; 00470 } 00471 00472 00473 /** 00474 * @brief Disable GPIO pull-up state in Standby mode and Shutdown modes. 00475 * @note Reset the relevant PUy bits of PWR_PUCRx register used to configure the I/O 00476 * in pull-up state in Standby and Shutdown modes. 00477 * @note Even if a PUy bit to reset is reserved, the other PUy bits entered as input 00478 * parameter at the same time are reset. 00479 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A, ..., PWR_GPIO_H 00480 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. 00481 * @param GPIONumber: Specify the I/O pins numbers. 00482 * This parameter can be one of the following values: 00483 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less 00484 * I/O pins are available) or the logical OR of several of them to reset 00485 * several bits for a given port in a single API call. 00486 * @retval HAL Status 00487 */ 00488 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber) 00489 { 00490 assert_param(IS_PWR_GPIO(GPIO)); 00491 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00492 00493 switch (GPIO) 00494 { 00495 case PWR_GPIO_A: 00496 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); 00497 break; 00498 case PWR_GPIO_B: 00499 CLEAR_BIT(PWR->PUCRB, GPIONumber); 00500 break; 00501 case PWR_GPIO_C: 00502 CLEAR_BIT(PWR->PUCRC, GPIONumber); 00503 break; 00504 #if defined(GPIOD) 00505 case PWR_GPIO_D: 00506 CLEAR_BIT(PWR->PUCRD, GPIONumber); 00507 break; 00508 #endif 00509 #if defined(GPIOE) 00510 case PWR_GPIO_E: 00511 CLEAR_BIT(PWR->PUCRE, GPIONumber); 00512 break; 00513 #endif 00514 #if defined(GPIOF) 00515 case PWR_GPIO_F: 00516 CLEAR_BIT(PWR->PUCRF, GPIONumber); 00517 break; 00518 #endif 00519 #if defined(GPIOG) 00520 case PWR_GPIO_G: 00521 CLEAR_BIT(PWR->PUCRG, GPIONumber); 00522 break; 00523 #endif 00524 case PWR_GPIO_H: 00525 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00526 break; 00527 #if defined(GPIOI) 00528 case PWR_GPIO_I: 00529 CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); 00530 break; 00531 #endif 00532 default: 00533 return HAL_ERROR; 00534 } 00535 00536 return HAL_OK; 00537 } 00538 00539 00540 00541 /** 00542 * @brief Enable GPIO pull-down state in Standby and Shutdown modes. 00543 * @note Set the relevant PDy bits of PWR_PDCRx register to configure the I/O in 00544 * pull-down state in Standby and Shutdown modes. 00545 * @note This state is effective in Standby and Shutdown modes only if APC bit 00546 * is set through HAL_PWREx_EnablePullUpPullDownConfig() API. 00547 * @note The configuration is lost when exiting the Shutdown mode due to the 00548 * power-on reset, maintained when exiting the Standby mode. 00549 * @note To avoid any conflict at Standby and Shutdown modes exits, the corresponding 00550 * PUy bit of PWR_PUCRx register is cleared unless it is reserved. 00551 * @note Even if a PDy bit to set is reserved, the other PDy bits entered as input 00552 * parameter at the same time are set. 00553 * @param GPIO: Specify the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H 00554 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. 00555 * @param GPIONumber: Specify the I/O pins numbers. 00556 * This parameter can be one of the following values: 00557 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less 00558 * I/O pins are available) or the logical OR of several of them to set 00559 * several bits for a given port in a single API call. 00560 * @retval HAL Status 00561 */ 00562 HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 00563 { 00564 assert_param(IS_PWR_GPIO(GPIO)); 00565 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00566 00567 switch (GPIO) 00568 { 00569 case PWR_GPIO_A: 00570 SET_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); 00571 CLEAR_BIT(PWR->PUCRA, (GPIONumber & (~(PWR_GPIO_BIT_14)))); 00572 break; 00573 case PWR_GPIO_B: 00574 SET_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); 00575 CLEAR_BIT(PWR->PUCRB, GPIONumber); 00576 break; 00577 case PWR_GPIO_C: 00578 SET_BIT(PWR->PDCRC, GPIONumber); 00579 CLEAR_BIT(PWR->PUCRC, GPIONumber); 00580 break; 00581 #if defined(GPIOD) 00582 case PWR_GPIO_D: 00583 SET_BIT(PWR->PDCRD, GPIONumber); 00584 CLEAR_BIT(PWR->PUCRD, GPIONumber); 00585 break; 00586 #endif 00587 #if defined(GPIOE) 00588 case PWR_GPIO_E: 00589 SET_BIT(PWR->PDCRE, GPIONumber); 00590 CLEAR_BIT(PWR->PUCRE, GPIONumber); 00591 break; 00592 #endif 00593 #if defined(GPIOF) 00594 case PWR_GPIO_F: 00595 SET_BIT(PWR->PDCRF, GPIONumber); 00596 CLEAR_BIT(PWR->PUCRF, GPIONumber); 00597 break; 00598 #endif 00599 #if defined(GPIOG) 00600 case PWR_GPIO_G: 00601 SET_BIT(PWR->PDCRG, GPIONumber); 00602 CLEAR_BIT(PWR->PUCRG, GPIONumber); 00603 break; 00604 #endif 00605 case PWR_GPIO_H: 00606 #if defined (STM32L496xx) || defined (STM32L4A6xx) 00607 SET_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); 00608 #else 00609 SET_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00610 #endif 00611 CLEAR_BIT(PWR->PUCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00612 break; 00613 #if defined(GPIOI) 00614 case PWR_GPIO_I: 00615 SET_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); 00616 CLEAR_BIT(PWR->PUCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); 00617 break; 00618 #endif 00619 default: 00620 return HAL_ERROR; 00621 } 00622 00623 return HAL_OK; 00624 } 00625 00626 00627 /** 00628 * @brief Disable GPIO pull-down state in Standby and Shutdown modes. 00629 * @note Reset the relevant PDy bits of PWR_PDCRx register used to configure the I/O 00630 * in pull-down state in Standby and Shutdown modes. 00631 * @note Even if a PDy bit to reset is reserved, the other PDy bits entered as input 00632 * parameter at the same time are reset. 00633 * @param GPIO: Specifies the IO port. This parameter can be PWR_GPIO_A..PWR_GPIO_H 00634 * (or PWR_GPIO_I depending on the devices) to select the GPIO peripheral. 00635 * @param GPIONumber: Specify the I/O pins numbers. 00636 * This parameter can be one of the following values: 00637 * PWR_GPIO_BIT_0, ..., PWR_GPIO_BIT_15 (except for the port where less 00638 * I/O pins are available) or the logical OR of several of them to reset 00639 * several bits for a given port in a single API call. 00640 * @retval HAL Status 00641 */ 00642 HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullDown(uint32_t GPIO, uint32_t GPIONumber) 00643 { 00644 assert_param(IS_PWR_GPIO(GPIO)); 00645 assert_param(IS_PWR_GPIO_BIT_NUMBER(GPIONumber)); 00646 00647 switch (GPIO) 00648 { 00649 case PWR_GPIO_A: 00650 CLEAR_BIT(PWR->PDCRA, (GPIONumber & (~(PWR_GPIO_BIT_13|PWR_GPIO_BIT_15)))); 00651 break; 00652 case PWR_GPIO_B: 00653 CLEAR_BIT(PWR->PDCRB, (GPIONumber & (~(PWR_GPIO_BIT_4)))); 00654 break; 00655 case PWR_GPIO_C: 00656 CLEAR_BIT(PWR->PDCRC, GPIONumber); 00657 break; 00658 #if defined(GPIOD) 00659 case PWR_GPIO_D: 00660 CLEAR_BIT(PWR->PDCRD, GPIONumber); 00661 break; 00662 #endif 00663 #if defined(GPIOE) 00664 case PWR_GPIO_E: 00665 CLEAR_BIT(PWR->PDCRE, GPIONumber); 00666 break; 00667 #endif 00668 #if defined(GPIOF) 00669 case PWR_GPIO_F: 00670 CLEAR_BIT(PWR->PDCRF, GPIONumber); 00671 break; 00672 #endif 00673 #if defined(GPIOG) 00674 case PWR_GPIO_G: 00675 CLEAR_BIT(PWR->PDCRG, GPIONumber); 00676 break; 00677 #endif 00678 case PWR_GPIO_H: 00679 #if defined (STM32L496xx) || defined (STM32L4A6xx) 00680 CLEAR_BIT(PWR->PDCRH, ((GPIONumber & PWR_PORTH_AVAILABLE_PINS) & (~(PWR_GPIO_BIT_3)))); 00681 #else 00682 CLEAR_BIT(PWR->PDCRH, (GPIONumber & PWR_PORTH_AVAILABLE_PINS)); 00683 #endif 00684 break; 00685 #if defined(GPIOI) 00686 case PWR_GPIO_I: 00687 CLEAR_BIT(PWR->PDCRI, (GPIONumber & PWR_PORTI_AVAILABLE_PINS)); 00688 break; 00689 #endif 00690 default: 00691 return HAL_ERROR; 00692 } 00693 00694 return HAL_OK; 00695 } 00696 00697 00698 00699 /** 00700 * @brief Enable pull-up and pull-down configuration. 00701 * @note When APC bit is set, the I/O pull-up and pull-down configurations defined in 00702 * PWR_PUCRx and PWR_PDCRx registers are applied in Standby and Shutdown modes. 00703 * @note Pull-up set by PUy bit of PWR_PUCRx register is not activated if the corresponding 00704 * PDy bit of PWR_PDCRx register is also set (pull-down configuration priority is higher). 00705 * HAL_PWREx_EnableGPIOPullUp() and HAL_PWREx_EnableGPIOPullDown() API's ensure there 00706 * is no conflict when setting PUy or PDy bit. 00707 * @retval None 00708 */ 00709 void HAL_PWREx_EnablePullUpPullDownConfig(void) 00710 { 00711 SET_BIT(PWR->CR3, PWR_CR3_APC); 00712 } 00713 00714 00715 /** 00716 * @brief Disable pull-up and pull-down configuration. 00717 * @note When APC bit is cleared, the I/O pull-up and pull-down configurations defined in 00718 * PWR_PUCRx and PWR_PDCRx registers are not applied in Standby and Shutdown modes. 00719 * @retval None 00720 */ 00721 void HAL_PWREx_DisablePullUpPullDownConfig(void) 00722 { 00723 CLEAR_BIT(PWR->CR3, PWR_CR3_APC); 00724 } 00725 00726 00727 00728 /** 00729 * @brief Enable SRAM2 content retention in Standby mode. 00730 * @note When RRS bit is set, SRAM2 is powered by the low-power regulator in 00731 * Standby mode and its content is kept. 00732 * @retval None 00733 */ 00734 void HAL_PWREx_EnableSRAM2ContentRetention(void) 00735 { 00736 SET_BIT(PWR->CR3, PWR_CR3_RRS); 00737 } 00738 00739 00740 /** 00741 * @brief Disable SRAM2 content retention in Standby mode. 00742 * @note When RRS bit is reset, SRAM2 is powered off in Standby mode 00743 * and its content is lost. 00744 * @retval None 00745 */ 00746 void HAL_PWREx_DisableSRAM2ContentRetention(void) 00747 { 00748 CLEAR_BIT(PWR->CR3, PWR_CR3_RRS); 00749 } 00750 00751 00752 #if defined(PWR_CR1_RRSTP) 00753 /** 00754 * @brief Enable SRAM3 content retention in Stop 2 mode. 00755 * @note When RRSTP bit is set, SRAM3 is powered by the low-power regulator in 00756 * Stop 2 mode and its content is kept. 00757 * @retval None 00758 */ 00759 void HAL_PWREx_EnableSRAM3ContentRetention(void) 00760 { 00761 SET_BIT(PWR->CR1, PWR_CR1_RRSTP); 00762 } 00763 00764 00765 /** 00766 * @brief Disable SRAM3 content retention in Stop 2 mode. 00767 * @note When RRSTP bit is reset, SRAM3 is powered off in Stop 2 mode 00768 * and its content is lost. 00769 * @retval None 00770 */ 00771 void HAL_PWREx_DisableSRAM3ContentRetention(void) 00772 { 00773 CLEAR_BIT(PWR->CR1, PWR_CR1_RRSTP); 00774 } 00775 #endif /* PWR_CR1_RRSTP */ 00776 00777 #if defined(PWR_CR3_DSIPDEN) 00778 /** 00779 * @brief Enable pull-down activation on DSI pins. 00780 * @retval None 00781 */ 00782 void HAL_PWREx_EnableDSIPinsPDActivation(void) 00783 { 00784 SET_BIT(PWR->CR3, PWR_CR3_DSIPDEN); 00785 } 00786 00787 00788 /** 00789 * @brief Disable pull-down activation on DSI pins. 00790 * @retval None 00791 */ 00792 void HAL_PWREx_DisableDSIPinsPDActivation(void) 00793 { 00794 CLEAR_BIT(PWR->CR3, PWR_CR3_DSIPDEN); 00795 } 00796 #endif /* PWR_CR3_DSIPDEN */ 00797 00798 #if defined(PWR_CR2_PVME1) 00799 /** 00800 * @brief Enable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. 00801 * @retval None 00802 */ 00803 void HAL_PWREx_EnablePVM1(void) 00804 { 00805 SET_BIT(PWR->CR2, PWR_PVM_1); 00806 } 00807 00808 /** 00809 * @brief Disable the Power Voltage Monitoring 1: VDDUSB versus 1.2V. 00810 * @retval None 00811 */ 00812 void HAL_PWREx_DisablePVM1(void) 00813 { 00814 CLEAR_BIT(PWR->CR2, PWR_PVM_1); 00815 } 00816 #endif /* PWR_CR2_PVME1 */ 00817 00818 00819 #if defined(PWR_CR2_PVME2) 00820 /** 00821 * @brief Enable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. 00822 * @retval None 00823 */ 00824 void HAL_PWREx_EnablePVM2(void) 00825 { 00826 SET_BIT(PWR->CR2, PWR_PVM_2); 00827 } 00828 00829 /** 00830 * @brief Disable the Power Voltage Monitoring 2: VDDIO2 versus 0.9V. 00831 * @retval None 00832 */ 00833 void HAL_PWREx_DisablePVM2(void) 00834 { 00835 CLEAR_BIT(PWR->CR2, PWR_PVM_2); 00836 } 00837 #endif /* PWR_CR2_PVME2 */ 00838 00839 00840 /** 00841 * @brief Enable the Power Voltage Monitoring 3: VDDA versus 1.62V. 00842 * @retval None 00843 */ 00844 void HAL_PWREx_EnablePVM3(void) 00845 { 00846 SET_BIT(PWR->CR2, PWR_PVM_3); 00847 } 00848 00849 /** 00850 * @brief Disable the Power Voltage Monitoring 3: VDDA versus 1.62V. 00851 * @retval None 00852 */ 00853 void HAL_PWREx_DisablePVM3(void) 00854 { 00855 CLEAR_BIT(PWR->CR2, PWR_PVM_3); 00856 } 00857 00858 00859 /** 00860 * @brief Enable the Power Voltage Monitoring 4: VDDA versus 2.2V. 00861 * @retval None 00862 */ 00863 void HAL_PWREx_EnablePVM4(void) 00864 { 00865 SET_BIT(PWR->CR2, PWR_PVM_4); 00866 } 00867 00868 /** 00869 * @brief Disable the Power Voltage Monitoring 4: VDDA versus 2.2V. 00870 * @retval None 00871 */ 00872 void HAL_PWREx_DisablePVM4(void) 00873 { 00874 CLEAR_BIT(PWR->CR2, PWR_PVM_4); 00875 } 00876 00877 00878 00879 00880 /** 00881 * @brief Configure the Peripheral Voltage Monitoring (PVM). 00882 * @param sConfigPVM: pointer to a PWR_PVMTypeDef structure that contains the 00883 * PVM configuration information. 00884 * @note The API configures a single PVM according to the information contained 00885 * in the input structure. To configure several PVMs, the API must be singly 00886 * called for each PVM used. 00887 * @note Refer to the electrical characteristics of your device datasheet for 00888 * more details about the voltage thresholds corresponding to each 00889 * detection level and to each monitored supply. 00890 * @retval HAL status 00891 */ 00892 HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) 00893 { 00894 /* Check the parameters */ 00895 assert_param(IS_PWR_PVM_TYPE(sConfigPVM->PVMType)); 00896 assert_param(IS_PWR_PVM_MODE(sConfigPVM->Mode)); 00897 00898 00899 /* Configure EXTI 35 to 38 interrupts if so required: 00900 scan thru PVMType to detect which PVMx is set and 00901 configure the corresponding EXTI line accordingly. */ 00902 switch (sConfigPVM->PVMType) 00903 { 00904 #if defined(PWR_CR2_PVME1) 00905 case PWR_PVM_1: 00906 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00907 __HAL_PWR_PVM1_EXTI_DISABLE_EVENT(); 00908 __HAL_PWR_PVM1_EXTI_DISABLE_IT(); 00909 __HAL_PWR_PVM1_EXTI_DISABLE_FALLING_EDGE(); 00910 __HAL_PWR_PVM1_EXTI_DISABLE_RISING_EDGE(); 00911 00912 /* Configure interrupt mode */ 00913 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00914 { 00915 __HAL_PWR_PVM1_EXTI_ENABLE_IT(); 00916 } 00917 00918 /* Configure event mode */ 00919 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00920 { 00921 __HAL_PWR_PVM1_EXTI_ENABLE_EVENT(); 00922 } 00923 00924 /* Configure the edge */ 00925 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00926 { 00927 __HAL_PWR_PVM1_EXTI_ENABLE_RISING_EDGE(); 00928 } 00929 00930 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00931 { 00932 __HAL_PWR_PVM1_EXTI_ENABLE_FALLING_EDGE(); 00933 } 00934 break; 00935 #endif /* PWR_CR2_PVME1 */ 00936 00937 #if defined(PWR_CR2_PVME2) 00938 case PWR_PVM_2: 00939 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00940 __HAL_PWR_PVM2_EXTI_DISABLE_EVENT(); 00941 __HAL_PWR_PVM2_EXTI_DISABLE_IT(); 00942 __HAL_PWR_PVM2_EXTI_DISABLE_FALLING_EDGE(); 00943 __HAL_PWR_PVM2_EXTI_DISABLE_RISING_EDGE(); 00944 00945 /* Configure interrupt mode */ 00946 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00947 { 00948 __HAL_PWR_PVM2_EXTI_ENABLE_IT(); 00949 } 00950 00951 /* Configure event mode */ 00952 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00953 { 00954 __HAL_PWR_PVM2_EXTI_ENABLE_EVENT(); 00955 } 00956 00957 /* Configure the edge */ 00958 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00959 { 00960 __HAL_PWR_PVM2_EXTI_ENABLE_RISING_EDGE(); 00961 } 00962 00963 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00964 { 00965 __HAL_PWR_PVM2_EXTI_ENABLE_FALLING_EDGE(); 00966 } 00967 break; 00968 #endif /* PWR_CR2_PVME2 */ 00969 00970 case PWR_PVM_3: 00971 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 00972 __HAL_PWR_PVM3_EXTI_DISABLE_EVENT(); 00973 __HAL_PWR_PVM3_EXTI_DISABLE_IT(); 00974 __HAL_PWR_PVM3_EXTI_DISABLE_FALLING_EDGE(); 00975 __HAL_PWR_PVM3_EXTI_DISABLE_RISING_EDGE(); 00976 00977 /* Configure interrupt mode */ 00978 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 00979 { 00980 __HAL_PWR_PVM3_EXTI_ENABLE_IT(); 00981 } 00982 00983 /* Configure event mode */ 00984 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 00985 { 00986 __HAL_PWR_PVM3_EXTI_ENABLE_EVENT(); 00987 } 00988 00989 /* Configure the edge */ 00990 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 00991 { 00992 __HAL_PWR_PVM3_EXTI_ENABLE_RISING_EDGE(); 00993 } 00994 00995 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 00996 { 00997 __HAL_PWR_PVM3_EXTI_ENABLE_FALLING_EDGE(); 00998 } 00999 break; 01000 01001 case PWR_PVM_4: 01002 /* Clear any previous config. Keep it clear if no event or IT mode is selected */ 01003 __HAL_PWR_PVM4_EXTI_DISABLE_EVENT(); 01004 __HAL_PWR_PVM4_EXTI_DISABLE_IT(); 01005 __HAL_PWR_PVM4_EXTI_DISABLE_FALLING_EDGE(); 01006 __HAL_PWR_PVM4_EXTI_DISABLE_RISING_EDGE(); 01007 01008 /* Configure interrupt mode */ 01009 if((sConfigPVM->Mode & PVM_MODE_IT) == PVM_MODE_IT) 01010 { 01011 __HAL_PWR_PVM4_EXTI_ENABLE_IT(); 01012 } 01013 01014 /* Configure event mode */ 01015 if((sConfigPVM->Mode & PVM_MODE_EVT) == PVM_MODE_EVT) 01016 { 01017 __HAL_PWR_PVM4_EXTI_ENABLE_EVENT(); 01018 } 01019 01020 /* Configure the edge */ 01021 if((sConfigPVM->Mode & PVM_RISING_EDGE) == PVM_RISING_EDGE) 01022 { 01023 __HAL_PWR_PVM4_EXTI_ENABLE_RISING_EDGE(); 01024 } 01025 01026 if((sConfigPVM->Mode & PVM_FALLING_EDGE) == PVM_FALLING_EDGE) 01027 { 01028 __HAL_PWR_PVM4_EXTI_ENABLE_FALLING_EDGE(); 01029 } 01030 break; 01031 01032 default: 01033 return HAL_ERROR; 01034 01035 } 01036 01037 01038 return HAL_OK; 01039 } 01040 01041 01042 01043 /** 01044 * @brief Enter Low-power Run mode 01045 * @note In Low-power Run mode, all I/O pins keep the same state as in Run mode. 01046 * @note When Regulator is set to PWR_LOWPOWERREGULATOR_ON, the user can optionally configure the 01047 * Flash in power-down monde in setting the RUN_PD bit in FLASH_ACR register. 01048 * Additionally, the clock frequency must be reduced below 2 MHz. 01049 * Setting RUN_PD in FLASH_ACR then appropriately reducing the clock frequency must 01050 * be done before calling HAL_PWREx_EnableLowPowerRunMode() API. 01051 * @retval None 01052 */ 01053 void HAL_PWREx_EnableLowPowerRunMode(void) 01054 { 01055 /* Set Regulator parameter */ 01056 SET_BIT(PWR->CR1, PWR_CR1_LPR); 01057 } 01058 01059 01060 /** 01061 * @brief Exit Low-power Run mode. 01062 * @note Before HAL_PWREx_DisableLowPowerRunMode() completion, the function checks that 01063 * REGLPF has been properly reset (otherwise, HAL_PWREx_DisableLowPowerRunMode 01064 * returns HAL_TIMEOUT status). The system clock frequency can then be 01065 * increased above 2 MHz. 01066 * @retval HAL Status 01067 */ 01068 HAL_StatusTypeDef HAL_PWREx_DisableLowPowerRunMode(void) 01069 { 01070 uint32_t wait_loop_index = 0; 01071 01072 /* Clear LPR bit */ 01073 CLEAR_BIT(PWR->CR1, PWR_CR1_LPR); 01074 01075 /* Wait until REGLPF is reset */ 01076 wait_loop_index = (PWR_FLAG_SETTING_DELAY_US * (SystemCoreClock / 1000000)); 01077 while ((wait_loop_index != 0) && (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF))) 01078 { 01079 wait_loop_index--; 01080 } 01081 if (HAL_IS_BIT_SET(PWR->SR2, PWR_SR2_REGLPF)) 01082 { 01083 return HAL_TIMEOUT; 01084 } 01085 01086 return HAL_OK; 01087 } 01088 01089 01090 /** 01091 * @brief Enter Stop 0 mode. 01092 * @note In Stop 0 mode, main and low voltage regulators are ON. 01093 * @note In Stop 0 mode, all I/O pins keep the same state as in Run mode. 01094 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, 01095 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 01096 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 01097 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 01098 * only to the peripheral requesting it. 01099 * SRAM1, SRAM2 and register contents are preserved. 01100 * The BOR is available. 01101 * @note When exiting Stop 0 mode by issuing an interrupt or a wakeup event, 01102 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register 01103 * is set; the MSI oscillator is selected if STOPWUCK is cleared. 01104 * @note By keeping the internal regulator ON during Stop 0 mode, the consumption 01105 * is higher although the startup time is reduced. 01106 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. 01107 * This parameter can be one of the following values: 01108 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction 01109 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction 01110 * @retval None 01111 */ 01112 void HAL_PWREx_EnterSTOP0Mode(uint8_t STOPEntry) 01113 { 01114 /* Check the parameters */ 01115 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 01116 01117 /* Stop 0 mode with Main Regulator */ 01118 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP0); 01119 01120 /* Set SLEEPDEEP bit of Cortex System Control Register */ 01121 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01122 01123 /* Select Stop mode entry --------------------------------------------------*/ 01124 if(STOPEntry == PWR_STOPENTRY_WFI) 01125 { 01126 /* Request Wait For Interrupt */ 01127 __WFI(); 01128 } 01129 else 01130 { 01131 /* Request Wait For Event */ 01132 __SEV(); 01133 __WFE(); 01134 __WFE(); 01135 } 01136 01137 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 01138 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01139 } 01140 01141 01142 /** 01143 * @brief Enter Stop 1 mode. 01144 * @note In Stop 1 mode, only low power voltage regulator is ON. 01145 * @note In Stop 1 mode, all I/O pins keep the same state as in Run mode. 01146 * @note All clocks in the VCORE domain are stopped; the PLL, the MSI, 01147 * the HSI and the HSE oscillators are disabled. Some peripherals with the wakeup capability 01148 * (I2Cx, USARTx and LPUART) can switch on the HSI to receive a frame, and switch off the HSI 01149 * after receiving the frame if it is not a wakeup frame. In this case, the HSI clock is propagated 01150 * only to the peripheral requesting it. 01151 * SRAM1, SRAM2 and register contents are preserved. 01152 * The BOR is available. 01153 * @note When exiting Stop 1 mode by issuing an interrupt or a wakeup event, 01154 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register 01155 * is set; the MSI oscillator is selected if STOPWUCK is cleared. 01156 * @note Due to low power mode, an additional startup delay is incurred when waking up from Stop 1 mode. 01157 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. 01158 * This parameter can be one of the following values: 01159 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction 01160 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction 01161 * @retval None 01162 */ 01163 void HAL_PWREx_EnterSTOP1Mode(uint8_t STOPEntry) 01164 { 01165 /* Check the parameters */ 01166 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 01167 01168 /* Stop 1 mode with Low-Power Regulator */ 01169 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP1); 01170 01171 /* Set SLEEPDEEP bit of Cortex System Control Register */ 01172 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01173 01174 /* Select Stop mode entry --------------------------------------------------*/ 01175 if(STOPEntry == PWR_STOPENTRY_WFI) 01176 { 01177 /* Request Wait For Interrupt */ 01178 __WFI(); 01179 } 01180 else 01181 { 01182 /* Request Wait For Event */ 01183 __SEV(); 01184 __WFE(); 01185 __WFE(); 01186 } 01187 01188 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 01189 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01190 } 01191 01192 01193 /** 01194 * @brief Enter Stop 2 mode. 01195 * @note In Stop 2 mode, only low power voltage regulator is ON. 01196 * @note In Stop 2 mode, all I/O pins keep the same state as in Run mode. 01197 * @note All clocks in the VCORE domain are stopped, the PLL, the MSI, 01198 * the HSI and the HSE oscillators are disabled. Some peripherals with wakeup capability 01199 * (LCD, LPTIM1, I2C3 and LPUART) can switch on the HSI to receive a frame, and switch off the HSI after 01200 * receiving the frame if it is not a wakeup frame. In this case the HSI clock is propagated only 01201 * to the peripheral requesting it. 01202 * SRAM1, SRAM2 and register contents are preserved. 01203 * The BOR is available. 01204 * The voltage regulator is set in low-power mode but LPR bit must be cleared to enter stop 2 mode. 01205 * Otherwise, Stop 1 mode is entered. 01206 * @note When exiting Stop 2 mode by issuing an interrupt or a wakeup event, 01207 * the HSI RC oscillator is selected as system clock if STOPWUCK bit in RCC_CFGR register 01208 * is set; the MSI oscillator is selected if STOPWUCK is cleared. 01209 * @param STOPEntry specifies if Stop mode in entered with WFI or WFE instruction. 01210 * This parameter can be one of the following values: 01211 * @arg @ref PWR_STOPENTRY_WFI Enter Stop mode with WFI instruction 01212 * @arg @ref PWR_STOPENTRY_WFE Enter Stop mode with WFE instruction 01213 * @retval None 01214 */ 01215 void HAL_PWREx_EnterSTOP2Mode(uint8_t STOPEntry) 01216 { 01217 /* Check the parameter */ 01218 assert_param(IS_PWR_STOP_ENTRY(STOPEntry)); 01219 01220 /* Set Stop mode 2 */ 01221 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_STOP2); 01222 01223 /* Set SLEEPDEEP bit of Cortex System Control Register */ 01224 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01225 01226 /* Select Stop mode entry --------------------------------------------------*/ 01227 if(STOPEntry == PWR_STOPENTRY_WFI) 01228 { 01229 /* Request Wait For Interrupt */ 01230 __WFI(); 01231 } 01232 else 01233 { 01234 /* Request Wait For Event */ 01235 __SEV(); 01236 __WFE(); 01237 __WFE(); 01238 } 01239 01240 /* Reset SLEEPDEEP bit of Cortex System Control Register */ 01241 CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01242 } 01243 01244 01245 01246 01247 01248 /** 01249 * @brief Enter Shutdown mode. 01250 * @note In Shutdown mode, the PLL, the HSI, the MSI, the LSI and the HSE oscillators are switched 01251 * off. The voltage regulator is disabled and Vcore domain is powered off. 01252 * SRAM1, SRAM2 and registers contents are lost except for registers in the Backup domain. 01253 * The BOR is not available. 01254 * @note The I/Os can be configured either with a pull-up or pull-down or can be kept in analog state. 01255 * @retval None 01256 */ 01257 void HAL_PWREx_EnterSHUTDOWNMode(void) 01258 { 01259 01260 /* Set Shutdown mode */ 01261 MODIFY_REG(PWR->CR1, PWR_CR1_LPMS, PWR_CR1_LPMS_SHUTDOWN); 01262 01263 /* Set SLEEPDEEP bit of Cortex System Control Register */ 01264 SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); 01265 01266 /* This option is used to ensure that store operations are completed */ 01267 #if defined ( __CC_ARM) 01268 __force_stores(); 01269 #endif 01270 /* Request Wait For Interrupt */ 01271 __WFI(); 01272 } 01273 01274 01275 01276 01277 /** 01278 * @brief This function handles the PWR PVD/PVMx interrupt request. 01279 * @note This API should be called under the PVD_PVM_IRQHandler(). 01280 * @retval None 01281 */ 01282 void HAL_PWREx_PVD_PVM_IRQHandler(void) 01283 { 01284 /* Check PWR exti flag */ 01285 if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET) 01286 { 01287 /* PWR PVD interrupt user callback */ 01288 HAL_PWR_PVDCallback(); 01289 01290 /* Clear PVD exti pending bit */ 01291 __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); 01292 } 01293 /* Next, successively check PVMx exti flags */ 01294 #if defined(PWR_CR2_PVME1) 01295 if(__HAL_PWR_PVM1_EXTI_GET_FLAG() != RESET) 01296 { 01297 /* PWR PVM1 interrupt user callback */ 01298 HAL_PWREx_PVM1Callback(); 01299 01300 /* Clear PVM1 exti pending bit */ 01301 __HAL_PWR_PVM1_EXTI_CLEAR_FLAG(); 01302 } 01303 #endif /* PWR_CR2_PVME1 */ 01304 #if defined(PWR_CR2_PVME2) 01305 if(__HAL_PWR_PVM2_EXTI_GET_FLAG() != RESET) 01306 { 01307 /* PWR PVM2 interrupt user callback */ 01308 HAL_PWREx_PVM2Callback(); 01309 01310 /* Clear PVM2 exti pending bit */ 01311 __HAL_PWR_PVM2_EXTI_CLEAR_FLAG(); 01312 } 01313 #endif /* PWR_CR2_PVME2 */ 01314 if(__HAL_PWR_PVM3_EXTI_GET_FLAG() != RESET) 01315 { 01316 /* PWR PVM3 interrupt user callback */ 01317 HAL_PWREx_PVM3Callback(); 01318 01319 /* Clear PVM3 exti pending bit */ 01320 __HAL_PWR_PVM3_EXTI_CLEAR_FLAG(); 01321 } 01322 if(__HAL_PWR_PVM4_EXTI_GET_FLAG() != RESET) 01323 { 01324 /* PWR PVM4 interrupt user callback */ 01325 HAL_PWREx_PVM4Callback(); 01326 01327 /* Clear PVM4 exti pending bit */ 01328 __HAL_PWR_PVM4_EXTI_CLEAR_FLAG(); 01329 } 01330 } 01331 01332 01333 #if defined(PWR_CR2_PVME1) 01334 /** 01335 * @brief PWR PVM1 interrupt callback 01336 * @retval None 01337 */ 01338 __weak void HAL_PWREx_PVM1Callback(void) 01339 { 01340 /* NOTE : This function should not be modified; when the callback is needed, 01341 HAL_PWREx_PVM1Callback() API can be implemented in the user file 01342 */ 01343 } 01344 #endif /* PWR_CR2_PVME1 */ 01345 01346 #if defined(PWR_CR2_PVME2) 01347 /** 01348 * @brief PWR PVM2 interrupt callback 01349 * @retval None 01350 */ 01351 __weak void HAL_PWREx_PVM2Callback(void) 01352 { 01353 /* NOTE : This function should not be modified; when the callback is needed, 01354 HAL_PWREx_PVM2Callback() API can be implemented in the user file 01355 */ 01356 } 01357 #endif /* PWR_CR2_PVME2 */ 01358 01359 /** 01360 * @brief PWR PVM3 interrupt callback 01361 * @retval None 01362 */ 01363 __weak void HAL_PWREx_PVM3Callback(void) 01364 { 01365 /* NOTE : This function should not be modified; when the callback is needed, 01366 HAL_PWREx_PVM3Callback() API can be implemented in the user file 01367 */ 01368 } 01369 01370 /** 01371 * @brief PWR PVM4 interrupt callback 01372 * @retval None 01373 */ 01374 __weak void HAL_PWREx_PVM4Callback(void) 01375 { 01376 /* NOTE : This function should not be modified; when the callback is needed, 01377 HAL_PWREx_PVM4Callback() API can be implemented in the user file 01378 */ 01379 } 01380 01381 01382 /** 01383 * @} 01384 */ 01385 01386 /** 01387 * @} 01388 */ 01389 01390 #endif /* HAL_PWR_MODULE_ENABLED */ 01391 /** 01392 * @} 01393 */ 01394 01395 /** 01396 * @} 01397 */ 01398 01399 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/