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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_ospi.h 00004 * @author MCD Application Team 00005 * @brief Header file of OSPI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef STM32L4xx_HAL_OSPI_H 00038 #define STM32L4xx_HAL_OSPI_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 #if defined(OCTOSPI) || defined(OCTOSPI1) || defined(OCTOSPI2) 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup OSPI 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup OSPI_Exported_Types OSPI Exported Types 00059 * @{ 00060 */ 00061 00062 /** 00063 * @brief OSPI Init structure definition 00064 */ 00065 typedef struct 00066 { 00067 uint32_t FifoThreshold; /* This is the threshold used byt the IP to generate the interrupt 00068 indicating that data are available in reception or free place 00069 is available in transmission. 00070 This parameter can be a value between 1 and 32 */ 00071 uint32_t DualQuad; /* It enables or not the dual-quad mode which allow to access up to 00072 quad mode on two different devices to increase the throughput. 00073 This parameter can be a value of @ref OSPI_DualQuad */ 00074 uint32_t MemoryType; /* It indicates the external device type connected to the OSPI. 00075 This parameter can be a value of @ref OSPI_MemoryType */ 00076 uint32_t DeviceSize; /* It defines the size of the external device connected to the OSPI, 00077 it corresponds to the number of address bits required to access 00078 the external device. 00079 This parameter can be a value between 1 and 32 */ 00080 uint32_t ChipSelectHighTime; /* It defines the minimun number of clocks which the chip select 00081 must remain high between commands. 00082 This parameter can be a value between 1 and 8 */ 00083 uint32_t FreeRunningClock; /* It enables or not the free running clock. 00084 This parameter can be a value of @ref OSPI_FreeRunningClock */ 00085 uint32_t ClockMode; /* It indicates the level of clock when the chip select is released. 00086 This parameter can be a value of @ref OSPI_ClockMode */ 00087 uint32_t WrapSize; /* It indicates the wrap-size corresponding the external device configuration. 00088 This parameter can be a value of @ref OSPI_WrapSize */ 00089 uint32_t ClockPrescaler; /* It specifies the prescaler factor used for generating 00090 the external clock based on the AHB clock. 00091 This parameter can be a value between 1 and 256 */ 00092 uint32_t SampleShifting; /* It allows to delay to 1/2 cycle the data sampling in order 00093 to take in account external signal delays. 00094 This parameter can be a value of @ref OSPI_SampleShifting */ 00095 uint32_t DelayHoldQuarterCycle; /* It allows to hold to 1/4 cycle the data. 00096 This parameter can be a value of @ref OSPI_DelayHoldQuarterCycle */ 00097 uint32_t ChipSelectBoundary; /* It enables the transaction boundary feature and 00098 defines the boundary of bytes to release the chip select. 00099 This parameter can be a value between 0 and 31 */ 00100 }OSPI_InitTypeDef; 00101 00102 /** 00103 * @brief HAL OSPI Handle Structure definition 00104 */ 00105 typedef struct __OSPI_HandleTypeDef 00106 { 00107 OCTOSPI_TypeDef *Instance; /* OSPI registers base address */ 00108 OSPI_InitTypeDef Init; /* OSPI initialization parameters */ 00109 uint8_t *pBuffPtr; /* Address of the OSPI buffer for transfer */ 00110 __IO uint32_t XferSize; /* Number of data to transfer */ 00111 __IO uint32_t XferCount; /* Counter of data transferred */ 00112 DMA_HandleTypeDef *hdma; /* Handle of the DMA channel used for the transfer */ 00113 __IO uint32_t State; /* Internal state of the OSPI HAL driver */ 00114 __IO uint32_t ErrorCode; /* Error code in case of HAL driver internal error */ 00115 uint32_t Timeout; /* Timeout used for the OSPI external device access */ 00116 #if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) 00117 void (* ErrorCallback) (struct __OSPI_HandleTypeDef *hospi); 00118 void (* AbortCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00119 void (* FifoThresholdCallback)(struct __OSPI_HandleTypeDef *hospi); 00120 void (* CmdCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00121 void (* RxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00122 void (* TxCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00123 void (* RxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00124 void (* TxHalfCpltCallback) (struct __OSPI_HandleTypeDef *hospi); 00125 void (* StatusMatchCallback) (struct __OSPI_HandleTypeDef *hospi); 00126 void (* TimeOutCallback) (struct __OSPI_HandleTypeDef *hospi); 00127 00128 void (* MspInitCallback) (struct __OSPI_HandleTypeDef *hospi); 00129 void (* MspDeInitCallback) (struct __OSPI_HandleTypeDef *hospi); 00130 #endif 00131 }OSPI_HandleTypeDef; 00132 00133 /** 00134 * @brief HAL OSPI Regular Command Structure definition 00135 */ 00136 typedef struct 00137 { 00138 uint32_t OperationType; /* It indicates if the configuration applies to the common regsiters or 00139 to the registers for the write operation (these registers are only 00140 used for memory-mapped mode). 00141 This parameter can be a value of @ref OSPI_OperationType */ 00142 uint32_t FlashId; /* It indicates which external device is selected for this command (it 00143 applies only if Dualquad is disabled in the initialization structure). 00144 This parameter can be a value of @ref OSPI_FlashId */ 00145 uint32_t Instruction; /* It contains the instruction to be sent to the device. 00146 This parameter can be a value between 0 and 0xFFFFFFFF */ 00147 uint32_t InstructionMode; /* It indicates the mode of the instruction. 00148 This parameter can be a value of @ref OSPI_InstructionMode */ 00149 uint32_t InstructionSize; /* It indicates the size of the instruction. 00150 This parameter can be a value of @ref OSPI_InstructionSize */ 00151 uint32_t InstructionDtrMode; /* It enables or not the DTR mode for the instruction phase. 00152 This parameter can be a value of @ref OSPI_InstructionDtrMode */ 00153 uint32_t Address; /* It contains the address to be sent to the device. 00154 This parameter can be a value between 0 and 0xFFFFFFFF */ 00155 uint32_t AddressMode; /* It indicates the mode of the address. 00156 This parameter can be a value of @ref OSPI_AddressMode */ 00157 uint32_t AddressSize; /* It indicates the size of the address. 00158 This parameter can be a value of @ref OSPI_AddressSize */ 00159 uint32_t AddressDtrMode; /* It enables or not the DTR mode for the address phase. 00160 This parameter can be a value of @ref OSPI_AddressDtrMode */ 00161 uint32_t AlternateBytes; /* It contains the alternate bytes to be sent to the device. 00162 This parameter can be a value between 0 and 0xFFFFFFFF */ 00163 uint32_t AlternateBytesMode; /* It indicates the mode of the alternate bytes. 00164 This parameter can be a value of @ref OSPI_AlternateBytesMode */ 00165 uint32_t AlternateBytesSize; /* It indicates the size of the alternate bytes. 00166 This parameter can be a value of @ref OSPI_AlternateBytesSize */ 00167 uint32_t AlternateBytesDtrMode; /* It enables or not the DTR mode for the alternate bytes phase. 00168 This parameter can be a value of @ref OSPI_AlternateBytesDtrMode */ 00169 uint32_t DataMode; /* It indicates the mode of the data. 00170 This parameter can be a value of @ref OSPI_DataMode */ 00171 uint32_t NbData; /* It indicates the number of data transferred with this command. 00172 This field is only used for indirect mode. 00173 This parameter can be a value between 1 and 0xFFFFFFFF */ 00174 uint32_t DataDtrMode; /* It enables or not the DTR mode for the data phase. 00175 This parameter can be a value of @ref OSPI_DataDtrMode */ 00176 uint32_t DummyCycles; /* It indicates the number of dummy cycles inserted before data phase. 00177 This parameter can be a value between 0 and 31 */ 00178 uint32_t DQSMode; /* It enables or not the data strobe management. 00179 This parameter can be a value of @ref OSPI_DQSMode */ 00180 uint32_t SIOOMode; /* It enables or not the SIOO mode. 00181 This parameter can be a value of @ref OSPI_SIOOMode */ 00182 }OSPI_RegularCmdTypeDef; 00183 00184 /** 00185 * @brief HAL OSPI Hyperbus Configuration Structure definition 00186 */ 00187 typedef struct 00188 { 00189 uint32_t RWRecoveryTime; /* It indicates the number of cycles for the device read write recovery time. 00190 This parameter can be a value between 0 and 255 */ 00191 uint32_t AccessTime; /* It indicates the number of cycles for the device acces time. 00192 This parameter can be a value between 0 and 255 */ 00193 uint32_t WriteZeroLatency; /* It enables or not the latency for the write access. 00194 This parameter can be a value of @ref OSPI_WriteZeroLatency */ 00195 uint32_t LatencyMode; /* It configures the latency mode. 00196 This parameter can be a value of @ref OSPI_LatencyMode */ 00197 }OSPI_HyperbusCfgTypeDef; 00198 00199 /** 00200 * @brief HAL OSPI Hyperbus Command Structure definition 00201 */ 00202 typedef struct 00203 { 00204 uint32_t AddressSpace; /* It indicates the address space accessed by the command. 00205 This parameter can be a value of @ref OSPI_AddressSpace */ 00206 uint32_t Address; /* It contains the address to be sent tot he device. 00207 This parameter can be a value between 0 and 0xFFFFFFFF */ 00208 uint32_t AddressSize; /* It indicates the size of the address. 00209 This parameter can be a value of @ref OSPI_AddressSize */ 00210 uint32_t NbData; /* It indicates the number of data transferred with this command. 00211 This field is only used for indirect mode. 00212 This parameter can be a value between 1 and 0xFFFFFFFF 00213 In case of autopolling mode, this parameter can be any value between 1 and 4 */ 00214 uint32_t DQSMode; /* It enables or not the data strobe management. 00215 This parameter can be a value of @ref OSPI_DQSMode */ 00216 }OSPI_HyperbusCmdTypeDef; 00217 00218 /** 00219 * @brief HAL OSPI Auto Polling mode configuration structure definition 00220 */ 00221 typedef struct 00222 { 00223 uint32_t Match; /* Specifies the value to be compared with the masked status register to get a match. 00224 This parameter can be any value between 0 and 0xFFFFFFFF */ 00225 uint32_t Mask; /* Specifies the mask to be applied to the status bytes received. 00226 This parameter can be any value between 0 and 0xFFFFFFFF */ 00227 uint32_t MatchMode; /* Specifies the method used for determining a match. 00228 This parameter can be a value of @ref OSPI_MatchMode */ 00229 uint32_t AutomaticStop; /* Specifies if automatic polling is stopped after a match. 00230 This parameter can be a value of @ref OSPI_AutomaticStop */ 00231 uint32_t Interval; /* Specifies the number of clock cycles between two read during automatic polling phases. 00232 This parameter can be any value between 0 and 0xFFFF */ 00233 }OSPI_AutoPollingTypeDef; 00234 00235 /** 00236 * @brief HAL OSPI Memory Mapped mode configuration structure definition 00237 */ 00238 typedef struct 00239 { 00240 uint32_t TimeOutActivation; /* Specifies if the timeout counter is enabled to release the chip select. 00241 This parameter can be a value of @ref OSPI_TimeOutActivation */ 00242 uint32_t TimeOutPeriod; /* Specifies the number of clock to wait when the FIFO is full before to release the chip select. 00243 This parameter can be any value between 0 and 0xFFFF */ 00244 }OSPI_MemoryMappedTypeDef; 00245 00246 /** 00247 * @brief HAL OSPI IO Manager Configuration structure definition 00248 */ 00249 typedef struct 00250 { 00251 uint32_t ClkPort; /* It indicates which port of the OSPI IO Manager is used for the CLK pins. 00252 This parameter can be a value between 1 and 8 */ 00253 uint32_t DQSPort; /* It indicates which port of the OSPI IO Manager is used for the DQS pin. 00254 This parameter can be a value between 1 and 8 */ 00255 uint32_t NCSPort; /* It indicates which port of the OSPI IO Manager is used for the NCS pin. 00256 This parameter can be a value between 1 and 8 */ 00257 uint32_t IOLowPort; /* It indicates which port of the OSPI IO Manager is used for the IO[3:0] pins. 00258 This parameter can be a value of @ref OSPIM_IOPort */ 00259 uint32_t IOHighPort; /* It indicates which port of the OSPI IO Manager is used for the IO[7:4] pins. 00260 This parameter can be a value of @ref OSPIM_IOPort */ 00261 }OSPIM_CfgTypeDef; 00262 00263 #if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) 00264 /** 00265 * @brief HAL OSPI Callback ID enumeration definition 00266 */ 00267 typedef enum 00268 { 00269 HAL_OSPI_ERROR_CB_ID = 0x00U, /*!< OSPI Error Callback ID */ 00270 HAL_OSPI_ABORT_CB_ID = 0x01U, /*!< OSPI Abort Callback ID */ 00271 HAL_OSPI_FIFO_THRESHOLD_CB_ID = 0x02U, /*!< OSPI FIFO Threshold Callback ID */ 00272 HAL_OSPI_CMD_CPLT_CB_ID = 0x03U, /*!< OSPI Command Complete Callback ID */ 00273 HAL_OSPI_RX_CPLT_CB_ID = 0x04U, /*!< OSPI Rx Complete Callback ID */ 00274 HAL_OSPI_TX_CPLT_CB_ID = 0x05U, /*!< OSPI Tx Complete Callback ID */ 00275 HAL_OSPI_RX_HALF_CPLT_CB_ID = 0x06U, /*!< OSPI Rx Half Complete Callback ID */ 00276 HAL_OSPI_TX_HALF_CPLT_CB_ID = 0x07U, /*!< OSPI Tx Half Complete Callback ID */ 00277 HAL_OSPI_STATUS_MATCH_CB_ID = 0x08U, /*!< OSPI Status Match Callback ID */ 00278 HAL_OSPI_TIMEOUT_CB_ID = 0x09U, /*!< OSPI Timeout Callback ID */ 00279 00280 HAL_OSPI_MSP_INIT_CB_ID = 0x0AU, /*!< OSPI MspInit Callback ID */ 00281 HAL_OSPI_MSP_DEINIT_CB_ID = 0x0BU /*!< OSPI MspDeInit Callback ID */ 00282 }HAL_OSPI_CallbackIDTypeDef; 00283 00284 /** 00285 * @brief HAL OSPI Callback pointer definition 00286 */ 00287 typedef void (*pOSPI_CallbackTypeDef)(OSPI_HandleTypeDef *hospi); 00288 #endif 00289 /** 00290 * @} 00291 */ 00292 00293 /* Exported constants --------------------------------------------------------*/ 00294 /** @defgroup OSPI_Exported_Constants OSPI Exported Constants 00295 * @{ 00296 */ 00297 00298 /** @defgroup OSPI_State OSPI State 00299 * @{ 00300 */ 00301 #define HAL_OSPI_STATE_RESET ((uint32_t)0x00000000U) /*!< Initial state */ 00302 #define HAL_OSPI_STATE_HYPERBUS_INIT ((uint32_t)0x00000001U) /*!< Initialization done in hyperbus mode but timing configuration not done */ 00303 #define HAL_OSPI_STATE_READY ((uint32_t)0x00000002U) /*!< Driver ready to be used */ 00304 #define HAL_OSPI_STATE_CMD_CFG ((uint32_t)0x00000004U) /*!< Command (regular or hyperbus) configured, ready for an action */ 00305 #define HAL_OSPI_STATE_READ_CMD_CFG ((uint32_t)0x00000014U) /*!< Read command configuration done, not the write command configuration */ 00306 #define HAL_OSPI_STATE_WRITE_CMD_CFG ((uint32_t)0x00000024U) /*!< Write command configuration done, not the read command configuration */ 00307 #define HAL_OSPI_STATE_BUSY_CMD ((uint32_t)0x00000008U) /*!< Command without data on-going */ 00308 #define HAL_OSPI_STATE_BUSY_TX ((uint32_t)0x00000018U) /*!< Indirect Tx on-going */ 00309 #define HAL_OSPI_STATE_BUSY_RX ((uint32_t)0x00000028U) /*!< Indirect Rx on-going */ 00310 #define HAL_OSPI_STATE_BUSY_AUTO_POLLING ((uint32_t)0x00000048U) /*!< Auto-polling on-going */ 00311 #define HAL_OSPI_STATE_BUSY_MEM_MAPPED ((uint32_t)0x00000088U) /*!< Memory-mapped on-going */ 00312 #define HAL_OSPI_STATE_ABORT ((uint32_t)0x00000100U) /*!< Abort on-going */ 00313 #define HAL_OSPI_STATE_ERROR ((uint32_t)0x00000200U) /*!< Blocking error, driver should be re-initialized */ 00314 /** 00315 * @} 00316 */ 00317 00318 /** @defgroup OSPI_ErrorCode OSPI Error Code 00319 * @{ 00320 */ 00321 #define HAL_OSPI_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ 00322 #define HAL_OSPI_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */ 00323 #define HAL_OSPI_ERROR_TRANSFER ((uint32_t)0x00000002U) /*!< Transfer error */ 00324 #define HAL_OSPI_ERROR_DMA ((uint32_t)0x00000004U) /*!< DMA transfer error */ 00325 #define HAL_OSPI_ERROR_INVALID_PARAM ((uint32_t)0x00000008U) /*!< Invalid parameters error */ 00326 #define HAL_OSPI_ERROR_INVALID_SEQUENCE ((uint32_t)0x00000010U) /*!< Sequence of the state machine is incorrect */ 00327 #if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) 00328 #define HAL_OSPI_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid callback error */ 00329 #endif 00330 /** 00331 * @} 00332 */ 00333 00334 /** @defgroup OSPI_DualQuad OSPI Dual-Quad 00335 * @{ 00336 */ 00337 #define HAL_OSPI_DUALQUAD_DISABLE ((uint32_t)0x00000000U) /*!< Dual-Quad mode disabled */ 00338 #define HAL_OSPI_DUALQUAD_ENABLE ((uint32_t)OCTOSPI_CR_DQM) /*!< Dual-Quad mode enabled */ 00339 /** 00340 * @} 00341 */ 00342 00343 /** @defgroup OSPI_MemoryType OSPI Memory Type 00344 * @{ 00345 */ 00346 #define HAL_OSPI_MEMTYPE_MICRON ((uint32_t)0x00000000U) /*!< Micron mode */ 00347 #define HAL_OSPI_MEMTYPE_MACRONIX ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< Macronix mode */ 00348 #define HAL_OSPI_MEMTYPE_MACRONIX_RAM ((uint32_t)(OCTOSPI_DCR1_MTYP_1 | OCTOSPI_DCR1_MTYP_0)) /*!< Macronix RAM mode */ 00349 #define HAL_OSPI_MEMTYPE_HYPERBUS ((uint32_t)OCTOSPI_DCR1_MTYP_2) /*!< Hyperbus mode */ 00350 /** 00351 * @} 00352 */ 00353 00354 /** @defgroup OSPI_FreeRunningClock OSPI Free Running Clock 00355 * @{ 00356 */ 00357 #define HAL_OSPI_FREERUNCLK_DISABLE ((uint32_t)0x00000000U) /*!< CLK is not free running */ 00358 #define HAL_OSPI_FREERUNCLK_ENABLE ((uint32_t)OCTOSPI_DCR1_FRCK) /*!< CLK is free running (always provided) */ 00359 /** 00360 * @} 00361 */ 00362 00363 /** @defgroup OSPI_ClockMode OSPI Clock Mode 00364 * @{ 00365 */ 00366 #define HAL_OSPI_CLOCK_MODE_0 ((uint32_t)0x00000000U) /*!< CLK must stay low while nCS is high */ 00367 #define HAL_OSPI_CLOCK_MODE_3 ((uint32_t)OCTOSPI_DCR1_CKMODE) /*!< CLK must stay high while nCS is high */ 00368 /** 00369 * @} 00370 */ 00371 00372 /** @defgroup OSPI_WrapSize OSPI Wrap-Size 00373 * @{ 00374 */ 00375 #define HAL_OSPI_WRAP_NOT_SUPPORTED ((uint32_t)0x00000000U) /*!< wrapped reads are not supported by the memory */ 00376 #define HAL_OSPI_WRAP_16_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_1) /*!< external memory supports wrap size of 16 bytes */ 00377 #define HAL_OSPI_WRAP_32_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_1)) /*!< external memory supports wrap size of 32 bytes */ 00378 #define HAL_OSPI_WRAP_64_BYTES ((uint32_t)OCTOSPI_DCR2_WRAPSIZE_2) /*!< external memory supports wrap size of 64 bytes */ 00379 #define HAL_OSPI_WRAP_128_BYTES ((uint32_t)(OCTOSPI_DCR2_WRAPSIZE_0 | OCTOSPI_DCR2_WRAPSIZE_2)) /*!< external memory supports wrap size of 128 bytes */ 00380 /** 00381 * @} 00382 */ 00383 00384 /** @defgroup OSPI_SampleShifting OSPI Sample Shifting 00385 * @{ 00386 */ 00387 #define HAL_OSPI_SAMPLE_SHIFTING_NONE ((uint32_t)0x00000000U) /*!< No shift */ 00388 #define HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE ((uint32_t)OCTOSPI_TCR_SSHIFT) /*!< 1/2 cycle shift */ 00389 /** 00390 * @} 00391 */ 00392 00393 /** @defgroup OSPI_DelayHoldQuarterCycle OSPI Delay Hold Quarter Cycle 00394 * @{ 00395 */ 00396 #define HAL_OSPI_DHQC_DISABLE ((uint32_t)0x00000000U) /*!< No Delay */ 00397 #define HAL_OSPI_DHQC_ENABLE ((uint32_t)OCTOSPI_TCR_DHQC) /*!< Delay Hold 1/4 cycle */ 00398 /** 00399 * @} 00400 */ 00401 00402 /** @defgroup OSPI_OperationType OSPI Operation Type 00403 * @{ 00404 */ 00405 #define HAL_OSPI_OPTYPE_COMMON_CFG ((uint32_t)0x00000000U) /*!< Common configuration (indirect or auto-polling mode) */ 00406 #define HAL_OSPI_OPTYPE_READ_CFG ((uint32_t)0x00000001U) /*!< Read configuration (memory-mapped mode) */ 00407 #define HAL_OSPI_OPTYPE_WRITE_CFG ((uint32_t)0x00000002U) /*!< Write configuration (memory-mapped mode) */ 00408 /** 00409 * @} 00410 */ 00411 00412 /** @defgroup OSPI_FlashID OSPI Flash Id 00413 * @{ 00414 */ 00415 #define HAL_OSPI_FLASH_ID_1 ((uint32_t)0x00000000U) /*!< FLASH 1 selected */ 00416 #define HAL_OSPI_FLASH_ID_2 ((uint32_t)OCTOSPI_CR_FSEL) /*!< FLASH 2 selected */ 00417 /** 00418 * @} 00419 */ 00420 00421 /** @defgroup OSPI_InstructionMode OSPI Instruction Mode 00422 * @{ 00423 */ 00424 #define HAL_OSPI_INSTRUCTION_NONE ((uint32_t)0x00000000U) /*!< No instruction */ 00425 #define HAL_OSPI_INSTRUCTION_1_LINE ((uint32_t)OCTOSPI_CCR_IMODE_0) /*!< Instruction on a single line */ 00426 #define HAL_OSPI_INSTRUCTION_2_LINES ((uint32_t)OCTOSPI_CCR_IMODE_1) /*!< Instruction on two lines */ 00427 #define HAL_OSPI_INSTRUCTION_4_LINES ((uint32_t)(OCTOSPI_CCR_IMODE_0 | OCTOSPI_CCR_IMODE_1)) /*!< Instruction on four lines */ 00428 #define HAL_OSPI_INSTRUCTION_8_LINES ((uint32_t)OCTOSPI_CCR_IMODE_2) /*!< Instruction on eight lines */ 00429 /** 00430 * @} 00431 */ 00432 00433 /** @defgroup OSPI_InstructionSize OSPI Instruction Size 00434 * @{ 00435 */ 00436 #define HAL_OSPI_INSTRUCTION_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit instruction */ 00437 #define HAL_OSPI_INSTRUCTION_16_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_0) /*!< 16-bit instruction */ 00438 #define HAL_OSPI_INSTRUCTION_24_BITS ((uint32_t)OCTOSPI_CCR_ISIZE_1) /*!< 24-bit instruction */ 00439 #define HAL_OSPI_INSTRUCTION_32_BITS ((uint32_t)OCTOSPI_CCR_ISIZE) /*!< 32-bit instruction */ 00440 /** 00441 * @} 00442 */ 00443 00444 /** @defgroup OSPI_InstructionDtrMode OSPI Instruction DTR Mode 00445 * @{ 00446 */ 00447 #define HAL_OSPI_INSTRUCTION_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for instruction phase */ 00448 #define HAL_OSPI_INSTRUCTION_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_IDTR) /*!< DTR mode enabled for instruction phase */ 00449 /** 00450 * @} 00451 */ 00452 00453 /** @defgroup OSPI_AddressMode OSPI Address Mode 00454 * @{ 00455 */ 00456 #define HAL_OSPI_ADDRESS_NONE ((uint32_t)0x00000000U) /*!< No address */ 00457 #define HAL_OSPI_ADDRESS_1_LINE ((uint32_t)OCTOSPI_CCR_ADMODE_0) /*!< Address on a single line */ 00458 #define HAL_OSPI_ADDRESS_2_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_1) /*!< Address on two lines */ 00459 #define HAL_OSPI_ADDRESS_4_LINES ((uint32_t)(OCTOSPI_CCR_ADMODE_0 | OCTOSPI_CCR_ADMODE_1)) /*!< Address on four lines */ 00460 #define HAL_OSPI_ADDRESS_8_LINES ((uint32_t)OCTOSPI_CCR_ADMODE_2) /*!< Address on eight lines */ 00461 /** 00462 * @} 00463 */ 00464 00465 /** @defgroup OSPI_AddressSize OSPI Address Size 00466 * @{ 00467 */ 00468 #define HAL_OSPI_ADDRESS_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit address */ 00469 #define HAL_OSPI_ADDRESS_16_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_0) /*!< 16-bit address */ 00470 #define HAL_OSPI_ADDRESS_24_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE_1) /*!< 24-bit address */ 00471 #define HAL_OSPI_ADDRESS_32_BITS ((uint32_t)OCTOSPI_CCR_ADSIZE) /*!< 32-bit address */ 00472 /** 00473 * @} 00474 */ 00475 00476 /** @defgroup OSPI_AddressDtrMode OSPI Address DTR Mode 00477 * @{ 00478 */ 00479 #define HAL_OSPI_ADDRESS_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for address phase */ 00480 #define HAL_OSPI_ADDRESS_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ADDTR) /*!< DTR mode enabled for address phase */ 00481 /** 00482 * @} 00483 */ 00484 00485 /** @defgroup OSPI_AlternateBytesMode OSPI Alternate Bytes Mode 00486 * @{ 00487 */ 00488 #define HAL_OSPI_ALTERNATE_BYTES_NONE ((uint32_t)0x00000000U) /*!< No alternate bytes */ 00489 #define HAL_OSPI_ALTERNATE_BYTES_1_LINE ((uint32_t)OCTOSPI_CCR_ABMODE_0) /*!< Alternate bytes on a single line */ 00490 #define HAL_OSPI_ALTERNATE_BYTES_2_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_1) /*!< Alternate bytes on two lines */ 00491 #define HAL_OSPI_ALTERNATE_BYTES_4_LINES ((uint32_t)(OCTOSPI_CCR_ABMODE_0 | OCTOSPI_CCR_ABMODE_1)) /*!< Alternate bytes on four lines */ 00492 #define HAL_OSPI_ALTERNATE_BYTES_8_LINES ((uint32_t)OCTOSPI_CCR_ABMODE_2) /*!< Alternate bytes on eight lines */ 00493 /** 00494 * @} 00495 */ 00496 00497 /** @defgroup OSPI_AlternateBytesSize OSPI Alternate Bytes Size 00498 * @{ 00499 */ 00500 #define HAL_OSPI_ALTERNATE_BYTES_8_BITS ((uint32_t)0x00000000U) /*!< 8-bit alternate bytes */ 00501 #define HAL_OSPI_ALTERNATE_BYTES_16_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_0) /*!< 16-bit alternate bytes */ 00502 #define HAL_OSPI_ALTERNATE_BYTES_24_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE_1) /*!< 24-bit alternate bytes */ 00503 #define HAL_OSPI_ALTERNATE_BYTES_32_BITS ((uint32_t)OCTOSPI_CCR_ABSIZE) /*!< 32-bit alternate bytes */ 00504 /** 00505 * @} 00506 */ 00507 00508 /** @defgroup OSPI_AlternateBytesDtrMode OSPI Alternate Bytes DTR Mode 00509 * @{ 00510 */ 00511 #define HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for alternate bytes phase */ 00512 #define HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_ABDTR) /*!< DTR mode enabled for alternate bytes phase */ 00513 /** 00514 * @} 00515 */ 00516 00517 /** @defgroup OSPI_DataMode OSPI Data Mode 00518 * @{ 00519 */ 00520 #define HAL_OSPI_DATA_NONE ((uint32_t)0x00000000U) /*!< No data */ 00521 #define HAL_OSPI_DATA_1_LINE ((uint32_t)OCTOSPI_CCR_DMODE_0) /*!< Data on a single line */ 00522 #define HAL_OSPI_DATA_2_LINES ((uint32_t)OCTOSPI_CCR_DMODE_1) /*!< Data on two lines */ 00523 #define HAL_OSPI_DATA_4_LINES ((uint32_t)(OCTOSPI_CCR_DMODE_0 | OCTOSPI_CCR_DMODE_1)) /*!< Data on four lines */ 00524 #define HAL_OSPI_DATA_8_LINES ((uint32_t)OCTOSPI_CCR_DMODE_2) /*!< Data on eight lines */ 00525 /** 00526 * @} 00527 */ 00528 00529 /** @defgroup OSPI_DataDtrMode OSPI Data DTR Mode 00530 * @{ 00531 */ 00532 #define HAL_OSPI_DATA_DTR_DISABLE ((uint32_t)0x00000000U) /*!< DTR mode disabled for data phase */ 00533 #define HAL_OSPI_DATA_DTR_ENABLE ((uint32_t)OCTOSPI_CCR_DDTR) /*!< DTR mode enabled for data phase */ 00534 /** 00535 * @} 00536 */ 00537 00538 /** @defgroup OSPI_DQSMode OSPI DQS Mode 00539 * @{ 00540 */ 00541 #define HAL_OSPI_DQS_DISABLE ((uint32_t)0x00000000U) /*!< DQS disabled */ 00542 #define HAL_OSPI_DQS_ENABLE ((uint32_t)OCTOSPI_CCR_DQSE) /*!< DQS enabled */ 00543 /** 00544 * @} 00545 */ 00546 00547 /** @defgroup OSPI_SIOOMode OSPI SIOO Mode 00548 * @{ 00549 */ 00550 #define HAL_OSPI_SIOO_INST_EVERY_CMD ((uint32_t)0x00000000U) /*!< Send instruction on every transaction */ 00551 #define HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD ((uint32_t)OCTOSPI_CCR_SIOO) /*!< Send instruction only for the first command */ 00552 /** 00553 * @} 00554 */ 00555 00556 /** @defgroup OSPI_WriteZeroLatency OSPI Hyperbus Write Zero Latency Activation 00557 * @{ 00558 */ 00559 #define HAL_OSPI_LATENCY_ON_WRITE ((uint32_t)0x00000000U) /*!< Latency on write accesses */ 00560 #define HAL_OSPI_NO_LATENCY_ON_WRITE ((uint32_t)OCTOSPI_HLCR_WZL) /*!< No latency on write accesses */ 00561 /** 00562 * @} 00563 */ 00564 00565 /** @defgroup OSPI_LatencyMode OSPI Hyperbus Latency Mode 00566 * @{ 00567 */ 00568 #define HAL_OSPI_VARIABLE_LATENCY ((uint32_t)0x00000000U) /*!< Variable initial latency */ 00569 #define HAL_OSPI_FIXED_LATENCY ((uint32_t)OCTOSPI_HLCR_LM) /*!< Fixed latency */ 00570 /** 00571 * @} 00572 */ 00573 00574 /** @defgroup OSPI_AddressSpace OSPI Hyperbus Address Space 00575 * @{ 00576 */ 00577 #define HAL_OSPI_MEMORY_ADDRESS_SPACE ((uint32_t)0x00000000U) /*!< HyperBus memory mode */ 00578 #define HAL_OSPI_REGISTER_ADDRESS_SPACE ((uint32_t)OCTOSPI_DCR1_MTYP_0) /*!< HyperBus register mode */ 00579 /** 00580 * @} 00581 */ 00582 00583 /** @defgroup OSPI_MatchMode OSPI Match Mode 00584 * @{ 00585 */ 00586 #define HAL_OSPI_MATCH_MODE_AND ((uint32_t)0x00000000U) /*!< AND match mode between unmasked bits */ 00587 #define HAL_OSPI_MATCH_MODE_OR ((uint32_t)OCTOSPI_CR_PMM) /*!< OR match mode between unmasked bits */ 00588 /** 00589 * @} 00590 */ 00591 00592 /** @defgroup OSPI_AutomaticStop OSPI Automatic Stop 00593 * @{ 00594 */ 00595 #define HAL_OSPI_AUTOMATIC_STOP_DISABLE ((uint32_t)0x00000000U) /*!< AutoPolling stops only with abort or OSPI disabling */ 00596 #define HAL_OSPI_AUTOMATIC_STOP_ENABLE ((uint32_t)OCTOSPI_CR_APMS) /*!< AutoPolling stops as soon as there is a match */ 00597 /** 00598 * @} 00599 */ 00600 00601 /** @defgroup OSPI_TimeOutActivation OSPI Timeout Activation 00602 * @{ 00603 */ 00604 #define HAL_OSPI_TIMEOUT_COUNTER_DISABLE ((uint32_t)0x00000000U) /*!< Timeout counter disabled, nCS remains active */ 00605 #define HAL_OSPI_TIMEOUT_COUNTER_ENABLE ((uint32_t)OCTOSPI_CR_TCEN) /*!< Timeout counter enabled, nCS released when timeout expires */ 00606 /** 00607 * @} 00608 */ 00609 00610 /** @defgroup OSPI_Flags OSPI Flags 00611 * @{ 00612 */ 00613 #define HAL_OSPI_FLAG_BUSY OCTOSPI_SR_BUSY /*!< Busy flag: operation is ongoing */ 00614 #define HAL_OSPI_FLAG_TO OCTOSPI_SR_TOF /*!< Timeout flag: timeout occurs in memory-mapped mode */ 00615 #define HAL_OSPI_FLAG_SM OCTOSPI_SR_SMF /*!< Status match flag: received data matches in autopolling mode */ 00616 #define HAL_OSPI_FLAG_FT OCTOSPI_SR_FTF /*!< Fifo threshold flag: Fifo threshold reached or data left after read from memory is complete */ 00617 #define HAL_OSPI_FLAG_TC OCTOSPI_SR_TCF /*!< Transfer complete flag: programmed number of data have been transferred or the transfer has been aborted */ 00618 #define HAL_OSPI_FLAG_TE OCTOSPI_SR_TEF /*!< Transfer error flag: invalid address is being accessed */ 00619 /** 00620 * @} 00621 */ 00622 00623 /** @defgroup OSPI_Interrupts OSPI Interrupts 00624 * @{ 00625 */ 00626 #define HAL_OSPI_IT_TO OCTOSPI_CR_TOIE /*!< Interrupt on the timeout flag */ 00627 #define HAL_OSPI_IT_SM OCTOSPI_CR_SMIE /*!< Interrupt on the status match flag */ 00628 #define HAL_OSPI_IT_FT OCTOSPI_CR_FTIE /*!< Interrupt on the fifo threshold flag */ 00629 #define HAL_OSPI_IT_TC OCTOSPI_CR_TCIE /*!< Interrupt on the transfer complete flag */ 00630 #define HAL_OSPI_IT_TE OCTOSPI_CR_TEIE /*!< Interrupt on the transfer error flag */ 00631 /** 00632 * @} 00633 */ 00634 00635 /** @defgroup OSPI_Timeout_definition OSPI Timeout definition 00636 * @{ 00637 */ 00638 #define HAL_OSPI_TIMEOUT_DEFAULT_VALUE ((uint32_t)5000U) /* 5 s */ 00639 /** 00640 * @} 00641 */ 00642 00643 /** @defgroup OSPIM_IOPort OSPI IO Manager IO Port 00644 * @{ 00645 */ 00646 #define HAL_OSPIM_IOPORT_1_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x1)) /*!< Port 1 - IO[3:0] */ 00647 #define HAL_OSPIM_IOPORT_1_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x1)) /*!< Port 1 - IO[7:4] */ 00648 #define HAL_OSPIM_IOPORT_2_LOW ((uint32_t)(OCTOSPIM_PCR_IOLEN | 0x2)) /*!< Port 2 - IO[3:0] */ 00649 #define HAL_OSPIM_IOPORT_2_HIGH ((uint32_t)(OCTOSPIM_PCR_IOHEN | 0x2)) /*!< Port 2 - IO[7:4] */ 00650 /** 00651 * @} 00652 */ 00653 /** 00654 * @} 00655 */ 00656 00657 /* Exported macros -----------------------------------------------------------*/ 00658 /** @defgroup OSPI_Exported_Macros OSPI Exported Macros 00659 * @{ 00660 */ 00661 /** @brief Reset OSPI handle state. 00662 * @param __HANDLE__: OSPI handle. 00663 * @retval None 00664 */ 00665 #if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) 00666 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) do { \ 00667 (__HANDLE__)->State = HAL_OSPI_STATE_RESET; \ 00668 (__HANDLE__)->MspInitCallback = NULL; \ 00669 (__HANDLE__)->MspDeInitCallback = NULL; \ 00670 } while(0) 00671 #else 00672 #define __HAL_OSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OSPI_STATE_RESET) 00673 #endif 00674 00675 /** @brief Enable the OSPI peripheral. 00676 * @param __HANDLE__: specifies the OSPI Handle. 00677 * @retval None 00678 */ 00679 #define __HAL_OSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 00680 00681 /** @brief Disable the OSPI peripheral. 00682 * @param __HANDLE__: specifies the OSPI Handle. 00683 * @retval None 00684 */ 00685 #define __HAL_OSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, OCTOSPI_CR_EN) 00686 00687 /** @brief Enable the specified OSPI interrupt. 00688 * @param __HANDLE__: specifies the OSPI Handle. 00689 * @param __INTERRUPT__: specifies the OSPI interrupt source to enable. 00690 * This parameter can be one of the following values: 00691 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 00692 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 00693 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 00694 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 00695 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 00696 * @retval None 00697 */ 00698 #define __HAL_OSPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) SET_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00699 00700 00701 /** @brief Disable the specified OSPI interrupt. 00702 * @param __HANDLE__: specifies the OSPI Handle. 00703 * @param __INTERRUPT__: specifies the OSPI interrupt source to disable. 00704 * This parameter can be one of the following values: 00705 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 00706 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 00707 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 00708 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 00709 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 00710 * @retval None 00711 */ 00712 #define __HAL_OSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) 00713 00714 /** @brief Check whether the specified OSPI interrupt source is enabled or not. 00715 * @param __HANDLE__: specifies the OSPI Handle. 00716 * @param __INTERRUPT__: specifies the OSPI interrupt source to check. 00717 * This parameter can be one of the following values: 00718 * @arg HAL_OSPI_IT_TO: OSPI Timeout interrupt 00719 * @arg HAL_OSPI_IT_SM: OSPI Status match interrupt 00720 * @arg HAL_OSPI_IT_FT: OSPI FIFO threshold interrupt 00721 * @arg HAL_OSPI_IT_TC: OSPI Transfer complete interrupt 00722 * @arg HAL_OSPI_IT_TE: OSPI Transfer error interrupt 00723 * @retval The new state of __INTERRUPT__ (TRUE or FALSE). 00724 */ 00725 #define __HAL_OSPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (READ_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) == (__INTERRUPT__)) 00726 00727 /** 00728 * @brief Check whether the selected OSPI flag is set or not. 00729 * @param __HANDLE__: specifies the OSPI Handle. 00730 * @param __FLAG__: specifies the OSPI flag to check. 00731 * This parameter can be one of the following values: 00732 * @arg HAL_OSPI_FLAG_BUSY: OSPI Busy flag 00733 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 00734 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 00735 * @arg HAL_OSPI_FLAG_FT: OSPI FIFO threshold flag 00736 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 00737 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 00738 * @retval None 00739 */ 00740 #define __HAL_OSPI_GET_FLAG(__HANDLE__, __FLAG__) ((READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) ? SET : RESET) 00741 00742 /** @brief Clears the specified OSPI's flag status. 00743 * @param __HANDLE__: specifies the OSPI Handle. 00744 * @param __FLAG__: specifies the OSPI clear register flag that needs to be set 00745 * This parameter can be one of the following values: 00746 * @arg HAL_OSPI_FLAG_TO: OSPI Timeout flag 00747 * @arg HAL_OSPI_FLAG_SM: OSPI Status match flag 00748 * @arg HAL_OSPI_FLAG_TC: OSPI Transfer complete flag 00749 * @arg HAL_OSPI_FLAG_TE: OSPI Transfer error flag 00750 * @retval None 00751 */ 00752 #define __HAL_OSPI_CLEAR_FLAG(__HANDLE__, __FLAG__) WRITE_REG((__HANDLE__)->Instance->FCR, (__FLAG__)) 00753 00754 /** 00755 * @} 00756 */ 00757 00758 /* Exported functions --------------------------------------------------------*/ 00759 /** @addtogroup OSPI_Exported_Functions 00760 * @{ 00761 */ 00762 00763 /* Initialization/de-initialization functions ********************************/ 00764 /** @addtogroup OSPI_Exported_Functions_Group1 00765 * @{ 00766 */ 00767 HAL_StatusTypeDef HAL_OSPI_Init (OSPI_HandleTypeDef *hospi); 00768 void HAL_OSPI_MspInit (OSPI_HandleTypeDef *hospi); 00769 HAL_StatusTypeDef HAL_OSPI_DeInit (OSPI_HandleTypeDef *hospi); 00770 void HAL_OSPI_MspDeInit (OSPI_HandleTypeDef *hospi); 00771 00772 /** 00773 * @} 00774 */ 00775 00776 /* IO operation functions *****************************************************/ 00777 /** @addtogroup OSPI_Exported_Functions_Group2 00778 * @{ 00779 */ 00780 /* OSPI IRQ handler function */ 00781 void HAL_OSPI_IRQHandler (OSPI_HandleTypeDef *hospi); 00782 00783 /* OSPI command configuration functions */ 00784 HAL_StatusTypeDef HAL_OSPI_Command (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd, uint32_t Timeout); 00785 HAL_StatusTypeDef HAL_OSPI_Command_IT (OSPI_HandleTypeDef *hospi, OSPI_RegularCmdTypeDef *cmd); 00786 HAL_StatusTypeDef HAL_OSPI_HyperbusCfg (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCfgTypeDef *cfg, uint32_t Timeout); 00787 HAL_StatusTypeDef HAL_OSPI_HyperbusCmd (OSPI_HandleTypeDef *hospi, OSPI_HyperbusCmdTypeDef *cmd, uint32_t Timeout); 00788 00789 /* OSPI indirect mode functions */ 00790 HAL_StatusTypeDef HAL_OSPI_Transmit (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 00791 HAL_StatusTypeDef HAL_OSPI_Receive (OSPI_HandleTypeDef *hospi, uint8_t *pData, uint32_t Timeout); 00792 HAL_StatusTypeDef HAL_OSPI_Transmit_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); 00793 HAL_StatusTypeDef HAL_OSPI_Receive_IT (OSPI_HandleTypeDef *hospi, uint8_t *pData); 00794 HAL_StatusTypeDef HAL_OSPI_Transmit_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); 00795 HAL_StatusTypeDef HAL_OSPI_Receive_DMA (OSPI_HandleTypeDef *hospi, uint8_t *pData); 00796 00797 /* OSPI status flag polling mode functions */ 00798 HAL_StatusTypeDef HAL_OSPI_AutoPolling (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg, uint32_t Timeout); 00799 HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT (OSPI_HandleTypeDef *hospi, OSPI_AutoPollingTypeDef *cfg); 00800 00801 /* OSPI memory-mapped mode functions */ 00802 HAL_StatusTypeDef HAL_OSPI_MemoryMapped (OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); 00803 00804 /* Callback functions in non-blocking modes ***********************************/ 00805 void HAL_OSPI_ErrorCallback (OSPI_HandleTypeDef *hospi); 00806 void HAL_OSPI_AbortCpltCallback (OSPI_HandleTypeDef *hospi); 00807 void HAL_OSPI_FifoThresholdCallback(OSPI_HandleTypeDef *hospi); 00808 00809 /* OSPI indirect mode functions */ 00810 void HAL_OSPI_CmdCpltCallback (OSPI_HandleTypeDef *hospi); 00811 void HAL_OSPI_RxCpltCallback (OSPI_HandleTypeDef *hospi); 00812 void HAL_OSPI_TxCpltCallback (OSPI_HandleTypeDef *hospi); 00813 void HAL_OSPI_RxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 00814 void HAL_OSPI_TxHalfCpltCallback (OSPI_HandleTypeDef *hospi); 00815 00816 /* OSPI status flag polling mode functions */ 00817 void HAL_OSPI_StatusMatchCallback (OSPI_HandleTypeDef *hospi); 00818 00819 /* OSPI memory-mapped mode functions */ 00820 void HAL_OSPI_TimeOutCallback (OSPI_HandleTypeDef *hospi); 00821 00822 #if (USE_HAL_OSPI_REGISTER_CALLBACKS == 1) 00823 /* OSPI callback registering/unregistering */ 00824 HAL_StatusTypeDef HAL_OSPI_RegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID, pOSPI_CallbackTypeDef pCallback); 00825 HAL_StatusTypeDef HAL_OSPI_UnRegisterCallback (OSPI_HandleTypeDef *hospi, HAL_OSPI_CallbackIDTypeDef CallbackID); 00826 #endif 00827 /** 00828 * @} 00829 */ 00830 00831 /* Peripheral Control and State functions ************************************/ 00832 /** @addtogroup OSPI_Exported_Functions_Group3 00833 * @{ 00834 */ 00835 HAL_StatusTypeDef HAL_OSPI_Abort (OSPI_HandleTypeDef *hospi); 00836 HAL_StatusTypeDef HAL_OSPI_Abort_IT (OSPI_HandleTypeDef *hospi); 00837 HAL_StatusTypeDef HAL_OSPI_SetFifoThreshold (OSPI_HandleTypeDef *hospi, uint32_t Threshold); 00838 uint32_t HAL_OSPI_GetFifoThreshold (OSPI_HandleTypeDef *hospi); 00839 HAL_StatusTypeDef HAL_OSPI_SetTimeout (OSPI_HandleTypeDef *hospi, uint32_t Timeout); 00840 uint32_t HAL_OSPI_GetError (OSPI_HandleTypeDef *hospi); 00841 uint32_t HAL_OSPI_GetState (OSPI_HandleTypeDef *hospi); 00842 00843 /** 00844 * @} 00845 */ 00846 00847 /* OSPI IO Manager configuration function ************************************/ 00848 /** @addtogroup OSPI_Exported_Functions_Group4 00849 * @{ 00850 */ 00851 HAL_StatusTypeDef HAL_OSPIM_Config (OSPI_HandleTypeDef *hospi, OSPIM_CfgTypeDef *cfg, uint32_t Timeout); 00852 00853 /** 00854 * @} 00855 */ 00856 00857 /** 00858 * @} 00859 */ 00860 /* End of exported functions -------------------------------------------------*/ 00861 00862 /* Private macros ------------------------------------------------------------*/ 00863 /** 00864 @cond 0 00865 */ 00866 #define IS_OSPI_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) >= 1U) && ((THRESHOLD) <= 32U)) 00867 00868 #define IS_OSPI_DUALQUAD_MODE(MODE) (((MODE) == HAL_OSPI_DUALQUAD_DISABLE) || \ 00869 ((MODE) == HAL_OSPI_DUALQUAD_ENABLE)) 00870 00871 #define IS_OSPI_MEMORY_TYPE(TYPE) (((TYPE) == HAL_OSPI_MEMTYPE_MICRON) || \ 00872 ((TYPE) == HAL_OSPI_MEMTYPE_MACRONIX) || \ 00873 ((TYPE) == HAL_OSPI_MEMTYPE_HYPERBUS)) 00874 00875 #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) 00876 00877 #define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) 00878 00879 #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ 00880 ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) 00881 00882 #define IS_OSPI_CLOCK_MODE(MODE) (((MODE) == HAL_OSPI_CLOCK_MODE_0) || \ 00883 ((MODE) == HAL_OSPI_CLOCK_MODE_3)) 00884 00885 #define IS_OSPI_WRAP_SIZE(SIZE) (((SIZE) == HAL_OSPI_WRAP_NOT_SUPPORTED) || \ 00886 ((SIZE) == HAL_OSPI_WRAP_16_BYTES) || \ 00887 ((SIZE) == HAL_OSPI_WRAP_32_BYTES) || \ 00888 ((SIZE) == HAL_OSPI_WRAP_64_BYTES) || \ 00889 ((SIZE) == HAL_OSPI_WRAP_128_BYTES)) 00890 00891 #define IS_OSPI_CLK_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 256U)) 00892 00893 #define IS_OSPI_SAMPLE_SHIFTING(CYCLE) (((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_NONE) || \ 00894 ((CYCLE) == HAL_OSPI_SAMPLE_SHIFTING_HALFCYCLE)) 00895 00896 #define IS_OSPI_DHQC(CYCLE) (((CYCLE) == HAL_OSPI_DHQC_DISABLE) || \ 00897 ((CYCLE) == HAL_OSPI_DHQC_ENABLE)) 00898 00899 #define IS_OSPI_OPERATION_TYPE(TYPE) (((TYPE) == HAL_OSPI_OPTYPE_COMMON_CFG) || \ 00900 ((TYPE) == HAL_OSPI_OPTYPE_READ_CFG) || \ 00901 ((TYPE) == HAL_OSPI_OPTYPE_WRITE_CFG)) 00902 00903 #define IS_OSPI_FLASH_ID(FLASH) (((FLASH) == HAL_OSPI_FLASH_ID_1) || \ 00904 ((FLASH) == HAL_OSPI_FLASH_ID_2)) 00905 00906 #define IS_OSPI_INSTRUCTION_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_NONE) || \ 00907 ((MODE) == HAL_OSPI_INSTRUCTION_1_LINE) || \ 00908 ((MODE) == HAL_OSPI_INSTRUCTION_2_LINES) || \ 00909 ((MODE) == HAL_OSPI_INSTRUCTION_4_LINES) || \ 00910 ((MODE) == HAL_OSPI_INSTRUCTION_8_LINES)) 00911 00912 #define IS_OSPI_INSTRUCTION_SIZE(SIZE) (((SIZE) == HAL_OSPI_INSTRUCTION_8_BITS) || \ 00913 ((SIZE) == HAL_OSPI_INSTRUCTION_16_BITS) || \ 00914 ((SIZE) == HAL_OSPI_INSTRUCTION_24_BITS) || \ 00915 ((SIZE) == HAL_OSPI_INSTRUCTION_32_BITS)) 00916 00917 #define IS_OSPI_INSTRUCTION_DTR_MODE(MODE) (((MODE) == HAL_OSPI_INSTRUCTION_DTR_DISABLE) || \ 00918 ((MODE) == HAL_OSPI_INSTRUCTION_DTR_ENABLE)) 00919 00920 #define IS_OSPI_ADDRESS_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_NONE) || \ 00921 ((MODE) == HAL_OSPI_ADDRESS_1_LINE) || \ 00922 ((MODE) == HAL_OSPI_ADDRESS_2_LINES) || \ 00923 ((MODE) == HAL_OSPI_ADDRESS_4_LINES) || \ 00924 ((MODE) == HAL_OSPI_ADDRESS_8_LINES)) 00925 00926 #define IS_OSPI_ADDRESS_SIZE(SIZE) (((SIZE) == HAL_OSPI_ADDRESS_8_BITS) || \ 00927 ((SIZE) == HAL_OSPI_ADDRESS_16_BITS) || \ 00928 ((SIZE) == HAL_OSPI_ADDRESS_24_BITS) || \ 00929 ((SIZE) == HAL_OSPI_ADDRESS_32_BITS)) 00930 00931 #define IS_OSPI_ADDRESS_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ADDRESS_DTR_DISABLE) || \ 00932 ((MODE) == HAL_OSPI_ADDRESS_DTR_ENABLE)) 00933 00934 #define IS_OSPI_ALT_BYTES_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_NONE) || \ 00935 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_1_LINE) || \ 00936 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_2_LINES) || \ 00937 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_4_LINES) || \ 00938 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_8_LINES)) 00939 00940 #define IS_OSPI_ALT_BYTES_SIZE(SIZE) (((SIZE) == HAL_OSPI_ALTERNATE_BYTES_8_BITS) || \ 00941 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_16_BITS) || \ 00942 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_24_BITS) || \ 00943 ((SIZE) == HAL_OSPI_ALTERNATE_BYTES_32_BITS)) 00944 00945 #define IS_OSPI_ALT_BYTES_DTR_MODE(MODE) (((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_DISABLE) || \ 00946 ((MODE) == HAL_OSPI_ALTERNATE_BYTES_DTR_ENABLE)) 00947 00948 #define IS_OSPI_DATA_MODE(MODE) (((MODE) == HAL_OSPI_DATA_NONE) || \ 00949 ((MODE) == HAL_OSPI_DATA_1_LINE) || \ 00950 ((MODE) == HAL_OSPI_DATA_2_LINES) || \ 00951 ((MODE) == HAL_OSPI_DATA_4_LINES) || \ 00952 ((MODE) == HAL_OSPI_DATA_8_LINES)) 00953 00954 #define IS_OSPI_NUMBER_DATA(NUMBER) ((NUMBER) >= 1U) 00955 00956 #define IS_OSPI_DATA_DTR_MODE(MODE) (((MODE) == HAL_OSPI_DATA_DTR_DISABLE) || \ 00957 ((MODE) == HAL_OSPI_DATA_DTR_ENABLE)) 00958 00959 #define IS_OSPI_DUMMY_CYCLES(NUMBER) ((NUMBER) <= 31U) 00960 00961 #define IS_OSPI_DQS_MODE(MODE) (((MODE) == HAL_OSPI_DQS_DISABLE) || \ 00962 ((MODE) == HAL_OSPI_DQS_ENABLE)) 00963 00964 #define IS_OSPI_SIOO_MODE(MODE) (((MODE) == HAL_OSPI_SIOO_INST_EVERY_CMD) || \ 00965 ((MODE) == HAL_OSPI_SIOO_INST_ONLY_FIRST_CMD)) 00966 00967 #define IS_OSPI_RW_RECOVERY_TIME(NUMBER) ((NUMBER) <= 255U) 00968 00969 #define IS_OSPI_ACCESS_TIME(NUMBER) ((NUMBER) <= 255U) 00970 00971 #define IS_OSPI_WRITE_ZERO_LATENCY(MODE) (((MODE) == HAL_OSPI_LATENCY_ON_WRITE) || \ 00972 ((MODE) == HAL_OSPI_NO_LATENCY_ON_WRITE)) 00973 00974 #define IS_OSPI_LATENCY_MODE(MODE) (((MODE) == HAL_OSPI_VARIABLE_LATENCY) || \ 00975 ((MODE) == HAL_OSPI_FIXED_LATENCY)) 00976 00977 #define IS_OSPI_ADDRESS_SPACE(SPACE) (((SPACE) == HAL_OSPI_MEMORY_ADDRESS_SPACE) || \ 00978 ((SPACE) == HAL_OSPI_REGISTER_ADDRESS_SPACE)) 00979 00980 #define IS_OSPI_MATCH_MODE(MODE) (((MODE) == HAL_OSPI_MATCH_MODE_AND) || \ 00981 ((MODE) == HAL_OSPI_MATCH_MODE_OR)) 00982 00983 #define IS_OSPI_AUTOMATIC_STOP(MODE) (((MODE) == HAL_OSPI_AUTOMATIC_STOP_ENABLE) || \ 00984 ((MODE) == HAL_OSPI_AUTOMATIC_STOP_DISABLE)) 00985 00986 #define IS_OSPI_INTERVAL(INTERVAL) ((INTERVAL) <= 0xFFFFU) 00987 00988 #define IS_OSPI_STATUS_BYTES_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 4U)) 00989 00990 #define IS_OSPI_TIMEOUT_ACTIVATION(MODE) (((MODE) == HAL_OSPI_TIMEOUT_COUNTER_DISABLE) || \ 00991 ((MODE) == HAL_OSPI_TIMEOUT_COUNTER_ENABLE)) 00992 00993 #define IS_OSPI_TIMEOUT_PERIOD(PERIOD) ((PERIOD) <= 0xFFFFU) 00994 00995 #define IS_OSPI_CS_BOUNDARY(BOUNDARY) ((BOUNDARY) <= 31U) 00996 00997 #define IS_OSPIM_PORT(NUMBER) (((NUMBER) >= 1U) && ((NUMBER) <= 2U)) 00998 00999 #define IS_OSPIM_IO_PORT(PORT) (((PORT) == HAL_OSPIM_IOPORT_1_LOW) || \ 01000 ((PORT) == HAL_OSPIM_IOPORT_1_HIGH) || \ 01001 ((PORT) == HAL_OSPIM_IOPORT_2_LOW) || \ 01002 ((PORT) == HAL_OSPIM_IOPORT_2_HIGH)) 01003 /** 01004 @endcond 01005 */ 01006 01007 /* End of private macros -----------------------------------------------------*/ 01008 01009 /** 01010 * @} 01011 */ 01012 01013 /** 01014 * @} 01015 */ 01016 01017 #endif /* OCTOSPI || OCTOSPI1 || OCTOSPI2 */ 01018 01019 #ifdef __cplusplus 01020 } 01021 #endif 01022 01023 #endif /* STM32L4xx_HAL_OSPI_H */ 01024 01025 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1