STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_nand.h 00004 * @author MCD Application Team 00005 * @brief Header file of NAND HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_NAND_H 00038 #define __STM32L4xx_HAL_NAND_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 #if defined(FMC_BANK3) 00045 00046 /* Includes ------------------------------------------------------------------*/ 00047 #include "stm32l4xx_ll_fmc.h" 00048 00049 /** @addtogroup STM32L4xx_HAL_Driver 00050 * @{ 00051 */ 00052 00053 /** @addtogroup NAND 00054 * @{ 00055 */ 00056 00057 /* Exported typedef ----------------------------------------------------------*/ 00058 /* Exported types ------------------------------------------------------------*/ 00059 /** @defgroup NAND_Exported_Types NAND Exported Types 00060 * @{ 00061 */ 00062 00063 /** 00064 * @brief HAL NAND State structures definition 00065 */ 00066 typedef enum 00067 { 00068 HAL_NAND_STATE_RESET = 0x00U, /*!< NAND not yet initialized or disabled */ 00069 HAL_NAND_STATE_READY = 0x01U, /*!< NAND initialized and ready for use */ 00070 HAL_NAND_STATE_BUSY = 0x02U, /*!< NAND internal process is ongoing */ 00071 HAL_NAND_STATE_ERROR = 0x03U /*!< NAND error state */ 00072 }HAL_NAND_StateTypeDef; 00073 00074 /** 00075 * @brief NAND Memory electronic signature Structure definition 00076 */ 00077 typedef struct 00078 { 00079 /*<! NAND memory electronic signature maker and device IDs */ 00080 uint8_t Maker_Id; 00081 00082 uint8_t Device_Id; 00083 00084 uint8_t Third_Id; 00085 00086 uint8_t Fourth_Id; 00087 }NAND_IDTypeDef; 00088 00089 /** 00090 * @brief NAND Memory address Structure definition 00091 */ 00092 typedef struct 00093 { 00094 uint16_t Page; /*!< NAND memory Page address */ 00095 00096 uint16_t Plane; /*!< NAND memory Zone address */ 00097 00098 uint16_t Block; /*!< NAND memory Block address */ 00099 }NAND_AddressTypeDef; 00100 00101 /** 00102 * @brief NAND Memory info Structure definition 00103 */ 00104 typedef struct 00105 { 00106 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in bytes 00107 for 8 bits adressing or words for 16 bits addressing */ 00108 00109 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in bytes 00110 for 8 bits adressing or words for 16 bits addressing */ 00111 00112 uint32_t BlockSize; /*!< NAND memory block size measured in number of pages */ 00113 00114 uint32_t BlockNbr; /*!< NAND memory number of total blocks */ 00115 00116 uint32_t PlaneNbr; /*!< NAND memory number of planes */ 00117 00118 uint32_t PlaneSize; /*!< NAND memory zone size measured in number of blocks */ 00119 00120 FunctionalState ExtraCommandEnable; /*!< NAND extra command needed for Page reading mode. This 00121 parameter is mandatory for some NAND parts after the read 00122 command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 00123 Example: Toshiba THTH58BYG3S0HBAI6. 00124 This parameter could be ENABLE or DISABLE 00125 Please check the Read Mode sequnece in the NAND device datasheet */ 00126 } NAND_DeviceConfigTypeDef; 00127 00128 /** 00129 * @brief NAND handle Structure definition 00130 */ 00131 typedef struct 00132 { 00133 FMC_NAND_TypeDef *Instance; /*!< Register base address */ 00134 00135 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */ 00136 00137 HAL_LockTypeDef Lock; /*!< NAND locking object */ 00138 00139 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */ 00140 00141 NAND_DeviceConfigTypeDef Config; /*!< NAND phusical characteristic information structure */ 00142 00143 } NAND_HandleTypeDef; 00144 /** 00145 * @} 00146 */ 00147 00148 /* Exported constants --------------------------------------------------------*/ 00149 /* Exported macro ------------------------------------------------------------*/ 00150 /** @defgroup NAND_Exported_Macros NAND Exported Macros 00151 * @{ 00152 */ 00153 00154 /** @brief Reset NAND handle state 00155 * @param __HANDLE__ specifies the NAND handle. 00156 * @retval None 00157 */ 00158 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) 00159 00160 /** 00161 * @} 00162 */ 00163 00164 /* Exported functions --------------------------------------------------------*/ 00165 /** @addtogroup NAND_Exported_Functions NAND Exported Functions 00166 * @{ 00167 */ 00168 00169 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions 00170 * @{ 00171 */ 00172 00173 /* Initialization/de-initialization functions ********************************/ 00174 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); 00175 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); 00176 00177 HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); 00178 00179 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); 00180 00181 void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand); 00182 void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand); 00183 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand); 00184 void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand); 00185 00186 /** 00187 * @} 00188 */ 00189 00190 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions 00191 * @{ 00192 */ 00193 00194 /* IO operation functions ****************************************************/ 00195 00196 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand); 00197 00198 HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead); 00199 HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite); 00200 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead); 00201 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite); 00202 00203 HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead); 00204 HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite); 00205 HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead); 00206 HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite); 00207 00208 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 00209 00210 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress); 00211 00212 /** 00213 * @} 00214 */ 00215 00216 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions 00217 * @{ 00218 */ 00219 00220 /* NAND Control functions ****************************************************/ 00221 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand); 00222 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand); 00223 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout); 00224 00225 /** 00226 * @} 00227 */ 00228 00229 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 00230 * @{ 00231 */ 00232 /* NAND State functions *******************************************************/ 00233 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand); 00234 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand); 00235 /** 00236 * @} 00237 */ 00238 00239 /** 00240 * @} 00241 */ 00242 /* Private types -------------------------------------------------------------*/ 00243 /* Private variables ---------------------------------------------------------*/ 00244 /* Private constants ---------------------------------------------------------*/ 00245 /** @defgroup NAND_Private_Constants NAND Private Constants 00246 * @{ 00247 */ 00248 #define NAND_DEVICE FMC_BANK3 00249 #define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000U) 00250 00251 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */ 00252 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */ 00253 00254 #define NAND_CMD_AREA_A ((uint8_t)0x00U) 00255 #define NAND_CMD_AREA_B ((uint8_t)0x01U) 00256 #define NAND_CMD_AREA_C ((uint8_t)0x50U) 00257 #define NAND_CMD_AREA_TRUE1 ((uint8_t)0x30U) 00258 00259 #define NAND_CMD_WRITE0 ((uint8_t)0x80U) 00260 #define NAND_CMD_WRITE_TRUE1 ((uint8_t)0x10U) 00261 #define NAND_CMD_ERASE0 ((uint8_t)0x60U) 00262 #define NAND_CMD_ERASE1 ((uint8_t)0xD0U) 00263 #define NAND_CMD_READID ((uint8_t)0x90U) 00264 #define NAND_CMD_STATUS ((uint8_t)0x70U) 00265 #define NAND_CMD_LOCK_STATUS ((uint8_t)0x7AU) 00266 #define NAND_CMD_RESET ((uint8_t)0xFFU) 00267 00268 /* NAND memory status */ 00269 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100U) 00270 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200U) 00271 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400U) 00272 #define NAND_BUSY ((uint32_t)0x00000000U) 00273 #define NAND_ERROR ((uint32_t)0x00000001U) 00274 #define NAND_READY ((uint32_t)0x00000040U) 00275 /** 00276 * @} 00277 */ 00278 00279 /* Private macros ------------------------------------------------------------*/ 00280 /** @defgroup NAND_Private_Macros NAND Private Macros 00281 * @{ 00282 */ 00283 00284 /** 00285 * @brief NAND memory address computation. 00286 * @param __ADDRESS__ NAND memory address. 00287 * @param __HANDLE__ NAND handle. 00288 * @retval NAND Raw address value 00289 */ 00290 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \ 00291 (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize))) 00292 00293 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) 00294 00295 /** 00296 * @brief NAND memory address cycling. 00297 * @param __ADDRESS__ NAND memory address. 00298 * @retval NAND address cycling value. 00299 */ 00300 #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ 00301 #define ADDR_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd addressing cycle */ 00302 #define ADDR_3RD_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 16) /* 3rd addressing cycle */ 00303 #define ADDR_4TH_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 24) /* 4th addressing cycle */ 00304 00305 /** 00306 * @brief NAND memory Columns cycling. 00307 * @param __ADDRESS__ NAND memory address. 00308 * @retval NAND Column address cycling value. 00309 */ 00310 #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */ 00311 #define COLUMN_2ND_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__) >> 8) /* 2nd Column addressing cycle */ 00312 00313 /** 00314 * @} 00315 */ 00316 00317 /** 00318 * @} 00319 */ 00320 00321 /** 00322 * @} 00323 */ 00324 00325 /** 00326 * @} 00327 */ 00328 00329 #endif /* FMC_BANK3 */ 00330 00331 #ifdef __cplusplus 00332 } 00333 #endif 00334 00335 #endif /* __STM32L4xx_HAL_NAND_H */ 00336 00337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/