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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dsi.h 00004 * @author MCD Application Team 00005 * @brief Header file of DSI HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef STM32L4xx_HAL_DSI_H 00038 #define STM32L4xx_HAL_DSI_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 #if defined(DSI) 00045 /* Includes ------------------------------------------------------------------*/ 00046 #include "stm32l4xx_hal_def.h" 00047 00048 /** @addtogroup STM32L4xx_HAL_Driver 00049 * @{ 00050 */ 00051 00052 /** @defgroup DSI DSI 00053 * @brief DSI HAL module driver 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** 00059 * @brief DSI Init Structure definition 00060 */ 00061 typedef struct 00062 { 00063 uint32_t AutomaticClockLaneControl; /*!< Automatic clock lane control 00064 This parameter can be any value of @ref DSI_Automatic_Clk_Lane_Control */ 00065 00066 uint32_t TXEscapeCkdiv; /*!< TX Escape clock division 00067 The values 0 and 1 stop the TX_ESC clock generation */ 00068 00069 uint32_t NumberOfLanes; /*!< Number of lanes 00070 This parameter can be any value of @ref DSI_Number_Of_Lanes */ 00071 00072 }DSI_InitTypeDef; 00073 00074 /** 00075 * @brief DSI PLL Clock structure definition 00076 */ 00077 typedef struct 00078 { 00079 uint32_t PLLNDIV; /*!< PLL Loop Division Factor 00080 This parameter must be a value between 10 and 125 */ 00081 00082 uint32_t PLLIDF; /*!< PLL Input Division Factor 00083 This parameter can be any value of @ref DSI_PLL_IDF */ 00084 00085 uint32_t PLLODF; /*!< PLL Output Division Factor 00086 This parameter can be any value of @ref DSI_PLL_ODF */ 00087 00088 }DSI_PLLInitTypeDef; 00089 00090 /** 00091 * @brief DSI Video mode configuration 00092 */ 00093 typedef struct 00094 { 00095 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 00096 00097 uint32_t ColorCoding; /*!< Color coding for LTDC interface 00098 This parameter can be any value of @ref DSI_Color_Coding */ 00099 00100 uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using 00101 18-bit configuration). 00102 This parameter can be any value of @ref DSI_LooselyPacked */ 00103 00104 uint32_t Mode; /*!< Video mode type 00105 This parameter can be any value of @ref DSI_Video_Mode_Type */ 00106 00107 uint32_t PacketSize; /*!< Video packet size */ 00108 00109 uint32_t NumberOfChunks; /*!< Number of chunks */ 00110 00111 uint32_t NullPacketSize; /*!< Null packet size */ 00112 00113 uint32_t HSPolarity; /*!< HSYNC pin polarity 00114 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 00115 00116 uint32_t VSPolarity; /*!< VSYNC pin polarity 00117 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 00118 00119 uint32_t DEPolarity; /*!< Data Enable pin polarity 00120 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 00121 00122 uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */ 00123 00124 uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */ 00125 00126 uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */ 00127 00128 uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */ 00129 00130 uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */ 00131 00132 uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */ 00133 00134 uint32_t VerticalActive; /*!< Vertical active duration */ 00135 00136 uint32_t LPCommandEnable; /*!< Low-power command enable 00137 This parameter can be any value of @ref DSI_LP_Command */ 00138 00139 uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 00140 can fit in a line during VSA, VBP and VFP regions */ 00141 00142 uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that 00143 can fit in a line during VACT region */ 00144 00145 uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable 00146 This parameter can be any value of @ref DSI_LP_HFP */ 00147 00148 uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable 00149 This parameter can be any value of @ref DSI_LP_HBP */ 00150 00151 uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable 00152 This parameter can be any value of @ref DSI_LP_VACT */ 00153 00154 uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable 00155 This parameter can be any value of @ref DSI_LP_VFP */ 00156 00157 uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable 00158 This parameter can be any value of @ref DSI_LP_VBP */ 00159 00160 uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable 00161 This parameter can be any value of @ref DSI_LP_VSYNC */ 00162 00163 uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable 00164 This parameter can be any value of @ref DSI_FBTA_acknowledge */ 00165 00166 }DSI_VidCfgTypeDef; 00167 00168 /** 00169 * @brief DSI Adapted command mode configuration 00170 */ 00171 typedef struct 00172 { 00173 uint32_t VirtualChannelID; /*!< Virtual channel ID */ 00174 00175 uint32_t ColorCoding; /*!< Color coding for LTDC interface 00176 This parameter can be any value of @ref DSI_Color_Coding */ 00177 00178 uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in 00179 pixels. This parameter can be any value between 0x00 and 0xFFFFU */ 00180 00181 uint32_t TearingEffectSource; /*!< Tearing effect source 00182 This parameter can be any value of @ref DSI_TearingEffectSource */ 00183 00184 uint32_t TearingEffectPolarity; /*!< Tearing effect pin polarity 00185 This parameter can be any value of @ref DSI_TearingEffectPolarity */ 00186 00187 uint32_t HSPolarity; /*!< HSYNC pin polarity 00188 This parameter can be any value of @ref DSI_HSYNC_Polarity */ 00189 00190 uint32_t VSPolarity; /*!< VSYNC pin polarity 00191 This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */ 00192 00193 uint32_t DEPolarity; /*!< Data Enable pin polarity 00194 This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */ 00195 00196 uint32_t VSyncPol; /*!< VSync edge on which the LTDC is halted 00197 This parameter can be any value of @ref DSI_Vsync_Polarity */ 00198 00199 uint32_t AutomaticRefresh; /*!< Automatic refresh mode 00200 This parameter can be any value of @ref DSI_AutomaticRefresh */ 00201 00202 uint32_t TEAcknowledgeRequest; /*!< Tearing Effect Acknowledge Request Enable 00203 This parameter can be any value of @ref DSI_TE_AcknowledgeRequest */ 00204 00205 }DSI_CmdCfgTypeDef; 00206 00207 /** 00208 * @brief DSI command transmission mode configuration 00209 */ 00210 typedef struct 00211 { 00212 uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission 00213 This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */ 00214 00215 uint32_t LPGenShortWriteOneP; /*!< Generic Short Write One parameter Transmission 00216 This parameter can be any value of @ref DSI_LP_LPGenShortWriteOneP */ 00217 00218 uint32_t LPGenShortWriteTwoP; /*!< Generic Short Write Two parameters Transmission 00219 This parameter can be any value of @ref DSI_LP_LPGenShortWriteTwoP */ 00220 00221 uint32_t LPGenShortReadNoP; /*!< Generic Short Read Zero parameters Transmission 00222 This parameter can be any value of @ref DSI_LP_LPGenShortReadNoP */ 00223 00224 uint32_t LPGenShortReadOneP; /*!< Generic Short Read One parameter Transmission 00225 This parameter can be any value of @ref DSI_LP_LPGenShortReadOneP */ 00226 00227 uint32_t LPGenShortReadTwoP; /*!< Generic Short Read Two parameters Transmission 00228 This parameter can be any value of @ref DSI_LP_LPGenShortReadTwoP */ 00229 00230 uint32_t LPGenLongWrite; /*!< Generic Long Write Transmission 00231 This parameter can be any value of @ref DSI_LP_LPGenLongWrite */ 00232 00233 uint32_t LPDcsShortWriteNoP; /*!< DCS Short Write Zero parameters Transmission 00234 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteNoP */ 00235 00236 uint32_t LPDcsShortWriteOneP; /*!< DCS Short Write One parameter Transmission 00237 This parameter can be any value of @ref DSI_LP_LPDcsShortWriteOneP */ 00238 00239 uint32_t LPDcsShortReadNoP; /*!< DCS Short Read Zero parameters Transmission 00240 This parameter can be any value of @ref DSI_LP_LPDcsShortReadNoP */ 00241 00242 uint32_t LPDcsLongWrite; /*!< DCS Long Write Transmission 00243 This parameter can be any value of @ref DSI_LP_LPDcsLongWrite */ 00244 00245 uint32_t LPMaxReadPacket; /*!< Maximum Read Packet Size Transmission 00246 This parameter can be any value of @ref DSI_LP_LPMaxReadPacket */ 00247 00248 uint32_t AcknowledgeRequest; /*!< Acknowledge Request Enable 00249 This parameter can be any value of @ref DSI_AcknowledgeRequest */ 00250 00251 }DSI_LPCmdTypeDef; 00252 00253 /** 00254 * @brief DSI PHY Timings definition 00255 */ 00256 typedef struct 00257 { 00258 uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed 00259 to low-power transmission */ 00260 00261 uint32_t ClockLaneLP2HSTime; /*!< The maximum time that the D-PHY clock lane takes to go from low-power 00262 to high-speed transmission */ 00263 00264 uint32_t DataLaneHS2LPTime; /*!< The maximum time that the D-PHY data lanes takes to go from high-speed 00265 to low-power transmission */ 00266 00267 uint32_t DataLaneLP2HSTime; /*!< The maximum time that the D-PHY data lanes takes to go from low-power 00268 to high-speed transmission */ 00269 00270 uint32_t DataLaneMaxReadTime; /*!< The maximum time required to perform a read command */ 00271 00272 uint32_t StopWaitTime; /*!< The minimum wait period to request a High-Speed transmission after the 00273 Stop state */ 00274 00275 }DSI_PHY_TimerTypeDef; 00276 00277 /** 00278 * @brief DSI HOST Timeouts definition 00279 */ 00280 typedef struct 00281 { 00282 uint32_t TimeoutCkdiv; /*!< Time-out clock division */ 00283 00284 uint32_t HighSpeedTransmissionTimeout; /*!< High-speed transmission time-out */ 00285 00286 uint32_t LowPowerReceptionTimeout; /*!< Low-power reception time-out */ 00287 00288 uint32_t HighSpeedReadTimeout; /*!< High-speed read time-out */ 00289 00290 uint32_t LowPowerReadTimeout; /*!< Low-power read time-out */ 00291 00292 uint32_t HighSpeedWriteTimeout; /*!< High-speed write time-out */ 00293 00294 uint32_t HighSpeedWritePrespMode; /*!< High-speed write presp mode 00295 This parameter can be any value of @ref DSI_HS_PrespMode */ 00296 00297 uint32_t LowPowerWriteTimeout; /*!< Low-speed write time-out */ 00298 00299 uint32_t BTATimeout; /*!< BTA time-out */ 00300 00301 }DSI_HOST_TimeoutTypeDef; 00302 00303 /** 00304 * @brief DSI States Structure definition 00305 */ 00306 typedef enum 00307 { 00308 HAL_DSI_STATE_RESET = 0x00U, 00309 HAL_DSI_STATE_READY = 0x01U, 00310 HAL_DSI_STATE_ERROR = 0x02U, 00311 HAL_DSI_STATE_BUSY = 0x03U, 00312 HAL_DSI_STATE_TIMEOUT = 0x04U 00313 }HAL_DSI_StateTypeDef; 00314 00315 /** 00316 * @brief DSI Handle Structure definition 00317 */ 00318 typedef struct __DSI_HandleTypeDef 00319 { 00320 DSI_TypeDef *Instance; /*!< Register base address */ 00321 DSI_InitTypeDef Init; /*!< DSI required parameters */ 00322 HAL_LockTypeDef Lock; /*!< DSI peripheral status */ 00323 __IO HAL_DSI_StateTypeDef State; /*!< DSI communication state */ 00324 __IO uint32_t ErrorCode; /*!< DSI Error code */ 00325 uint32_t ErrorMsk; /*!< DSI Error monitoring mask */ 00326 00327 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00328 void (* TearingEffectCallback)(struct __DSI_HandleTypeDef *hdsi); /*!< DSI Tearing Effect Callback */ 00329 void (* EndOfRefreshCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI End Of Refresh Callback */ 00330 void (* ErrorCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Error Callback */ 00331 00332 void (* MspInitCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp Init callback */ 00333 void (* MspDeInitCallback) (struct __DSI_HandleTypeDef *hdsi); /*!< DSI Msp DeInit callback */ 00334 00335 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00336 00337 }DSI_HandleTypeDef; 00338 00339 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00340 /** 00341 * @brief HAL DSI Callback ID enumeration definition 00342 */ 00343 typedef enum 00344 { 00345 HAL_DSI_MSPINIT_CB_ID = 0x00U, /*!< DSI MspInit callback ID */ 00346 HAL_DSI_MSPDEINIT_CB_ID = 0x01U, /*!< DSI MspDeInit callback ID */ 00347 00348 HAL_DSI_TEARING_EFFECT_CB_ID = 0x02U, /*!< DSI Tearing Effect Callback ID */ 00349 HAL_DSI_ENDOF_REFRESH_CB_ID = 0x03U, /*!< DSI End Of Refresh Callback ID */ 00350 HAL_DSI_ERROR_CB_ID = 0x04U /*!< DSI Error Callback ID */ 00351 00352 }HAL_DSI_CallbackIDTypeDef; 00353 00354 /** 00355 * @brief HAL DSI Callback pointer definition 00356 */ 00357 typedef void (*pDSI_CallbackTypeDef)(DSI_HandleTypeDef * hdsi); /*!< pointer to an DSI callback function */ 00358 00359 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00360 00361 /* Exported constants --------------------------------------------------------*/ 00362 /** @defgroup DSI_DCS_Command DSI DCS Command 00363 * @{ 00364 */ 00365 #define DSI_ENTER_IDLE_MODE 0x39U 00366 #define DSI_ENTER_INVERT_MODE 0x21U 00367 #define DSI_ENTER_NORMAL_MODE 0x13U 00368 #define DSI_ENTER_PARTIAL_MODE 0x12U 00369 #define DSI_ENTER_SLEEP_MODE 0x10U 00370 #define DSI_EXIT_IDLE_MODE 0x38U 00371 #define DSI_EXIT_INVERT_MODE 0x20U 00372 #define DSI_EXIT_SLEEP_MODE 0x11U 00373 #define DSI_GET_3D_CONTROL 0x3FU 00374 #define DSI_GET_ADDRESS_MODE 0x0BU 00375 #define DSI_GET_BLUE_CHANNEL 0x08U 00376 #define DSI_GET_DIAGNOSTIC_RESULT 0x0FU 00377 #define DSI_GET_DISPLAY_MODE 0x0DU 00378 #define DSI_GET_GREEN_CHANNEL 0x07U 00379 #define DSI_GET_PIXEL_FORMAT 0x0CU 00380 #define DSI_GET_POWER_MODE 0x0AU 00381 #define DSI_GET_RED_CHANNEL 0x06U 00382 #define DSI_GET_SCANLINE 0x45U 00383 #define DSI_GET_SIGNAL_MODE 0x0EU 00384 #define DSI_NOP 0x00U 00385 #define DSI_READ_DDB_CONTINUE 0xA8U 00386 #define DSI_READ_DDB_START 0xA1U 00387 #define DSI_READ_MEMORY_CONTINUE 0x3EU 00388 #define DSI_READ_MEMORY_START 0x2EU 00389 #define DSI_SET_3D_CONTROL 0x3DU 00390 #define DSI_SET_ADDRESS_MODE 0x36U 00391 #define DSI_SET_COLUMN_ADDRESS 0x2AU 00392 #define DSI_SET_DISPLAY_OFF 0x28U 00393 #define DSI_SET_DISPLAY_ON 0x29U 00394 #define DSI_SET_GAMMA_CURVE 0x26U 00395 #define DSI_SET_PAGE_ADDRESS 0x2BU 00396 #define DSI_SET_PARTIAL_COLUMNS 0x31U 00397 #define DSI_SET_PARTIAL_ROWS 0x30U 00398 #define DSI_SET_PIXEL_FORMAT 0x3AU 00399 #define DSI_SET_SCROLL_AREA 0x33U 00400 #define DSI_SET_SCROLL_START 0x37U 00401 #define DSI_SET_TEAR_OFF 0x34U 00402 #define DSI_SET_TEAR_ON 0x35U 00403 #define DSI_SET_TEAR_SCANLINE 0x44U 00404 #define DSI_SET_VSYNC_TIMING 0x40U 00405 #define DSI_SOFT_RESET 0x01U 00406 #define DSI_WRITE_LUT 0x2DU 00407 #define DSI_WRITE_MEMORY_CONTINUE 0x3CU 00408 #define DSI_WRITE_MEMORY_START 0x2CU 00409 /** 00410 * @} 00411 */ 00412 00413 /** @defgroup DSI_Video_Mode_Type DSI Video Mode Type 00414 * @{ 00415 */ 00416 #define DSI_VID_MODE_NB_PULSES 0U 00417 #define DSI_VID_MODE_NB_EVENTS 1U 00418 #define DSI_VID_MODE_BURST 2U 00419 /** 00420 * @} 00421 */ 00422 00423 /** @defgroup DSI_Color_Mode DSI Color Mode 00424 * @{ 00425 */ 00426 #define DSI_COLOR_MODE_FULL 0x00000000U 00427 #define DSI_COLOR_MODE_EIGHT DSI_WCR_COLM 00428 /** 00429 * @} 00430 */ 00431 00432 /** @defgroup DSI_ShutDown DSI ShutDown 00433 * @{ 00434 */ 00435 #define DSI_DISPLAY_ON 0x00000000U 00436 #define DSI_DISPLAY_OFF DSI_WCR_SHTDN 00437 /** 00438 * @} 00439 */ 00440 00441 /** @defgroup DSI_LP_Command DSI LP Command 00442 * @{ 00443 */ 00444 #define DSI_LP_COMMAND_DISABLE 0x00000000U 00445 #define DSI_LP_COMMAND_ENABLE DSI_VMCR_LPCE 00446 /** 00447 * @} 00448 */ 00449 00450 /** @defgroup DSI_LP_HFP DSI LP HFP 00451 * @{ 00452 */ 00453 #define DSI_LP_HFP_DISABLE 0x00000000U 00454 #define DSI_LP_HFP_ENABLE DSI_VMCR_LPHFPE 00455 /** 00456 * @} 00457 */ 00458 00459 /** @defgroup DSI_LP_HBP DSI LP HBP 00460 * @{ 00461 */ 00462 #define DSI_LP_HBP_DISABLE 0x00000000U 00463 #define DSI_LP_HBP_ENABLE DSI_VMCR_LPHBPE 00464 /** 00465 * @} 00466 */ 00467 00468 /** @defgroup DSI_LP_VACT DSI LP VACT 00469 * @{ 00470 */ 00471 #define DSI_LP_VACT_DISABLE 0x00000000U 00472 #define DSI_LP_VACT_ENABLE DSI_VMCR_LPVAE 00473 /** 00474 * @} 00475 */ 00476 00477 /** @defgroup DSI_LP_VFP DSI LP VFP 00478 * @{ 00479 */ 00480 #define DSI_LP_VFP_DISABLE 0x00000000U 00481 #define DSI_LP_VFP_ENABLE DSI_VMCR_LPVFPE 00482 /** 00483 * @} 00484 */ 00485 00486 /** @defgroup DSI_LP_VBP DSI LP VBP 00487 * @{ 00488 */ 00489 #define DSI_LP_VBP_DISABLE 0x00000000U 00490 #define DSI_LP_VBP_ENABLE DSI_VMCR_LPVBPE 00491 /** 00492 * @} 00493 */ 00494 00495 /** @defgroup DSI_LP_VSYNC DSI LP VSYNC 00496 * @{ 00497 */ 00498 #define DSI_LP_VSYNC_DISABLE 0x00000000U 00499 #define DSI_LP_VSYNC_ENABLE DSI_VMCR_LPVSAE 00500 /** 00501 * @} 00502 */ 00503 00504 /** @defgroup DSI_FBTA_acknowledge DSI FBTA Acknowledge 00505 * @{ 00506 */ 00507 #define DSI_FBTAA_DISABLE 0x00000000U 00508 #define DSI_FBTAA_ENABLE DSI_VMCR_FBTAAE 00509 /** 00510 * @} 00511 */ 00512 00513 /** @defgroup DSI_TearingEffectSource DSI Tearing Effect Source 00514 * @{ 00515 */ 00516 #define DSI_TE_DSILINK 0x00000000U 00517 #define DSI_TE_EXTERNAL DSI_WCFGR_TESRC 00518 /** 00519 * @} 00520 */ 00521 00522 /** @defgroup DSI_TearingEffectPolarity DSI Tearing Effect Polarity 00523 * @{ 00524 */ 00525 #define DSI_TE_RISING_EDGE 0x00000000U 00526 #define DSI_TE_FALLING_EDGE DSI_WCFGR_TEPOL 00527 /** 00528 * @} 00529 */ 00530 00531 /** @defgroup DSI_Vsync_Polarity DSI Vsync Polarity 00532 * @{ 00533 */ 00534 #define DSI_VSYNC_FALLING 0x00000000U 00535 #define DSI_VSYNC_RISING DSI_WCFGR_VSPOL 00536 /** 00537 * @} 00538 */ 00539 00540 /** @defgroup DSI_AutomaticRefresh DSI Automatic Refresh 00541 * @{ 00542 */ 00543 #define DSI_AR_DISABLE 0x00000000U 00544 #define DSI_AR_ENABLE DSI_WCFGR_AR 00545 /** 00546 * @} 00547 */ 00548 00549 /** @defgroup DSI_TE_AcknowledgeRequest DSI TE Acknowledge Request 00550 * @{ 00551 */ 00552 #define DSI_TE_ACKNOWLEDGE_DISABLE 0x00000000U 00553 #define DSI_TE_ACKNOWLEDGE_ENABLE DSI_CMCR_TEARE 00554 /** 00555 * @} 00556 */ 00557 00558 /** @defgroup DSI_AcknowledgeRequest DSI Acknowledge Request 00559 * @{ 00560 */ 00561 #define DSI_ACKNOWLEDGE_DISABLE 0x00000000U 00562 #define DSI_ACKNOWLEDGE_ENABLE DSI_CMCR_ARE 00563 /** 00564 * @} 00565 */ 00566 00567 /** @defgroup DSI_LP_LPGenShortWriteNoP DSI LP LPGen Short Write NoP 00568 * @{ 00569 */ 00570 #define DSI_LP_GSW0P_DISABLE 0x00000000U 00571 #define DSI_LP_GSW0P_ENABLE DSI_CMCR_GSW0TX 00572 /** 00573 * @} 00574 */ 00575 00576 /** @defgroup DSI_LP_LPGenShortWriteOneP DSI LP LPGen Short Write OneP 00577 * @{ 00578 */ 00579 #define DSI_LP_GSW1P_DISABLE 0x00000000U 00580 #define DSI_LP_GSW1P_ENABLE DSI_CMCR_GSW1TX 00581 /** 00582 * @} 00583 */ 00584 00585 /** @defgroup DSI_LP_LPGenShortWriteTwoP DSI LP LPGen Short Write TwoP 00586 * @{ 00587 */ 00588 #define DSI_LP_GSW2P_DISABLE 0x00000000U 00589 #define DSI_LP_GSW2P_ENABLE DSI_CMCR_GSW2TX 00590 /** 00591 * @} 00592 */ 00593 00594 /** @defgroup DSI_LP_LPGenShortReadNoP DSI LP LPGen Short Read NoP 00595 * @{ 00596 */ 00597 #define DSI_LP_GSR0P_DISABLE 0x00000000U 00598 #define DSI_LP_GSR0P_ENABLE DSI_CMCR_GSR0TX 00599 /** 00600 * @} 00601 */ 00602 00603 /** @defgroup DSI_LP_LPGenShortReadOneP DSI LP LPGen Short Read OneP 00604 * @{ 00605 */ 00606 #define DSI_LP_GSR1P_DISABLE 0x00000000U 00607 #define DSI_LP_GSR1P_ENABLE DSI_CMCR_GSR1TX 00608 /** 00609 * @} 00610 */ 00611 00612 /** @defgroup DSI_LP_LPGenShortReadTwoP DSI LP LPGen Short Read TwoP 00613 * @{ 00614 */ 00615 #define DSI_LP_GSR2P_DISABLE 0x00000000U 00616 #define DSI_LP_GSR2P_ENABLE DSI_CMCR_GSR2TX 00617 /** 00618 * @} 00619 */ 00620 00621 /** @defgroup DSI_LP_LPGenLongWrite DSI LP LPGen LongWrite 00622 * @{ 00623 */ 00624 #define DSI_LP_GLW_DISABLE 0x00000000U 00625 #define DSI_LP_GLW_ENABLE DSI_CMCR_GLWTX 00626 /** 00627 * @} 00628 */ 00629 00630 /** @defgroup DSI_LP_LPDcsShortWriteNoP DSI LP LPDcs Short Write NoP 00631 * @{ 00632 */ 00633 #define DSI_LP_DSW0P_DISABLE 0x00000000U 00634 #define DSI_LP_DSW0P_ENABLE DSI_CMCR_DSW0TX 00635 /** 00636 * @} 00637 */ 00638 00639 /** @defgroup DSI_LP_LPDcsShortWriteOneP DSI LP LPDcs Short Write OneP 00640 * @{ 00641 */ 00642 #define DSI_LP_DSW1P_DISABLE 0x00000000U 00643 #define DSI_LP_DSW1P_ENABLE DSI_CMCR_DSW1TX 00644 /** 00645 * @} 00646 */ 00647 00648 /** @defgroup DSI_LP_LPDcsShortReadNoP DSI LP LPDcs Short Read NoP 00649 * @{ 00650 */ 00651 #define DSI_LP_DSR0P_DISABLE 0x00000000U 00652 #define DSI_LP_DSR0P_ENABLE DSI_CMCR_DSR0TX 00653 /** 00654 * @} 00655 */ 00656 00657 /** @defgroup DSI_LP_LPDcsLongWrite DSI LP LPDcs Long Write 00658 * @{ 00659 */ 00660 #define DSI_LP_DLW_DISABLE 0x00000000U 00661 #define DSI_LP_DLW_ENABLE DSI_CMCR_DLWTX 00662 /** 00663 * @} 00664 */ 00665 00666 /** @defgroup DSI_LP_LPMaxReadPacket DSI LP LPMax Read Packet 00667 * @{ 00668 */ 00669 #define DSI_LP_MRDP_DISABLE 0x00000000U 00670 #define DSI_LP_MRDP_ENABLE DSI_CMCR_MRDPS 00671 /** 00672 * @} 00673 */ 00674 00675 /** @defgroup DSI_HS_PrespMode DSI HS Presp Mode 00676 * @{ 00677 */ 00678 #define DSI_HS_PM_DISABLE 0x00000000U 00679 #define DSI_HS_PM_ENABLE DSI_TCCR3_PM 00680 /** 00681 * @} 00682 */ 00683 00684 00685 /** @defgroup DSI_Automatic_Clk_Lane_Control DSI Automatic Clk Lane Control 00686 * @{ 00687 */ 00688 #define DSI_AUTO_CLK_LANE_CTRL_DISABLE 0x00000000U 00689 #define DSI_AUTO_CLK_LANE_CTRL_ENABLE DSI_CLCR_ACR 00690 /** 00691 * @} 00692 */ 00693 00694 /** @defgroup DSI_Number_Of_Lanes DSI Number Of Lanes 00695 * @{ 00696 */ 00697 #define DSI_ONE_DATA_LANE 0U 00698 #define DSI_TWO_DATA_LANES 1U 00699 /** 00700 * @} 00701 */ 00702 00703 /** @defgroup DSI_FlowControl DSI Flow Control 00704 * @{ 00705 */ 00706 #define DSI_FLOW_CONTROL_CRC_RX DSI_PCR_CRCRXE 00707 #define DSI_FLOW_CONTROL_ECC_RX DSI_PCR_ECCRXE 00708 #define DSI_FLOW_CONTROL_BTA DSI_PCR_BTAE 00709 #define DSI_FLOW_CONTROL_EOTP_RX DSI_PCR_ETRXE 00710 #define DSI_FLOW_CONTROL_EOTP_TX DSI_PCR_ETTXE 00711 #define DSI_FLOW_CONTROL_ALL (DSI_FLOW_CONTROL_CRC_RX | DSI_FLOW_CONTROL_ECC_RX | \ 00712 DSI_FLOW_CONTROL_BTA | DSI_FLOW_CONTROL_EOTP_RX | \ 00713 DSI_FLOW_CONTROL_EOTP_TX) 00714 /** 00715 * @} 00716 */ 00717 00718 /** @defgroup DSI_Color_Coding DSI Color Coding 00719 * @{ 00720 */ 00721 #define DSI_RGB565 0x00000000U /*!< The values 0x00000001 and 0x00000002 can also be used for the RGB565 color mode configuration */ 00722 #define DSI_RGB666 0x00000003U /*!< The value 0x00000004 can also be used for the RGB666 color mode configuration */ 00723 #define DSI_RGB888 0x00000005U 00724 /** 00725 * @} 00726 */ 00727 00728 /** @defgroup DSI_LooselyPacked DSI Loosely Packed 00729 * @{ 00730 */ 00731 #define DSI_LOOSELY_PACKED_ENABLE DSI_LCOLCR_LPE 00732 #define DSI_LOOSELY_PACKED_DISABLE 0x00000000U 00733 /** 00734 * @} 00735 */ 00736 00737 /** @defgroup DSI_HSYNC_Polarity DSI HSYNC Polarity 00738 * @{ 00739 */ 00740 #define DSI_HSYNC_ACTIVE_HIGH 0x00000000U 00741 #define DSI_HSYNC_ACTIVE_LOW DSI_LPCR_HSP 00742 /** 00743 * @} 00744 */ 00745 00746 /** @defgroup DSI_VSYNC_Active_Polarity DSI VSYNC Active Polarity 00747 * @{ 00748 */ 00749 #define DSI_VSYNC_ACTIVE_HIGH 0x00000000U 00750 #define DSI_VSYNC_ACTIVE_LOW DSI_LPCR_VSP 00751 /** 00752 * @} 00753 */ 00754 00755 /** @defgroup DSI_DATA_ENABLE_Polarity DSI DATA ENABLE Polarity 00756 * @{ 00757 */ 00758 #define DSI_DATA_ENABLE_ACTIVE_HIGH 0x00000000U 00759 #define DSI_DATA_ENABLE_ACTIVE_LOW DSI_LPCR_DEP 00760 /** 00761 * @} 00762 */ 00763 00764 /** @defgroup DSI_PLL_IDF DSI PLL IDF 00765 * @{ 00766 */ 00767 #define DSI_PLL_IN_DIV1 0x00000001U 00768 #define DSI_PLL_IN_DIV2 0x00000002U 00769 #define DSI_PLL_IN_DIV3 0x00000003U 00770 #define DSI_PLL_IN_DIV4 0x00000004U 00771 #define DSI_PLL_IN_DIV5 0x00000005U 00772 #define DSI_PLL_IN_DIV6 0x00000006U 00773 #define DSI_PLL_IN_DIV7 0x00000007U 00774 /** 00775 * @} 00776 */ 00777 00778 /** @defgroup DSI_PLL_ODF DSI PLL ODF 00779 * @{ 00780 */ 00781 #define DSI_PLL_OUT_DIV1 0x00000000U 00782 #define DSI_PLL_OUT_DIV2 0x00000001U 00783 #define DSI_PLL_OUT_DIV4 0x00000002U 00784 #define DSI_PLL_OUT_DIV8 0x00000003U 00785 /** 00786 * @} 00787 */ 00788 00789 /** @defgroup DSI_Flags DSI Flags 00790 * @{ 00791 */ 00792 #define DSI_FLAG_TE DSI_WISR_TEIF 00793 #define DSI_FLAG_ER DSI_WISR_ERIF 00794 #define DSI_FLAG_BUSY DSI_WISR_BUSY 00795 #define DSI_FLAG_PLLLS DSI_WISR_PLLLS 00796 #define DSI_FLAG_PLLL DSI_WISR_PLLLIF 00797 #define DSI_FLAG_PLLU DSI_WISR_PLLUIF 00798 #define DSI_FLAG_RRS DSI_WISR_RRS 00799 #define DSI_FLAG_RR DSI_WISR_RRIF 00800 /** 00801 * @} 00802 */ 00803 00804 /** @defgroup DSI_Interrupts DSI Interrupts 00805 * @{ 00806 */ 00807 #define DSI_IT_TE DSI_WIER_TEIE 00808 #define DSI_IT_ER DSI_WIER_ERIE 00809 #define DSI_IT_PLLL DSI_WIER_PLLLIE 00810 #define DSI_IT_PLLU DSI_WIER_PLLUIE 00811 #define DSI_IT_RR DSI_WIER_RRIE 00812 /** 00813 * @} 00814 */ 00815 00816 /** @defgroup DSI_SHORT_WRITE_PKT_Data_Type DSI SHORT WRITE PKT Data Type 00817 * @{ 00818 */ 00819 #define DSI_DCS_SHORT_PKT_WRITE_P0 0x00000005U /*!< DCS short write, no parameters */ 00820 #define DSI_DCS_SHORT_PKT_WRITE_P1 0x00000015U /*!< DCS short write, one parameter */ 00821 #define DSI_GEN_SHORT_PKT_WRITE_P0 0x00000003U /*!< Generic short write, no parameters */ 00822 #define DSI_GEN_SHORT_PKT_WRITE_P1 0x00000013U /*!< Generic short write, one parameter */ 00823 #define DSI_GEN_SHORT_PKT_WRITE_P2 0x00000023U /*!< Generic short write, two parameters */ 00824 /** 00825 * @} 00826 */ 00827 00828 /** @defgroup DSI_LONG_WRITE_PKT_Data_Type DSI LONG WRITE PKT Data Type 00829 * @{ 00830 */ 00831 #define DSI_DCS_LONG_PKT_WRITE 0x00000039U /*!< DCS long write */ 00832 #define DSI_GEN_LONG_PKT_WRITE 0x00000029U /*!< Generic long write */ 00833 /** 00834 * @} 00835 */ 00836 00837 /** @defgroup DSI_SHORT_READ_PKT_Data_Type DSI SHORT READ PKT Data Type 00838 * @{ 00839 */ 00840 #define DSI_DCS_SHORT_PKT_READ 0x00000006U /*!< DCS short read */ 00841 #define DSI_GEN_SHORT_PKT_READ_P0 0x00000004U /*!< Generic short read, no parameters */ 00842 #define DSI_GEN_SHORT_PKT_READ_P1 0x00000014U /*!< Generic short read, one parameter */ 00843 #define DSI_GEN_SHORT_PKT_READ_P2 0x00000024U /*!< Generic short read, two parameters */ 00844 /** 00845 * @} 00846 */ 00847 00848 /** @defgroup DSI_Error_Data_Type DSI Error Data Type 00849 * @{ 00850 */ 00851 #define HAL_DSI_ERROR_NONE 0U 00852 #define HAL_DSI_ERROR_ACK 0x00000001U /*!< acknowledge errors */ 00853 #define HAL_DSI_ERROR_PHY 0x00000002U /*!< PHY related errors */ 00854 #define HAL_DSI_ERROR_TX 0x00000004U /*!< transmission error */ 00855 #define HAL_DSI_ERROR_RX 0x00000008U /*!< reception error */ 00856 #define HAL_DSI_ERROR_ECC 0x00000010U /*!< ECC errors */ 00857 #define HAL_DSI_ERROR_CRC 0x00000020U /*!< CRC error */ 00858 #define HAL_DSI_ERROR_PSE 0x00000040U /*!< Packet Size error */ 00859 #define HAL_DSI_ERROR_EOT 0x00000080U /*!< End Of Transmission error */ 00860 #define HAL_DSI_ERROR_OVF 0x00000100U /*!< FIFO overflow error */ 00861 #define HAL_DSI_ERROR_GEN 0x00000200U /*!< Generic FIFO related errors */ 00862 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00863 #define HAL_DSI_ERROR_INVALID_CALLBACK 0x00000400U /*!< DSI Invalid Callback error */ 00864 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00865 /** 00866 * @} 00867 */ 00868 00869 /** @defgroup DSI_Lane_Group DSI Lane Group 00870 * @{ 00871 */ 00872 #define DSI_CLOCK_LANE 0x00000000U 00873 #define DSI_DATA_LANES 0x00000001U 00874 /** 00875 * @} 00876 */ 00877 00878 /** @defgroup DSI_Communication_Delay DSI Communication Delay 00879 * @{ 00880 */ 00881 #define DSI_SLEW_RATE_HSTX 0x00000000U 00882 #define DSI_SLEW_RATE_LPTX 0x00000001U 00883 #define DSI_HS_DELAY 0x00000002U 00884 /** 00885 * @} 00886 */ 00887 00888 /** @defgroup DSI_CustomLane DSI CustomLane 00889 * @{ 00890 */ 00891 #define DSI_SWAP_LANE_PINS 0x00000000U 00892 #define DSI_INVERT_HS_SIGNAL 0x00000001U 00893 /** 00894 * @} 00895 */ 00896 00897 /** @defgroup DSI_Lane_Select DSI Lane Select 00898 * @{ 00899 */ 00900 #define DSI_CLK_LANE 0x00000000U 00901 #define DSI_DATA_LANE0 0x00000001U 00902 #define DSI_DATA_LANE1 0x00000002U 00903 /** 00904 * @} 00905 */ 00906 00907 /** @defgroup DSI_PHY_Timing DSI PHY Timing 00908 * @{ 00909 */ 00910 #define DSI_TCLK_POST 0x00000000U 00911 #define DSI_TLPX_CLK 0x00000001U 00912 #define DSI_THS_EXIT 0x00000002U 00913 #define DSI_TLPX_DATA 0x00000003U 00914 #define DSI_THS_ZERO 0x00000004U 00915 #define DSI_THS_TRAIL 0x00000005U 00916 #define DSI_THS_PREPARE 0x00000006U 00917 #define DSI_TCLK_ZERO 0x00000007U 00918 #define DSI_TCLK_PREPARE 0x00000008U 00919 /** 00920 * @} 00921 */ 00922 00923 /* Exported macros -----------------------------------------------------------*/ 00924 /** 00925 * @brief Reset DSI handle state. 00926 * @param __HANDLE__: DSI handle 00927 * @retval None 00928 */ 00929 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00930 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00931 (__HANDLE__)->State = HAL_DSI_STATE_RESET; \ 00932 (__HANDLE__)->MspInitCallback = NULL; \ 00933 (__HANDLE__)->MspDeInitCallback = NULL; \ 00934 } while(0) 00935 #else 00936 #define __HAL_DSI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DSI_STATE_RESET) 00937 #endif /*USE_HAL_DSI_REGISTER_CALLBACKS */ 00938 00939 /** 00940 * @brief Enables the DSI host. 00941 * @param __HANDLE__ DSI handle 00942 * @retval None. 00943 */ 00944 #define __HAL_DSI_ENABLE(__HANDLE__) do { \ 00945 __IO uint32_t tmpreg = 0x00U; \ 00946 SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00947 /* Delay after an DSI Host enabling */ \ 00948 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00949 UNUSED(tmpreg); \ 00950 }while(0U) 00951 00952 /** 00953 * @brief Disables the DSI host. 00954 * @param __HANDLE__ DSI handle 00955 * @retval None. 00956 */ 00957 #define __HAL_DSI_DISABLE(__HANDLE__) do { \ 00958 __IO uint32_t tmpreg = 0x00U; \ 00959 CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00960 /* Delay after an DSI Host disabling */ \ 00961 tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\ 00962 UNUSED(tmpreg); \ 00963 }while(0U) 00964 00965 /** 00966 * @brief Enables the DSI wrapper. 00967 * @param __HANDLE__ DSI handle 00968 * @retval None. 00969 */ 00970 #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \ 00971 __IO uint32_t tmpreg = 0x00U; \ 00972 SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00973 /* Delay after an DSI warpper enabling */ \ 00974 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00975 UNUSED(tmpreg); \ 00976 }while(0U) 00977 00978 /** 00979 * @brief Disable the DSI wrapper. 00980 * @param __HANDLE__ DSI handle 00981 * @retval None. 00982 */ 00983 #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \ 00984 __IO uint32_t tmpreg = 0x00U; \ 00985 CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00986 /* Delay after an DSI warpper disabling*/ \ 00987 tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\ 00988 UNUSED(tmpreg); \ 00989 }while(0U) 00990 00991 /** 00992 * @brief Enables the DSI PLL. 00993 * @param __HANDLE__ DSI handle 00994 * @retval None. 00995 */ 00996 #define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \ 00997 __IO uint32_t tmpreg = 0x00U; \ 00998 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 00999 /* Delay after an DSI PLL enabling */ \ 01000 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 01001 UNUSED(tmpreg); \ 01002 }while(0U) 01003 01004 /** 01005 * @brief Disables the DSI PLL. 01006 * @param __HANDLE__ DSI handle 01007 * @retval None. 01008 */ 01009 #define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \ 01010 __IO uint32_t tmpreg = 0x00U; \ 01011 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 01012 /* Delay after an DSI PLL disabling */ \ 01013 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\ 01014 UNUSED(tmpreg); \ 01015 }while(0U) 01016 01017 /** 01018 * @brief Enables the DSI regulator. 01019 * @param __HANDLE__ DSI handle 01020 * @retval None. 01021 */ 01022 #define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \ 01023 __IO uint32_t tmpreg = 0x00U; \ 01024 SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01025 /* Delay after an DSI regulator enabling */ \ 01026 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01027 UNUSED(tmpreg); \ 01028 }while(0U) 01029 01030 /** 01031 * @brief Disables the DSI regulator. 01032 * @param __HANDLE__ DSI handle 01033 * @retval None. 01034 */ 01035 #define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \ 01036 __IO uint32_t tmpreg = 0x00U; \ 01037 CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01038 /* Delay after an DSI regulator disabling */ \ 01039 tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\ 01040 UNUSED(tmpreg); \ 01041 }while(0U) 01042 01043 /** 01044 * @brief Get the DSI pending flags. 01045 * @param __HANDLE__ DSI handle. 01046 * @param __FLAG__ Get the specified flag. 01047 * This parameter can be any combination of the following values: 01048 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 01049 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 01050 * @arg DSI_FLAG_BUSY : Busy Flag 01051 * @arg DSI_FLAG_PLLLS: PLL Lock Status 01052 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 01053 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 01054 * @arg DSI_FLAG_RRS : Regulator Ready Flag 01055 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 01056 * @retval The state of FLAG (SET or RESET). 01057 */ 01058 #define __HAL_DSI_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WISR & (__FLAG__)) 01059 01060 /** 01061 * @brief Clears the DSI pending flags. 01062 * @param __HANDLE__ DSI handle. 01063 * @param __FLAG__ specifies the flag to clear. 01064 * This parameter can be any combination of the following values: 01065 * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag 01066 * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag 01067 * @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag 01068 * @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag 01069 * @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag 01070 * @retval None 01071 */ 01072 #define __HAL_DSI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WIFCR = (__FLAG__)) 01073 01074 /** 01075 * @brief Enables the specified DSI interrupts. 01076 * @param __HANDLE__ DSI handle. 01077 * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. 01078 * This parameter can be any combination of the following values: 01079 * @arg DSI_IT_TE : Tearing Effect Interrupt 01080 * @arg DSI_IT_ER : End of Refresh Interrupt 01081 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01082 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01083 * @arg DSI_IT_RR : Regulator Ready Interrupt 01084 * @retval None 01085 */ 01086 #define __HAL_DSI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER |= (__INTERRUPT__)) 01087 01088 /** 01089 * @brief Disables the specified DSI interrupts. 01090 * @param __HANDLE__ DSI handle 01091 * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. 01092 * This parameter can be any combination of the following values: 01093 * @arg DSI_IT_TE : Tearing Effect Interrupt 01094 * @arg DSI_IT_ER : End of Refresh Interrupt 01095 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01096 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01097 * @arg DSI_IT_RR : Regulator Ready Interrupt 01098 * @retval None 01099 */ 01100 #define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__)) 01101 01102 /** 01103 * @brief Checks whether the specified DSI interrupt source is enabled or not. 01104 * @param __HANDLE__ DSI handle 01105 * @param __INTERRUPT__ specifies the DSI interrupt source to check. 01106 * This parameter can be one of the following values: 01107 * @arg DSI_IT_TE : Tearing Effect Interrupt 01108 * @arg DSI_IT_ER : End of Refresh Interrupt 01109 * @arg DSI_IT_PLLL: PLL Lock Interrupt 01110 * @arg DSI_IT_PLLU: PLL Unlock Interrupt 01111 * @arg DSI_IT_RR : Regulator Ready Interrupt 01112 * @retval The state of INTERRUPT (SET or RESET). 01113 */ 01114 #define __HAL_DSI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER & (__INTERRUPT__)) 01115 01116 /* Exported functions --------------------------------------------------------*/ 01117 /** @defgroup DSI_Exported_Functions DSI Exported Functions 01118 * @{ 01119 */ 01120 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit); 01121 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi); 01122 void HAL_DSI_MspInit(DSI_HandleTypeDef *hdsi); 01123 void HAL_DSI_MspDeInit(DSI_HandleTypeDef *hdsi); 01124 01125 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi); 01126 void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi); 01127 void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi); 01128 void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi); 01129 01130 /* Callbacks Register/UnRegister functions ***********************************/ 01131 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 01132 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, pDSI_CallbackTypeDef pCallback); 01133 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID); 01134 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 01135 01136 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID); 01137 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg); 01138 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg); 01139 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd); 01140 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl); 01141 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers); 01142 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts); 01143 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi); 01144 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi); 01145 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi); 01146 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode); 01147 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown); 01148 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, 01149 uint32_t ChannelID, 01150 uint32_t Mode, 01151 uint32_t Param1, 01152 uint32_t Param2); 01153 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, 01154 uint32_t ChannelID, 01155 uint32_t Mode, 01156 uint32_t NbParams, 01157 uint32_t Param1, 01158 uint8_t* ParametersTable); 01159 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, 01160 uint32_t ChannelNbr, 01161 uint8_t* Array, 01162 uint32_t Size, 01163 uint32_t Mode, 01164 uint32_t DCSCmd, 01165 uint8_t* ParametersTable); 01166 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi); 01167 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi); 01168 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi); 01169 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi); 01170 01171 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation); 01172 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi); 01173 01174 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value); 01175 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency); 01176 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State); 01177 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State); 01178 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value); 01179 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State); 01180 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State); 01181 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State); 01182 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State); 01183 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State); 01184 01185 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi); 01186 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors); 01187 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi); 01188 /** 01189 * @} 01190 */ 01191 01192 /* Private types -------------------------------------------------------------*/ 01193 /** @defgroup DSI_Private_Types DSI Private Types 01194 * @{ 01195 */ 01196 01197 /** 01198 * @} 01199 */ 01200 01201 /* Private defines -----------------------------------------------------------*/ 01202 /** @defgroup DSI_Private_Defines DSI Private Defines 01203 * @{ 01204 */ 01205 01206 /** 01207 * @} 01208 */ 01209 01210 /* Private variables ---------------------------------------------------------*/ 01211 /** @defgroup DSI_Private_Variables DSI Private Variables 01212 * @{ 01213 */ 01214 01215 /** 01216 * @} 01217 */ 01218 01219 /* Private constants ---------------------------------------------------------*/ 01220 /** @defgroup DSI_Private_Constants DSI Private Constants 01221 * @{ 01222 */ 01223 #define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */ 01224 /** 01225 * @} 01226 */ 01227 01228 /* Private macros ------------------------------------------------------------*/ 01229 /** @defgroup DSI_Private_Macros DSI Private Macros 01230 * @{ 01231 */ 01232 #define IS_DSI_PLL_NDIV(NDIV) ((10U <= (NDIV)) && ((NDIV) <= 125U)) 01233 #define IS_DSI_PLL_IDF(IDF) (((IDF) == DSI_PLL_IN_DIV1) || \ 01234 ((IDF) == DSI_PLL_IN_DIV2) || \ 01235 ((IDF) == DSI_PLL_IN_DIV3) || \ 01236 ((IDF) == DSI_PLL_IN_DIV4) || \ 01237 ((IDF) == DSI_PLL_IN_DIV5) || \ 01238 ((IDF) == DSI_PLL_IN_DIV6) || \ 01239 ((IDF) == DSI_PLL_IN_DIV7)) 01240 #define IS_DSI_PLL_ODF(ODF) (((ODF) == DSI_PLL_OUT_DIV1) || \ 01241 ((ODF) == DSI_PLL_OUT_DIV2) || \ 01242 ((ODF) == DSI_PLL_OUT_DIV4) || \ 01243 ((ODF) == DSI_PLL_OUT_DIV8)) 01244 #define IS_DSI_AUTO_CLKLANE_CONTROL(AutoClkLane) (((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_DISABLE) || ((AutoClkLane) == DSI_AUTO_CLK_LANE_CTRL_ENABLE)) 01245 #define IS_DSI_NUMBER_OF_LANES(NumberOfLanes) (((NumberOfLanes) == DSI_ONE_DATA_LANE) || ((NumberOfLanes) == DSI_TWO_DATA_LANES)) 01246 #define IS_DSI_FLOW_CONTROL(FlowControl) (((FlowControl) | DSI_FLOW_CONTROL_ALL) == DSI_FLOW_CONTROL_ALL) 01247 #define IS_DSI_COLOR_CODING(ColorCoding) ((ColorCoding) <= 5U) 01248 #define IS_DSI_LOOSELY_PACKED(LooselyPacked) (((LooselyPacked) == DSI_LOOSELY_PACKED_ENABLE) || ((LooselyPacked) == DSI_LOOSELY_PACKED_DISABLE)) 01249 #define IS_DSI_DE_POLARITY(DataEnable) (((DataEnable) == DSI_DATA_ENABLE_ACTIVE_HIGH) || ((DataEnable) == DSI_DATA_ENABLE_ACTIVE_LOW)) 01250 #define IS_DSI_VSYNC_POLARITY(VSYNC) (((VSYNC) == DSI_VSYNC_ACTIVE_HIGH) || ((VSYNC) == DSI_VSYNC_ACTIVE_LOW)) 01251 #define IS_DSI_HSYNC_POLARITY(HSYNC) (((HSYNC) == DSI_HSYNC_ACTIVE_HIGH) || ((HSYNC) == DSI_HSYNC_ACTIVE_LOW)) 01252 #define IS_DSI_VIDEO_MODE_TYPE(VideoModeType) (((VideoModeType) == DSI_VID_MODE_NB_PULSES) || \ 01253 ((VideoModeType) == DSI_VID_MODE_NB_EVENTS) || \ 01254 ((VideoModeType) == DSI_VID_MODE_BURST)) 01255 #define IS_DSI_COLOR_MODE(ColorMode) (((ColorMode) == DSI_COLOR_MODE_FULL) || ((ColorMode) == DSI_COLOR_MODE_EIGHT)) 01256 #define IS_DSI_SHUT_DOWN(ShutDown) (((ShutDown) == DSI_DISPLAY_ON) || ((ShutDown) == DSI_DISPLAY_OFF)) 01257 #define IS_DSI_LP_COMMAND(LPCommand) (((LPCommand) == DSI_LP_COMMAND_DISABLE) || ((LPCommand) == DSI_LP_COMMAND_ENABLE)) 01258 #define IS_DSI_LP_HFP(LPHFP) (((LPHFP) == DSI_LP_HFP_DISABLE) || ((LPHFP) == DSI_LP_HFP_ENABLE)) 01259 #define IS_DSI_LP_HBP(LPHBP) (((LPHBP) == DSI_LP_HBP_DISABLE) || ((LPHBP) == DSI_LP_HBP_ENABLE)) 01260 #define IS_DSI_LP_VACTIVE(LPVActive) (((LPVActive) == DSI_LP_VACT_DISABLE) || ((LPVActive) == DSI_LP_VACT_ENABLE)) 01261 #define IS_DSI_LP_VFP(LPVFP) (((LPVFP) == DSI_LP_VFP_DISABLE) || ((LPVFP) == DSI_LP_VFP_ENABLE)) 01262 #define IS_DSI_LP_VBP(LPVBP) (((LPVBP) == DSI_LP_VBP_DISABLE) || ((LPVBP) == DSI_LP_VBP_ENABLE)) 01263 #define IS_DSI_LP_VSYNC(LPVSYNC) (((LPVSYNC) == DSI_LP_VSYNC_DISABLE) || ((LPVSYNC) == DSI_LP_VSYNC_ENABLE)) 01264 #define IS_DSI_FBTAA(FrameBTAAcknowledge) (((FrameBTAAcknowledge) == DSI_FBTAA_DISABLE) || ((FrameBTAAcknowledge) == DSI_FBTAA_ENABLE)) 01265 #define IS_DSI_TE_SOURCE(TESource) (((TESource) == DSI_TE_DSILINK) || ((TESource) == DSI_TE_EXTERNAL)) 01266 #define IS_DSI_TE_POLARITY(TEPolarity) (((TEPolarity) == DSI_TE_RISING_EDGE) || ((TEPolarity) == DSI_TE_FALLING_EDGE)) 01267 #define IS_DSI_AUTOMATIC_REFRESH(AutomaticRefresh) (((AutomaticRefresh) == DSI_AR_DISABLE) || ((AutomaticRefresh) == DSI_AR_ENABLE)) 01268 #define IS_DSI_VS_POLARITY(VSPolarity) (((VSPolarity) == DSI_VSYNC_FALLING) || ((VSPolarity) == DSI_VSYNC_RISING)) 01269 #define IS_DSI_TE_ACK_REQUEST(TEAcknowledgeRequest) (((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_DISABLE) || ((TEAcknowledgeRequest) == DSI_TE_ACKNOWLEDGE_ENABLE)) 01270 #define IS_DSI_ACK_REQUEST(AcknowledgeRequest) (((AcknowledgeRequest) == DSI_ACKNOWLEDGE_DISABLE) || ((AcknowledgeRequest) == DSI_ACKNOWLEDGE_ENABLE)) 01271 #define IS_DSI_LP_GSW0P(LP_GSW0P) (((LP_GSW0P) == DSI_LP_GSW0P_DISABLE) || ((LP_GSW0P) == DSI_LP_GSW0P_ENABLE)) 01272 #define IS_DSI_LP_GSW1P(LP_GSW1P) (((LP_GSW1P) == DSI_LP_GSW1P_DISABLE) || ((LP_GSW1P) == DSI_LP_GSW1P_ENABLE)) 01273 #define IS_DSI_LP_GSW2P(LP_GSW2P) (((LP_GSW2P) == DSI_LP_GSW2P_DISABLE) || ((LP_GSW2P) == DSI_LP_GSW2P_ENABLE)) 01274 #define IS_DSI_LP_GSR0P(LP_GSR0P) (((LP_GSR0P) == DSI_LP_GSR0P_DISABLE) || ((LP_GSR0P) == DSI_LP_GSR0P_ENABLE)) 01275 #define IS_DSI_LP_GSR1P(LP_GSR1P) (((LP_GSR1P) == DSI_LP_GSR1P_DISABLE) || ((LP_GSR1P) == DSI_LP_GSR1P_ENABLE)) 01276 #define IS_DSI_LP_GSR2P(LP_GSR2P) (((LP_GSR2P) == DSI_LP_GSR2P_DISABLE) || ((LP_GSR2P) == DSI_LP_GSR2P_ENABLE)) 01277 #define IS_DSI_LP_GLW(LP_GLW) (((LP_GLW) == DSI_LP_GLW_DISABLE) || ((LP_GLW) == DSI_LP_GLW_ENABLE)) 01278 #define IS_DSI_LP_DSW0P(LP_DSW0P) (((LP_DSW0P) == DSI_LP_DSW0P_DISABLE) || ((LP_DSW0P) == DSI_LP_DSW0P_ENABLE)) 01279 #define IS_DSI_LP_DSW1P(LP_DSW1P) (((LP_DSW1P) == DSI_LP_DSW1P_DISABLE) || ((LP_DSW1P) == DSI_LP_DSW1P_ENABLE)) 01280 #define IS_DSI_LP_DSR0P(LP_DSR0P) (((LP_DSR0P) == DSI_LP_DSR0P_DISABLE) || ((LP_DSR0P) == DSI_LP_DSR0P_ENABLE)) 01281 #define IS_DSI_LP_DLW(LP_DLW) (((LP_DLW) == DSI_LP_DLW_DISABLE) || ((LP_DLW) == DSI_LP_DLW_ENABLE)) 01282 #define IS_DSI_LP_MRDP(LP_MRDP) (((LP_MRDP) == DSI_LP_MRDP_DISABLE) || ((LP_MRDP) == DSI_LP_MRDP_ENABLE)) 01283 #define IS_DSI_SHORT_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_WRITE_P0) || \ 01284 ((MODE) == DSI_DCS_SHORT_PKT_WRITE_P1) || \ 01285 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P0) || \ 01286 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P1) || \ 01287 ((MODE) == DSI_GEN_SHORT_PKT_WRITE_P2)) 01288 #define IS_DSI_LONG_WRITE_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_LONG_PKT_WRITE) || \ 01289 ((MODE) == DSI_GEN_LONG_PKT_WRITE)) 01290 #define IS_DSI_READ_PACKET_TYPE(MODE) (((MODE) == DSI_DCS_SHORT_PKT_READ) || \ 01291 ((MODE) == DSI_GEN_SHORT_PKT_READ_P0) || \ 01292 ((MODE) == DSI_GEN_SHORT_PKT_READ_P1) || \ 01293 ((MODE) == DSI_GEN_SHORT_PKT_READ_P2)) 01294 #define IS_DSI_COMMUNICATION_DELAY(CommDelay) (((CommDelay) == DSI_SLEW_RATE_HSTX) || ((CommDelay) == DSI_SLEW_RATE_LPTX) || ((CommDelay) == DSI_HS_DELAY)) 01295 #define IS_DSI_LANE_GROUP(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANES)) 01296 #define IS_DSI_CUSTOM_LANE(CustomLane) (((CustomLane) == DSI_SWAP_LANE_PINS) || ((CustomLane) == DSI_INVERT_HS_SIGNAL)) 01297 #define IS_DSI_LANE(Lane) (((Lane) == DSI_CLOCK_LANE) || ((Lane) == DSI_DATA_LANE0) || ((Lane) == DSI_DATA_LANE1)) 01298 #define IS_DSI_PHY_TIMING(Timing) (((Timing) == DSI_TCLK_POST ) || \ 01299 ((Timing) == DSI_TLPX_CLK ) || \ 01300 ((Timing) == DSI_THS_EXIT ) || \ 01301 ((Timing) == DSI_TLPX_DATA ) || \ 01302 ((Timing) == DSI_THS_ZERO ) || \ 01303 ((Timing) == DSI_THS_TRAIL ) || \ 01304 ((Timing) == DSI_THS_PREPARE ) || \ 01305 ((Timing) == DSI_TCLK_ZERO ) || \ 01306 ((Timing) == DSI_TCLK_PREPARE)) 01307 01308 /** 01309 * @} 01310 */ 01311 01312 /* Private functions prototypes ----------------------------------------------*/ 01313 /** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes 01314 * @{ 01315 */ 01316 01317 /** 01318 * @} 01319 */ 01320 01321 /* Private functions ---------------------------------------------------------*/ 01322 /** @defgroup DSI_Private_Functions DSI Private Functions 01323 * @{ 01324 */ 01325 01326 /** 01327 * @} 01328 */ 01329 01330 /** 01331 * @} 01332 */ 01333 01334 /** 01335 * @} 01336 */ 01337 #endif /* DSI */ 01338 01339 #ifdef __cplusplus 01340 } 01341 #endif 01342 01343 #endif /* STM32L4xx_HAL_DSI_H */ 01344 01345 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1