STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dsi.c 00004 * @author MCD Application Team 00005 * @brief DSI HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the DSI peripheral: 00008 * + Initialization and de-initialization functions 00009 * + IO operation functions 00010 * + Peripheral Control functions 00011 * + Peripheral State and Errors functions 00012 @verbatim 00013 ============================================================================== 00014 ##### How to use this driver ##### 00015 ============================================================================== 00016 [..] 00017 (#) Use @ref HAL_DSI_Init() function to initialize the DSI Host IP and program the required 00018 PLL parameters, number of lanes and TX Escape clock divider. 00019 (#) Use @ref HAL_DSI_ConfigAdaptedCommandMode() function to configure the DSI host in adapted 00020 command mode. 00021 (#) When operating in video mode , use @ref HAL_DSI_ConfigVideoMode() to configure the DSI host. 00022 (#) Function @ref HAL_DSI_ConfigCommand() is used to configure the DSI commands behavior in low power mode. 00023 (#) To configure the DSI PHY timings parameters, use function @ref HAL_DSI_ConfigPhyTimer(). 00024 (#) The DSI Host can be started/stopped using respectively functions @ref HAL_DSI_Start() and @ref HAL_DSI_Stop(). 00025 Functions @ref HAL_DSI_ShortWrite(), @ref HAL_DSI_LongWrite() and @ref HAL_DSI_Read() allows respectively 00026 to write DSI short packets, long packets and to read DSI packets. 00027 00028 (#) The DSI Host Offers two Low power modes : 00029 (+) Low Power Mode on data lanes only: Only DSI data lanes are shut down. 00030 It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPMData() 00031 and @ref HAL_DSI_ExitULPMData() 00032 00033 (+) Low Power Mode on data and clock lanes : All DSI lanes are shut down including data and clock lanes. 00034 It is possible to enter/exit from this mode using respectively functions @ref HAL_DSI_EnterULPM() 00035 and @ref HAL_DSI_ExitULPM() 00036 00037 (#) User can select the DSI errors to be reported/monitored using function @ref HAL_DSI_ConfigErrorMonitor() 00038 When an error occurs, the callback @ref HAL_DSI_ErrorCallback() is asserted and then user can retrieve 00039 the error code by calling function @ref HAL_DSI_GetError() 00040 00041 (#) To control DSI state you can use the following function: HAL_DSI_GetState() 00042 00043 *** DSI HAL driver macros list *** 00044 ============================================= 00045 [..] 00046 Below the list of most used macros in DSI HAL driver. 00047 00048 (+) __HAL_DSI_ENABLE: Enable the DSI Host. 00049 (+) __HAL_DSI_DISABLE: Disable the DSI Host. 00050 (+) __HAL_DSI_WRAPPER_ENABLE: Enables the DSI wrapper. 00051 (+) __HAL_DSI_WRAPPER_DISABLE: Disable the DSI wrapper. 00052 (+) __HAL_DSI_PLL_ENABLE: Enables the DSI PLL. 00053 (+) __HAL_DSI_PLL_DISABLE: Disables the DSI PLL. 00054 (+) __HAL_DSI_REG_ENABLE: Enables the DSI regulator. 00055 (+) __HAL_DSI_REG_DISABLE: Disables the DSI regulator. 00056 (+) __HAL_DSI_GET_FLAG: Get the DSI pending flags. 00057 (+) __HAL_DSI_CLEAR_FLAG: Clears the DSI pending flags. 00058 (+) __HAL_DSI_ENABLE_IT: Enables the specified DSI interrupts. 00059 (+) __HAL_DSI_DISABLE_IT: Disables the specified DSI interrupts. 00060 (+) __HAL_DSI_GET_IT_SOURCE: Checks whether the specified DSI interrupt source is enabled or not. 00061 00062 00063 00064 *** Callback registration *** 00065 ============================================= 00066 00067 The compilation define USE_HAL_DSI_REGISTER_CALLBACKS when set to 1 00068 allows the user to configure dynamically the driver callbacks. 00069 Use Function @ref HAL_DSI_RegisterCallback() to register a callback. 00070 00071 Function @ref HAL_DSI_RegisterCallback() allows to register following callbacks: 00072 (+) TearingEffectCallback : DSI Tearing Effect Callback. 00073 (+) EndOfRefreshCallback : DSI End Of Refresh Callback. 00074 (+) ErrorCallback : DSI Error Callback 00075 (+) MspInitCallback : DSI MspInit. 00076 (+) MspDeInitCallback : DSI MspDeInit. 00077 This function takes as parameters the HAL peripheral handle, the Callback ID 00078 and a pointer to the user callback function. 00079 00080 Use function @ref HAL_DSI_UnRegisterCallback() to reset a callback to the default 00081 weak function. 00082 @ref HAL_DSI_UnRegisterCallback takes as parameters the HAL peripheral handle, 00083 and the Callback ID. 00084 This function allows to reset following callbacks: 00085 (+) TearingEffectCallback : DSI Tearing Effect Callback. 00086 (+) EndOfRefreshCallback : DSI End Of Refresh Callback. 00087 (+) ErrorCallback : DSI Error Callback 00088 (+) MspInitCallback : DSI MspInit. 00089 (+) MspDeInitCallback : DSI MspDeInit. 00090 00091 By default, after the HAL_DSI_Init and when the state is HAL_DSI_STATE_RESET 00092 all callbacks are set to the corresponding weak functions: 00093 examples @ref HAL_DSI_TearingEffectCallback(), @ref HAL_DSI_EndOfRefreshCallback(). 00094 Exception done for MspInit and MspDeInit functions that are 00095 reset to the legacy weak function in the HAL_DSI_Init/ @ref HAL_DSI_DeInit only when 00096 these callbacks are null (not registered beforehand). 00097 if not, MspInit or MspDeInit are not null, the @ref HAL_DSI_Init/ @ref HAL_DSI_DeInit 00098 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) 00099 00100 Callbacks can be registered/unregistered in HAL_DSI_STATE_READY state only. 00101 Exception done MspInit/MspDeInit that can be registered/unregistered 00102 in HAL_DSI_STATE_READY or HAL_DSI_STATE_RESET state, 00103 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. 00104 In that case first register the MspInit/MspDeInit user callbacks 00105 using @ref HAL_DSI_RegisterCallback() before calling @ref HAL_DSI_DeInit 00106 or HAL_DSI_Init function. 00107 00108 When The compilation define USE_HAL_DSI_REGISTER_CALLBACKS is set to 0 or 00109 not defined, the callback registration feature is not available and all callbacks 00110 are set to the corresponding weak functions. 00111 00112 [..] 00113 (@) You can refer to the DSI HAL driver header file for more useful macros 00114 00115 @endverbatim 00116 ****************************************************************************** 00117 * @attention 00118 * 00119 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00120 * 00121 * Redistribution and use in source and binary forms, with or without modification, 00122 * are permitted provided that the following conditions are met: 00123 * 1. Redistributions of source code must retain the above copyright notice, 00124 * this list of conditions and the following disclaimer. 00125 * 2. Redistributions in binary form must reproduce the above copyright notice, 00126 * this list of conditions and the following disclaimer in the documentation 00127 * and/or other materials provided with the distribution. 00128 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00129 * may be used to endorse or promote products derived from this software 00130 * without specific prior written permission. 00131 * 00132 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00133 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00134 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00135 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00136 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00137 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00138 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00139 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00140 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00141 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00142 * 00143 ****************************************************************************** 00144 */ 00145 00146 /* Includes ------------------------------------------------------------------*/ 00147 #include "stm32l4xx_hal.h" 00148 00149 /** @addtogroup STM32L4xx_HAL_Driver 00150 * @{ 00151 */ 00152 00153 #ifdef HAL_DSI_MODULE_ENABLED 00154 00155 #if defined(DSI) 00156 00157 /** @addtogroup DSI 00158 * @{ 00159 */ 00160 00161 /* Private types -------------------------------------------------------------*/ 00162 /* Private defines -----------------------------------------------------------*/ 00163 /** @addtogroup DSI_Private_Constants 00164 * @{ 00165 */ 00166 #define DSI_TIMEOUT_VALUE ((uint32_t)1000U) /* 1s */ 00167 00168 #define DSI_ERROR_ACK_MASK (DSI_ISR0_AE0 | DSI_ISR0_AE1 | DSI_ISR0_AE2 | DSI_ISR0_AE3 | \ 00169 DSI_ISR0_AE4 | DSI_ISR0_AE5 | DSI_ISR0_AE6 | DSI_ISR0_AE7 | \ 00170 DSI_ISR0_AE8 | DSI_ISR0_AE9 | DSI_ISR0_AE10 | DSI_ISR0_AE11 | \ 00171 DSI_ISR0_AE12 | DSI_ISR0_AE13 | DSI_ISR0_AE14 | DSI_ISR0_AE15) 00172 #define DSI_ERROR_PHY_MASK (DSI_ISR0_PE0 | DSI_ISR0_PE1 | DSI_ISR0_PE2 | DSI_ISR0_PE3 | DSI_ISR0_PE4) 00173 #define DSI_ERROR_TX_MASK DSI_ISR1_TOHSTX 00174 #define DSI_ERROR_RX_MASK DSI_ISR1_TOLPRX 00175 #define DSI_ERROR_ECC_MASK (DSI_ISR1_ECCSE | DSI_ISR1_ECCME) 00176 #define DSI_ERROR_CRC_MASK DSI_ISR1_CRCE 00177 #define DSI_ERROR_PSE_MASK DSI_ISR1_PSE 00178 #define DSI_ERROR_EOT_MASK DSI_ISR1_EOTPE 00179 #define DSI_ERROR_OVF_MASK DSI_ISR1_LPWRE 00180 #define DSI_ERROR_GEN_MASK (DSI_ISR1_GCWRE | DSI_ISR1_GPWRE | DSI_ISR1_GPTXE | DSI_ISR1_GPRDE | DSI_ISR1_GPRXE) 00181 /** 00182 * @} 00183 */ 00184 00185 /* Private variables ---------------------------------------------------------*/ 00186 /* Private constants ---------------------------------------------------------*/ 00187 /* Private macros ------------------------------------------------------------*/ 00188 /* Private function prototypes -----------------------------------------------*/ 00189 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, uint32_t ChannelID, uint32_t DataType, uint32_t Data0, uint32_t Data1); 00190 00191 /* Private functions ---------------------------------------------------------*/ 00192 /** 00193 * @brief Generic DSI packet header configuration 00194 * @param DSIx Pointer to DSI register base 00195 * @param ChannelID Virtual channel ID of the header packet 00196 * @param DataType Packet data type of the header packet 00197 * This parameter can be any value of : 00198 * @ref DSI_SHORT_WRITE_PKT_Data_Type 00199 * or @ref DSI_LONG_WRITE_PKT_Data_Type 00200 * or @ref DSI_SHORT_READ_PKT_Data_Type 00201 * or DSI_MAX_RETURN_PKT_SIZE 00202 * @param Data0 Word count LSB 00203 * @param Data1 Word count MSB 00204 * @retval None 00205 */ 00206 static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, 00207 uint32_t ChannelID, 00208 uint32_t DataType, 00209 uint32_t Data0, 00210 uint32_t Data1) 00211 { 00212 /* Update the DSI packet header with new information */ 00213 DSIx->GHCR = (DataType | (ChannelID<<6U) | (Data0<<8U) | (Data1<<16U)); 00214 } 00215 00216 /* Exported functions --------------------------------------------------------*/ 00217 /** @addtogroup DSI_Exported_Functions 00218 * @{ 00219 */ 00220 00221 /** @defgroup DSI_Group1 Initialization and Configuration functions 00222 * @brief Initialization and Configuration functions 00223 * 00224 @verbatim 00225 =============================================================================== 00226 ##### Initialization and Configuration functions ##### 00227 =============================================================================== 00228 [..] This section provides functions allowing to: 00229 (+) Initialize and configure the DSI 00230 (+) De-initialize the DSI 00231 00232 @endverbatim 00233 * @{ 00234 */ 00235 00236 /** 00237 * @brief Initializes the DSI according to the specified 00238 * parameters in the DSI_InitTypeDef and create the associated handle. 00239 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00240 * the configuration information for the DSI. 00241 * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains 00242 * the PLL Clock structure definition for the DSI. 00243 * @retval HAL status 00244 */ 00245 HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit) 00246 { 00247 uint32_t tickstart; 00248 uint32_t unitIntervalx4; 00249 uint32_t tempIDF; 00250 00251 /* Check the DSI handle allocation */ 00252 if(hdsi == NULL) 00253 { 00254 return HAL_ERROR; 00255 } 00256 00257 /* Check function parameters */ 00258 assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV)); 00259 assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF)); 00260 assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF)); 00261 assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl)); 00262 assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes)); 00263 00264 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00265 if(hdsi->State == HAL_DSI_STATE_RESET) 00266 { 00267 /* Reset the DSI callback to the legacy weak callbacks */ 00268 hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ 00269 hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ 00270 hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ 00271 00272 if(hdsi->MspInitCallback == NULL) 00273 { 00274 hdsi->MspInitCallback = HAL_DSI_MspInit; 00275 } 00276 /* Initialize the low level hardware */ 00277 hdsi->MspInitCallback(hdsi); 00278 } 00279 #else 00280 if(hdsi->State == HAL_DSI_STATE_RESET) 00281 { 00282 /* Initialize the low level hardware */ 00283 HAL_DSI_MspInit(hdsi); 00284 } 00285 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00286 00287 /* Change DSI peripheral state */ 00288 hdsi->State = HAL_DSI_STATE_BUSY; 00289 00290 /**************** Turn on the regulator and enable the DSI PLL ****************/ 00291 00292 /* Enable the regulator */ 00293 __HAL_DSI_REG_ENABLE(hdsi); 00294 00295 /* Get tick */ 00296 tickstart = HAL_GetTick(); 00297 00298 /* Wait until the regulator is ready */ 00299 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == 0U) 00300 { 00301 /* Check for the Timeout */ 00302 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 00303 { 00304 return HAL_TIMEOUT; 00305 } 00306 } 00307 00308 /* Set the PLL division factors */ 00309 hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF); 00310 hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U)); 00311 00312 /* Enable the DSI PLL */ 00313 __HAL_DSI_PLL_ENABLE(hdsi); 00314 00315 /* Get tick */ 00316 tickstart = HAL_GetTick(); 00317 00318 /* Wait for the lock of the PLL */ 00319 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) 00320 { 00321 /* Check for the Timeout */ 00322 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 00323 { 00324 return HAL_TIMEOUT; 00325 } 00326 } 00327 00328 /*************************** Set the PHY parameters ***************************/ 00329 00330 /* D-PHY clock and digital enable*/ 00331 hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN); 00332 00333 /* Clock lane configuration */ 00334 hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR); 00335 hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl); 00336 00337 /* Configure the number of active data lanes */ 00338 hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL; 00339 hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes; 00340 00341 /************************ Set the DSI clock parameters ************************/ 00342 00343 /* Set the TX escape clock division factor */ 00344 hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV; 00345 hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv; 00346 00347 /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */ 00348 /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */ 00349 /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */ 00350 tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U; 00351 unitIntervalx4 = (4000000U * tempIDF * ((1UL << PLLInit->PLLODF))) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV); 00352 00353 /* Set the bit period in high-speed mode */ 00354 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4; 00355 hdsi->Instance->WPCR[0U] |= unitIntervalx4; 00356 00357 /****************************** Error management *****************************/ 00358 00359 /* Disable all error interrupts and reset the Error Mask */ 00360 hdsi->Instance->IER[0U] = 0U; 00361 hdsi->Instance->IER[1U] = 0U; 00362 hdsi->ErrorMsk = 0U; 00363 00364 /* Initialise the error code */ 00365 hdsi->ErrorCode = HAL_DSI_ERROR_NONE; 00366 00367 /* Initialize the DSI state*/ 00368 hdsi->State = HAL_DSI_STATE_READY; 00369 00370 return HAL_OK; 00371 } 00372 00373 /** 00374 * @brief De-initializes the DSI peripheral registers to their default reset 00375 * values. 00376 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00377 * the configuration information for the DSI. 00378 * @retval HAL status 00379 */ 00380 HAL_StatusTypeDef HAL_DSI_DeInit(DSI_HandleTypeDef *hdsi) 00381 { 00382 /* Check the DSI handle allocation */ 00383 if(hdsi == NULL) 00384 { 00385 return HAL_ERROR; 00386 } 00387 00388 /* Change DSI peripheral state */ 00389 hdsi->State = HAL_DSI_STATE_BUSY; 00390 00391 /* Disable the DSI wrapper */ 00392 __HAL_DSI_WRAPPER_DISABLE(hdsi); 00393 00394 /* Disable the DSI host */ 00395 __HAL_DSI_DISABLE(hdsi); 00396 00397 /* D-PHY clock and digital disable */ 00398 hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN); 00399 00400 /* Turn off the DSI PLL */ 00401 __HAL_DSI_PLL_DISABLE(hdsi); 00402 00403 /* Disable the regulator */ 00404 __HAL_DSI_REG_DISABLE(hdsi); 00405 00406 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00407 if(hdsi->MspDeInitCallback == NULL) 00408 { 00409 hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; 00410 } 00411 /* DeInit the low level hardware */ 00412 hdsi->MspDeInitCallback(hdsi); 00413 #else 00414 /* DeInit the low level hardware */ 00415 HAL_DSI_MspDeInit(hdsi); 00416 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00417 00418 /* Initialise the error code */ 00419 hdsi->ErrorCode = HAL_DSI_ERROR_NONE; 00420 00421 /* Initialize the DSI state*/ 00422 hdsi->State = HAL_DSI_STATE_RESET; 00423 00424 /* Release Lock */ 00425 __HAL_UNLOCK(hdsi); 00426 00427 return HAL_OK; 00428 } 00429 00430 /** 00431 * @brief Enable the error monitor flags 00432 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00433 * the configuration information for the DSI. 00434 * @param ActiveErrors indicates which error interrupts will be enabled. 00435 * This parameter can be any combination of @ref DSI_Error_Data_Type. 00436 * @retval HAL status 00437 */ 00438 HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors) 00439 { 00440 /* Process locked */ 00441 __HAL_LOCK(hdsi); 00442 00443 hdsi->Instance->IER[0U] = 0U; 00444 hdsi->Instance->IER[1U] = 0U; 00445 00446 /* Store active errors to the handle */ 00447 hdsi->ErrorMsk = ActiveErrors; 00448 00449 if((ActiveErrors & HAL_DSI_ERROR_ACK) != 0U) 00450 { 00451 /* Enable the interrupt generation on selected errors */ 00452 hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK; 00453 } 00454 00455 if((ActiveErrors & HAL_DSI_ERROR_PHY) != 0U) 00456 { 00457 /* Enable the interrupt generation on selected errors */ 00458 hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK; 00459 } 00460 00461 if((ActiveErrors & HAL_DSI_ERROR_TX) != 0U) 00462 { 00463 /* Enable the interrupt generation on selected errors */ 00464 hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK; 00465 } 00466 00467 if((ActiveErrors & HAL_DSI_ERROR_RX) != 0U) 00468 { 00469 /* Enable the interrupt generation on selected errors */ 00470 hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK; 00471 } 00472 00473 if((ActiveErrors & HAL_DSI_ERROR_ECC) != 0U) 00474 { 00475 /* Enable the interrupt generation on selected errors */ 00476 hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK; 00477 } 00478 00479 if((ActiveErrors & HAL_DSI_ERROR_CRC) != 0U) 00480 { 00481 /* Enable the interrupt generation on selected errors */ 00482 hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK; 00483 } 00484 00485 if((ActiveErrors & HAL_DSI_ERROR_PSE) != 0U) 00486 { 00487 /* Enable the interrupt generation on selected errors */ 00488 hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK; 00489 } 00490 00491 if((ActiveErrors & HAL_DSI_ERROR_EOT) != 0U) 00492 { 00493 /* Enable the interrupt generation on selected errors */ 00494 hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK; 00495 } 00496 00497 if((ActiveErrors & HAL_DSI_ERROR_OVF) != 0U) 00498 { 00499 /* Enable the interrupt generation on selected errors */ 00500 hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK; 00501 } 00502 00503 if((ActiveErrors & HAL_DSI_ERROR_GEN) != 0U) 00504 { 00505 /* Enable the interrupt generation on selected errors */ 00506 hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK; 00507 } 00508 00509 /* Process Unlocked */ 00510 __HAL_UNLOCK(hdsi); 00511 00512 return HAL_OK; 00513 } 00514 00515 /** 00516 * @brief Initializes the DSI MSP. 00517 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00518 * the configuration information for the DSI. 00519 * @retval None 00520 */ 00521 __weak void HAL_DSI_MspInit(DSI_HandleTypeDef* hdsi) 00522 { 00523 /* Prevent unused argument(s) compilation warning */ 00524 UNUSED(hdsi); 00525 /* NOTE : This function Should not be modified, when the callback is needed, 00526 the HAL_DSI_MspInit could be implemented in the user file 00527 */ 00528 } 00529 00530 /** 00531 * @brief De-initializes the DSI MSP. 00532 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00533 * the configuration information for the DSI. 00534 * @retval None 00535 */ 00536 __weak void HAL_DSI_MspDeInit(DSI_HandleTypeDef* hdsi) 00537 { 00538 /* Prevent unused argument(s) compilation warning */ 00539 UNUSED(hdsi); 00540 /* NOTE : This function Should not be modified, when the callback is needed, 00541 the HAL_DSI_MspDeInit could be implemented in the user file 00542 */ 00543 } 00544 00545 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00546 /** 00547 * @brief Register a User DSI Callback 00548 * To be used instead of the weak predefined callback 00549 * @param hdsi dsi handle 00550 * @param CallbackID ID of the callback to be registered 00551 * This parameter can be one of the following values: 00552 * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID 00553 * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID 00554 * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID 00555 * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID 00556 * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID 00557 * @param pCallback pointer to the Callback function 00558 * @retval status 00559 */ 00560 HAL_StatusTypeDef HAL_DSI_RegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID, pDSI_CallbackTypeDef pCallback) 00561 { 00562 HAL_StatusTypeDef status = HAL_OK; 00563 00564 if(pCallback == NULL) 00565 { 00566 /* Update the error code */ 00567 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; 00568 00569 return HAL_ERROR; 00570 } 00571 /* Process locked */ 00572 __HAL_LOCK(hdsi); 00573 00574 if(hdsi->State == HAL_DSI_STATE_READY) 00575 { 00576 switch (CallbackID) 00577 { 00578 case HAL_DSI_TEARING_EFFECT_CB_ID : 00579 hdsi->TearingEffectCallback = pCallback; 00580 break; 00581 00582 case HAL_DSI_ENDOF_REFRESH_CB_ID : 00583 hdsi->EndOfRefreshCallback = pCallback; 00584 break; 00585 00586 case HAL_DSI_ERROR_CB_ID : 00587 hdsi->ErrorCallback = pCallback; 00588 break; 00589 00590 case HAL_DSI_MSPINIT_CB_ID : 00591 hdsi->MspInitCallback = pCallback; 00592 break; 00593 00594 case HAL_DSI_MSPDEINIT_CB_ID : 00595 hdsi->MspDeInitCallback = pCallback; 00596 break; 00597 00598 default : 00599 /* Update the error code */ 00600 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; 00601 /* Return error status */ 00602 status = HAL_ERROR; 00603 break; 00604 } 00605 } 00606 else if(hdsi->State == HAL_DSI_STATE_RESET) 00607 { 00608 switch (CallbackID) 00609 { 00610 case HAL_DSI_MSPINIT_CB_ID : 00611 hdsi->MspInitCallback = pCallback; 00612 break; 00613 00614 case HAL_DSI_MSPDEINIT_CB_ID : 00615 hdsi->MspDeInitCallback = pCallback; 00616 break; 00617 00618 default : 00619 /* Update the error code */ 00620 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; 00621 /* Return error status */ 00622 status = HAL_ERROR; 00623 break; 00624 } 00625 } 00626 else 00627 { 00628 /* Update the error code */ 00629 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; 00630 /* Return error status */ 00631 status = HAL_ERROR; 00632 } 00633 00634 /* Release Lock */ 00635 __HAL_UNLOCK(hdsi); 00636 00637 return status; 00638 } 00639 00640 /** 00641 * @brief Unregister a DSI Callback 00642 * DSI callabck is redirected to the weak predefined callback 00643 * @param hdsi dsi handle 00644 * @param CallbackID ID of the callback to be unregistered 00645 * This parameter can be one of the following values: 00646 * @arg @ref HAL_DSI_TEARING_EFFECT_CB_ID Tearing Effect Callback ID 00647 * @arg @ref HAL_DSI_ENDOF_REFRESH_CB_ID End Of Refresh Callback ID 00648 * @arg @ref HAL_DSI_ERROR_CB_ID Error Callback ID 00649 * @arg @ref HAL_DSI_MSPINIT_CB_ID MspInit callback ID 00650 * @arg @ref HAL_DSI_MSPDEINIT_CB_ID MspDeInit callback ID 00651 * @retval status 00652 */ 00653 HAL_StatusTypeDef HAL_DSI_UnRegisterCallback(DSI_HandleTypeDef *hdsi, HAL_DSI_CallbackIDTypeDef CallbackID) 00654 { 00655 HAL_StatusTypeDef status = HAL_OK; 00656 00657 /* Process locked */ 00658 __HAL_LOCK(hdsi); 00659 00660 if(hdsi->State == HAL_DSI_STATE_READY) 00661 { 00662 switch (CallbackID) 00663 { 00664 case HAL_DSI_TEARING_EFFECT_CB_ID : 00665 hdsi->TearingEffectCallback = HAL_DSI_TearingEffectCallback; /* Legacy weak TearingEffectCallback */ 00666 break; 00667 00668 case HAL_DSI_ENDOF_REFRESH_CB_ID : 00669 hdsi->EndOfRefreshCallback = HAL_DSI_EndOfRefreshCallback; /* Legacy weak EndOfRefreshCallback */ 00670 break; 00671 00672 case HAL_DSI_ERROR_CB_ID : 00673 hdsi->ErrorCallback = HAL_DSI_ErrorCallback; /* Legacy weak ErrorCallback */ 00674 break; 00675 00676 case HAL_DSI_MSPINIT_CB_ID : 00677 hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ 00678 break; 00679 00680 case HAL_DSI_MSPDEINIT_CB_ID : 00681 hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ 00682 break; 00683 00684 default : 00685 /* Update the error code */ 00686 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; 00687 /* Return error status */ 00688 status = HAL_ERROR; 00689 break; 00690 } 00691 } 00692 else if(hdsi->State == HAL_DSI_STATE_RESET) 00693 { 00694 switch (CallbackID) 00695 { 00696 case HAL_DSI_MSPINIT_CB_ID : 00697 hdsi->MspInitCallback = HAL_DSI_MspInit; /* Legcay weak MspInit Callback */ 00698 break; 00699 00700 case HAL_DSI_MSPDEINIT_CB_ID : 00701 hdsi->MspDeInitCallback = HAL_DSI_MspDeInit; /* Legcay weak MspDeInit Callback */ 00702 break; 00703 00704 default : 00705 /* Update the error code */ 00706 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; 00707 /* Return error status */ 00708 status = HAL_ERROR; 00709 break; 00710 } 00711 } 00712 else 00713 { 00714 /* Update the error code */ 00715 hdsi->ErrorCode |= HAL_DSI_ERROR_INVALID_CALLBACK; 00716 /* Return error status */ 00717 status = HAL_ERROR; 00718 } 00719 00720 /* Release Lock */ 00721 __HAL_UNLOCK(hdsi); 00722 00723 return status; 00724 } 00725 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00726 00727 /** 00728 * @} 00729 */ 00730 00731 /** @defgroup DSI_Group2 IO operation functions 00732 * @brief IO operation functions 00733 * 00734 @verbatim 00735 =============================================================================== 00736 ##### IO operation functions ##### 00737 =============================================================================== 00738 [..] This section provides function allowing to: 00739 (+) Handle DSI interrupt request 00740 00741 @endverbatim 00742 * @{ 00743 */ 00744 /** 00745 * @brief Handles DSI interrupt request. 00746 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00747 * the configuration information for the DSI. 00748 * @retval HAL status 00749 */ 00750 void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi) 00751 { 00752 uint32_t ErrorStatus0, ErrorStatus1; 00753 00754 /* Tearing Effect Interrupt management ***************************************/ 00755 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != 0U) 00756 { 00757 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_TE) != 0U) 00758 { 00759 /* Clear the Tearing Effect Interrupt Flag */ 00760 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE); 00761 00762 /* Tearing Effect Callback */ 00763 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00764 /*Call registered Tearing Effect callback */ 00765 hdsi->TearingEffectCallback(hdsi); 00766 #else 00767 /*Call legacy Tearing Effect callback*/ 00768 HAL_DSI_TearingEffectCallback(hdsi); 00769 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00770 } 00771 } 00772 00773 /* End of Refresh Interrupt management ***************************************/ 00774 if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != 0U) 00775 { 00776 if(__HAL_DSI_GET_IT_SOURCE(hdsi, DSI_IT_ER) != 0U) 00777 { 00778 /* Clear the End of Refresh Interrupt Flag */ 00779 __HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER); 00780 00781 /* End of Refresh Callback */ 00782 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00783 /*Call registered End of refresh callback */ 00784 hdsi->EndOfRefreshCallback(hdsi); 00785 #else 00786 /*Call Legacy End of refresh callback */ 00787 HAL_DSI_EndOfRefreshCallback(hdsi); 00788 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00789 } 00790 } 00791 00792 /* Error Interrupts management ***********************************************/ 00793 if(hdsi->ErrorMsk != 0U) 00794 { 00795 ErrorStatus0 = hdsi->Instance->ISR[0U]; 00796 ErrorStatus0 &= hdsi->Instance->IER[0U]; 00797 ErrorStatus1 = hdsi->Instance->ISR[1U]; 00798 ErrorStatus1 &= hdsi->Instance->IER[1U]; 00799 00800 if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != 0U) 00801 { 00802 hdsi->ErrorCode |= HAL_DSI_ERROR_ACK; 00803 } 00804 00805 if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != 0U) 00806 { 00807 hdsi->ErrorCode |= HAL_DSI_ERROR_PHY; 00808 } 00809 00810 if((ErrorStatus1 & DSI_ERROR_TX_MASK) != 0U) 00811 { 00812 hdsi->ErrorCode |= HAL_DSI_ERROR_TX; 00813 } 00814 00815 if((ErrorStatus1 & DSI_ERROR_RX_MASK) != 0U) 00816 { 00817 hdsi->ErrorCode |= HAL_DSI_ERROR_RX; 00818 } 00819 00820 if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != 0U) 00821 { 00822 hdsi->ErrorCode |= HAL_DSI_ERROR_ECC; 00823 } 00824 00825 if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != 0U) 00826 { 00827 hdsi->ErrorCode |= HAL_DSI_ERROR_CRC; 00828 } 00829 00830 if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != 0U) 00831 { 00832 hdsi->ErrorCode |= HAL_DSI_ERROR_PSE; 00833 } 00834 00835 if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != 0U) 00836 { 00837 hdsi->ErrorCode |= HAL_DSI_ERROR_EOT; 00838 } 00839 00840 if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != 0U) 00841 { 00842 hdsi->ErrorCode |= HAL_DSI_ERROR_OVF; 00843 } 00844 00845 if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != 0U) 00846 { 00847 hdsi->ErrorCode |= HAL_DSI_ERROR_GEN; 00848 } 00849 00850 /* Check only selected errors */ 00851 if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE) 00852 { 00853 /* DSI error interrupt callback */ 00854 #if (USE_HAL_DSI_REGISTER_CALLBACKS == 1) 00855 /*Call registered Error callback */ 00856 hdsi->ErrorCallback(hdsi); 00857 #else 00858 /*Call Legacy Error callback */ 00859 HAL_DSI_ErrorCallback(hdsi); 00860 #endif /* USE_HAL_DSI_REGISTER_CALLBACKS */ 00861 } 00862 } 00863 } 00864 00865 /** 00866 * @brief Tearing Effect DSI callback. 00867 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00868 * the configuration information for the DSI. 00869 * @retval None 00870 */ 00871 __weak void HAL_DSI_TearingEffectCallback(DSI_HandleTypeDef *hdsi) 00872 { 00873 /* Prevent unused argument(s) compilation warning */ 00874 UNUSED(hdsi); 00875 /* NOTE : This function Should not be modified, when the callback is needed, 00876 the HAL_DSI_TearingEffectCallback could be implemented in the user file 00877 */ 00878 } 00879 00880 /** 00881 * @brief End of Refresh DSI callback. 00882 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00883 * the configuration information for the DSI. 00884 * @retval None 00885 */ 00886 __weak void HAL_DSI_EndOfRefreshCallback(DSI_HandleTypeDef *hdsi) 00887 { 00888 /* Prevent unused argument(s) compilation warning */ 00889 UNUSED(hdsi); 00890 /* NOTE : This function Should not be modified, when the callback is needed, 00891 the HAL_DSI_EndOfRefreshCallback could be implemented in the user file 00892 */ 00893 } 00894 00895 /** 00896 * @brief Operation Error DSI callback. 00897 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00898 * the configuration information for the DSI. 00899 * @retval None 00900 */ 00901 __weak void HAL_DSI_ErrorCallback(DSI_HandleTypeDef *hdsi) 00902 { 00903 /* Prevent unused argument(s) compilation warning */ 00904 UNUSED(hdsi); 00905 /* NOTE : This function Should not be modified, when the callback is needed, 00906 the HAL_DSI_ErrorCallback could be implemented in the user file 00907 */ 00908 } 00909 00910 /** 00911 * @} 00912 */ 00913 00914 /** @defgroup DSI_Group3 Peripheral Control functions 00915 * @brief Peripheral Control functions 00916 * 00917 @verbatim 00918 =============================================================================== 00919 ##### Peripheral Control functions ##### 00920 =============================================================================== 00921 [..] This section provides functions allowing to: 00922 (+) Configure the Generic interface read-back Virtual Channel ID 00923 (+) Select video mode and configure the corresponding parameters 00924 (+) Configure command transmission mode: High-speed or Low-power 00925 (+) Configure the flow control 00926 (+) Configure the DSI PHY timer 00927 (+) Configure the DSI HOST timeout 00928 (+) Configure the DSI HOST timeout 00929 (+) Start/Stop the DSI module 00930 (+) Refresh the display in command mode 00931 (+) Controls the display color mode in Video mode 00932 (+) Control the display shutdown in Video mode 00933 (+) write short DCS or short Generic command 00934 (+) write long DCS or long Generic command 00935 (+) Read command (DCS or generic) 00936 (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running) 00937 (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off) 00938 (+) Start/Stop test pattern generation 00939 (+) Slew-Rate And Delay Tuning 00940 (+) Low-Power Reception Filter Tuning 00941 (+) Activate an additional current path on all lanes to meet the SDDTx parameter 00942 (+) Custom lane pins configuration 00943 (+) Set custom timing for the PHY 00944 (+) Force the Clock/Data Lane in TX Stop Mode 00945 (+) Force LP Receiver in Low-Power Mode 00946 (+) Force Data Lanes in RX Mode after a BTA 00947 (+) Enable a pull-down on the lanes to prevent from floating states when unused 00948 (+) Switch off the contention detection on data lanes 00949 00950 @endverbatim 00951 * @{ 00952 */ 00953 00954 /** 00955 * @brief Configure the Generic interface read-back Virtual Channel ID. 00956 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00957 * the configuration information for the DSI. 00958 * @param VirtualChannelID Virtual channel ID 00959 * @retval HAL status 00960 */ 00961 HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) 00962 { 00963 /* Process locked */ 00964 __HAL_LOCK(hdsi); 00965 00966 /* Update the GVCID register */ 00967 hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID; 00968 hdsi->Instance->GVCIDR |= VirtualChannelID; 00969 00970 /* Process unlocked */ 00971 __HAL_UNLOCK(hdsi); 00972 00973 return HAL_OK; 00974 } 00975 00976 /** 00977 * @brief Select video mode and configure the corresponding parameters 00978 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 00979 * the configuration information for the DSI. 00980 * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains 00981 * the DSI video mode configuration parameters 00982 * @retval HAL status 00983 */ 00984 HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg) 00985 { 00986 /* Process locked */ 00987 __HAL_LOCK(hdsi); 00988 00989 /* Check the parameters */ 00990 assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding)); 00991 assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode)); 00992 assert_param(IS_DSI_LP_COMMAND(VidCfg->LPCommandEnable)); 00993 assert_param(IS_DSI_LP_HFP(VidCfg->LPHorizontalFrontPorchEnable)); 00994 assert_param(IS_DSI_LP_HBP(VidCfg->LPHorizontalBackPorchEnable)); 00995 assert_param(IS_DSI_LP_VACTIVE(VidCfg->LPVerticalActiveEnable)); 00996 assert_param(IS_DSI_LP_VFP(VidCfg->LPVerticalFrontPorchEnable)); 00997 assert_param(IS_DSI_LP_VBP(VidCfg->LPVerticalBackPorchEnable)); 00998 assert_param(IS_DSI_LP_VSYNC(VidCfg->LPVerticalSyncActiveEnable)); 00999 assert_param(IS_DSI_FBTAA(VidCfg->FrameBTAAcknowledgeEnable)); 01000 assert_param(IS_DSI_DE_POLARITY(VidCfg->DEPolarity)); 01001 assert_param(IS_DSI_VSYNC_POLARITY(VidCfg->VSPolarity)); 01002 assert_param(IS_DSI_HSYNC_POLARITY(VidCfg->HSPolarity)); 01003 /* Check the LooselyPacked variant only in 18-bit mode */ 01004 if(VidCfg->ColorCoding == DSI_RGB666) 01005 { 01006 assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked)); 01007 } 01008 01009 /* Select video mode by resetting CMDM and DSIM bits */ 01010 hdsi->Instance->MCR &= ~DSI_MCR_CMDM; 01011 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; 01012 01013 /* Configure the video mode transmission type */ 01014 hdsi->Instance->VMCR &= ~DSI_VMCR_VMT; 01015 hdsi->Instance->VMCR |= VidCfg->Mode; 01016 01017 /* Configure the video packet size */ 01018 hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE; 01019 hdsi->Instance->VPCR |= VidCfg->PacketSize; 01020 01021 /* Set the chunks number to be transmitted through the DSI link */ 01022 hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC; 01023 hdsi->Instance->VCCR |= VidCfg->NumberOfChunks; 01024 01025 /* Set the size of the null packet */ 01026 hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE; 01027 hdsi->Instance->VNPCR |= VidCfg->NullPacketSize; 01028 01029 /* Select the virtual channel for the LTDC interface traffic */ 01030 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; 01031 hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID; 01032 01033 /* Configure the polarity of control signals */ 01034 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); 01035 hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity); 01036 01037 /* Select the color coding for the host */ 01038 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; 01039 hdsi->Instance->LCOLCR |= VidCfg->ColorCoding; 01040 01041 /* Select the color coding for the wrapper */ 01042 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; 01043 hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U); 01044 01045 /* Enable/disable the loosely packed variant to 18-bit configuration */ 01046 if(VidCfg->ColorCoding == DSI_RGB666) 01047 { 01048 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE; 01049 hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked; 01050 } 01051 01052 /* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */ 01053 hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA; 01054 hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive; 01055 01056 /* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */ 01057 hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP; 01058 hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch; 01059 01060 /* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */ 01061 hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE; 01062 hdsi->Instance->VLCR |= VidCfg->HorizontalLine; 01063 01064 /* Set the Vertical Synchronization Active (VSA) */ 01065 hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA; 01066 hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive; 01067 01068 /* Set the Vertical Back Porch (VBP)*/ 01069 hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP; 01070 hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch; 01071 01072 /* Set the Vertical Front Porch (VFP)*/ 01073 hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP; 01074 hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch; 01075 01076 /* Set the Vertical Active period*/ 01077 hdsi->Instance->VVACR &= ~DSI_VVACR_VA; 01078 hdsi->Instance->VVACR |= VidCfg->VerticalActive; 01079 01080 /* Configure the command transmission mode */ 01081 hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE; 01082 hdsi->Instance->VMCR |= VidCfg->LPCommandEnable; 01083 01084 /* Low power largest packet size */ 01085 hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE; 01086 hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U); 01087 01088 /* Low power VACT largest packet size */ 01089 hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE; 01090 hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize; 01091 01092 /* Enable LP transition in HFP period */ 01093 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE; 01094 hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable; 01095 01096 /* Enable LP transition in HBP period */ 01097 hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE; 01098 hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable; 01099 01100 /* Enable LP transition in VACT period */ 01101 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE; 01102 hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable; 01103 01104 /* Enable LP transition in VFP period */ 01105 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE; 01106 hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable; 01107 01108 /* Enable LP transition in VBP period */ 01109 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE; 01110 hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable; 01111 01112 /* Enable LP transition in vertical sync period */ 01113 hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE; 01114 hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable; 01115 01116 /* Enable the request for an acknowledge response at the end of a frame */ 01117 hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE; 01118 hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable; 01119 01120 /* Process unlocked */ 01121 __HAL_UNLOCK(hdsi); 01122 01123 return HAL_OK; 01124 } 01125 01126 /** 01127 * @brief Select adapted command mode and configure the corresponding parameters 01128 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01129 * the configuration information for the DSI. 01130 * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains 01131 * the DSI command mode configuration parameters 01132 * @retval HAL status 01133 */ 01134 HAL_StatusTypeDef HAL_DSI_ConfigAdaptedCommandMode(DSI_HandleTypeDef *hdsi, DSI_CmdCfgTypeDef *CmdCfg) 01135 { 01136 /* Process locked */ 01137 __HAL_LOCK(hdsi); 01138 01139 /* Check the parameters */ 01140 assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding)); 01141 assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource)); 01142 assert_param(IS_DSI_TE_POLARITY(CmdCfg->TearingEffectPolarity)); 01143 assert_param(IS_DSI_AUTOMATIC_REFRESH(CmdCfg->AutomaticRefresh)); 01144 assert_param(IS_DSI_VS_POLARITY(CmdCfg->VSyncPol)); 01145 assert_param(IS_DSI_TE_ACK_REQUEST(CmdCfg->TEAcknowledgeRequest)); 01146 assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity)); 01147 assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity)); 01148 assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity)); 01149 01150 /* Select command mode by setting CMDM and DSIM bits */ 01151 hdsi->Instance->MCR |= DSI_MCR_CMDM; 01152 hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM; 01153 hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM; 01154 01155 /* Select the virtual channel for the LTDC interface traffic */ 01156 hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID; 01157 hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID; 01158 01159 /* Configure the polarity of control signals */ 01160 hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP); 01161 hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity); 01162 01163 /* Select the color coding for the host */ 01164 hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC; 01165 hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding; 01166 01167 /* Select the color coding for the wrapper */ 01168 hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX; 01169 hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U); 01170 01171 /* Configure the maximum allowed size for write memory command */ 01172 hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE; 01173 hdsi->Instance->LCCR |= CmdCfg->CommandSize; 01174 01175 /* Configure the tearing effect source and polarity and select the refresh mode */ 01176 hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL); 01177 hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol); 01178 01179 /* Configure the tearing effect acknowledge request */ 01180 hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE; 01181 hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest; 01182 01183 /* Enable the Tearing Effect interrupt */ 01184 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE); 01185 01186 /* Enable the End of Refresh interrupt */ 01187 __HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER); 01188 01189 /* Process unlocked */ 01190 __HAL_UNLOCK(hdsi); 01191 01192 return HAL_OK; 01193 } 01194 01195 /** 01196 * @brief Configure command transmission mode: High-speed or Low-power 01197 * and enable/disable acknowledge request after packet transmission 01198 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01199 * the configuration information for the DSI. 01200 * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains 01201 * the DSI command transmission mode configuration parameters 01202 * @retval HAL status 01203 */ 01204 HAL_StatusTypeDef HAL_DSI_ConfigCommand(DSI_HandleTypeDef *hdsi, DSI_LPCmdTypeDef *LPCmd) 01205 { 01206 /* Process locked */ 01207 __HAL_LOCK(hdsi); 01208 01209 assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP)); 01210 assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP)); 01211 assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP)); 01212 assert_param(IS_DSI_LP_GSR0P(LPCmd->LPGenShortReadNoP)); 01213 assert_param(IS_DSI_LP_GSR1P(LPCmd->LPGenShortReadOneP)); 01214 assert_param(IS_DSI_LP_GSR2P(LPCmd->LPGenShortReadTwoP)); 01215 assert_param(IS_DSI_LP_GLW(LPCmd->LPGenLongWrite)); 01216 assert_param(IS_DSI_LP_DSW0P(LPCmd->LPDcsShortWriteNoP)); 01217 assert_param(IS_DSI_LP_DSW1P(LPCmd->LPDcsShortWriteOneP)); 01218 assert_param(IS_DSI_LP_DSR0P(LPCmd->LPDcsShortReadNoP)); 01219 assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite)); 01220 assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket)); 01221 assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest)); 01222 01223 /* Select High-speed or Low-power for command transmission */ 01224 hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\ 01225 DSI_CMCR_GSW1TX |\ 01226 DSI_CMCR_GSW2TX |\ 01227 DSI_CMCR_GSR0TX |\ 01228 DSI_CMCR_GSR1TX |\ 01229 DSI_CMCR_GSR2TX |\ 01230 DSI_CMCR_GLWTX |\ 01231 DSI_CMCR_DSW0TX |\ 01232 DSI_CMCR_DSW1TX |\ 01233 DSI_CMCR_DSR0TX |\ 01234 DSI_CMCR_DLWTX |\ 01235 DSI_CMCR_MRDPS); 01236 hdsi->Instance->CMCR |= (LPCmd->LPGenShortWriteNoP |\ 01237 LPCmd->LPGenShortWriteOneP |\ 01238 LPCmd->LPGenShortWriteTwoP |\ 01239 LPCmd->LPGenShortReadNoP |\ 01240 LPCmd->LPGenShortReadOneP |\ 01241 LPCmd->LPGenShortReadTwoP |\ 01242 LPCmd->LPGenLongWrite |\ 01243 LPCmd->LPDcsShortWriteNoP |\ 01244 LPCmd->LPDcsShortWriteOneP |\ 01245 LPCmd->LPDcsShortReadNoP |\ 01246 LPCmd->LPDcsLongWrite |\ 01247 LPCmd->LPMaxReadPacket); 01248 01249 /* Configure the acknowledge request after each packet transmission */ 01250 hdsi->Instance->CMCR &= ~DSI_CMCR_ARE; 01251 hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest; 01252 01253 /* Process unlocked */ 01254 __HAL_UNLOCK(hdsi); 01255 01256 return HAL_OK; 01257 } 01258 01259 /** 01260 * @brief Configure the flow control parameters 01261 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01262 * the configuration information for the DSI. 01263 * @param FlowControl flow control feature(s) to be enabled. 01264 * This parameter can be any combination of @ref DSI_FlowControl. 01265 * @retval HAL status 01266 */ 01267 HAL_StatusTypeDef HAL_DSI_ConfigFlowControl(DSI_HandleTypeDef *hdsi, uint32_t FlowControl) 01268 { 01269 /* Process locked */ 01270 __HAL_LOCK(hdsi); 01271 01272 /* Check the parameters */ 01273 assert_param(IS_DSI_FLOW_CONTROL(FlowControl)); 01274 01275 /* Set the DSI Host Protocol Configuration Register */ 01276 hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL; 01277 hdsi->Instance->PCR |= FlowControl; 01278 01279 /* Process unlocked */ 01280 __HAL_UNLOCK(hdsi); 01281 01282 return HAL_OK; 01283 } 01284 01285 /** 01286 * @brief Configure the DSI PHY timer parameters 01287 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01288 * the configuration information for the DSI. 01289 * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains 01290 * the DSI PHY timing parameters 01291 * @retval HAL status 01292 */ 01293 HAL_StatusTypeDef HAL_DSI_ConfigPhyTimer(DSI_HandleTypeDef *hdsi, DSI_PHY_TimerTypeDef *PhyTimers) 01294 { 01295 uint32_t maxTime; 01296 /* Process locked */ 01297 __HAL_LOCK(hdsi); 01298 01299 maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime; 01300 01301 /* Clock lane timer configuration */ 01302 01303 /* In Automatic Clock Lane control mode, the DSI Host can turn off the clock lane between two 01304 High-Speed transmission. 01305 To do so, the DSI Host calculates the time required for the clock lane to change from HighSpeed 01306 to Low-Power and from Low-Power to High-Speed. 01307 This timings are configured by the HS2LP_TIME and LP2HS_TIME in the DSI Host Clock Lane Timer Configuration Register (DSI_CLTCR). 01308 But the DSI Host is not calculating LP2HS_TIME + HS2LP_TIME but 2 x HS2LP_TIME. 01309 01310 Workaround : Configure HS2LP_TIME and LP2HS_TIME with the same value being the max of HS2LP_TIME or LP2HS_TIME. 01311 */ 01312 hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME); 01313 hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U)); 01314 01315 /* Data lane timer configuration */ 01316 hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME); 01317 hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U)); 01318 01319 /* Configure the wait period to request HS transmission after a stop state */ 01320 hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME; 01321 hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U); 01322 01323 /* Process unlocked */ 01324 __HAL_UNLOCK(hdsi); 01325 01326 return HAL_OK; 01327 } 01328 01329 /** 01330 * @brief Configure the DSI HOST timeout parameters 01331 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01332 * the configuration information for the DSI. 01333 * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains 01334 * the DSI host timeout parameters 01335 * @retval HAL status 01336 */ 01337 HAL_StatusTypeDef HAL_DSI_ConfigHostTimeouts(DSI_HandleTypeDef *hdsi, DSI_HOST_TimeoutTypeDef *HostTimeouts) 01338 { 01339 /* Process locked */ 01340 __HAL_LOCK(hdsi); 01341 01342 /* Set the timeout clock division factor */ 01343 hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV; 01344 hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U); 01345 01346 /* High-speed transmission timeout */ 01347 hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT; 01348 hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U); 01349 01350 /* Low-power reception timeout */ 01351 hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT; 01352 hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout; 01353 01354 /* High-speed read timeout */ 01355 hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT; 01356 hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout; 01357 01358 /* Low-power read timeout */ 01359 hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT; 01360 hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout; 01361 01362 /* High-speed write timeout */ 01363 hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT; 01364 hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout; 01365 01366 /* High-speed write presp mode */ 01367 hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM; 01368 hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode; 01369 01370 /* Low-speed write timeout */ 01371 hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT; 01372 hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout; 01373 01374 /* BTA timeout */ 01375 hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT; 01376 hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout; 01377 01378 /* Process unlocked */ 01379 __HAL_UNLOCK(hdsi); 01380 01381 return HAL_OK; 01382 } 01383 01384 /** 01385 * @brief Start the DSI module 01386 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01387 * the configuration information for the DSI. 01388 * @retval HAL status 01389 */ 01390 HAL_StatusTypeDef HAL_DSI_Start(DSI_HandleTypeDef *hdsi) 01391 { 01392 /* Process locked */ 01393 __HAL_LOCK(hdsi); 01394 01395 /* Enable the DSI host */ 01396 __HAL_DSI_ENABLE(hdsi); 01397 01398 /* Enable the DSI wrapper */ 01399 __HAL_DSI_WRAPPER_ENABLE(hdsi); 01400 01401 /* Process unlocked */ 01402 __HAL_UNLOCK(hdsi); 01403 01404 return HAL_OK; 01405 } 01406 01407 /** 01408 * @brief Stop the DSI module 01409 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01410 * the configuration information for the DSI. 01411 * @retval HAL status 01412 */ 01413 HAL_StatusTypeDef HAL_DSI_Stop(DSI_HandleTypeDef *hdsi) 01414 { 01415 /* Process locked */ 01416 __HAL_LOCK(hdsi); 01417 01418 /* Disable the DSI host */ 01419 __HAL_DSI_DISABLE(hdsi); 01420 01421 /* Disable the DSI wrapper */ 01422 __HAL_DSI_WRAPPER_DISABLE(hdsi); 01423 01424 /* Process unlocked */ 01425 __HAL_UNLOCK(hdsi); 01426 01427 return HAL_OK; 01428 } 01429 01430 /** 01431 * @brief Refresh the display in command mode 01432 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01433 * the configuration information for the DSI. 01434 * @retval HAL status 01435 */ 01436 HAL_StatusTypeDef HAL_DSI_Refresh(DSI_HandleTypeDef *hdsi) 01437 { 01438 /* Process locked */ 01439 __HAL_LOCK(hdsi); 01440 01441 /* Update the display */ 01442 hdsi->Instance->WCR |= DSI_WCR_LTDCEN; 01443 01444 /* Process unlocked */ 01445 __HAL_UNLOCK(hdsi); 01446 01447 return HAL_OK; 01448 } 01449 01450 /** 01451 * @brief Controls the display color mode in Video mode 01452 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01453 * the configuration information for the DSI. 01454 * @param ColorMode Color mode (full or 8-colors). 01455 * This parameter can be any value of @ref DSI_Color_Mode 01456 * @retval HAL status 01457 */ 01458 HAL_StatusTypeDef HAL_DSI_ColorMode(DSI_HandleTypeDef *hdsi, uint32_t ColorMode) 01459 { 01460 /* Process locked */ 01461 __HAL_LOCK(hdsi); 01462 01463 /* Check the parameters */ 01464 assert_param(IS_DSI_COLOR_MODE(ColorMode)); 01465 01466 /* Update the display color mode */ 01467 hdsi->Instance->WCR &= ~DSI_WCR_COLM; 01468 hdsi->Instance->WCR |= ColorMode; 01469 01470 /* Process unlocked */ 01471 __HAL_UNLOCK(hdsi); 01472 01473 return HAL_OK; 01474 } 01475 01476 /** 01477 * @brief Control the display shutdown in Video mode 01478 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01479 * the configuration information for the DSI. 01480 * @param Shutdown Shut-down (Display-ON or Display-OFF). 01481 * This parameter can be any value of @ref DSI_ShutDown 01482 * @retval HAL status 01483 */ 01484 HAL_StatusTypeDef HAL_DSI_Shutdown(DSI_HandleTypeDef *hdsi, uint32_t Shutdown) 01485 { 01486 /* Process locked */ 01487 __HAL_LOCK(hdsi); 01488 01489 /* Check the parameters */ 01490 assert_param(IS_DSI_SHUT_DOWN(Shutdown)); 01491 01492 /* Update the display Shutdown */ 01493 hdsi->Instance->WCR &= ~DSI_WCR_SHTDN; 01494 hdsi->Instance->WCR |= Shutdown; 01495 01496 /* Process unlocked */ 01497 __HAL_UNLOCK(hdsi); 01498 01499 return HAL_OK; 01500 } 01501 01502 /** 01503 * @brief write short DCS or short Generic command 01504 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01505 * the configuration information for the DSI. 01506 * @param ChannelID Virtual channel ID. 01507 * @param Mode DSI short packet data type. 01508 * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. 01509 * @param Param1 DSC command or first generic parameter. 01510 * This parameter can be any value of @ref DSI_DCS_Command or a 01511 * generic command code. 01512 * @param Param2 DSC parameter or second generic parameter. 01513 * @retval HAL status 01514 */ 01515 HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, 01516 uint32_t ChannelID, 01517 uint32_t Mode, 01518 uint32_t Param1, 01519 uint32_t Param2) 01520 { 01521 uint32_t tickstart; 01522 01523 /* Process locked */ 01524 __HAL_LOCK(hdsi); 01525 01526 /* Check the parameters */ 01527 assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode)); 01528 01529 /* Get tick */ 01530 tickstart = HAL_GetTick(); 01531 01532 /* Wait for Command FIFO Empty */ 01533 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) 01534 { 01535 /* Check for the Timeout */ 01536 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01537 { 01538 /* Process Unlocked */ 01539 __HAL_UNLOCK(hdsi); 01540 01541 return HAL_TIMEOUT; 01542 } 01543 } 01544 01545 /* Configure the packet to send a short DCS command with 0 or 1 parameter */ 01546 DSI_ConfigPacketHeader(hdsi->Instance, 01547 ChannelID, 01548 Mode, 01549 Param1, 01550 Param2); 01551 01552 /* Process unlocked */ 01553 __HAL_UNLOCK(hdsi); 01554 01555 return HAL_OK; 01556 } 01557 01558 /** 01559 * @brief write long DCS or long Generic command 01560 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01561 * the configuration information for the DSI. 01562 * @param ChannelID Virtual channel ID. 01563 * @param Mode DSI long packet data type. 01564 * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. 01565 * @param NbParams Number of parameters. 01566 * @param Param1 DSC command or first generic parameter. 01567 * This parameter can be any value of @ref DSI_DCS_Command or a 01568 * generic command code 01569 * @param ParametersTable Pointer to parameter values table. 01570 * @retval HAL status 01571 */ 01572 HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, 01573 uint32_t ChannelID, 01574 uint32_t Mode, 01575 uint32_t NbParams, 01576 uint32_t Param1, 01577 uint8_t* ParametersTable) 01578 { 01579 uint32_t uicounter, nbBytes, count; 01580 uint32_t tickstart; 01581 uint32_t fifoword; 01582 uint8_t* pparams = ParametersTable; 01583 01584 /* Process locked */ 01585 __HAL_LOCK(hdsi); 01586 01587 /* Check the parameters */ 01588 assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode)); 01589 01590 /* Get tick */ 01591 tickstart = HAL_GetTick(); 01592 01593 /* Wait for Command FIFO Empty */ 01594 while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U) 01595 { 01596 /* Check for the Timeout */ 01597 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01598 { 01599 /* Process Unlocked */ 01600 __HAL_UNLOCK(hdsi); 01601 01602 return HAL_TIMEOUT; 01603 } 01604 } 01605 01606 /* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/ 01607 fifoword = Param1; 01608 nbBytes = (NbParams < 3U) ? NbParams : 3U; 01609 01610 for(count = 0U; count < nbBytes; count++) 01611 { 01612 fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count))); 01613 } 01614 hdsi->Instance->GPDR = fifoword; 01615 01616 uicounter = NbParams - nbBytes; 01617 pparams += nbBytes; 01618 /* Set the Next parameters on the write FIFO command*/ 01619 while(uicounter != 0U) 01620 { 01621 nbBytes = (uicounter < 4U) ? uicounter : 4U; 01622 fifoword = 0U; 01623 for(count = 0U; count < nbBytes; count++) 01624 { 01625 fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count)); 01626 } 01627 hdsi->Instance->GPDR = fifoword; 01628 01629 uicounter -= nbBytes; 01630 pparams += nbBytes; 01631 } 01632 01633 /* Configure the packet to send a long DCS command */ 01634 DSI_ConfigPacketHeader(hdsi->Instance, 01635 ChannelID, 01636 Mode, 01637 ((NbParams+1U)&0x00FFU), 01638 (((NbParams+1U)&0xFF00U)>>8U)); 01639 01640 /* Process unlocked */ 01641 __HAL_UNLOCK(hdsi); 01642 01643 return HAL_OK; 01644 } 01645 01646 /** 01647 * @brief Read command (DCS or generic) 01648 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01649 * the configuration information for the DSI. 01650 * @param ChannelNbr Virtual channel ID 01651 * @param Array pointer to a buffer to store the payload of a read back operation. 01652 * @param Size Data size to be read (in byte). 01653 * @param Mode DSI read packet data type. 01654 * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. 01655 * @param DCSCmd DCS get/read command. 01656 * @param ParametersTable Pointer to parameter values table. 01657 * @retval HAL status 01658 */ 01659 HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, 01660 uint32_t ChannelNbr, 01661 uint8_t* Array, 01662 uint32_t Size, 01663 uint32_t Mode, 01664 uint32_t DCSCmd, 01665 uint8_t* ParametersTable) 01666 { 01667 uint32_t tickstart; 01668 uint8_t* pdata = Array; 01669 uint32_t datasize = Size; 01670 uint32_t fifoword; 01671 uint32_t nbbytes; 01672 uint32_t count; 01673 01674 /* Process locked */ 01675 __HAL_LOCK(hdsi); 01676 01677 /* Check the parameters */ 01678 assert_param(IS_DSI_READ_PACKET_TYPE(Mode)); 01679 01680 if(datasize > 2U) 01681 { 01682 /* set max return packet size */ 01683 if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK) 01684 { 01685 /* Process Unlocked */ 01686 __HAL_UNLOCK(hdsi); 01687 01688 return HAL_ERROR; 01689 } 01690 } 01691 01692 /* Configure the packet to read command */ 01693 if (Mode == DSI_DCS_SHORT_PKT_READ) 01694 { 01695 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, DCSCmd, 0U); 01696 } 01697 else if (Mode == DSI_GEN_SHORT_PKT_READ_P0) 01698 { 01699 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, 0U, 0U); 01700 } 01701 else if (Mode == DSI_GEN_SHORT_PKT_READ_P1) 01702 { 01703 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], 0U); 01704 } 01705 else if (Mode == DSI_GEN_SHORT_PKT_READ_P2) 01706 { 01707 DSI_ConfigPacketHeader(hdsi->Instance, ChannelNbr, Mode, ParametersTable[0U], ParametersTable[1U]); 01708 } 01709 else 01710 { 01711 /* Process Unlocked */ 01712 __HAL_UNLOCK(hdsi); 01713 01714 return HAL_ERROR; 01715 } 01716 01717 /* Get tick */ 01718 tickstart = HAL_GetTick(); 01719 01720 /* If DSI fifo is not empty, read requested bytes */ 01721 while(((int)(datasize)) > 0) 01722 { 01723 if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U) 01724 { 01725 fifoword = hdsi->Instance->GPDR; 01726 nbbytes = (datasize < 4U) ? datasize : 4U; 01727 01728 for(count = 0U; count < nbbytes; count++) 01729 { 01730 *pdata++ = (uint8_t)(fifoword >> (8U*count)); 01731 datasize--; 01732 } 01733 } 01734 01735 /* Check for the Timeout */ 01736 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01737 { 01738 /* Process Unlocked */ 01739 __HAL_UNLOCK(hdsi); 01740 01741 return HAL_TIMEOUT; 01742 } 01743 } 01744 01745 /* Process unlocked */ 01746 __HAL_UNLOCK(hdsi); 01747 01748 return HAL_OK; 01749 } 01750 01751 /** 01752 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running 01753 * (only data lanes are in ULPM) 01754 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01755 * the configuration information for the DSI. 01756 * @retval HAL status 01757 */ 01758 HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi) 01759 { 01760 uint32_t tickstart; 01761 01762 /* Process locked */ 01763 __HAL_LOCK(hdsi); 01764 01765 /* ULPS Request on Data Lanes */ 01766 hdsi->Instance->PUCR |= DSI_PUCR_URDL; 01767 01768 /* Get tick */ 01769 tickstart = HAL_GetTick(); 01770 01771 /* Wait until the D-PHY active lanes enter into ULPM */ 01772 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) 01773 { 01774 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != 0U) 01775 { 01776 /* Check for the Timeout */ 01777 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01778 { 01779 /* Process Unlocked */ 01780 __HAL_UNLOCK(hdsi); 01781 01782 return HAL_TIMEOUT; 01783 } 01784 } 01785 } 01786 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) 01787 { 01788 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != 0U) 01789 { 01790 /* Check for the Timeout */ 01791 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01792 { 01793 /* Process Unlocked */ 01794 __HAL_UNLOCK(hdsi); 01795 01796 return HAL_TIMEOUT; 01797 } 01798 } 01799 } 01800 else 01801 { 01802 /* Process unlocked */ 01803 __HAL_UNLOCK(hdsi); 01804 01805 return HAL_ERROR; 01806 } 01807 01808 /* Process unlocked */ 01809 __HAL_UNLOCK(hdsi); 01810 01811 return HAL_OK; 01812 } 01813 01814 /** 01815 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running 01816 * (only data lanes are in ULPM) 01817 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01818 * the configuration information for the DSI. 01819 * @retval HAL status 01820 */ 01821 HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi) 01822 { 01823 uint32_t tickstart; 01824 01825 /* Process locked */ 01826 __HAL_LOCK(hdsi); 01827 01828 /* Exit ULPS on Data Lanes */ 01829 hdsi->Instance->PUCR |= DSI_PUCR_UEDL; 01830 01831 /* Get tick */ 01832 tickstart = HAL_GetTick(); 01833 01834 /* Wait until all active lanes exit ULPM */ 01835 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) 01836 { 01837 while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0) 01838 { 01839 /* Check for the Timeout */ 01840 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01841 { 01842 /* Process Unlocked */ 01843 __HAL_UNLOCK(hdsi); 01844 01845 return HAL_TIMEOUT; 01846 } 01847 } 01848 } 01849 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) 01850 { 01851 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1)) 01852 { 01853 /* Check for the Timeout */ 01854 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01855 { 01856 /* Process Unlocked */ 01857 __HAL_UNLOCK(hdsi); 01858 01859 return HAL_TIMEOUT; 01860 } 01861 } 01862 } 01863 else 01864 { 01865 /* Process unlocked */ 01866 __HAL_UNLOCK(hdsi); 01867 01868 return HAL_ERROR; 01869 } 01870 01871 /* wait for 1 ms*/ 01872 HAL_Delay(1U); 01873 01874 /* De-assert the ULPM requests and the ULPM exit bits */ 01875 hdsi->Instance->PUCR = 0U; 01876 01877 /* Process unlocked */ 01878 __HAL_UNLOCK(hdsi); 01879 01880 return HAL_OK; 01881 } 01882 01883 /** 01884 * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off 01885 * (both data and clock lanes are in ULPM) 01886 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01887 * the configuration information for the DSI. 01888 * @retval HAL status 01889 */ 01890 HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi) 01891 { 01892 uint32_t tickstart; 01893 01894 /* Process locked */ 01895 __HAL_LOCK(hdsi); 01896 01897 /* Clock lane configuration: no more HS request */ 01898 hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC; 01899 01900 /* Use system PLL as byte lane clock source before stopping DSIPHY clock source */ 01901 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLSAI2); 01902 01903 /* ULPS Request on Clock and Data Lanes */ 01904 hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL); 01905 01906 /* Get tick */ 01907 tickstart = HAL_GetTick(); 01908 01909 /* Wait until all active lanes exit ULPM */ 01910 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) 01911 { 01912 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != 0U) 01913 { 01914 /* Check for the Timeout */ 01915 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01916 { 01917 /* Process Unlocked */ 01918 __HAL_UNLOCK(hdsi); 01919 01920 return HAL_TIMEOUT; 01921 } 01922 } 01923 } 01924 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) 01925 { 01926 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != 0U) 01927 { 01928 /* Check for the Timeout */ 01929 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01930 { 01931 /* Process Unlocked */ 01932 __HAL_UNLOCK(hdsi); 01933 01934 return HAL_TIMEOUT; 01935 } 01936 } 01937 } 01938 else 01939 { 01940 /* Process unlocked */ 01941 __HAL_UNLOCK(hdsi); 01942 01943 return HAL_ERROR; 01944 } 01945 01946 /* Turn off the DSI PLL */ 01947 __HAL_DSI_PLL_DISABLE(hdsi); 01948 01949 /* Process unlocked */ 01950 __HAL_UNLOCK(hdsi); 01951 01952 return HAL_OK; 01953 } 01954 01955 /** 01956 * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off 01957 * (both data and clock lanes are in ULPM) 01958 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 01959 * the configuration information for the DSI. 01960 * @retval HAL status 01961 */ 01962 HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi) 01963 { 01964 uint32_t tickstart; 01965 01966 /* Process locked */ 01967 __HAL_LOCK(hdsi); 01968 01969 /* Turn on the DSI PLL */ 01970 __HAL_DSI_PLL_ENABLE(hdsi); 01971 01972 /* Get tick */ 01973 tickstart = HAL_GetTick(); 01974 01975 /* Wait for the lock of the PLL */ 01976 while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == 0U) 01977 { 01978 /* Check for the Timeout */ 01979 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 01980 { 01981 /* Process Unlocked */ 01982 __HAL_UNLOCK(hdsi); 01983 01984 return HAL_TIMEOUT; 01985 } 01986 } 01987 01988 /* Exit ULPS on Clock and Data Lanes */ 01989 hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL); 01990 01991 /* Get tick */ 01992 tickstart = HAL_GetTick(); 01993 01994 /* Wait until all active lanes exit ULPM */ 01995 if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE) 01996 { 01997 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC)) 01998 { 01999 /* Check for the Timeout */ 02000 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 02001 { 02002 /* Process Unlocked */ 02003 __HAL_UNLOCK(hdsi); 02004 02005 return HAL_TIMEOUT; 02006 } 02007 } 02008 } 02009 else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES) 02010 { 02011 while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) 02012 { 02013 /* Check for the Timeout */ 02014 if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE) 02015 { 02016 /* Process Unlocked */ 02017 __HAL_UNLOCK(hdsi); 02018 02019 return HAL_TIMEOUT; 02020 } 02021 } 02022 } 02023 else 02024 { 02025 /* Process unlocked */ 02026 __HAL_UNLOCK(hdsi); 02027 02028 return HAL_ERROR; 02029 } 02030 02031 /* wait for 1 ms */ 02032 HAL_Delay(1U); 02033 02034 /* De-assert the ULPM requests and the ULPM exit bits */ 02035 hdsi->Instance->PUCR = 0U; 02036 02037 /* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */ 02038 __HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY); 02039 02040 /* Restore clock lane configuration to HS */ 02041 hdsi->Instance->CLCR |= DSI_CLCR_DPCC; 02042 02043 /* Process unlocked */ 02044 __HAL_UNLOCK(hdsi); 02045 02046 return HAL_OK; 02047 } 02048 02049 /** 02050 * @brief Start test pattern generation 02051 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02052 * the configuration information for the DSI. 02053 * @param Mode Pattern generator mode 02054 * This parameter can be one of the following values: 02055 * 0 : Color bars (horizontal or vertical) 02056 * 1 : BER pattern (vertical only) 02057 * @param Orientation Pattern generator orientation 02058 * This parameter can be one of the following values: 02059 * 0 : Vertical color bars 02060 * 1 : Horizontal color bars 02061 * @retval HAL status 02062 */ 02063 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStart(DSI_HandleTypeDef *hdsi, uint32_t Mode, uint32_t Orientation) 02064 { 02065 /* Process locked */ 02066 __HAL_LOCK(hdsi); 02067 02068 /* Configure pattern generator mode and orientation */ 02069 hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO); 02070 hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U)); 02071 02072 /* Enable pattern generator by setting PGE bit */ 02073 hdsi->Instance->VMCR |= DSI_VMCR_PGE; 02074 02075 /* Process unlocked */ 02076 __HAL_UNLOCK(hdsi); 02077 02078 return HAL_OK; 02079 } 02080 02081 /** 02082 * @brief Stop test pattern generation 02083 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02084 * the configuration information for the DSI. 02085 * @retval HAL status 02086 */ 02087 HAL_StatusTypeDef HAL_DSI_PatternGeneratorStop(DSI_HandleTypeDef *hdsi) 02088 { 02089 /* Process locked */ 02090 __HAL_LOCK(hdsi); 02091 02092 /* Disable pattern generator by clearing PGE bit */ 02093 hdsi->Instance->VMCR &= ~DSI_VMCR_PGE; 02094 02095 /* Process unlocked */ 02096 __HAL_UNLOCK(hdsi); 02097 02098 return HAL_OK; 02099 } 02100 02101 /** 02102 * @brief Set Slew-Rate And Delay Tuning 02103 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02104 * the configuration information for the DSI. 02105 * @param CommDelay Communication delay to be adjusted. 02106 * This parameter can be any value of @ref DSI_Communication_Delay 02107 * @param Lane select between clock or data lanes. 02108 * This parameter can be any value of @ref DSI_Lane_Group 02109 * @param Value Custom value of the slew-rate or delay 02110 * @retval HAL status 02111 */ 02112 HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) 02113 { 02114 /* Process locked */ 02115 __HAL_LOCK(hdsi); 02116 02117 /* Check function parameters */ 02118 assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay)); 02119 assert_param(IS_DSI_LANE_GROUP(Lane)); 02120 02121 switch(CommDelay) 02122 { 02123 case DSI_SLEW_RATE_HSTX: 02124 if(Lane == DSI_CLOCK_LANE) 02125 { 02126 /* High-Speed Transmission Slew Rate Control on Clock Lane */ 02127 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCCL; 02128 hdsi->Instance->WPCR[1U] |= Value<<16U; 02129 } 02130 else if(Lane == DSI_DATA_LANES) 02131 { 02132 /* High-Speed Transmission Slew Rate Control on Data Lanes */ 02133 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL; 02134 hdsi->Instance->WPCR[1U] |= Value<<18U; 02135 } 02136 else 02137 { 02138 /* Process unlocked */ 02139 __HAL_UNLOCK(hdsi); 02140 02141 return HAL_ERROR; 02142 } 02143 break; 02144 case DSI_SLEW_RATE_LPTX: 02145 if(Lane == DSI_CLOCK_LANE) 02146 { 02147 /* Low-Power transmission Slew Rate Compensation on Clock Lane */ 02148 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCCL; 02149 hdsi->Instance->WPCR[1U] |= Value<<6U; 02150 } 02151 else if(Lane == DSI_DATA_LANES) 02152 { 02153 /* Low-Power transmission Slew Rate Compensation on Data Lanes */ 02154 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL; 02155 hdsi->Instance->WPCR[1U] |= Value<<8U; 02156 } 02157 else 02158 { 02159 /* Process unlocked */ 02160 __HAL_UNLOCK(hdsi); 02161 02162 return HAL_ERROR; 02163 } 02164 break; 02165 case DSI_HS_DELAY: 02166 if(Lane == DSI_CLOCK_LANE) 02167 { 02168 /* High-Speed Transmission Delay on Clock Lane */ 02169 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDCL; 02170 hdsi->Instance->WPCR[1U] |= Value; 02171 } 02172 else if(Lane == DSI_DATA_LANES) 02173 { 02174 /* High-Speed Transmission Delay on Data Lanes */ 02175 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL; 02176 hdsi->Instance->WPCR[1U] |= Value<<2U; 02177 } 02178 else 02179 { 02180 /* Process unlocked */ 02181 __HAL_UNLOCK(hdsi); 02182 02183 return HAL_ERROR; 02184 } 02185 break; 02186 default: 02187 break; 02188 } 02189 02190 /* Process unlocked */ 02191 __HAL_UNLOCK(hdsi); 02192 02193 return HAL_OK; 02194 } 02195 02196 /** 02197 * @brief Low-Power Reception Filter Tuning 02198 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02199 * the configuration information for the DSI. 02200 * @param Frequency cutoff frequency of low-pass filter at the input of LPRX 02201 * @retval HAL status 02202 */ 02203 HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) 02204 { 02205 /* Process locked */ 02206 __HAL_LOCK(hdsi); 02207 02208 /* Low-Power RX low-pass Filtering Tuning */ 02209 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT; 02210 hdsi->Instance->WPCR[1U] |= Frequency<<25U; 02211 02212 /* Process unlocked */ 02213 __HAL_UNLOCK(hdsi); 02214 02215 return HAL_OK; 02216 } 02217 02218 /** 02219 * @brief Activate an additional current path on all lanes to meet the SDDTx parameter 02220 * defined in the MIPI D-PHY specification 02221 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02222 * the configuration information for the DSI. 02223 * @param State ENABLE or DISABLE 02224 * @retval HAL status 02225 */ 02226 HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) 02227 { 02228 /* Process locked */ 02229 __HAL_LOCK(hdsi); 02230 02231 /* Check function parameters */ 02232 assert_param(IS_FUNCTIONAL_STATE(State)); 02233 02234 /* Activate/Disactivate additional current path on all lanes */ 02235 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC; 02236 hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U); 02237 02238 /* Process unlocked */ 02239 __HAL_UNLOCK(hdsi); 02240 02241 return HAL_OK; 02242 } 02243 02244 /** 02245 * @brief Custom lane pins configuration 02246 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02247 * the configuration information for the DSI. 02248 * @param CustomLane Function to be applyed on selected lane. 02249 * This parameter can be any value of @ref DSI_CustomLane 02250 * @param Lane select between clock or data lane 0 or data lane 1. 02251 * This parameter can be any value of @ref DSI_Lane_Select 02252 * @param State ENABLE or DISABLE 02253 * @retval HAL status 02254 */ 02255 HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) 02256 { 02257 /* Process locked */ 02258 __HAL_LOCK(hdsi); 02259 02260 /* Check function parameters */ 02261 assert_param(IS_DSI_CUSTOM_LANE(CustomLane)); 02262 assert_param(IS_DSI_LANE(Lane)); 02263 assert_param(IS_FUNCTIONAL_STATE(State)); 02264 02265 switch(CustomLane) 02266 { 02267 case DSI_SWAP_LANE_PINS: 02268 if(Lane == DSI_CLK_LANE) 02269 { 02270 /* Swap pins on clock lane */ 02271 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL; 02272 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 6U); 02273 } 02274 else if(Lane == DSI_DATA_LANE0) 02275 { 02276 /* Swap pins on data lane 0 */ 02277 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL0; 02278 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 7U); 02279 } 02280 else if(Lane == DSI_DATA_LANE1) 02281 { 02282 /* Swap pins on data lane 1 */ 02283 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1; 02284 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U); 02285 } 02286 else 02287 { 02288 /* Process unlocked */ 02289 __HAL_UNLOCK(hdsi); 02290 02291 return HAL_ERROR; 02292 } 02293 break; 02294 case DSI_INVERT_HS_SIGNAL: 02295 if(Lane == DSI_CLK_LANE) 02296 { 02297 /* Invert HS signal on clock lane */ 02298 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL; 02299 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 9U); 02300 } 02301 else if(Lane == DSI_DATA_LANE0) 02302 { 02303 /* Invert HS signal on data lane 0 */ 02304 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL0; 02305 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 10U); 02306 } 02307 else if(Lane == DSI_DATA_LANE1) 02308 { 02309 /* Invert HS signal on data lane 1 */ 02310 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1; 02311 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U); 02312 } 02313 else 02314 { 02315 /* Process unlocked */ 02316 __HAL_UNLOCK(hdsi); 02317 02318 return HAL_ERROR; 02319 } 02320 break; 02321 default: 02322 break; 02323 } 02324 02325 /* Process unlocked */ 02326 __HAL_UNLOCK(hdsi); 02327 02328 return HAL_OK; 02329 } 02330 02331 /** 02332 * @brief Set custom timing for the PHY 02333 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02334 * the configuration information for the DSI. 02335 * @param Timing PHY timing to be adjusted. 02336 * This parameter can be any value of @ref DSI_PHY_Timing 02337 * @param State ENABLE or DISABLE 02338 * @param Value Custom value of the timing 02339 * @retval HAL status 02340 */ 02341 HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) 02342 { 02343 /* Process locked */ 02344 __HAL_LOCK(hdsi); 02345 02346 /* Check function parameters */ 02347 assert_param(IS_DSI_PHY_TIMING(Timing)); 02348 assert_param(IS_FUNCTIONAL_STATE(State)); 02349 02350 switch(Timing) 02351 { 02352 case DSI_TCLK_POST: 02353 /* Enable/Disable custom timing setting */ 02354 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN; 02355 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U); 02356 02357 if(State != DISABLE) 02358 { 02359 /* Set custom value */ 02360 hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST; 02361 hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST; 02362 } 02363 02364 break; 02365 case DSI_TLPX_CLK: 02366 /* Enable/Disable custom timing setting */ 02367 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN; 02368 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U); 02369 02370 if(State != DISABLE) 02371 { 02372 /* Set custom value */ 02373 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC; 02374 hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC; 02375 } 02376 02377 break; 02378 case DSI_THS_EXIT: 02379 /* Enable/Disable custom timing setting */ 02380 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN; 02381 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U); 02382 02383 if(State != DISABLE) 02384 { 02385 /* Set custom value */ 02386 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT; 02387 hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT; 02388 } 02389 02390 break; 02391 case DSI_TLPX_DATA: 02392 /* Enable/Disable custom timing setting */ 02393 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN; 02394 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U); 02395 02396 if(State != DISABLE) 02397 { 02398 /* Set custom value */ 02399 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD; 02400 hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD; 02401 } 02402 02403 break; 02404 case DSI_THS_ZERO: 02405 /* Enable/Disable custom timing setting */ 02406 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN; 02407 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U); 02408 02409 if(State != DISABLE) 02410 { 02411 /* Set custom value */ 02412 hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO; 02413 hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO; 02414 } 02415 02416 break; 02417 case DSI_THS_TRAIL: 02418 /* Enable/Disable custom timing setting */ 02419 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN; 02420 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U); 02421 02422 if(State != DISABLE) 02423 { 02424 /* Set custom value */ 02425 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL; 02426 hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL; 02427 } 02428 02429 break; 02430 case DSI_THS_PREPARE: 02431 /* Enable/Disable custom timing setting */ 02432 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN; 02433 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U); 02434 02435 if(State != DISABLE) 02436 { 02437 /* Set custom value */ 02438 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP; 02439 hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP; 02440 } 02441 02442 break; 02443 case DSI_TCLK_ZERO: 02444 /* Enable/Disable custom timing setting */ 02445 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN; 02446 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U); 02447 02448 if(State != DISABLE) 02449 { 02450 /* Set custom value */ 02451 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO; 02452 hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO; 02453 } 02454 02455 break; 02456 case DSI_TCLK_PREPARE: 02457 /* Enable/Disable custom timing setting */ 02458 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN; 02459 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U); 02460 02461 if(State != DISABLE) 02462 { 02463 /* Set custom value */ 02464 hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP; 02465 hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP; 02466 } 02467 02468 break; 02469 default: 02470 break; 02471 } 02472 02473 /* Process unlocked */ 02474 __HAL_UNLOCK(hdsi); 02475 02476 return HAL_OK; 02477 } 02478 02479 /** 02480 * @brief Force the Clock/Data Lane in TX Stop Mode 02481 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02482 * the configuration information for the DSI. 02483 * @param Lane select between clock or data lanes. 02484 * This parameter can be any value of @ref DSI_Lane_Group 02485 * @param State ENABLE or DISABLE 02486 * @retval HAL status 02487 */ 02488 HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) 02489 { 02490 /* Process locked */ 02491 __HAL_LOCK(hdsi); 02492 02493 /* Check function parameters */ 02494 assert_param(IS_DSI_LANE_GROUP(Lane)); 02495 assert_param(IS_FUNCTIONAL_STATE(State)); 02496 02497 if(Lane == DSI_CLOCK_LANE) 02498 { 02499 /* Force/Unforce the Clock Lane in TX Stop Mode */ 02500 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMCL; 02501 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 12U); 02502 } 02503 else if(Lane == DSI_DATA_LANES) 02504 { 02505 /* Force/Unforce the Data Lanes in TX Stop Mode */ 02506 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL; 02507 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U); 02508 } 02509 else 02510 { 02511 /* Process unlocked */ 02512 __HAL_UNLOCK(hdsi); 02513 02514 return HAL_ERROR; 02515 } 02516 02517 /* Process unlocked */ 02518 __HAL_UNLOCK(hdsi); 02519 02520 return HAL_OK; 02521 } 02522 02523 /** 02524 * @brief Force LP Receiver in Low-Power Mode 02525 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02526 * the configuration information for the DSI. 02527 * @param State ENABLE or DISABLE 02528 * @retval HAL status 02529 */ 02530 HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) 02531 { 02532 /* Process locked */ 02533 __HAL_LOCK(hdsi); 02534 02535 /* Check function parameters */ 02536 assert_param(IS_FUNCTIONAL_STATE(State)); 02537 02538 /* Force/Unforce LP Receiver in Low-Power Mode */ 02539 hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM; 02540 hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U); 02541 02542 /* Process unlocked */ 02543 __HAL_UNLOCK(hdsi); 02544 02545 return HAL_OK; 02546 } 02547 02548 /** 02549 * @brief Force Data Lanes in RX Mode after a BTA 02550 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02551 * the configuration information for the DSI. 02552 * @param State ENABLE or DISABLE 02553 * @retval HAL status 02554 */ 02555 HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) 02556 { 02557 /* Process locked */ 02558 __HAL_LOCK(hdsi); 02559 02560 /* Check function parameters */ 02561 assert_param(IS_FUNCTIONAL_STATE(State)); 02562 02563 /* Force Data Lanes in RX Mode */ 02564 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL; 02565 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U); 02566 02567 /* Process unlocked */ 02568 __HAL_UNLOCK(hdsi); 02569 02570 return HAL_OK; 02571 } 02572 02573 /** 02574 * @brief Enable a pull-down on the lanes to prevent from floating states when unused 02575 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02576 * the configuration information for the DSI. 02577 * @param State ENABLE or DISABLE 02578 * @retval HAL status 02579 */ 02580 HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) 02581 { 02582 /* Process locked */ 02583 __HAL_LOCK(hdsi); 02584 02585 /* Check function parameters */ 02586 assert_param(IS_FUNCTIONAL_STATE(State)); 02587 02588 /* Enable/Disable pull-down on lanes */ 02589 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN; 02590 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U); 02591 02592 /* Process unlocked */ 02593 __HAL_UNLOCK(hdsi); 02594 02595 return HAL_OK; 02596 } 02597 02598 /** 02599 * @brief Switch off the contention detection on data lanes 02600 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02601 * the configuration information for the DSI. 02602 * @param State ENABLE or DISABLE 02603 * @retval HAL status 02604 */ 02605 HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) 02606 { 02607 /* Process locked */ 02608 __HAL_LOCK(hdsi); 02609 02610 /* Check function parameters */ 02611 assert_param(IS_FUNCTIONAL_STATE(State)); 02612 02613 /* Contention Detection on Data Lanes OFF */ 02614 hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL; 02615 hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U); 02616 02617 /* Process unlocked */ 02618 __HAL_UNLOCK(hdsi); 02619 02620 return HAL_OK; 02621 } 02622 02623 /** 02624 * @} 02625 */ 02626 02627 /** @defgroup DSI_Group4 Peripheral State and Errors functions 02628 * @brief Peripheral State and Errors functions 02629 * 02630 @verbatim 02631 =============================================================================== 02632 ##### Peripheral State and Errors functions ##### 02633 =============================================================================== 02634 [..] 02635 This subsection provides functions allowing to 02636 (+) Check the DSI state. 02637 (+) Get error code. 02638 02639 @endverbatim 02640 * @{ 02641 */ 02642 02643 /** 02644 * @brief Return the DSI state 02645 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02646 * the configuration information for the DSI. 02647 * @retval HAL state 02648 */ 02649 HAL_DSI_StateTypeDef HAL_DSI_GetState(DSI_HandleTypeDef *hdsi) 02650 { 02651 return hdsi->State; 02652 } 02653 02654 /** 02655 * @brief Return the DSI error code 02656 * @param hdsi pointer to a DSI_HandleTypeDef structure that contains 02657 * the configuration information for the DSI. 02658 * @retval DSI Error Code 02659 */ 02660 uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi) 02661 { 02662 /* Get the error code */ 02663 return hdsi->ErrorCode; 02664 } 02665 02666 /** 02667 * @} 02668 */ 02669 02670 /** 02671 * @} 02672 */ 02673 02674 /** 02675 * @} 02676 */ 02677 02678 #endif /* DSI */ 02679 02680 #endif /* HAL_DSI_MODULE_ENABLED */ 02681 02682 /** 02683 * @} 02684 */ 02685 02686 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/