STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dma.c 00004 * @author MCD Application Team 00005 * @brief DMA HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the Direct Memory Access (DMA) peripheral: 00008 * + Initialization and de-initialization functions 00009 * + IO operation functions 00010 * + Peripheral State and errors functions 00011 @verbatim 00012 ============================================================================== 00013 ##### How to use this driver ##### 00014 ============================================================================== 00015 [..] 00016 (#) Enable and configure the peripheral to be connected to the DMA Channel 00017 (except for internal SRAM / FLASH memories: no initialization is 00018 necessary). Please refer to the Reference manual for connection between peripherals 00019 and DMA requests. 00020 00021 (#) For a given Channel, program the required configuration through the following parameters: 00022 Channel request, Transfer Direction, Source and Destination data formats, 00023 Circular or Normal mode, Channel Priority level, Source and Destination Increment mode 00024 using HAL_DMA_Init() function. 00025 00026 Prior to HAL_DMA_Init the peripheral clock shall be enabled for both DMA & DMAMUX 00027 thanks to: 00028 (##) DMA1 or DMA2: __HAL_RCC_DMA1_CLK_ENABLE() or __HAL_RCC_DMA2_CLK_ENABLE() ; 00029 (##) DMAMUX1: __HAL_RCC_DMAMUX1_CLK_ENABLE(); 00030 00031 (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 00032 detection. 00033 00034 (#) Use HAL_DMA_Abort() function to abort the current transfer 00035 00036 -@- In Memory-to-Memory transfer mode, Circular mode is not allowed. 00037 00038 *** Polling mode IO operation *** 00039 ================================= 00040 [..] 00041 (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 00042 address and destination address and the Length of data to be transferred 00043 (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this 00044 case a fixed Timeout can be configured by User depending from his application. 00045 00046 *** Interrupt mode IO operation *** 00047 =================================== 00048 [..] 00049 (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority() 00050 (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() 00051 (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of 00052 Source address and destination address and the Length of data to be transferred. 00053 In this case the DMA interrupt is configured 00054 (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine 00055 (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 00056 add his own function to register callbacks with HAL_DMA_RegisterCallback(). 00057 00058 *** DMA HAL driver macros list *** 00059 ============================================= 00060 [..] 00061 Below the list of macros in DMA HAL driver. 00062 00063 (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel. 00064 (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel. 00065 (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags. 00066 (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags. 00067 (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts. 00068 (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts. 00069 (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. 00070 00071 [..] 00072 (@) You can refer to the DMA HAL driver header file for more useful macros 00073 00074 @endverbatim 00075 ****************************************************************************** 00076 * @attention 00077 * 00078 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00079 * 00080 * Redistribution and use in source and binary forms, with or without modification, 00081 * are permitted provided that the following conditions are met: 00082 * 1. Redistributions of source code must retain the above copyright notice, 00083 * this list of conditions and the following disclaimer. 00084 * 2. Redistributions in binary form must reproduce the above copyright notice, 00085 * this list of conditions and the following disclaimer in the documentation 00086 * and/or other materials provided with the distribution. 00087 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00088 * may be used to endorse or promote products derived from this software 00089 * without specific prior written permission. 00090 * 00091 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00092 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00093 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00094 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00095 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00096 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00097 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00098 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00099 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00100 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00101 * 00102 ****************************************************************************** 00103 */ 00104 00105 /* Includes ------------------------------------------------------------------*/ 00106 #include "stm32l4xx_hal.h" 00107 00108 /** @addtogroup STM32L4xx_HAL_Driver 00109 * @{ 00110 */ 00111 00112 /** @defgroup DMA DMA 00113 * @brief DMA HAL module driver 00114 * @{ 00115 */ 00116 00117 #ifdef HAL_DMA_MODULE_ENABLED 00118 00119 /* Private typedef -----------------------------------------------------------*/ 00120 /* Private define ------------------------------------------------------------*/ 00121 /* Private macro -------------------------------------------------------------*/ 00122 /* Private variables ---------------------------------------------------------*/ 00123 /* Private function prototypes -----------------------------------------------*/ 00124 /** @defgroup DMA_Private_Functions DMA Private Functions 00125 * @{ 00126 */ 00127 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); 00128 #if defined(DMAMUX1) 00129 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma); 00130 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma); 00131 #endif /* DMAMUX1 */ 00132 00133 /** 00134 * @} 00135 */ 00136 00137 /* Exported functions ---------------------------------------------------------*/ 00138 00139 /** @defgroup DMA_Exported_Functions DMA Exported Functions 00140 * @{ 00141 */ 00142 00143 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions 00144 * @brief Initialization and de-initialization functions 00145 * 00146 @verbatim 00147 =============================================================================== 00148 ##### Initialization and de-initialization functions ##### 00149 =============================================================================== 00150 [..] 00151 This section provides functions allowing to initialize the DMA Channel source 00152 and destination addresses, incrementation and data sizes, transfer direction, 00153 circular/normal mode selection, memory-to-memory mode selection and Channel priority value. 00154 [..] 00155 The HAL_DMA_Init() function follows the DMA configuration procedures as described in 00156 reference manual. 00157 00158 @endverbatim 00159 * @{ 00160 */ 00161 00162 /** 00163 * @brief Initialize the DMA according to the specified 00164 * parameters in the DMA_InitTypeDef and initialize the associated handle. 00165 * @param hdma Pointer to a DMA_HandleTypeDef structure that contains 00166 * the configuration information for the specified DMA Channel. 00167 * @retval HAL status 00168 */ 00169 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma) 00170 { 00171 uint32_t tmp; 00172 00173 /* Check the DMA handle allocation */ 00174 if(hdma == NULL) 00175 { 00176 return HAL_ERROR; 00177 } 00178 00179 /* Check the parameters */ 00180 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); 00181 assert_param(IS_DMA_DIRECTION(hdma->Init.Direction)); 00182 assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc)); 00183 assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc)); 00184 assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment)); 00185 assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment)); 00186 assert_param(IS_DMA_MODE(hdma->Init.Mode)); 00187 assert_param(IS_DMA_PRIORITY(hdma->Init.Priority)); 00188 00189 assert_param(IS_DMA_ALL_REQUEST(hdma->Init.Request)); 00190 00191 /* Compute the channel index */ 00192 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 00193 { 00194 /* DMA1 */ 00195 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 00196 hdma->DmaBaseAddress = DMA1; 00197 } 00198 else 00199 { 00200 /* DMA2 */ 00201 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 00202 hdma->DmaBaseAddress = DMA2; 00203 } 00204 00205 /* Change DMA peripheral state */ 00206 hdma->State = HAL_DMA_STATE_BUSY; 00207 00208 /* Get the CR register value */ 00209 tmp = hdma->Instance->CCR; 00210 00211 /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR and MEM2MEM bits */ 00212 tmp &= ((uint32_t)~(DMA_CCR_PL | DMA_CCR_MSIZE | DMA_CCR_PSIZE | 00213 DMA_CCR_MINC | DMA_CCR_PINC | DMA_CCR_CIRC | 00214 DMA_CCR_DIR | DMA_CCR_MEM2MEM)); 00215 00216 /* Prepare the DMA Channel configuration */ 00217 tmp |= hdma->Init.Direction | 00218 hdma->Init.PeriphInc | hdma->Init.MemInc | 00219 hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment | 00220 hdma->Init.Mode | hdma->Init.Priority; 00221 00222 /* Write to DMA Channel CR register */ 00223 hdma->Instance->CCR = tmp; 00224 00225 00226 #if defined(DMAMUX1) 00227 /* Initialize parameters for DMAMUX channel : 00228 DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask 00229 */ 00230 DMA_CalcDMAMUXChannelBaseAndMask(hdma); 00231 00232 if(hdma->Init.Direction == DMA_MEMORY_TO_MEMORY) 00233 { 00234 /* if memory to memory force the request to 0*/ 00235 hdma->Init.Request = DMA_REQUEST_MEM2MEM; 00236 } 00237 00238 /* Set peripheral request to DMAMUX channel */ 00239 hdma->DMAmuxChannel->CCR = (hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID); 00240 00241 /* Clear the DMAMUX synchro overrun flag */ 00242 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 00243 00244 if(((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 00245 { 00246 /* Initialize parameters for DMAMUX request generator : 00247 DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask 00248 */ 00249 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 00250 00251 /* Reset the DMAMUX request generator register*/ 00252 hdma->DMAmuxRequestGen->RGCR = 0U; 00253 00254 /* Clear the DMAMUX request generator overrun flag */ 00255 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 00256 } 00257 else 00258 { 00259 hdma->DMAmuxRequestGen = 0U; 00260 hdma->DMAmuxRequestGenStatus = 0U; 00261 hdma->DMAmuxRequestGenStatusMask = 0U; 00262 } 00263 #endif /* DMAMUX1 */ 00264 00265 #if !defined (DMAMUX1) 00266 00267 /* Set request selection */ 00268 if(hdma->Init.Direction != DMA_MEMORY_TO_MEMORY) 00269 { 00270 /* Write to DMA channel selection register */ 00271 if (DMA1 == hdma->DmaBaseAddress) 00272 { 00273 /* Reset request selection for DMA1 Channelx */ 00274 DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); 00275 00276 /* Configure request selection for DMA1 Channelx */ 00277 DMA1_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); 00278 } 00279 else /* DMA2 */ 00280 { 00281 /* Reset request selection for DMA2 Channelx */ 00282 DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); 00283 00284 /* Configure request selection for DMA2 Channelx */ 00285 DMA2_CSELR->CSELR |= (uint32_t) (hdma->Init.Request << (hdma->ChannelIndex & 0x1cU)); 00286 } 00287 } 00288 00289 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ 00290 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ 00291 /* STM32L496xx || STM32L4A6xx */ 00292 00293 /* Initialise the error code */ 00294 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 00295 00296 /* Initialize the DMA state*/ 00297 hdma->State = HAL_DMA_STATE_READY; 00298 00299 /* Allocate lock resource and initialize it */ 00300 hdma->Lock = HAL_UNLOCKED; 00301 00302 return HAL_OK; 00303 } 00304 00305 /** 00306 * @brief DeInitialize the DMA peripheral. 00307 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00308 * the configuration information for the specified DMA Channel. 00309 * @retval HAL status 00310 */ 00311 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma) 00312 { 00313 00314 /* Check the DMA handle allocation */ 00315 if (NULL == hdma ) 00316 { 00317 return HAL_ERROR; 00318 } 00319 00320 /* Check the parameters */ 00321 assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance)); 00322 00323 /* Disable the selected DMA Channelx */ 00324 __HAL_DMA_DISABLE(hdma); 00325 00326 /* Compute the channel index */ 00327 if ((uint32_t)(hdma->Instance) < (uint32_t)(DMA2_Channel1)) 00328 { 00329 /* DMA1 */ 00330 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA1_Channel1) / ((uint32_t)DMA1_Channel2 - (uint32_t)DMA1_Channel1)) << 2; 00331 hdma->DmaBaseAddress = DMA1; 00332 } 00333 else 00334 { 00335 /* DMA2 */ 00336 hdma->ChannelIndex = (((uint32_t)hdma->Instance - (uint32_t)DMA2_Channel1) / ((uint32_t)DMA2_Channel2 - (uint32_t)DMA2_Channel1)) << 2; 00337 hdma->DmaBaseAddress = DMA2; 00338 } 00339 00340 /* Reset DMA Channel control register */ 00341 hdma->Instance->CCR = 0; 00342 00343 /* Clear all flags */ 00344 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 00345 00346 #if !defined (DMAMUX1) 00347 00348 /* Reset DMA channel selection register */ 00349 if (DMA1 == hdma->DmaBaseAddress) 00350 { 00351 /* DMA1 */ 00352 DMA1_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); 00353 } 00354 else 00355 { 00356 /* DMA2 */ 00357 DMA2_CSELR->CSELR &= ~(DMA_CSELR_C1S << (hdma->ChannelIndex & 0x1cU)); 00358 } 00359 #endif /* STM32L431xx || STM32L432xx || STM32L433xx || STM32L442xx || STM32L443xx */ 00360 /* STM32L471xx || STM32L475xx || STM32L476xx || STM32L442xx || STM32L486xx */ 00361 /* STM32L496xx || STM32L4A6xx */ 00362 00363 #if defined(DMAMUX1) 00364 00365 /* Initialize parameters for DMAMUX channel : 00366 DMAmuxChannel, DMAmuxChannelStatus and DMAmuxChannelStatusMask */ 00367 00368 DMA_CalcDMAMUXChannelBaseAndMask(hdma); 00369 00370 /* Reset the DMAMUX channel that corresponds to the DMA channel */ 00371 hdma->DMAmuxChannel->CCR = 0; 00372 00373 /* Clear the DMAMUX synchro overrun flag */ 00374 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 00375 00376 /* Reset Request generator parameters if any */ 00377 if(((hdma->Init.Request > 0UL) && (hdma->Init.Request <= DMA_REQUEST_GENERATOR3))) 00378 { 00379 /* Initialize parameters for DMAMUX request generator : 00380 DMAmuxRequestGen, DMAmuxRequestGenStatus and DMAmuxRequestGenStatusMask 00381 */ 00382 DMA_CalcDMAMUXRequestGenBaseAndMask(hdma); 00383 00384 /* Reset the DMAMUX request generator register*/ 00385 hdma->DMAmuxRequestGen->RGCR = 0U; 00386 00387 /* Clear the DMAMUX request generator overrun flag */ 00388 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 00389 } 00390 00391 hdma->DMAmuxRequestGen = 0U; 00392 hdma->DMAmuxRequestGenStatus = 0U; 00393 hdma->DMAmuxRequestGenStatusMask = 0U; 00394 00395 #endif /* DMAMUX1 */ 00396 00397 /* Clean callbacks */ 00398 hdma->XferCpltCallback = NULL; 00399 hdma->XferHalfCpltCallback = NULL; 00400 hdma->XferErrorCallback = NULL; 00401 hdma->XferAbortCallback = NULL; 00402 00403 /* Initialise the error code */ 00404 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 00405 00406 /* Initialize the DMA state */ 00407 hdma->State = HAL_DMA_STATE_RESET; 00408 00409 /* Release Lock */ 00410 __HAL_UNLOCK(hdma); 00411 00412 return HAL_OK; 00413 } 00414 00415 /** 00416 * @} 00417 */ 00418 00419 /** @defgroup DMA_Exported_Functions_Group2 Input and Output operation functions 00420 * @brief Input and Output operation functions 00421 * 00422 @verbatim 00423 =============================================================================== 00424 ##### IO operation functions ##### 00425 =============================================================================== 00426 [..] This section provides functions allowing to: 00427 (+) Configure the source, destination address and data length and Start DMA transfer 00428 (+) Configure the source, destination address and data length and 00429 Start DMA transfer with interrupt 00430 (+) Abort DMA transfer 00431 (+) Poll for transfer complete 00432 (+) Handle DMA interrupt request 00433 00434 @endverbatim 00435 * @{ 00436 */ 00437 00438 /** 00439 * @brief Start the DMA Transfer. 00440 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00441 * the configuration information for the specified DMA Channel. 00442 * @param SrcAddress The source memory Buffer address 00443 * @param DstAddress The destination memory Buffer address 00444 * @param DataLength The length of data to be transferred from source to destination 00445 * @retval HAL status 00446 */ 00447 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) 00448 { 00449 HAL_StatusTypeDef status = HAL_OK; 00450 00451 /* Check the parameters */ 00452 assert_param(IS_DMA_BUFFER_SIZE(DataLength)); 00453 00454 /* Process locked */ 00455 __HAL_LOCK(hdma); 00456 00457 if(HAL_DMA_STATE_READY == hdma->State) 00458 { 00459 /* Change DMA peripheral state */ 00460 hdma->State = HAL_DMA_STATE_BUSY; 00461 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 00462 00463 /* Disable the peripheral */ 00464 __HAL_DMA_DISABLE(hdma); 00465 00466 /* Configure the source, destination address and the data length & clear flags*/ 00467 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 00468 00469 /* Enable the Peripheral */ 00470 __HAL_DMA_ENABLE(hdma); 00471 } 00472 else 00473 { 00474 /* Process Unlocked */ 00475 __HAL_UNLOCK(hdma); 00476 status = HAL_BUSY; 00477 } 00478 return status; 00479 } 00480 00481 /** 00482 * @brief Start the DMA Transfer with interrupt enabled. 00483 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00484 * the configuration information for the specified DMA Channel. 00485 * @param SrcAddress The source memory Buffer address 00486 * @param DstAddress The destination memory Buffer address 00487 * @param DataLength The length of data to be transferred from source to destination 00488 * @retval HAL status 00489 */ 00490 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) 00491 { 00492 HAL_StatusTypeDef status = HAL_OK; 00493 00494 /* Check the parameters */ 00495 assert_param(IS_DMA_BUFFER_SIZE(DataLength)); 00496 00497 /* Process locked */ 00498 __HAL_LOCK(hdma); 00499 00500 if(HAL_DMA_STATE_READY == hdma->State) 00501 { 00502 /* Change DMA peripheral state */ 00503 hdma->State = HAL_DMA_STATE_BUSY; 00504 hdma->ErrorCode = HAL_DMA_ERROR_NONE; 00505 00506 /* Disable the peripheral */ 00507 __HAL_DMA_DISABLE(hdma); 00508 00509 /* Configure the source, destination address and the data length & clear flags*/ 00510 DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength); 00511 00512 /* Enable the transfer complete interrupt */ 00513 /* Enable the transfer Error interrupt */ 00514 if(NULL != hdma->XferHalfCpltCallback ) 00515 { 00516 /* Enable the Half transfer complete interrupt as well */ 00517 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 00518 } 00519 else 00520 { 00521 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 00522 __HAL_DMA_ENABLE_IT(hdma, (DMA_IT_TC | DMA_IT_TE)); 00523 } 00524 00525 #ifdef DMAMUX1 00526 00527 /* Check if DMAMUX Synchronization is enabled*/ 00528 if((hdma->DMAmuxChannel->CCR & DMAMUX_CxCR_SE) != 0U) 00529 { 00530 /* Enable DMAMUX sync overrun IT*/ 00531 hdma->DMAmuxChannel->CCR |= DMAMUX_CxCR_SOIE; 00532 } 00533 00534 if(hdma->DMAmuxRequestGen != 0U) 00535 { 00536 /* if using DMAMUX request generator, enable the DMAMUX request generator overrun IT*/ 00537 /* enable the request gen overrun IT*/ 00538 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 00539 } 00540 00541 #endif /* DMAMUX1 */ 00542 00543 /* Enable the Peripheral */ 00544 __HAL_DMA_ENABLE(hdma); 00545 } 00546 else 00547 { 00548 /* Process Unlocked */ 00549 __HAL_UNLOCK(hdma); 00550 00551 /* Remain BUSY */ 00552 status = HAL_BUSY; 00553 } 00554 return status; 00555 } 00556 00557 /** 00558 * @brief Abort the DMA Transfer. 00559 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00560 * the configuration information for the specified DMA Channel. 00561 * @retval HAL status 00562 */ 00563 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma) 00564 { 00565 HAL_StatusTypeDef status = HAL_OK; 00566 00567 /* Check the DMA peripheral handle */ 00568 if(NULL == hdma) 00569 { 00570 return HAL_ERROR; 00571 } 00572 00573 /* Disable DMA IT */ 00574 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 00575 00576 #if defined(DMAMUX1) 00577 /* disable the DMAMUX sync overrun IT*/ 00578 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 00579 #endif /* DMAMUX1 */ 00580 00581 /* Disable the channel */ 00582 __HAL_DMA_DISABLE(hdma); 00583 00584 /* Clear all flags */ 00585 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 00586 00587 #if defined(DMAMUX1) 00588 /* Clear the DMAMUX synchro overrun flag */ 00589 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 00590 00591 if(hdma->DMAmuxRequestGen != 0U) 00592 { 00593 /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ 00594 /* disable the request gen overrun IT*/ 00595 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 00596 00597 /* Clear the DMAMUX request generator overrun flag */ 00598 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 00599 } 00600 00601 #endif /* DMAMUX1 */ 00602 00603 /* Change the DMA state */ 00604 hdma->State = HAL_DMA_STATE_READY; 00605 00606 /* Process Unlocked */ 00607 __HAL_UNLOCK(hdma); 00608 00609 return status; 00610 } 00611 00612 /** 00613 * @brief Aborts the DMA Transfer in Interrupt mode. 00614 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00615 * the configuration information for the specified DMA Channel. 00616 * @retval HAL status 00617 */ 00618 HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma) 00619 { 00620 HAL_StatusTypeDef status = HAL_OK; 00621 00622 if(HAL_DMA_STATE_BUSY != hdma->State) 00623 { 00624 /* no transfer ongoing */ 00625 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 00626 00627 status = HAL_ERROR; 00628 } 00629 else 00630 { 00631 /* Disable DMA IT */ 00632 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 00633 00634 /* Disable the channel */ 00635 __HAL_DMA_DISABLE(hdma); 00636 00637 #if defined(DMAMUX1) 00638 /* disable the DMAMUX sync overrun IT*/ 00639 hdma->DMAmuxChannel->CCR &= ~DMAMUX_CxCR_SOIE; 00640 00641 /* Clear all flags */ 00642 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 00643 00644 /* Clear the DMAMUX synchro overrun flag */ 00645 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 00646 00647 if(hdma->DMAmuxRequestGen != 0U) 00648 { 00649 /* if using DMAMUX request generator, disable the DMAMUX request generator overrun IT*/ 00650 /* disable the request gen overrun IT*/ 00651 hdma->DMAmuxRequestGen->RGCR &= ~DMAMUX_RGxCR_OIE; 00652 00653 /* Clear the DMAMUX request generator overrun flag */ 00654 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 00655 } 00656 00657 #else 00658 /* Clear all flags */ 00659 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 00660 #endif /* DMAMUX1 */ 00661 00662 /* Change the DMA state */ 00663 hdma->State = HAL_DMA_STATE_READY; 00664 00665 /* Process Unlocked */ 00666 __HAL_UNLOCK(hdma); 00667 00668 /* Call User Abort callback */ 00669 if(hdma->XferAbortCallback != NULL) 00670 { 00671 hdma->XferAbortCallback(hdma); 00672 } 00673 } 00674 return status; 00675 } 00676 00677 /** 00678 * @brief Polling for transfer complete. 00679 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00680 * the configuration information for the specified DMA Channel. 00681 * @param CompleteLevel Specifies the DMA level complete. 00682 * @param Timeout Timeout duration. 00683 * @retval HAL status 00684 */ 00685 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout) 00686 { 00687 uint32_t temp; 00688 uint32_t tickstart; 00689 00690 if(HAL_DMA_STATE_BUSY != hdma->State) 00691 { 00692 /* no transfer ongoing */ 00693 hdma->ErrorCode = HAL_DMA_ERROR_NO_XFER; 00694 __HAL_UNLOCK(hdma); 00695 return HAL_ERROR; 00696 } 00697 00698 /* Polling mode not supported in circular mode */ 00699 if (0U != (hdma->Instance->CCR & DMA_CCR_CIRC)) 00700 { 00701 hdma->ErrorCode = HAL_DMA_ERROR_NOT_SUPPORTED; 00702 return HAL_ERROR; 00703 } 00704 00705 /* Get the level transfer complete flag */ 00706 if (HAL_DMA_FULL_TRANSFER == CompleteLevel) 00707 { 00708 /* Transfer Complete flag */ 00709 temp = DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU); 00710 } 00711 else 00712 { 00713 /* Half Transfer Complete flag */ 00714 temp = DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU); 00715 } 00716 00717 /* Get tick */ 00718 tickstart = HAL_GetTick(); 00719 00720 while(0U == (hdma->DmaBaseAddress->ISR & temp)) 00721 { 00722 if((0U != (hdma->DmaBaseAddress->ISR & (DMA_FLAG_TE1 << (hdma->ChannelIndex& 0x1cU))))) 00723 { 00724 /* When a DMA transfer error occurs */ 00725 /* A hardware clear of its EN bits is performed */ 00726 /* Clear all flags */ 00727 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 00728 00729 /* Update error code */ 00730 hdma->ErrorCode = HAL_DMA_ERROR_TE; 00731 00732 /* Change the DMA state */ 00733 hdma->State= HAL_DMA_STATE_READY; 00734 00735 /* Process Unlocked */ 00736 __HAL_UNLOCK(hdma); 00737 00738 return HAL_ERROR; 00739 } 00740 /* Check for the Timeout */ 00741 if(Timeout != HAL_MAX_DELAY) 00742 { 00743 if(((HAL_GetTick() - tickstart) > Timeout) || (Timeout == 0U)) 00744 { 00745 /* Update error code */ 00746 hdma->ErrorCode = HAL_DMA_ERROR_TIMEOUT; 00747 00748 /* Change the DMA state */ 00749 hdma->State = HAL_DMA_STATE_READY; 00750 00751 /* Process Unlocked */ 00752 __HAL_UNLOCK(hdma); 00753 00754 return HAL_ERROR; 00755 } 00756 } 00757 } 00758 00759 #if defined(DMAMUX1) 00760 /*Check for DMAMUX Request generator (if used) overrun status */ 00761 if(hdma->DMAmuxRequestGen != 0U) 00762 { 00763 /* if using DMAMUX request generator Check for DMAMUX request generator overrun */ 00764 if((hdma->DMAmuxRequestGenStatus->RGSR & hdma->DMAmuxRequestGenStatusMask) != 0U) 00765 { 00766 /* Disable the request gen overrun interrupt */ 00767 hdma->DMAmuxRequestGen->RGCR |= DMAMUX_RGxCR_OIE; 00768 00769 /* Clear the DMAMUX request generator overrun flag */ 00770 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 00771 00772 /* Update error code */ 00773 hdma->ErrorCode |= HAL_DMA_ERROR_REQGEN; 00774 } 00775 } 00776 00777 /* Check for DMAMUX Synchronization overrun */ 00778 if((hdma->DMAmuxChannelStatus->CSR & hdma->DMAmuxChannelStatusMask) != 0U) 00779 { 00780 /* Clear the DMAMUX synchro overrun flag */ 00781 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 00782 00783 /* Update error code */ 00784 hdma->ErrorCode |= HAL_DMA_ERROR_SYNC; 00785 } 00786 #endif /* DMAMUX1 */ 00787 00788 if(HAL_DMA_FULL_TRANSFER == CompleteLevel) 00789 { 00790 /* Clear the transfer complete flag */ 00791 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_TC1 << (hdma->ChannelIndex& 0x1cU)); 00792 00793 /* The selected Channelx EN bit is cleared (DMA is disabled and 00794 all transfers are complete) */ 00795 hdma->State = HAL_DMA_STATE_READY; 00796 } 00797 else 00798 { 00799 /* Clear the half transfer complete flag */ 00800 hdma->DmaBaseAddress->IFCR = (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)); 00801 } 00802 00803 /* Process unlocked */ 00804 __HAL_UNLOCK(hdma); 00805 00806 return HAL_OK; 00807 } 00808 00809 /** 00810 * @brief Handle DMA interrupt request. 00811 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00812 * the configuration information for the specified DMA Channel. 00813 * @retval None 00814 */ 00815 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) 00816 { 00817 uint32_t flag_it = hdma->DmaBaseAddress->ISR; 00818 uint32_t source_it = hdma->Instance->CCR; 00819 00820 /* Half Transfer Complete Interrupt management ******************************/ 00821 if ((0U != (flag_it & (DMA_FLAG_HT1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_HT))) 00822 { 00823 /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */ 00824 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 00825 { 00826 /* Disable the half transfer interrupt */ 00827 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT); 00828 } 00829 /* Clear the half transfer complete flag */ 00830 hdma->DmaBaseAddress->IFCR = DMA_ISR_HTIF1 << (hdma->ChannelIndex & 0x1cU); 00831 00832 /* DMA peripheral state is not updated in Half Transfer */ 00833 /* but in Transfer Complete case */ 00834 00835 if(hdma->XferHalfCpltCallback != NULL) 00836 { 00837 /* Half transfer callback */ 00838 hdma->XferHalfCpltCallback(hdma); 00839 } 00840 } 00841 00842 /* Transfer Complete Interrupt management ***********************************/ 00843 else if ((0U != (flag_it & (DMA_FLAG_TC1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TC))) 00844 { 00845 if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U) 00846 { 00847 /* Disable the transfer complete and error interrupt */ 00848 __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE | DMA_IT_TC); 00849 00850 /* Change the DMA state */ 00851 hdma->State = HAL_DMA_STATE_READY; 00852 } 00853 /* Clear the transfer complete flag */ 00854 hdma->DmaBaseAddress->IFCR = (DMA_ISR_TCIF1 << (hdma->ChannelIndex & 0x1cU)); 00855 00856 /* Process Unlocked */ 00857 __HAL_UNLOCK(hdma); 00858 00859 if(hdma->XferCpltCallback != NULL) 00860 { 00861 /* Transfer complete callback */ 00862 hdma->XferCpltCallback(hdma); 00863 } 00864 } 00865 00866 /* Transfer Error Interrupt management **************************************/ 00867 else if ((0U != (flag_it & (DMA_FLAG_TE1 << (hdma->ChannelIndex & 0x1cU)))) && (0U != (source_it & DMA_IT_TE))) 00868 { 00869 /* When a DMA transfer error occurs */ 00870 /* A hardware clear of its EN bits is performed */ 00871 /* Disable ALL DMA IT */ 00872 __HAL_DMA_DISABLE_IT(hdma, (DMA_IT_TC | DMA_IT_HT | DMA_IT_TE)); 00873 00874 /* Clear all flags */ 00875 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 00876 00877 /* Update error code */ 00878 hdma->ErrorCode = HAL_DMA_ERROR_TE; 00879 00880 /* Change the DMA state */ 00881 hdma->State = HAL_DMA_STATE_READY; 00882 00883 /* Process Unlocked */ 00884 __HAL_UNLOCK(hdma); 00885 00886 if (hdma->XferErrorCallback != NULL) 00887 { 00888 /* Transfer error callback */ 00889 hdma->XferErrorCallback(hdma); 00890 } 00891 } 00892 else 00893 { 00894 /* Nothing To Do */ 00895 } 00896 return; 00897 } 00898 00899 /** 00900 * @brief Register callbacks 00901 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00902 * the configuration information for the specified DMA Channel. 00903 * @param CallbackID User Callback identifer 00904 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. 00905 * @param pCallback pointer to private callbacsk function which has pointer to 00906 * a DMA_HandleTypeDef structure as parameter. 00907 * @retval HAL status 00908 */ 00909 HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)( DMA_HandleTypeDef * _hdma)) 00910 { 00911 HAL_StatusTypeDef status = HAL_OK; 00912 00913 /* Process locked */ 00914 __HAL_LOCK(hdma); 00915 00916 if(HAL_DMA_STATE_READY == hdma->State) 00917 { 00918 switch (CallbackID) 00919 { 00920 case HAL_DMA_XFER_CPLT_CB_ID: 00921 hdma->XferCpltCallback = pCallback; 00922 break; 00923 00924 case HAL_DMA_XFER_HALFCPLT_CB_ID: 00925 hdma->XferHalfCpltCallback = pCallback; 00926 break; 00927 00928 case HAL_DMA_XFER_ERROR_CB_ID: 00929 hdma->XferErrorCallback = pCallback; 00930 break; 00931 00932 case HAL_DMA_XFER_ABORT_CB_ID: 00933 hdma->XferAbortCallback = pCallback; 00934 break; 00935 00936 default: 00937 status = HAL_ERROR; 00938 break; 00939 } 00940 } 00941 else 00942 { 00943 status = HAL_ERROR; 00944 } 00945 00946 /* Release Lock */ 00947 __HAL_UNLOCK(hdma); 00948 00949 return status; 00950 } 00951 00952 /** 00953 * @brief UnRegister callbacks 00954 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 00955 * the configuration information for the specified DMA Channel. 00956 * @param CallbackID User Callback identifer 00957 * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. 00958 * @retval HAL status 00959 */ 00960 HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID) 00961 { 00962 HAL_StatusTypeDef status = HAL_OK; 00963 00964 /* Process locked */ 00965 __HAL_LOCK(hdma); 00966 00967 if(HAL_DMA_STATE_READY == hdma->State) 00968 { 00969 switch (CallbackID) 00970 { 00971 case HAL_DMA_XFER_CPLT_CB_ID: 00972 hdma->XferCpltCallback = NULL; 00973 break; 00974 00975 case HAL_DMA_XFER_HALFCPLT_CB_ID: 00976 hdma->XferHalfCpltCallback = NULL; 00977 break; 00978 00979 case HAL_DMA_XFER_ERROR_CB_ID: 00980 hdma->XferErrorCallback = NULL; 00981 break; 00982 00983 case HAL_DMA_XFER_ABORT_CB_ID: 00984 hdma->XferAbortCallback = NULL; 00985 break; 00986 00987 case HAL_DMA_XFER_ALL_CB_ID: 00988 hdma->XferCpltCallback = NULL; 00989 hdma->XferHalfCpltCallback = NULL; 00990 hdma->XferErrorCallback = NULL; 00991 hdma->XferAbortCallback = NULL; 00992 break; 00993 00994 default: 00995 status = HAL_ERROR; 00996 break; 00997 } 00998 } 00999 else 01000 { 01001 status = HAL_ERROR; 01002 } 01003 01004 /* Release Lock */ 01005 __HAL_UNLOCK(hdma); 01006 01007 return status; 01008 } 01009 01010 /** 01011 * @} 01012 */ 01013 01014 01015 01016 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State and Errors functions 01017 * @brief Peripheral State and Errors functions 01018 * 01019 @verbatim 01020 =============================================================================== 01021 ##### Peripheral State and Errors functions ##### 01022 =============================================================================== 01023 [..] 01024 This subsection provides functions allowing to 01025 (+) Check the DMA state 01026 (+) Get error code 01027 01028 @endverbatim 01029 * @{ 01030 */ 01031 01032 /** 01033 * @brief Return the DMA hande state. 01034 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01035 * the configuration information for the specified DMA Channel. 01036 * @retval HAL state 01037 */ 01038 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma) 01039 { 01040 /* Return DMA handle state */ 01041 return hdma->State; 01042 } 01043 01044 /** 01045 * @brief Return the DMA error code. 01046 * @param hdma : pointer to a DMA_HandleTypeDef structure that contains 01047 * the configuration information for the specified DMA Channel. 01048 * @retval DMA Error Code 01049 */ 01050 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma) 01051 { 01052 return hdma->ErrorCode; 01053 } 01054 01055 /** 01056 * @} 01057 */ 01058 01059 /** 01060 * @} 01061 */ 01062 01063 /** @addtogroup DMA_Private_Functions 01064 * @{ 01065 */ 01066 01067 /** 01068 * @brief Sets the DMA Transfer parameter. 01069 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01070 * the configuration information for the specified DMA Channel. 01071 * @param SrcAddress The source memory Buffer address 01072 * @param DstAddress The destination memory Buffer address 01073 * @param DataLength The length of data to be transferred from source to destination 01074 * @retval HAL status 01075 */ 01076 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength) 01077 { 01078 #if defined(DMAMUX1) 01079 /* Clear the DMAMUX synchro overrun flag */ 01080 hdma->DMAmuxChannelStatus->CFR = hdma->DMAmuxChannelStatusMask; 01081 01082 if(hdma->DMAmuxRequestGen != 0U) 01083 { 01084 /* Clear the DMAMUX request generator overrun flag */ 01085 hdma->DMAmuxRequestGenStatus->RGCFR = hdma->DMAmuxRequestGenStatusMask; 01086 } 01087 #endif 01088 01089 /* Clear all flags */ 01090 hdma->DmaBaseAddress->IFCR = (DMA_ISR_GIF1 << (hdma->ChannelIndex & 0x1cU)); 01091 01092 /* Configure DMA Channel data length */ 01093 hdma->Instance->CNDTR = DataLength; 01094 01095 /* Memory to Peripheral */ 01096 if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH) 01097 { 01098 /* Configure DMA Channel destination address */ 01099 hdma->Instance->CPAR = DstAddress; 01100 01101 /* Configure DMA Channel source address */ 01102 hdma->Instance->CMAR = SrcAddress; 01103 } 01104 /* Peripheral to Memory */ 01105 else 01106 { 01107 /* Configure DMA Channel source address */ 01108 hdma->Instance->CPAR = SrcAddress; 01109 01110 /* Configure DMA Channel destination address */ 01111 hdma->Instance->CMAR = DstAddress; 01112 } 01113 } 01114 01115 #if defined(DMAMUX1) 01116 01117 /** 01118 * @brief Updates the DMA handle with the DMAMUX channel and status mask depending on stream number 01119 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01120 * the configuration information for the specified DMA Stream. 01121 * @retval None 01122 */ 01123 static void DMA_CalcDMAMUXChannelBaseAndMask(DMA_HandleTypeDef *hdma) 01124 { 01125 uint32_t channel_number; 01126 DMAMUX_Channel_TypeDef *DMAMUX1_ChannelBase; 01127 01128 /* check if instance is not outside the DMA channel range */ 01129 if ((uint32_t)hdma->Instance < (uint32_t)DMA2_Channel1) 01130 { 01131 /* DMA1 */ 01132 DMAMUX1_ChannelBase = DMAMUX1_Channel0; 01133 } 01134 else 01135 { 01136 /* DMA2 */ 01137 DMAMUX1_ChannelBase = DMAMUX1_Channel7; 01138 } 01139 channel_number = (((uint32_t)hdma->Instance & 0xFFU) - 8U) / 20U; 01140 hdma->DMAmuxChannel = (DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_ChannelBase + ((hdma->ChannelIndex >> 2U) * ((uint32_t)DMAMUX1_Channel1 - (uint32_t)DMAMUX1_Channel0))); 01141 hdma->DMAmuxChannelStatus = DMAMUX1_ChannelStatus; 01142 hdma->DMAmuxChannelStatusMask = 1UL << (channel_number & 0x1cU); 01143 } 01144 01145 /** 01146 * @brief Updates the DMA handle with the DMAMUX request generator params 01147 * @param hdma pointer to a DMA_HandleTypeDef structure that contains 01148 * the configuration information for the specified DMA Stream. 01149 * @retval None 01150 */ 01151 01152 static void DMA_CalcDMAMUXRequestGenBaseAndMask(DMA_HandleTypeDef *hdma) 01153 { 01154 uint32_t request = hdma->Init.Request & DMAMUX_CxCR_DMAREQ_ID; 01155 01156 /* DMA Channels are connected to DMAMUX1 request generator blocks*/ 01157 hdma->DMAmuxRequestGen = (DMAMUX_RequestGen_TypeDef *)((uint32_t)(((uint32_t)DMAMUX1_RequestGenerator0) + ((request - 1U) * 4U))); 01158 01159 hdma->DMAmuxRequestGenStatus = DMAMUX1_RequestGenStatus; 01160 01161 /* here "Request" is either DMA_REQUEST_GENERATOR0 to 4, i.e. <= 4*/ 01162 hdma->DMAmuxRequestGenStatusMask = 1UL << ((request - 1U) & 0x3U); 01163 01164 } 01165 01166 #endif /* DMAMUX1 */ 01167 01168 /** 01169 * @} 01170 */ 01171 01172 /** 01173 * @} 01174 */ 01175 01176 #endif /* HAL_DMA_MODULE_ENABLED */ 01177 /** 01178 * @} 01179 */ 01180 01181 /** 01182 * @} 01183 */ 01184 01185 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/