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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dma2d.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA2D HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef STM32L4xx_HAL_DMA2D_H 00038 #define STM32L4xx_HAL_DMA2D_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 #if defined (DMA2D) 00045 /* Includes ------------------------------------------------------------------*/ 00046 #include "stm32l4xx_hal_def.h" 00047 00048 /** @addtogroup STM32L4xx_HAL_Driver 00049 * @{ 00050 */ 00051 00052 /** @addtogroup DMA2D DMA2D 00053 * @brief DMA2D HAL module driver 00054 * @{ 00055 */ 00056 00057 /* Exported types ------------------------------------------------------------*/ 00058 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types 00059 * @{ 00060 */ 00061 #define MAX_DMA2D_LAYER 2U /*!< DMA2D maximum number of layers */ 00062 00063 /** 00064 * @brief DMA2D color Structure definition 00065 */ 00066 typedef struct 00067 { 00068 uint32_t Blue; /*!< Configures the blue value. 00069 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 00070 00071 uint32_t Green; /*!< Configures the green value. 00072 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 00073 00074 uint32_t Red; /*!< Configures the red value. 00075 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */ 00076 } DMA2D_ColorTypeDef; 00077 00078 /** 00079 * @brief DMA2D CLUT Structure definition 00080 */ 00081 typedef struct 00082 { 00083 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/ 00084 00085 uint32_t CLUTColorMode; /*!< Configures the DMA2D CLUT color mode. 00086 This parameter can be one value of @ref DMA2D_CLUT_CM. */ 00087 00088 uint32_t Size; /*!< Configures the DMA2D CLUT size. 00089 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/ 00090 } DMA2D_CLUTCfgTypeDef; 00091 00092 /** 00093 * @brief DMA2D Init structure definition 00094 */ 00095 typedef struct 00096 { 00097 uint32_t Mode; /*!< Configures the DMA2D transfer mode. 00098 This parameter can be one value of @ref DMA2D_Mode. */ 00099 00100 uint32_t ColorMode; /*!< Configures the color format of the output image. 00101 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */ 00102 00103 uint32_t OutputOffset; /*!< Specifies the Offset value. 00104 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 00105 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value for the output pixel format converter. 00106 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 00107 00108 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR) 00109 for the output pixel format converter. 00110 This parameter can be one value of @ref DMA2D_RB_Swap. */ 00111 00112 00113 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 00114 uint32_t BytesSwap; /*!< Select byte regular mode or bytes swap mode (two by two). 00115 This parameter can be one value of @ref DMA2D_Bytes_Swap. */ 00116 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 00117 00118 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 00119 uint32_t LineOffsetMode; /*!< Configures how is expressed the line offset for the foreground, background and output. 00120 This parameter can be one value of @ref DMA2D_Line_Offset_Mode. */ 00121 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 00122 00123 } DMA2D_InitTypeDef; 00124 00125 00126 /** 00127 * @brief DMA2D Layer structure definition 00128 */ 00129 typedef struct 00130 { 00131 uint32_t InputOffset; /*!< Configures the DMA2D foreground or background offset. 00132 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */ 00133 00134 uint32_t InputColorMode; /*!< Configures the DMA2D foreground or background color mode. 00135 This parameter can be one value of @ref DMA2D_Input_Color_Mode. */ 00136 00137 uint32_t AlphaMode; /*!< Configures the DMA2D foreground or background alpha mode. 00138 This parameter can be one value of @ref DMA2D_Alpha_Mode. */ 00139 00140 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode. 00141 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below. 00142 @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between 00143 Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where 00144 - InputAlpha[24:31] is the alpha value ALPHA[0:7] 00145 - InputAlpha[16:23] is the red value RED[0:7] 00146 - InputAlpha[8:15] is the green value GREEN[0:7] 00147 - InputAlpha[0:7] is the blue value BLUE[0:7]. */ 00148 uint32_t AlphaInverted; /*!< Select regular or inverted alpha value. 00149 This parameter can be one value of @ref DMA2D_Alpha_Inverted. */ 00150 00151 uint32_t RedBlueSwap; /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR). 00152 This parameter can be one value of @ref DMA2D_RB_Swap. */ 00153 00154 00155 } DMA2D_LayerCfgTypeDef; 00156 00157 /** 00158 * @brief HAL DMA2D State structures definition 00159 */ 00160 typedef enum 00161 { 00162 HAL_DMA2D_STATE_RESET = 0x00U, /*!< DMA2D not yet initialized or disabled */ 00163 HAL_DMA2D_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ 00164 HAL_DMA2D_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ 00165 HAL_DMA2D_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ 00166 HAL_DMA2D_STATE_ERROR = 0x04U, /*!< DMA2D state error */ 00167 HAL_DMA2D_STATE_SUSPEND = 0x05U /*!< DMA2D process is suspended */ 00168 }HAL_DMA2D_StateTypeDef; 00169 00170 /** 00171 * @brief DMA2D handle Structure definition 00172 */ 00173 typedef struct __DMA2D_HandleTypeDef 00174 { 00175 DMA2D_TypeDef *Instance; /*!< DMA2D register base address. */ 00176 00177 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters. */ 00178 00179 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback. */ 00180 00181 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback. */ 00182 00183 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00184 void (* LineEventCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D line event callback. */ 00185 00186 void (* CLUTLoadingCpltCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D CLUT loading completion callback. */ 00187 00188 void (* MspInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp Init callback. */ 00189 00190 void (* MspDeInitCallback)( struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D Msp DeInit callback. */ 00191 00192 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */ 00193 00194 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */ 00195 00196 HAL_LockTypeDef Lock; /*!< DMA2D lock. */ 00197 00198 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state. */ 00199 00200 __IO uint32_t ErrorCode; /*!< DMA2D error code. */ 00201 } DMA2D_HandleTypeDef; 00202 00203 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00204 /** 00205 * @brief HAL DMA2D Callback pointer definition 00206 */ 00207 typedef void (*pDMA2D_CallbackTypeDef)(DMA2D_HandleTypeDef * hdma2d); /*!< Pointer to a DMA2D common callback function */ 00208 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00209 /** 00210 * @} 00211 */ 00212 00213 /* Exported constants --------------------------------------------------------*/ 00214 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants 00215 * @{ 00216 */ 00217 00218 /** @defgroup DMA2D_Error_Code DMA2D Error Code 00219 * @{ 00220 */ 00221 #define HAL_DMA2D_ERROR_NONE 0x00000000U /*!< No error */ 00222 #define HAL_DMA2D_ERROR_TE 0x00000001U /*!< Transfer error */ 00223 #define HAL_DMA2D_ERROR_CE 0x00000002U /*!< Configuration error */ 00224 #define HAL_DMA2D_ERROR_CAE 0x00000004U /*!< CLUT access error */ 00225 #define HAL_DMA2D_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */ 00226 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00227 #define HAL_DMA2D_ERROR_INVALID_CALLBACK 0x00000040U /*!< Invalid callback error */ 00228 #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ 00229 00230 /** 00231 * @} 00232 */ 00233 00234 /** @defgroup DMA2D_Mode DMA2D Mode 00235 * @{ 00236 */ 00237 #define DMA2D_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */ 00238 #define DMA2D_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */ 00239 #define DMA2D_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */ 00240 #define DMA2D_R2M (DMA2D_CR_MODE_1 | DMA2D_CR_MODE_0) /*!< DMA2D register to memory transfer mode */ 00241 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) 00242 #define DMA2D_M2M_BLEND_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color FG */ 00243 #define DMA2D_M2M_BLEND_BG (DMA2D_CR_MODE_2 | DMA2D_CR_MODE_0) /*!< DMA2D memory to memory with blending transfer mode and fixed color BG */ 00244 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ 00245 /** 00246 * @} 00247 */ 00248 00249 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode 00250 * @{ 00251 */ 00252 #define DMA2D_OUTPUT_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D color mode */ 00253 #define DMA2D_OUTPUT_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 DMA2D color mode */ 00254 #define DMA2D_OUTPUT_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 DMA2D color mode */ 00255 #define DMA2D_OUTPUT_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */ 00256 #define DMA2D_OUTPUT_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 DMA2D color mode */ 00257 /** 00258 * @} 00259 */ 00260 00261 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode 00262 * @{ 00263 */ 00264 #define DMA2D_INPUT_ARGB8888 0x00000000U /*!< ARGB8888 color mode */ 00265 #define DMA2D_INPUT_RGB888 0x00000001U /*!< RGB888 color mode */ 00266 #define DMA2D_INPUT_RGB565 0x00000002U /*!< RGB565 color mode */ 00267 #define DMA2D_INPUT_ARGB1555 0x00000003U /*!< ARGB1555 color mode */ 00268 #define DMA2D_INPUT_ARGB4444 0x00000004U /*!< ARGB4444 color mode */ 00269 #define DMA2D_INPUT_L8 0x00000005U /*!< L8 color mode */ 00270 #define DMA2D_INPUT_AL44 0x00000006U /*!< AL44 color mode */ 00271 #define DMA2D_INPUT_AL88 0x00000007U /*!< AL88 color mode */ 00272 #define DMA2D_INPUT_L4 0x00000008U /*!< L4 color mode */ 00273 #define DMA2D_INPUT_A8 0x00000009U /*!< A8 color mode */ 00274 #define DMA2D_INPUT_A4 0x0000000AU /*!< A4 color mode */ 00275 /** 00276 * @} 00277 */ 00278 00279 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode 00280 * @{ 00281 */ 00282 #define DMA2D_NO_MODIF_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 00283 #define DMA2D_REPLACE_ALPHA 0x00000001U /*!< Replace original alpha channel value by programmed alpha value */ 00284 #define DMA2D_COMBINE_ALPHA 0x00000002U /*!< Replace original alpha channel value by programmed alpha value 00285 with original alpha channel value */ 00286 /** 00287 * @} 00288 */ 00289 00290 /** @defgroup DMA2D_Alpha_Inverted DMA2D Alpha Inversion 00291 * @{ 00292 */ 00293 #define DMA2D_REGULAR_ALPHA 0x00000000U /*!< No modification of the alpha channel value */ 00294 #define DMA2D_INVERTED_ALPHA 0x00000001U /*!< Invert the alpha channel value */ 00295 /** 00296 * @} 00297 */ 00298 00299 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap 00300 * @{ 00301 */ 00302 #define DMA2D_RB_REGULAR 0x00000000U /*!< Select regular mode (RGB or ARGB) */ 00303 #define DMA2D_RB_SWAP 0x00000001U /*!< Select swap mode (BGR or ABGR) */ 00304 /** 00305 * @} 00306 */ 00307 00308 00309 00310 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 00311 /** @defgroup DMA2D_Line_Offset_Mode DMA2D Line Offset Mode 00312 * @{ 00313 */ 00314 #define DMA2D_LOM_PIXELS 0x00000000U /*!< Line offsets expressed in pixels */ 00315 #define DMA2D_LOM_BYTES DMA2D_CR_LOM /*!< Line offsets expressed in bytes */ 00316 /** 00317 * @} 00318 */ 00319 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 00320 00321 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 00322 /** @defgroup DMA2D_Bytes_Swap DMA2D Bytes Swap 00323 * @{ 00324 */ 00325 #define DMA2D_BYTES_REGULAR 0x00000000U /*!< Bytes in regular order in output FIFO */ 00326 #define DMA2D_BYTES_SWAP DMA2D_OPFCCR_SB /*!< Bytes are swapped two by two in output FIFO */ 00327 /** 00328 * @} 00329 */ 00330 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 00331 00332 00333 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode 00334 * @{ 00335 */ 00336 #define DMA2D_CCM_ARGB8888 0x00000000U /*!< ARGB8888 DMA2D CLUT color mode */ 00337 #define DMA2D_CCM_RGB888 0x00000001U /*!< RGB888 DMA2D CLUT color mode */ 00338 /** 00339 * @} 00340 */ 00341 00342 /** @defgroup DMA2D_Interrupts DMA2D Interrupts 00343 * @{ 00344 */ 00345 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */ 00346 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */ 00347 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */ 00348 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */ 00349 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */ 00350 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */ 00351 /** 00352 * @} 00353 */ 00354 00355 /** @defgroup DMA2D_Flags DMA2D Flags 00356 * @{ 00357 */ 00358 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */ 00359 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */ 00360 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */ 00361 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */ 00362 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */ 00363 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */ 00364 /** 00365 * @} 00366 */ 00367 00368 /** @defgroup DMA2D_Aliases DMA2D API Aliases 00369 * @{ 00370 */ 00371 #define HAL_DMA2D_DisableCLUT HAL_DMA2D_CLUTLoading_Abort /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */ 00372 /** 00373 * @} 00374 */ 00375 00376 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00377 /** 00378 * @brief HAL DMA2D common Callback ID enumeration definition 00379 */ 00380 typedef enum 00381 { 00382 HAL_DMA2D_MSPINIT_CB_ID = 0x00U, /*!< DMA2D MspInit callback ID */ 00383 HAL_DMA2D_MSPDEINIT_CB_ID = 0x01U, /*!< DMA2D MspDeInit callback ID */ 00384 HAL_DMA2D_TRANSFERCOMPLETE_CB_ID = 0x02U, /*!< DMA2D transfer complete callback ID */ 00385 HAL_DMA2D_TRANSFERERROR_CB_ID = 0x03U, /*!< DMA2D transfer error callback ID */ 00386 HAL_DMA2D_LINEEVENT_CB_ID = 0x04U, /*!< DMA2D line event callback ID */ 00387 HAL_DMA2D_CLUTLOADINGCPLT_CB_ID = 0x05U, /*!< DMA2D CLUT loading completion callback ID */ 00388 }HAL_DMA2D_CallbackIDTypeDef; 00389 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00390 00391 00392 /** 00393 * @} 00394 */ 00395 /* Exported macros ------------------------------------------------------------*/ 00396 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros 00397 * @{ 00398 */ 00399 00400 /** @brief Reset DMA2D handle state 00401 * @param __HANDLE__ specifies the DMA2D handle. 00402 * @retval None 00403 */ 00404 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00405 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) do{ \ 00406 (__HANDLE__)->State = HAL_DMA2D_STATE_RESET;\ 00407 (__HANDLE__)->MspInitCallback = NULL; \ 00408 (__HANDLE__)->MspDeInitCallback = NULL; \ 00409 }while(0) 00410 #else 00411 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) 00412 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00413 00414 00415 /** 00416 * @brief Enable the DMA2D. 00417 * @param __HANDLE__ DMA2D handle 00418 * @retval None. 00419 */ 00420 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) 00421 00422 00423 /* Interrupt & Flag management */ 00424 /** 00425 * @brief Get the DMA2D pending flags. 00426 * @param __HANDLE__ DMA2D handle 00427 * @param __FLAG__ flag to check. 00428 * This parameter can be any combination of the following values: 00429 * @arg DMA2D_FLAG_CE: Configuration error flag 00430 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 00431 * @arg DMA2D_FLAG_CAE: CLUT access error flag 00432 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 00433 * @arg DMA2D_FLAG_TC: Transfer complete flag 00434 * @arg DMA2D_FLAG_TE: Transfer error flag 00435 * @retval The state of FLAG. 00436 */ 00437 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__)) 00438 00439 /** 00440 * @brief Clear the DMA2D pending flags. 00441 * @param __HANDLE__ DMA2D handle 00442 * @param __FLAG__ specifies the flag to clear. 00443 * This parameter can be any combination of the following values: 00444 * @arg DMA2D_FLAG_CE: Configuration error flag 00445 * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag 00446 * @arg DMA2D_FLAG_CAE: CLUT access error flag 00447 * @arg DMA2D_FLAG_TW: Transfer Watermark flag 00448 * @arg DMA2D_FLAG_TC: Transfer complete flag 00449 * @arg DMA2D_FLAG_TE: Transfer error flag 00450 * @retval None 00451 */ 00452 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__)) 00453 00454 /** 00455 * @brief Enable the specified DMA2D interrupts. 00456 * @param __HANDLE__ DMA2D handle 00457 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. 00458 * This parameter can be any combination of the following values: 00459 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00460 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00461 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00462 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00463 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00464 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00465 * @retval None 00466 */ 00467 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) 00468 00469 /** 00470 * @brief Disable the specified DMA2D interrupts. 00471 * @param __HANDLE__ DMA2D handle 00472 * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. 00473 * This parameter can be any combination of the following values: 00474 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00475 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00476 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00477 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00478 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00479 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00480 * @retval None 00481 */ 00482 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) 00483 00484 /** 00485 * @brief Check whether the specified DMA2D interrupt source is enabled or not. 00486 * @param __HANDLE__ DMA2D handle 00487 * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. 00488 * This parameter can be one of the following values: 00489 * @arg DMA2D_IT_CE: Configuration error interrupt mask 00490 * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask 00491 * @arg DMA2D_IT_CAE: CLUT access error interrupt mask 00492 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask 00493 * @arg DMA2D_IT_TC: Transfer complete interrupt mask 00494 * @arg DMA2D_IT_TE: Transfer error interrupt mask 00495 * @retval The state of INTERRUPT source. 00496 */ 00497 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) 00498 00499 /** 00500 * @} 00501 */ 00502 00503 /* Exported functions --------------------------------------------------------*/ 00504 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions 00505 * @{ 00506 */ 00507 00508 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions 00509 * @{ 00510 */ 00511 00512 /* Initialization and de-initialization functions *******************************/ 00513 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d); 00514 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d); 00515 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d); 00516 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d); 00517 /* Callbacks Register/UnRegister functions ***********************************/ 00518 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1) 00519 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback); 00520 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID); 00521 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */ 00522 00523 /** 00524 * @} 00525 */ 00526 00527 00528 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions 00529 * @{ 00530 */ 00531 00532 /* IO operation functions *******************************************************/ 00533 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); 00534 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); 00535 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height); 00536 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height); 00537 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d); 00538 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d); 00539 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d); 00540 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00541 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00542 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00543 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00544 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00545 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00546 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout); 00547 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d); 00548 void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d); 00549 void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d); 00550 00551 /** 00552 * @} 00553 */ 00554 00555 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions 00556 * @{ 00557 */ 00558 00559 /* Peripheral Control functions *************************************************/ 00560 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx); 00561 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx); 00562 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line); 00563 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d); 00564 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d); 00565 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime); 00566 00567 /** 00568 * @} 00569 */ 00570 00571 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions 00572 * @{ 00573 */ 00574 00575 /* Peripheral State functions ***************************************************/ 00576 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d); 00577 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d); 00578 00579 /** 00580 * @} 00581 */ 00582 00583 /** 00584 * @} 00585 */ 00586 00587 /* Private constants ---------------------------------------------------------*/ 00588 00589 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants 00590 * @{ 00591 */ 00592 00593 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark 00594 * @{ 00595 */ 00596 #define DMA2D_LINE_WATERMARK_MAX DMA2D_LWR_LW /*!< DMA2D maximum line watermark */ 00597 /** 00598 * @} 00599 */ 00600 00601 /** @defgroup DMA2D_Color_Value DMA2D Color Value 00602 * @{ 00603 */ 00604 #define DMA2D_COLOR_VALUE 0x000000FFU /*!< Color value mask */ 00605 /** 00606 * @} 00607 */ 00608 00609 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers 00610 * @{ 00611 */ 00612 #define DMA2D_MAX_LAYER 2U /*!< DMA2D maximum number of layers */ 00613 /** 00614 * @} 00615 */ 00616 00617 /** @defgroup DMA2D_Layers DMA2D Layers 00618 * @{ 00619 */ 00620 #define DMA2D_BACKGROUND_LAYER 0x00000000U /*!< DMA2D Background Layer (layer 0) */ 00621 #define DMA2D_FOREGROUND_LAYER 0x00000001U /*!< DMA2D Foreground Layer (layer 1) */ 00622 /** 00623 * @} 00624 */ 00625 00626 /** @defgroup DMA2D_Offset DMA2D Offset 00627 * @{ 00628 */ 00629 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< maximum Line Offset */ 00630 /** 00631 * @} 00632 */ 00633 00634 /** @defgroup DMA2D_Size DMA2D Size 00635 * @{ 00636 */ 00637 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16U) /*!< DMA2D maximum number of pixels per line */ 00638 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D maximum number of lines */ 00639 /** 00640 * @} 00641 */ 00642 00643 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size 00644 * @{ 00645 */ 00646 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8U) /*!< DMA2D maximum CLUT size */ 00647 /** 00648 * @} 00649 */ 00650 00651 /** 00652 * @} 00653 */ 00654 00655 00656 /* Private macros ------------------------------------------------------------*/ 00657 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros 00658 * @{ 00659 */ 00660 #define IS_DMA2D_LAYER(LAYER) (((LAYER) == DMA2D_BACKGROUND_LAYER) || ((LAYER) == DMA2D_FOREGROUND_LAYER)) 00661 00662 #if defined(DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT) 00663 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 00664 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M) || \ 00665 ((MODE) == DMA2D_M2M_BLEND_FG) || ((MODE) == DMA2D_M2M_BLEND_BG)) 00666 #else 00667 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \ 00668 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M)) 00669 #endif /* DMA2D_M2M_BLEND_FIXED_COLOR_FG_BG_SUPPORT */ 00670 00671 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888) || \ 00672 ((MODE_ARGB) == DMA2D_OUTPUT_RGB565) || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \ 00673 ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444)) 00674 00675 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= DMA2D_COLOR_VALUE) 00676 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE) 00677 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL) 00678 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET) 00679 00680 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888) || \ 00681 ((INPUT_CM) == DMA2D_INPUT_RGB565) || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \ 00682 ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8) || \ 00683 ((INPUT_CM) == DMA2D_INPUT_AL44) || ((INPUT_CM) == DMA2D_INPUT_AL88) || \ 00684 ((INPUT_CM) == DMA2D_INPUT_L4) || ((INPUT_CM) == DMA2D_INPUT_A8) || \ 00685 ((INPUT_CM) == DMA2D_INPUT_A4)) 00686 00687 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \ 00688 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \ 00689 ((AlphaMode) == DMA2D_COMBINE_ALPHA)) 00690 00691 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \ 00692 ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA)) 00693 00694 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \ 00695 ((RB_Swap) == DMA2D_RB_SWAP)) 00696 00697 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT) 00698 #define IS_DMA2D_LOM_MODE(LOM) (((LOM) == DMA2D_LOM_PIXELS) || \ 00699 ((LOM) == DMA2D_LOM_BYTES)) 00700 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */ 00701 00702 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT) 00703 #define IS_DMA2D_BYTES_SWAP(BYTES_SWAP) (((BYTES_SWAP) == DMA2D_BYTES_REGULAR) || \ 00704 ((BYTES_SWAP) == DMA2D_BYTES_SWAP)) 00705 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */ 00706 00707 00708 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888)) 00709 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE) 00710 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX) 00711 #define IS_DMA2D_IT(IT) (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \ 00712 ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \ 00713 ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE)) 00714 #define IS_DMA2D_GET_FLAG(FLAG) (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \ 00715 ((FLAG) == DMA2D_FLAG_TW) || ((FLAG) == DMA2D_FLAG_TC) || \ 00716 ((FLAG) == DMA2D_FLAG_TE) || ((FLAG) == DMA2D_FLAG_CE)) 00717 /** 00718 * @} 00719 */ 00720 00721 /** 00722 * @} 00723 */ 00724 00725 /** 00726 * @} 00727 */ 00728 00729 #endif /* DMA2D */ 00730 00731 #ifdef __cplusplus 00732 } 00733 #endif 00734 00735 #endif /* STM32L4xx_HAL_DMA2D_H */ 00736 00737 00738 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1