STM32L486xx HAL User Manual
stm32l4xx_hal_dma2d.c
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00001 /**
00002   ******************************************************************************
00003   * @file    stm32l4xx_hal_dma2d.c
00004   * @author  MCD Application Team
00005   * @brief   DMA2D HAL module driver.
00006   *          This file provides firmware functions to manage the following
00007   *          functionalities of the DMA2D peripheral:
00008   *           + Initialization and de-initialization functions
00009   *           + IO operation functions
00010   *           + Peripheral Control functions
00011   *           + Peripheral State and Errors functions
00012   *
00013   @verbatim
00014   ==============================================================================
00015                         ##### How to use this driver #####
00016   ==============================================================================
00017     [..]
00018       (#) Program the required configuration through the following parameters:
00019           the transfer mode, the output color mode and the output offset using
00020           HAL_DMA2D_Init() function.
00021 
00022       (#) Program the required configuration through the following parameters:
00023           the input color mode, the input color, the input alpha value, the alpha mode,
00024           the red/blue swap mode, the inverted alpha mode and the input offset using
00025           HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
00026 
00027      *** Polling mode IO operation ***
00028      =================================
00029     [..]
00030        (#) Configure pdata parameter (explained hereafter), destination and data length
00031            and enable the transfer using HAL_DMA2D_Start().
00032        (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
00033            user can specify the value of timeout according to his end application.
00034 
00035      *** Interrupt mode IO operation ***
00036      ===================================
00037      [..]
00038        (#) Configure pdata parameter, destination and data length and enable
00039            the transfer using HAL_DMA2D_Start_IT().
00040        (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
00041        (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
00042            add his own function by customization of function pointer XferCpltCallback (member
00043            of DMA2D handle structure).
00044        (#) In case of error, the HAL_DMA2D_IRQHandler() function calls the callback
00045            XferErrorCallback.
00046 
00047          -@-   In Register-to-Memory transfer mode, pdata parameter is the register
00048                color, in Memory-to-memory or Memory-to-Memory with pixel format
00049                conversion pdata is the source address.
00050 
00051          -@-   Configure the foreground source address, the background source address,
00052                the destination and data length then Enable the transfer using
00053                HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
00054                in interrupt mode.
00055 
00056          -@-   HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
00057                are used if the memory to memory with blending transfer mode is selected.
00058 
00059       (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
00060           mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
00061 
00062       (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent().
00063 
00064       (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
00065           consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
00066           and enable/disable the functionality  with the APIs HAL_DMA2D_EnableDeadTime() or
00067           HAL_DMA2D_DisableDeadTime().
00068 
00069       (#) The transfer can be suspended, resumed and aborted using the following
00070           functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
00071 
00072       (#) The CLUT loading can be suspended, resumed and aborted using the following
00073           functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
00074           HAL_DMA2D_CLUTLoading_Abort().
00075 
00076       (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
00077 
00078       (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
00079 
00080      *** DMA2D HAL driver macros list ***
00081      =============================================
00082      [..]
00083        Below the list of most used macros in DMA2D HAL driver :
00084 
00085       (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
00086       (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
00087       (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
00088       (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
00089       (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
00090       (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
00091 
00092      *** Callback registration ***
00093      ===================================
00094      [..]
00095       (#) The compilation define  USE_HAL_DMA2D_REGISTER_CALLBACKS when set to 1
00096           allows the user to configure dynamically the driver callbacks.
00097           Use function @ref HAL_DMA2D_RegisterCallback() to register a user callback.
00098 
00099       (#) Function @ref HAL_DMA2D_RegisterCallback() allows to register following callbacks:
00100             (+) XferCpltCallback : callback for transfer complete.
00101             (+) XferErrorCallback : callback for transfer error.
00102             (+) LineEventCallback : callback for line event.
00103             (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
00104             (+) MspInitCallback    : DMA2D MspInit.
00105             (+) MspDeInitCallback  : DMA2D MspDeInit.
00106           This function takes as parameters the HAL peripheral handle, the Callback ID
00107           and a pointer to the user callback function.
00108 
00109       (#) Use function @ref HAL_DMA2D_UnRegisterCallback() to reset a callback to the default
00110           weak (surcharged) function.
00111           @ref HAL_DMA2D_UnRegisterCallback() takes as parameters the HAL peripheral handle,
00112           and the Callback ID.
00113           This function allows to reset following callbacks:
00114             (+) XferCpltCallback : callback for transfer complete.
00115             (+) XferErrorCallback : callback for transfer error.
00116             (+) LineEventCallback : callback for line event.
00117             (+) CLUTLoadingCpltCallback : callback for CLUT loading completion.
00118             (+) MspInitCallback    : DMA2D MspInit.
00119             (+) MspDeInitCallback  : DMA2D MspDeInit.
00120 
00121       (#) By default, after the @ref HAL_DMA2D_Init and if the state is HAL_DMA2D_STATE_RESET
00122           all callbacks are reset to the corresponding legacy weak (surcharged) functions:
00123           examples @ref HAL_DMA2D_LineEventCallback(), @ref HAL_DMA2D_CLUTLoadingCpltCallback()
00124           Exception done for MspInit and MspDeInit callbacks that are respectively
00125           reset to the legacy weak (surcharged) functions in the @ref HAL_DMA2D_Init
00126           and @ref HAL_DMA2D_DeInit only when these callbacks are null (not registered beforehand)
00127           If not, MspInit or MspDeInit are not null, the @ref HAL_DMA2D_Init and @ref HAL_DMA2D_DeInit
00128           keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
00129 
00130           Exception as well for Transfer Completion and Transfer Error callbacks that are not defined
00131           as weak (surcharged) functions. They must be defined by the user to be resorted to.
00132 
00133           Callbacks can be registered/unregistered in READY state only.
00134           Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered
00135           in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used
00136           during the Init/DeInit.
00137           In that case first register the MspInit/MspDeInit user callbacks
00138           using @ref HAL_DMA2D_RegisterCallback before calling @ref HAL_DMA2D_DeInit
00139           or @ref HAL_DMA2D_Init function.
00140 
00141           When The compilation define USE_HAL_DMA2D_REGISTER_CALLBACKS is set to 0 or
00142           not defined, the callback registering feature is not available
00143           and weak (surcharged) callbacks are used.
00144 
00145      [..]
00146       (@) You can refer to the DMA2D HAL driver header file for more useful macros
00147 
00148   @endverbatim
00149   ******************************************************************************
00150   * @attention
00151   *
00152   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
00153   *
00154   * Redistribution and use in source and binary forms, with or without modification,
00155   * are permitted provided that the following conditions are met:
00156   *   1. Redistributions of source code must retain the above copyright notice,
00157   *      this list of conditions and the following disclaimer.
00158   *   2. Redistributions in binary form must reproduce the above copyright notice,
00159   *      this list of conditions and the following disclaimer in the documentation
00160   *      and/or other materials provided with the distribution.
00161   *   3. Neither the name of STMicroelectronics nor the names of its contributors
00162   *      may be used to endorse or promote products derived from this software
00163   *      without specific prior written permission.
00164   *
00165   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
00166   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
00167   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
00168   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
00169   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
00170   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
00171   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
00172   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
00173   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
00174   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
00175   *
00176   ******************************************************************************
00177   */
00178 
00179 /* Includes ------------------------------------------------------------------*/
00180 #include "stm32l4xx_hal.h"
00181 
00182 #ifdef HAL_DMA2D_MODULE_ENABLED
00183 #if defined (DMA2D)
00184 
00185 /** @addtogroup STM32L4xx_HAL_Driver
00186   * @{
00187   */
00188 
00189 /** @defgroup DMA2D  DMA2D
00190   * @brief DMA2D HAL module driver
00191   * @{
00192   */
00193 
00194 /* Private types -------------------------------------------------------------*/
00195 /* Private define ------------------------------------------------------------*/
00196 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
00197   * @{
00198   */
00199 
00200 /** @defgroup DMA2D_TimeOut DMA2D Time Out
00201   * @{
00202   */
00203 #define DMA2D_TIMEOUT_ABORT           (1000U)  /*!<  1s  */
00204 #define DMA2D_TIMEOUT_SUSPEND         (1000U)  /*!<  1s  */
00205 /**
00206   * @}
00207   */
00208 
00209 /**
00210   * @}
00211   */
00212 
00213 /* Private variables ---------------------------------------------------------*/
00214 /* Private constants ---------------------------------------------------------*/
00215 /* Private macro -------------------------------------------------------------*/
00216 /* Private function prototypes -----------------------------------------------*/
00217 /** @addtogroup DMA2D_Private_Functions DMA2D Private Functions
00218   * @{
00219   */
00220 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
00221 /**
00222   * @}
00223   */
00224 
00225 /* Private functions ---------------------------------------------------------*/
00226 /* Exported functions --------------------------------------------------------*/
00227 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
00228   * @{
00229   */
00230 
00231 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
00232  *  @brief   Initialization and Configuration functions
00233  *
00234 @verbatim
00235  ===============================================================================
00236                 ##### Initialization and Configuration functions #####
00237  ===============================================================================
00238     [..]  This section provides functions allowing to:
00239       (+) Initialize and configure the DMA2D
00240       (+) De-initialize the DMA2D
00241 
00242 @endverbatim
00243   * @{
00244   */
00245 
00246 /**
00247   * @brief  Initialize the DMA2D according to the specified
00248   *         parameters in the DMA2D_InitTypeDef and create the associated handle.
00249   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00250   *                 the configuration information for the DMA2D.
00251   * @retval HAL status
00252   */
00253 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
00254 {
00255   /* Check the DMA2D peripheral state */
00256   if(hdma2d == NULL)
00257   {
00258      return HAL_ERROR;
00259   }
00260 
00261   /* Check the parameters */
00262   assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
00263   assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
00264   assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
00265   assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
00266   assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->Init.AlphaInverted));
00267   assert_param(IS_DMA2D_RB_SWAP(hdma2d->Init.RedBlueSwap));
00268 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
00269   assert_param(IS_DMA2D_LOM_MODE(hdma2d->Init.LineOffsetMode));
00270 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
00271 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
00272   assert_param(IS_DMA2D_BYTES_SWAP(hdma2d->Init.BytesSwap));
00273 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
00274 
00275 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00276   if (hdma2d->State == HAL_DMA2D_STATE_RESET)
00277   {
00278     /* Reset Callback pointers in HAL_DMA2D_STATE_RESET only */
00279     hdma2d->LineEventCallback       = HAL_DMA2D_LineEventCallback;
00280     hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
00281     if(hdma2d->MspInitCallback == NULL)
00282     {
00283       hdma2d->MspInitCallback = HAL_DMA2D_MspInit;
00284     }
00285 
00286     /* Init the low level hardware */
00287     hdma2d->MspInitCallback(hdma2d);
00288   }
00289 #else
00290   if(hdma2d->State == HAL_DMA2D_STATE_RESET)
00291   {
00292     /* Allocate lock resource and initialize it */
00293     hdma2d->Lock = HAL_UNLOCKED;
00294     /* Init the low level hardware */
00295     HAL_DMA2D_MspInit(hdma2d);
00296   }
00297 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
00298 
00299   /* Change DMA2D peripheral state */
00300   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00301 
00302   /* DMA2D CR register configuration -------------------------------------------*/
00303 #if defined(DMA2D_LINE_OFFSET_MODE_SUPPORT)
00304   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE | DMA2D_CR_LOM, hdma2d->Init.Mode | hdma2d->Init.LineOffsetMode);
00305 #else
00306   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
00307 #endif /* DMA2D_LINE_OFFSET_MODE_SUPPORT */
00308 
00309   /* DMA2D OPFCCR register configuration ---------------------------------------*/
00310 #if defined(DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT)
00311   MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM | DMA2D_OPFCCR_SB, hdma2d->Init.ColorMode | hdma2d->Init.BytesSwap);
00312 #else
00313   MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
00314 #endif /* DMA2D_OUTPUT_TWO_BY_TWO_SWAP_SUPPORT */
00315 
00316   /* DMA2D OOR register configuration ------------------------------------------*/
00317   MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
00318   /* DMA2D OPFCCR AI and RBS fields setting (Output Alpha Inversion)*/
00319   MODIFY_REG(hdma2d->Instance->OPFCCR,(DMA2D_OPFCCR_AI|DMA2D_OPFCCR_RBS), ((hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos) | (hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos)));
00320 
00321 
00322   /* Update error code */
00323   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00324 
00325   /* Initialize the DMA2D state*/
00326   hdma2d->State  = HAL_DMA2D_STATE_READY;
00327 
00328   return HAL_OK;
00329 }
00330 
00331 /**
00332   * @brief  Deinitializes the DMA2D peripheral registers to their default reset
00333   *         values.
00334   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00335   *                 the configuration information for the DMA2D.
00336   * @retval None
00337   */
00338 
00339 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
00340 {
00341 
00342   /* Check the DMA2D peripheral state */
00343   if(hdma2d == NULL)
00344   {
00345      return HAL_ERROR;
00346   }
00347 
00348   /* Before aborting any DMA2D transfer or CLUT loading, check
00349      first whether or not DMA2D clock is enabled */
00350   if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
00351   {
00352     /* Abort DMA2D transfer if any */
00353     if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
00354     {
00355       if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
00356       {
00357         /* Issue when aborting DMA2D transfer */
00358         return HAL_ERROR;
00359       }
00360     }
00361     else
00362     {
00363       /* Abort background CLUT loading if any */
00364       if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
00365       {
00366         if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0U) != HAL_OK)
00367         {
00368           /* Issue when aborting background CLUT loading */
00369           return HAL_ERROR;
00370         }
00371       }
00372       else
00373       {
00374         /* Abort foreground CLUT loading if any */
00375         if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
00376         {
00377           if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1U) != HAL_OK)
00378           {
00379             /* Issue when aborting foreground CLUT loading */
00380             return HAL_ERROR;
00381           }
00382         }
00383       }
00384     }
00385   }
00386 
00387   /* Reset DMA2D control registers*/
00388   hdma2d->Instance->CR       =    0U;
00389   hdma2d->Instance->IFCR     = 0x3FU;
00390   hdma2d->Instance->FGOR     =    0U;
00391   hdma2d->Instance->BGOR     =    0U;
00392   hdma2d->Instance->FGPFCCR  =    0U;
00393   hdma2d->Instance->BGPFCCR  =    0U;
00394   hdma2d->Instance->OPFCCR   =    0U;
00395 
00396 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00397 
00398     if(hdma2d->MspDeInitCallback == NULL)
00399     {
00400       hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;
00401     }
00402 
00403     /* DeInit the low level hardware */
00404     hdma2d->MspDeInitCallback(hdma2d);
00405 
00406 #else
00407   /* Carry on with de-initialization of low level hardware */
00408   HAL_DMA2D_MspDeInit(hdma2d);
00409 #endif /* (USE_HAL_DMA2D_REGISTER_CALLBACKS) */
00410 
00411   /* Update error code */
00412   hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
00413 
00414   /* Initialize the DMA2D state*/
00415   hdma2d->State  = HAL_DMA2D_STATE_RESET;
00416 
00417   /* Release Lock */
00418   __HAL_UNLOCK(hdma2d);
00419 
00420   return HAL_OK;
00421 }
00422 
00423 /**
00424   * @brief  Initializes the DMA2D MSP.
00425   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00426   *                 the configuration information for the DMA2D.
00427   * @retval None
00428   */
00429 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
00430 {
00431   /* Prevent unused argument(s) compilation warning */
00432   UNUSED(hdma2d);
00433 
00434   /* NOTE : This function should not be modified; when the callback is needed,
00435             the HAL_DMA2D_MspInit can be implemented in the user file.
00436    */
00437 }
00438 
00439 /**
00440   * @brief  DeInitializes the DMA2D MSP.
00441   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00442   *                 the configuration information for the DMA2D.
00443   * @retval None
00444   */
00445 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
00446 {
00447   /* Prevent unused argument(s) compilation warning */
00448   UNUSED(hdma2d);
00449 
00450   /* NOTE : This function should not be modified; when the callback is needed,
00451             the HAL_DMA2D_MspDeInit can be implemented in the user file.
00452    */
00453 }
00454 
00455 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
00456 /**
00457   * @brief  Register a User DMA2D Callback
00458   *         To be used instead of the weak (surcharged) predefined callback
00459   * @param hdma2d DMA2D handle
00460   * @param CallbackID ID of the callback to be registered
00461   *        This parameter can be one of the following values:
00462   *          @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
00463   *          @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
00464   *          @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
00465   *          @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
00466   *          @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
00467   *          @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
00468   * @param pCallback pointer to the Callback function
00469   * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
00470   * @retval status
00471   */
00472 HAL_StatusTypeDef HAL_DMA2D_RegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID, pDMA2D_CallbackTypeDef pCallback)
00473 {
00474   HAL_StatusTypeDef status = HAL_OK;
00475 
00476   if(pCallback == NULL)
00477   {
00478     /* Update the error code */
00479     hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00480     return HAL_ERROR;
00481   }
00482   /* Process locked */
00483   __HAL_LOCK(hdma2d);
00484 
00485   if(HAL_DMA2D_STATE_READY == hdma2d->State)
00486   {
00487     switch (CallbackID)
00488     {
00489     case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
00490       hdma2d->XferCpltCallback = pCallback;
00491       break;
00492 
00493     case HAL_DMA2D_TRANSFERERROR_CB_ID :
00494       hdma2d->XferErrorCallback = pCallback;
00495       break;
00496 
00497     case HAL_DMA2D_LINEEVENT_CB_ID :
00498       hdma2d->LineEventCallback = pCallback;
00499       break;
00500 
00501     case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
00502       hdma2d->CLUTLoadingCpltCallback = pCallback;
00503       break;
00504 
00505     case HAL_DMA2D_MSPINIT_CB_ID :
00506       hdma2d->MspInitCallback = pCallback;
00507       break;
00508 
00509     case HAL_DMA2D_MSPDEINIT_CB_ID :
00510       hdma2d->MspDeInitCallback = pCallback;
00511       break;
00512 
00513     default :
00514      /* Update the error code */
00515      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00516      /* update return status */
00517       status =  HAL_ERROR;
00518       break;
00519     }
00520   }
00521   else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
00522   {
00523     switch (CallbackID)
00524     {
00525     case HAL_DMA2D_MSPINIT_CB_ID :
00526       hdma2d->MspInitCallback = pCallback;
00527       break;
00528 
00529     case HAL_DMA2D_MSPDEINIT_CB_ID :
00530       hdma2d->MspDeInitCallback = pCallback;
00531       break;
00532 
00533     default :
00534      /* Update the error code */
00535      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00536      /* update return status */
00537       status =  HAL_ERROR;
00538       break;
00539     }
00540   }
00541   else
00542   {
00543     /* Update the error code */
00544      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00545      /* update return status */
00546       status =  HAL_ERROR;
00547   }
00548 
00549   /* Release Lock */
00550   __HAL_UNLOCK(hdma2d);
00551   return status;
00552 }
00553 
00554 /**
00555   * @brief  Unregister a DMA2D Callback
00556   *         DMA2D Callback is redirected to the weak (surcharged) predefined callback
00557   * @param hdma2d DMA2D handle
00558   * @param CallbackID ID of the callback to be unregistered
00559   *        This parameter can be one of the following values:
00560   *          @arg @ref HAL_DMA2D_TRANSFERCOMPLETE_CB_ID DMA2D transfer complete Callback ID
00561   *          @arg @ref HAL_DMA2D_TRANSFERERROR_CB_ID DMA2D transfer error Callback ID
00562   *          @arg @ref HAL_DMA2D_LINEEVENT_CB_ID DMA2D line event Callback ID
00563   *          @arg @ref HAL_DMA2D_CLUTLOADINGCPLT_CB_ID DMA2D CLUT loading completion Callback ID
00564   *          @arg @ref HAL_DMA2D_MSPINIT_CB_ID DMA2D MspInit callback ID
00565   *          @arg @ref HAL_DMA2D_MSPDEINIT_CB_ID DMA2D MspDeInit callback ID
00566   * @note No weak predefined callbacks are defined for HAL_DMA2D_TRANSFERCOMPLETE_CB_ID or HAL_DMA2D_TRANSFERERROR_CB_ID
00567   * @retval status
00568   */
00569 HAL_StatusTypeDef HAL_DMA2D_UnRegisterCallback(DMA2D_HandleTypeDef *hdma2d, HAL_DMA2D_CallbackIDTypeDef CallbackID)
00570 {
00571 HAL_StatusTypeDef status = HAL_OK;
00572 
00573   /* Process locked */
00574   __HAL_LOCK(hdma2d);
00575 
00576   if(HAL_DMA2D_STATE_READY == hdma2d->State)
00577   {
00578     switch (CallbackID)
00579     {
00580     case HAL_DMA2D_TRANSFERCOMPLETE_CB_ID :
00581       hdma2d->XferCpltCallback = NULL;
00582       break;
00583 
00584     case HAL_DMA2D_TRANSFERERROR_CB_ID :
00585       hdma2d->XferErrorCallback = NULL;
00586       break;
00587 
00588     case HAL_DMA2D_LINEEVENT_CB_ID :
00589       hdma2d->LineEventCallback = HAL_DMA2D_LineEventCallback;
00590       break;
00591 
00592     case HAL_DMA2D_CLUTLOADINGCPLT_CB_ID :
00593       hdma2d->CLUTLoadingCpltCallback = HAL_DMA2D_CLUTLoadingCpltCallback;
00594       break;
00595 
00596     case HAL_DMA2D_MSPINIT_CB_ID :
00597       hdma2d->MspInitCallback = HAL_DMA2D_MspInit; /* Legacy weak (surcharged) Msp Init */
00598       break;
00599 
00600     case HAL_DMA2D_MSPDEINIT_CB_ID :
00601       hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit; /* Legacy weak (surcharged) Msp DeInit */
00602       break;
00603 
00604     default :
00605      /* Update the error code */
00606      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00607      /* update return status */
00608       status =  HAL_ERROR;
00609       break;
00610     }
00611   }
00612   else if(HAL_DMA2D_STATE_RESET == hdma2d->State)
00613   {
00614     switch (CallbackID)
00615     {
00616     case HAL_DMA2D_MSPINIT_CB_ID :
00617       hdma2d->MspInitCallback = HAL_DMA2D_MspInit;   /* Legacy weak (surcharged) Msp Init */
00618       break;
00619 
00620     case HAL_DMA2D_MSPDEINIT_CB_ID :
00621       hdma2d->MspDeInitCallback = HAL_DMA2D_MspDeInit;  /* Legacy weak (surcharged) Msp DeInit */
00622       break;
00623 
00624     default :
00625      /* Update the error code */
00626      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00627      /* update return status */
00628       status =  HAL_ERROR;
00629       break;
00630     }
00631   }
00632   else
00633   {
00634      /* Update the error code */
00635      hdma2d->ErrorCode |= HAL_DMA2D_ERROR_INVALID_CALLBACK;
00636      /* update return status */
00637       status =  HAL_ERROR;
00638   }
00639 
00640   /* Release Lock */
00641   __HAL_UNLOCK(hdma2d);
00642   return status;
00643 }
00644 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
00645 
00646 /**
00647   * @}
00648   */
00649 
00650 
00651 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
00652  *  @brief   IO operation functions
00653  *
00654 @verbatim
00655  ===============================================================================
00656                       #####  IO operation functions  #####
00657  ===============================================================================
00658     [..]  This section provides functions allowing to:
00659       (+) Configure the pdata, destination address and data size then
00660           start the DMA2D transfer.
00661       (+) Configure the source for foreground and background, destination address
00662           and data size then start a MultiBuffer DMA2D transfer.
00663       (+) Configure the pdata, destination address and data size then
00664           start the DMA2D transfer with interrupt.
00665       (+) Configure the source for foreground and background, destination address
00666           and data size then start a MultiBuffer DMA2D transfer with interrupt.
00667       (+) Abort DMA2D transfer.
00668       (+) Suspend DMA2D transfer.
00669       (+) Resume DMA2D transfer.
00670       (+) Enable CLUT transfer.
00671       (+) Configure CLUT loading then start transfer in polling mode.
00672       (+) Configure CLUT loading then start transfer in interrupt mode.
00673       (+) Abort DMA2D CLUT loading.
00674       (+) Suspend DMA2D CLUT loading.
00675       (+) Resume DMA2D CLUT loading.
00676       (+) Poll for transfer complete.
00677       (+) handle DMA2D interrupt request.
00678       (+) Transfer watermark callback.
00679       (+) CLUT Transfer Complete callback.
00680 
00681 
00682 @endverbatim
00683   * @{
00684   */
00685 
00686 /**
00687   * @brief  Start the DMA2D Transfer.
00688   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
00689   *                     the configuration information for the DMA2D.
00690   * @param  pdata      Configure the source memory Buffer address if
00691   *                     Memory-to-Memory or Memory-to-Memory with pixel format
00692   *                     conversion mode is selected, or configure
00693   *                     the color value if Register-to-Memory mode is selected.
00694   * @param  DstAddress The destination memory Buffer address.
00695   * @param  Width      The width of data to be transferred from source to destination (expressed in number of pixels per line).
00696   * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
00697   * @retval HAL status
00698   */
00699 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00700 {
00701   /* Check the parameters */
00702   assert_param(IS_DMA2D_LINE(Height));
00703   assert_param(IS_DMA2D_PIXEL(Width));
00704 
00705   /* Process locked */
00706   __HAL_LOCK(hdma2d);
00707 
00708   /* Change DMA2D peripheral state */
00709   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00710 
00711   /* Configure the source, destination address and the data size */
00712   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00713 
00714   /* Enable the Peripheral */
00715   __HAL_DMA2D_ENABLE(hdma2d);
00716 
00717   return HAL_OK;
00718 }
00719 
00720 /**
00721   * @brief  Start the DMA2D Transfer with interrupt enabled.
00722   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
00723   *                     the configuration information for the DMA2D.
00724   * @param  pdata      Configure the source memory Buffer address if
00725   *                     the Memory-to-Memory or Memory-to-Memory with pixel format
00726   *                     conversion mode is selected, or configure
00727   *                     the color value if Register-to-Memory mode is selected.
00728   * @param  DstAddress The destination memory Buffer address.
00729   * @param  Width      The width of data to be transferred from source to destination (expressed in number of pixels per line).
00730   * @param  Height     The height of data to be transferred from source to destination (expressed in number of lines).
00731   * @retval HAL status
00732   */
00733 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00734 {
00735   /* Check the parameters */
00736   assert_param(IS_DMA2D_LINE(Height));
00737   assert_param(IS_DMA2D_PIXEL(Width));
00738 
00739   /* Process locked */
00740   __HAL_LOCK(hdma2d);
00741 
00742   /* Change DMA2D peripheral state */
00743   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00744 
00745   /* Configure the source, destination address and the data size */
00746   DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
00747 
00748   /* Enable the transfer complete, transfer error and configuration error interrupts */
00749   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00750 
00751   /* Enable the Peripheral */
00752   __HAL_DMA2D_ENABLE(hdma2d);
00753 
00754   return HAL_OK;
00755 }
00756 
00757 /**
00758   * @brief  Start the multi-source DMA2D Transfer.
00759   * @param  hdma2d      Pointer to a DMA2D_HandleTypeDef structure that contains
00760   *                      the configuration information for the DMA2D.
00761   * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
00762   * @param  SrcAddress2 The source memory Buffer address for the background layer.
00763   * @param  DstAddress  The destination memory Buffer address.
00764   * @param  Width       The width of data to be transferred from source to destination (expressed in number of pixels per line).
00765   * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
00766   * @retval HAL status
00767   */
00768 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00769 {
00770   /* Check the parameters */
00771   assert_param(IS_DMA2D_LINE(Height));
00772   assert_param(IS_DMA2D_PIXEL(Width));
00773 
00774   /* Process locked */
00775   __HAL_LOCK(hdma2d);
00776 
00777   /* Change DMA2D peripheral state */
00778   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00779 
00780   /* Configure DMA2D Stream source2 address */
00781   WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
00782 
00783   /* Configure the source, destination address and the data size */
00784   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00785 
00786   /* Enable the Peripheral */
00787   __HAL_DMA2D_ENABLE(hdma2d);
00788 
00789   return HAL_OK;
00790 }
00791 
00792 /**
00793   * @brief  Start the multi-source DMA2D Transfer with interrupt enabled.
00794   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
00795   *                     the configuration information for the DMA2D.
00796   * @param  SrcAddress1 The source memory Buffer address for the foreground layer.
00797   * @param  SrcAddress2 The source memory Buffer address for the background layer.
00798   * @param  DstAddress  The destination memory Buffer address.
00799   * @param  Width       The width of data to be transferred from source to destination (expressed in number of pixels per line).
00800   * @param  Height      The height of data to be transferred from source to destination (expressed in number of lines).
00801   * @retval HAL status
00802   */
00803 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t  SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height)
00804 {
00805   /* Check the parameters */
00806   assert_param(IS_DMA2D_LINE(Height));
00807   assert_param(IS_DMA2D_PIXEL(Width));
00808 
00809   /* Process locked */
00810   __HAL_LOCK(hdma2d);
00811 
00812   /* Change DMA2D peripheral state */
00813   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00814 
00815   /* Configure DMA2D Stream source2 address */
00816   WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
00817 
00818   /* Configure the source, destination address and the data size */
00819   DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
00820 
00821   /* Enable the transfer complete, transfer error and configuration error interrupts */
00822   __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00823 
00824   /* Enable the Peripheral */
00825   __HAL_DMA2D_ENABLE(hdma2d);
00826 
00827   return HAL_OK;
00828 }
00829 
00830 /**
00831   * @brief  Abort the DMA2D Transfer.
00832   * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
00833   *                  the configuration information for the DMA2D.
00834   * @retval HAL status
00835   */
00836 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
00837 {
00838   uint32_t tickstart;
00839 
00840   /* Abort the DMA2D transfer */
00841   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00842      between the register read and the register write by the CPU (writing 0 has no
00843      effect on START bitvalue) */
00844    MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
00845 
00846   /* Get tick */
00847   tickstart = HAL_GetTick();
00848 
00849   /* Check if the DMA2D is effectively disabled */
00850   while((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
00851   {
00852     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
00853     {
00854       /* Update error code */
00855       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00856 
00857       /* Change the DMA2D state */
00858       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00859 
00860       /* Process Unlocked */
00861       __HAL_UNLOCK(hdma2d);
00862 
00863       return HAL_TIMEOUT;
00864     }
00865   }
00866 
00867   /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
00868   __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
00869 
00870   /* Change the DMA2D state*/
00871   hdma2d->State = HAL_DMA2D_STATE_READY;
00872 
00873   /* Process Unlocked */
00874   __HAL_UNLOCK(hdma2d);
00875 
00876   return HAL_OK;
00877 }
00878 
00879 /**
00880   * @brief  Suspend the DMA2D Transfer.
00881   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00882   *                 the configuration information for the DMA2D.
00883   * @retval HAL status
00884   */
00885 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
00886 {
00887   uint32_t tickstart;
00888 
00889   /* Suspend the DMA2D transfer */
00890   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00891      between the register read and the register write by the CPU (writing 0 has no
00892      effect on START bitvalue). */
00893   MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
00894 
00895   /* Get tick */
00896   tickstart = HAL_GetTick();
00897 
00898   /* Check if the DMA2D is effectively suspended */
00899   while ((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == DMA2D_CR_START)
00900   {
00901     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
00902     {
00903       /* Update error code */
00904       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
00905 
00906       /* Change the DMA2D state */
00907       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
00908 
00909       return HAL_TIMEOUT;
00910     }
00911   }
00912 
00913    /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
00914   if ((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
00915   {
00916     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
00917   }
00918   else
00919   {
00920     /* Make sure SUSP bit is cleared since it is meaningless
00921        when no tranfer is on-going */
00922     CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
00923   }
00924 
00925   return HAL_OK;
00926 }
00927 
00928 /**
00929   * @brief  Resume the DMA2D Transfer.
00930   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
00931   *                 the configuration information for the DMA2D.
00932   * @retval HAL status
00933   */
00934 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
00935 {
00936   /* Check the SUSP and START bits */
00937   if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
00938   {
00939     /* Ongoing transfer is suspended: change the DMA2D state before resuming */
00940     hdma2d->State = HAL_DMA2D_STATE_BUSY;
00941   }
00942 
00943   /* Resume the DMA2D transfer */
00944   /* START bit is reset to make sure not to set it again, in the event the HW clears it
00945      between the register read and the register write by the CPU (writing 0 has no
00946      effect on START bitvalue). */
00947   CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
00948 
00949   return HAL_OK;
00950 }
00951 
00952 
00953 /**
00954   * @brief  Enable the DMA2D CLUT Transfer.
00955   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
00956   *                   the configuration information for the DMA2D.
00957   * @param  LayerIdx DMA2D Layer index.
00958   *                   This parameter can be one of the following values:
00959   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
00960   * @retval HAL status
00961   */
00962 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
00963 {
00964   /* Check the parameters */
00965   assert_param(IS_DMA2D_LAYER(LayerIdx));
00966 
00967   /* Process locked */
00968   __HAL_LOCK(hdma2d);
00969 
00970   /* Change DMA2D peripheral state */
00971   hdma2d->State = HAL_DMA2D_STATE_BUSY;
00972 
00973   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
00974   {
00975     /* Enable the background CLUT loading */
00976     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
00977   }
00978   else
00979   {
00980     /* Enable the foreground CLUT loading */
00981     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
00982   }
00983 
00984   return HAL_OK;
00985 }
00986 
00987 
00988 /**
00989   * @brief  Start DMA2D CLUT Loading.
00990   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
00991   *                   the configuration information for the DMA2D.
00992   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
00993   *                   the configuration information for the color look up table.
00994   * @param  LayerIdx DMA2D Layer index.
00995   *                   This parameter can be one of the following values:
00996   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
00997   * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
00998   * @retval HAL status
00999   */
01000 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
01001 {
01002   /* Check the parameters */
01003   assert_param(IS_DMA2D_LAYER(LayerIdx));
01004   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
01005   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
01006 
01007   /* Process locked */
01008   __HAL_LOCK(hdma2d);
01009 
01010   /* Change DMA2D peripheral state */
01011   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01012 
01013   /* Configure the CLUT of the background DMA2D layer */
01014   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
01015   {
01016     /* Write background CLUT memory address */
01017     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
01018 
01019     /* Write background CLUT size and CLUT color mode */
01020     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
01021             ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
01022 
01023     /* Enable the CLUT loading for the background */
01024     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
01025   }
01026   /* Configure the CLUT of the foreground DMA2D layer */
01027   else
01028   {
01029     /* Write foreground CLUT memory address */
01030     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
01031 
01032     /* Write foreground CLUT size and CLUT color mode */
01033     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
01034             ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
01035 
01036  /* Enable the CLUT loading for the foreground */
01037     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
01038   }
01039 
01040   return HAL_OK;
01041 }
01042 
01043 /**
01044   * @brief  Start DMA2D CLUT Loading with interrupt enabled.
01045   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
01046   *                   the configuration information for the DMA2D.
01047   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
01048   *                   the configuration information for the color look up table.
01049   * @param  LayerIdx DMA2D Layer index.
01050   *                   This parameter can be one of the following values:
01051   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01052   * @retval HAL status
01053   */
01054 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
01055 {
01056   /* Check the parameters */
01057   assert_param(IS_DMA2D_LAYER(LayerIdx));
01058   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
01059   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
01060 
01061   /* Process locked */
01062   __HAL_LOCK(hdma2d);
01063 
01064   /* Change DMA2D peripheral state */
01065   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01066 
01067   /* Configure the CLUT of the background DMA2D layer */
01068   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
01069   {
01070     /* Write background CLUT memory address */
01071     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
01072 
01073     /* Write background CLUT size and CLUT color mode */
01074     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
01075             ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
01076 
01077     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
01078     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
01079 
01080     /* Enable the CLUT loading for the background */
01081     SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
01082   }
01083   /* Configure the CLUT of the foreground DMA2D layer */
01084   else
01085   {
01086     /* Write foreground CLUT memory address */
01087     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
01088 
01089     /* Write foreground CLUT size and CLUT color mode */
01090     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
01091             ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
01092 
01093     /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
01094     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
01095 
01096     /* Enable the CLUT loading for the foreground */
01097     SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
01098   }
01099 
01100   return HAL_OK;
01101 }
01102 
01103 /**
01104   * @brief  Abort the DMA2D CLUT loading.
01105   * @param  hdma2d  Pointer to a DMA2D_HandleTypeDef structure that contains
01106   *                  the configuration information for the DMA2D.
01107   * @param  LayerIdx DMA2D Layer index.
01108   *                   This parameter can be one of the following values:
01109   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01110   * @retval HAL status
01111   */
01112 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01113 {
01114   uint32_t tickstart;
01115   const __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
01116 
01117   /* Abort the CLUT loading */
01118   SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
01119 
01120   /* If foreground CLUT loading is considered, update local variables */
01121   if(LayerIdx == DMA2D_FOREGROUND_LAYER)
01122   {
01123     reg  = &(hdma2d->Instance->FGPFCCR);
01124   }
01125 
01126 
01127   /* Get tick */
01128   tickstart = HAL_GetTick();
01129 
01130   /* Check if the CLUT loading is aborted */
01131   while((*reg & DMA2D_BGPFCCR_START) != 0U)
01132   {
01133     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
01134     {
01135       /* Update error code */
01136       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01137 
01138       /* Change the DMA2D state */
01139       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
01140 
01141       /* Process Unlocked */
01142       __HAL_UNLOCK(hdma2d);
01143 
01144       return HAL_TIMEOUT;
01145     }
01146   }
01147 
01148   /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
01149   __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
01150 
01151   /* Change the DMA2D state*/
01152   hdma2d->State = HAL_DMA2D_STATE_READY;
01153 
01154   /* Process Unlocked */
01155   __HAL_UNLOCK(hdma2d);
01156 
01157   return HAL_OK;
01158 }
01159 
01160 /**
01161   * @brief  Suspend the DMA2D CLUT loading.
01162   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01163   *                 the configuration information for the DMA2D.
01164   * @param  LayerIdx DMA2D Layer index.
01165   *                   This parameter can be one of the following values:
01166   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01167   * @retval HAL status
01168   */
01169 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01170 {
01171   uint32_t tickstart;
01172   uint32_t loadsuspended;
01173   const __IO uint32_t * reg =  &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
01174 
01175   /* Suspend the CLUT loading */
01176   SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
01177 
01178   /* If foreground CLUT loading is considered, update local variables */
01179   if(LayerIdx == DMA2D_FOREGROUND_LAYER)
01180   {
01181     reg  = &(hdma2d->Instance->FGPFCCR);
01182   }
01183 
01184   /* Get tick */
01185   tickstart = HAL_GetTick();
01186 
01187   /* Check if the CLUT loading is suspended */
01188   loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
01189   loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
01190   while (loadsuspended == 0UL)
01191   {
01192     if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
01193     {
01194       /* Update error code */
01195       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01196 
01197       /* Change the DMA2D state */
01198       hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
01199 
01200       return HAL_TIMEOUT;
01201     }
01202     loadsuspended = ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)? 1UL: 0UL; /*1st condition: Suspend Check*/
01203     loadsuspended |= ((*reg & DMA2D_BGPFCCR_START) != DMA2D_BGPFCCR_START)? 1UL: 0UL; /*2nd condition: Not Start Check */
01204   }
01205 
01206    /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
01207   if ((*reg & DMA2D_BGPFCCR_START) != 0U)
01208   {
01209     hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
01210   }
01211   else
01212   {
01213     /* Make sure SUSP bit is cleared since it is meaningless
01214        when no tranfer is on-going */
01215     CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
01216   }
01217 
01218   return HAL_OK;
01219 }
01220 
01221 /**
01222   * @brief  Resume the DMA2D CLUT loading.
01223   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01224   *                 the configuration information for the DMA2D.
01225   * @param  LayerIdx DMA2D Layer index.
01226   *                   This parameter can be one of the following values:
01227   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01228   * @retval HAL status
01229   */
01230 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01231 {
01232   /* Check the SUSP and START bits for background or foreground CLUT loading */
01233   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
01234   {
01235     /* Background CLUT loading suspension check */
01236     if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
01237     {
01238       if((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
01239       {
01240       /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
01241       hdma2d->State = HAL_DMA2D_STATE_BUSY;
01242     }
01243   }
01244   }
01245   else
01246   {
01247     /* Foreground CLUT loading suspension check */
01248     if ((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
01249     {
01250       if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
01251       {
01252       /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
01253       hdma2d->State = HAL_DMA2D_STATE_BUSY;
01254     }
01255   }
01256   }
01257 
01258   /* Resume the CLUT loading */
01259   CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
01260 
01261   return HAL_OK;
01262 }
01263 
01264 
01265 /**
01266 
01267   * @brief  Polling for transfer complete or CLUT loading.
01268   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01269   *                 the configuration information for the DMA2D.
01270   * @param  Timeout Timeout duration
01271   * @retval HAL status
01272   */
01273 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
01274 {
01275   uint32_t tickstart;
01276   uint32_t layer_start;
01277   __IO uint32_t isrflags = 0x0U;
01278 
01279   /* Polling for DMA2D transfer */
01280   if((hdma2d->Instance->CR & DMA2D_CR_START) != 0U)
01281   {
01282    /* Get tick */
01283    tickstart = HAL_GetTick();
01284 
01285     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == 0U)
01286     {
01287       isrflags = READ_REG(hdma2d->Instance->ISR);
01288       if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
01289       {
01290         if ((isrflags & DMA2D_FLAG_CE) != 0U)
01291         {
01292           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01293         }
01294         if ((isrflags & DMA2D_FLAG_TE) != 0U)
01295         {
01296           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01297         }
01298         /* Clear the transfer and configuration error flags */
01299         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
01300 
01301         /* Change DMA2D state */
01302         hdma2d->State = HAL_DMA2D_STATE_ERROR;
01303 
01304         /* Process unlocked */
01305         __HAL_UNLOCK(hdma2d);
01306 
01307         return HAL_ERROR;
01308       }
01309       /* Check for the Timeout */
01310       if(Timeout != HAL_MAX_DELAY)
01311       {
01312         if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01313         {
01314           /* Update error code */
01315           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01316 
01317           /* Change the DMA2D state */
01318           hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
01319 
01320           /* Process unlocked */
01321           __HAL_UNLOCK(hdma2d);
01322 
01323           return HAL_TIMEOUT;
01324         }
01325       }
01326     }
01327   }
01328   /* Polling for CLUT loading (foreground or background) */
01329   layer_start = hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START;
01330   layer_start |= hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START;
01331   if (layer_start != 0U)
01332   {
01333     /* Get tick */
01334     tickstart = HAL_GetTick();
01335 
01336     while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == 0U)
01337     {
01338       isrflags = READ_REG(hdma2d->Instance->ISR);
01339       if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != 0U)
01340       {
01341         if ((isrflags & DMA2D_FLAG_CAE) != 0U)
01342         {
01343           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
01344         }
01345         if ((isrflags & DMA2D_FLAG_CE) != 0U)
01346         {
01347           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01348         }
01349         if ((isrflags & DMA2D_FLAG_TE) != 0U)
01350         {
01351           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01352         }
01353         /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
01354         __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
01355 
01356         /* Change DMA2D state */
01357         hdma2d->State= HAL_DMA2D_STATE_ERROR;
01358 
01359         /* Process unlocked */
01360         __HAL_UNLOCK(hdma2d);
01361 
01362         return HAL_ERROR;
01363       }
01364       /* Check for the Timeout */
01365       if(Timeout != HAL_MAX_DELAY)
01366       {
01367         if(((HAL_GetTick() - tickstart ) > Timeout)||(Timeout == 0U))
01368         {
01369           /* Update error code */
01370           hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
01371 
01372           /* Change the DMA2D state */
01373           hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
01374 
01375           /* Process unlocked */
01376           __HAL_UNLOCK(hdma2d);
01377 
01378           return HAL_TIMEOUT;
01379         }
01380       }
01381     }
01382   }
01383 
01384   /* Clear the transfer complete and CLUT loading flags */
01385   __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
01386 
01387   /* Change DMA2D state */
01388   hdma2d->State = HAL_DMA2D_STATE_READY;
01389 
01390   /* Process unlocked */
01391   __HAL_UNLOCK(hdma2d);
01392 
01393   return HAL_OK;
01394 }
01395 /**
01396   * @brief  Handle DMA2D interrupt request.
01397   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01398   *                 the configuration information for the DMA2D.
01399   * @retval HAL status
01400   */
01401 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
01402 {
01403   uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
01404   uint32_t crflags = READ_REG(hdma2d->Instance->CR);
01405 
01406   /* Transfer Error Interrupt management ***************************************/
01407   if ((isrflags & DMA2D_FLAG_TE) != 0U)
01408   {
01409     if ((crflags & DMA2D_IT_TE) != 0U)
01410     {
01411       /* Disable the transfer Error interrupt */
01412       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
01413 
01414       /* Update error code */
01415       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
01416 
01417       /* Clear the transfer error flag */
01418       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
01419 
01420       /* Change DMA2D state */
01421       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01422 
01423       /* Process Unlocked */
01424       __HAL_UNLOCK(hdma2d);
01425 
01426       if(hdma2d->XferErrorCallback != NULL)
01427       {
01428         /* Transfer error Callback */
01429         hdma2d->XferErrorCallback(hdma2d);
01430       }
01431     }
01432   }
01433   /* Configuration Error Interrupt management **********************************/
01434   if ((isrflags & DMA2D_FLAG_CE) != 0U)
01435   {
01436     if ((crflags & DMA2D_IT_CE) != 0U)
01437     {
01438       /* Disable the Configuration Error interrupt */
01439       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
01440 
01441       /* Clear the Configuration error flag */
01442       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
01443 
01444       /* Update error code */
01445       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
01446 
01447       /* Change DMA2D state */
01448       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01449 
01450       /* Process Unlocked */
01451       __HAL_UNLOCK(hdma2d);
01452 
01453       if(hdma2d->XferErrorCallback != NULL)
01454       {
01455         /* Transfer error Callback */
01456         hdma2d->XferErrorCallback(hdma2d);
01457       }
01458     }
01459   }
01460   /* CLUT access Error Interrupt management ***********************************/
01461   if ((isrflags & DMA2D_FLAG_CAE) != 0U)
01462   {
01463     if ((crflags & DMA2D_IT_CAE) != 0U)
01464     {
01465       /* Disable the CLUT access error interrupt */
01466       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
01467 
01468       /* Clear the CLUT access error flag */
01469       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
01470 
01471       /* Update error code */
01472       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
01473 
01474       /* Change DMA2D state */
01475       hdma2d->State = HAL_DMA2D_STATE_ERROR;
01476 
01477       /* Process Unlocked */
01478       __HAL_UNLOCK(hdma2d);
01479 
01480       if(hdma2d->XferErrorCallback != NULL)
01481       {
01482         /* Transfer error Callback */
01483         hdma2d->XferErrorCallback(hdma2d);
01484       }
01485     }
01486   }
01487   /* Transfer watermark Interrupt management **********************************/
01488   if ((isrflags & DMA2D_FLAG_TW) != 0U)
01489   {
01490     if ((crflags & DMA2D_IT_TW) != 0U)
01491     {
01492       /* Disable the transfer watermark interrupt */
01493       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
01494 
01495       /* Clear the transfer watermark flag */
01496       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
01497 
01498       /* Transfer watermark Callback */
01499 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
01500       hdma2d->LineEventCallback(hdma2d);
01501 #else
01502       HAL_DMA2D_LineEventCallback(hdma2d);
01503 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
01504 
01505     }
01506   }
01507   /* Transfer Complete Interrupt management ************************************/
01508   if ((isrflags & DMA2D_FLAG_TC) != 0U)
01509   {
01510     if ((crflags & DMA2D_IT_TC) != 0U)
01511     {
01512       /* Disable the transfer complete interrupt */
01513       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
01514 
01515       /* Clear the transfer complete flag */
01516       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
01517 
01518       /* Update error code */
01519       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
01520 
01521       /* Change DMA2D state */
01522       hdma2d->State = HAL_DMA2D_STATE_READY;
01523 
01524       /* Process Unlocked */
01525       __HAL_UNLOCK(hdma2d);
01526 
01527       if(hdma2d->XferCpltCallback != NULL)
01528       {
01529         /* Transfer complete Callback */
01530         hdma2d->XferCpltCallback(hdma2d);
01531       }
01532     }
01533   }
01534   /* CLUT Transfer Complete Interrupt management ******************************/
01535   if ((isrflags & DMA2D_FLAG_CTC) != 0U)
01536   {
01537     if ((crflags & DMA2D_IT_CTC) != 0U)
01538     {
01539       /* Disable the CLUT transfer complete interrupt */
01540       __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
01541 
01542       /* Clear the CLUT transfer complete flag */
01543       __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
01544 
01545       /* Update error code */
01546       hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
01547 
01548       /* Change DMA2D state */
01549       hdma2d->State = HAL_DMA2D_STATE_READY;
01550 
01551       /* Process Unlocked */
01552       __HAL_UNLOCK(hdma2d);
01553 
01554       /* CLUT Transfer complete Callback */
01555 #if (USE_HAL_DMA2D_REGISTER_CALLBACKS == 1)
01556       hdma2d->CLUTLoadingCpltCallback(hdma2d);
01557 #else
01558       HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
01559 #endif /* USE_HAL_DMA2D_REGISTER_CALLBACKS */
01560     }
01561   }
01562 
01563 }
01564 
01565 /**
01566   * @brief  Transfer watermark callback.
01567   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01568   *                 the configuration information for the DMA2D.
01569   * @retval None
01570   */
01571 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
01572 {
01573   /* Prevent unused argument(s) compilation warning */
01574   UNUSED(hdma2d);
01575 
01576   /* NOTE : This function should not be modified; when the callback is needed,
01577             the HAL_DMA2D_LineEventCallback can be implemented in the user file.
01578    */
01579 }
01580 
01581 /**
01582   * @brief  CLUT Transfer Complete callback.
01583   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01584   *                 the configuration information for the DMA2D.
01585   * @retval None
01586   */
01587 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
01588 {
01589   /* Prevent unused argument(s) compilation warning */
01590   UNUSED(hdma2d);
01591 
01592   /* NOTE : This function should not be modified; when the callback is needed,
01593             the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
01594    */
01595 }
01596 
01597 /**
01598   * @}
01599   */
01600 
01601 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
01602  *  @brief    Peripheral Control functions
01603  *
01604 @verbatim
01605  ===============================================================================
01606                     ##### Peripheral Control functions #####
01607  ===============================================================================
01608     [..]  This section provides functions allowing to:
01609       (+) Configure the DMA2D foreground or background layer parameters.
01610       (+) Configure the DMA2D CLUT transfer.
01611       (+) Configure the line watermark
01612       (+) Configure the dead time value.
01613       (+) Enable or disable the dead time value functionality.
01614 
01615 
01616 @endverbatim
01617   * @{
01618   */
01619 
01620 /**
01621   * @brief  Configure the DMA2D Layer according to the specified
01622   *         parameters in the DMA2D_HandleTypeDef.
01623   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01624   *                 the configuration information for the DMA2D.
01625   * @param  LayerIdx DMA2D Layer index.
01626   *                   This parameter can be one of the following values:
01627   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01628   * @retval HAL status
01629   */
01630 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
01631 {
01632   DMA2D_LayerCfgTypeDef *pLayerCfg;
01633   uint32_t regMask, regValue;
01634 
01635   /* Check the parameters */
01636   assert_param(IS_DMA2D_LAYER(LayerIdx));
01637   assert_param(IS_DMA2D_OFFSET(hdma2d->LayerCfg[LayerIdx].InputOffset));
01638   if(hdma2d->Init.Mode != DMA2D_R2M)
01639   {
01640     assert_param(IS_DMA2D_INPUT_COLOR_MODE(hdma2d->LayerCfg[LayerIdx].InputColorMode));
01641     if(hdma2d->Init.Mode != DMA2D_M2M)
01642     {
01643       assert_param(IS_DMA2D_ALPHA_MODE(hdma2d->LayerCfg[LayerIdx].AlphaMode));
01644     }
01645   }
01646   assert_param(IS_DMA2D_ALPHA_INVERTED(hdma2d->LayerCfg[LayerIdx].AlphaInverted));
01647   assert_param(IS_DMA2D_RB_SWAP(hdma2d->LayerCfg[LayerIdx].RedBlueSwap));
01648 
01649   /* Process locked */
01650   __HAL_LOCK(hdma2d);
01651 
01652   /* Change DMA2D peripheral state */
01653   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01654 
01655   pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
01656 
01657   /* Prepare the value to be written to the BGPFCCR or FGPFCCR register */
01658   regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos) |\
01659              (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos) | (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
01660   regMask  = (DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA | DMA2D_BGPFCCR_AI | DMA2D_BGPFCCR_RBS);
01661 
01662 
01663   if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01664   {
01665     regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
01666   }
01667   else
01668   {
01669     regValue |=  (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
01670   }
01671 
01672   /* Configure the background DMA2D layer */
01673   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
01674   {
01675     /* Write DMA2D BGPFCCR register */
01676     MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
01677 
01678     /* DMA2D BGOR register configuration -------------------------------------*/
01679     WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
01680 
01681     /* DMA2D BGCOLR register configuration -------------------------------------*/
01682     if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01683     {
01684       WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
01685     }
01686   }
01687   /* Configure the foreground DMA2D layer */
01688   else
01689   {
01690 
01691 
01692      /* Write DMA2D FGPFCCR register */
01693     MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
01694 
01695     /* DMA2D FGOR register configuration -------------------------------------*/
01696     WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
01697 
01698     /* DMA2D FGCOLR register configuration -------------------------------------*/
01699     if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
01700     {
01701       WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
01702     }
01703   }
01704   /* Initialize the DMA2D state*/
01705   hdma2d->State = HAL_DMA2D_STATE_READY;
01706 
01707   /* Process unlocked */
01708   __HAL_UNLOCK(hdma2d);
01709 
01710   return HAL_OK;
01711 }
01712 
01713 /**
01714   * @brief  Configure the DMA2D CLUT Transfer.
01715   * @param  hdma2d   Pointer to a DMA2D_HandleTypeDef structure that contains
01716   *                   the configuration information for the DMA2D.
01717   * @param  CLUTCfg  Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
01718   *                   the configuration information for the color look up table.
01719   * @param  LayerIdx DMA2D Layer index.
01720   *                   This parameter can be one of the following values:
01721   *                   DMA2D_BACKGROUND_LAYER(0) / DMA2D_FOREGROUND_LAYER(1)
01722   * @retval HAL status
01723   */
01724 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
01725 {
01726   /* Check the parameters */
01727   assert_param(IS_DMA2D_LAYER(LayerIdx));
01728   assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
01729   assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
01730 
01731   /* Process locked */
01732   __HAL_LOCK(hdma2d);
01733 
01734   /* Change DMA2D peripheral state */
01735   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01736 
01737   /* Configure the CLUT of the background DMA2D layer */
01738   if(LayerIdx == DMA2D_BACKGROUND_LAYER)
01739   {
01740     /* Write background CLUT memory address */
01741     WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
01742 
01743     /* Write background CLUT size and CLUT color mode */
01744     MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
01745             ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
01746  }
01747  /* Configure the CLUT of the foreground DMA2D layer */
01748  else
01749  {
01750    /* Write foreground CLUT memory address */
01751     WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
01752 
01753     /* Write foreground CLUT size and CLUT color mode */
01754     MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
01755             ((CLUTCfg.Size << DMA2D_FGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
01756   }
01757 
01758   /* Set the DMA2D state to Ready*/
01759   hdma2d->State = HAL_DMA2D_STATE_READY;
01760 
01761   /* Process unlocked */
01762   __HAL_UNLOCK(hdma2d);
01763 
01764   return HAL_OK;
01765 }
01766 
01767 
01768 /**
01769   * @brief  Configure the line watermark.
01770   * @param  hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
01771   *                 the configuration information for the DMA2D.
01772   * @param  Line   Line Watermark configuration (maximum 16-bit long value expected).
01773   * @note   HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
01774   * @note   The transfer watermark interrupt is disabled once it has occurred.
01775   * @retval HAL status
01776   */
01777 
01778 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
01779 {
01780   /* Check the parameters */
01781   assert_param(IS_DMA2D_LINEWATERMARK(Line));
01782 
01783   if (Line > DMA2D_LWR_LW)
01784   {
01785     return HAL_ERROR;
01786   }
01787   else
01788   {
01789     /* Process locked */
01790     __HAL_LOCK(hdma2d);
01791 
01792     /* Change DMA2D peripheral state */
01793     hdma2d->State = HAL_DMA2D_STATE_BUSY;
01794 
01795     /* Sets the Line watermark configuration */
01796     WRITE_REG(hdma2d->Instance->LWR, Line);
01797 
01798     /* Enable the Line interrupt */
01799     __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
01800 
01801     /* Initialize the DMA2D state*/
01802     hdma2d->State = HAL_DMA2D_STATE_READY;
01803 
01804     /* Process unlocked */
01805     __HAL_UNLOCK(hdma2d);
01806 
01807     return HAL_OK;
01808   }
01809 }
01810 
01811 /**
01812   * @brief Enable DMA2D dead time feature.
01813   * @param hdma2d DMA2D handle.
01814   * @retval HAL status
01815   */
01816 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
01817 {
01818   /* Process Locked */
01819   __HAL_LOCK(hdma2d);
01820 
01821   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01822 
01823   /* Set DMA2D_AMTCR EN bit */
01824   SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
01825 
01826   hdma2d->State = HAL_DMA2D_STATE_READY;
01827 
01828   /* Process Unlocked */
01829   __HAL_UNLOCK(hdma2d);
01830 
01831   return HAL_OK;
01832 }
01833 
01834 /**
01835   * @brief Disable DMA2D dead time feature.
01836   * @param hdma2d DMA2D handle.
01837   * @retval HAL status
01838   */
01839 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
01840 {
01841   /* Process Locked */
01842   __HAL_LOCK(hdma2d);
01843 
01844   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01845 
01846   /* Clear DMA2D_AMTCR EN bit */
01847   CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
01848 
01849   hdma2d->State = HAL_DMA2D_STATE_READY;
01850 
01851   /* Process Unlocked */
01852   __HAL_UNLOCK(hdma2d);
01853 
01854   return HAL_OK;
01855 }
01856 
01857 /**
01858   * @brief Configure dead time.
01859   * @note The dead time value represents the guaranteed minimum number of cycles between
01860   *       two consecutive transactions on the AHB bus.
01861   * @param hdma2d DMA2D handle.
01862   * @param DeadTime dead time value.
01863   * @retval HAL status
01864   */
01865 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
01866 {
01867   /* Process Locked */
01868   __HAL_LOCK(hdma2d);
01869 
01870   hdma2d->State = HAL_DMA2D_STATE_BUSY;
01871 
01872   /* Set DMA2D_AMTCR DT field */
01873   MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
01874 
01875   hdma2d->State = HAL_DMA2D_STATE_READY;
01876 
01877   /* Process Unlocked */
01878   __HAL_UNLOCK(hdma2d);
01879 
01880   return HAL_OK;
01881 }
01882 
01883 /**
01884   * @}
01885   */
01886 
01887 
01888 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
01889  *  @brief    Peripheral State functions
01890  *
01891 @verbatim
01892  ===============================================================================
01893                   ##### Peripheral State and Errors functions #####
01894  ===============================================================================
01895     [..]
01896     This subsection provides functions allowing to:
01897       (+) Get the DMA2D state
01898       (+) Get the DMA2D error code
01899 
01900 @endverbatim
01901   * @{
01902   */
01903 
01904 /**
01905   * @brief  Return the DMA2D state
01906   * @param  hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
01907   *                 the configuration information for the DMA2D.
01908   * @retval HAL state
01909   */
01910 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
01911 {
01912   return hdma2d->State;
01913 }
01914 
01915 /**
01916   * @brief  Return the DMA2D error code
01917   * @param  hdma2d  pointer to a DMA2D_HandleTypeDef structure that contains
01918   *               the configuration information for DMA2D.
01919   * @retval DMA2D Error Code
01920   */
01921 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
01922 {
01923   return hdma2d->ErrorCode;
01924 }
01925 
01926 /**
01927   * @}
01928   */
01929 
01930 /**
01931   * @}
01932   */
01933 
01934 
01935 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
01936   * @{
01937   */
01938 
01939 /**
01940   * @brief  Set the DMA2D transfer parameters.
01941   * @param  hdma2d     Pointer to a DMA2D_HandleTypeDef structure that contains
01942   *                     the configuration information for the specified DMA2D.
01943   * @param  pdata      The source memory Buffer address
01944   * @param  DstAddress The destination memory Buffer address
01945   * @param  Width      The width of data to be transferred from source to destination.
01946   * @param  Height     The height of data to be transferred from source to destination.
01947   * @retval HAL status
01948   */
01949 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
01950 {
01951   uint32_t tmp;
01952   uint32_t tmp1;
01953   uint32_t tmp2;
01954   uint32_t tmp3;
01955   uint32_t tmp4;
01956 
01957   /* Configure DMA2D data size */
01958   MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
01959 
01960   /* Configure DMA2D destination address */
01961   WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
01962 
01963   /* Register to memory DMA2D mode selected */
01964   if (hdma2d->Init.Mode == DMA2D_R2M)
01965   {
01966     tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
01967     tmp2 = pdata & DMA2D_OCOLR_RED_1;
01968     tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
01969     tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
01970 
01971     /* Prepare the value to be written to the OCOLR register according to the color mode */
01972     if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
01973     {
01974       tmp = (tmp3 | tmp2 | tmp1| tmp4);
01975     }
01976     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
01977     {
01978       tmp = (tmp3 | tmp2 | tmp4);
01979     }
01980     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
01981     {
01982       tmp2 = (tmp2 >> 19U);
01983       tmp3 = (tmp3 >> 10U);
01984       tmp4 = (tmp4 >> 3U );
01985       tmp  = ((tmp3 << 5U) | (tmp2 << 11U) | tmp4);
01986     }
01987     else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
01988     {
01989       tmp1 = (tmp1 >> 31U);
01990       tmp2 = (tmp2 >> 19U);
01991       tmp3 = (tmp3 >> 11U);
01992       tmp4 = (tmp4 >> 3U );
01993       tmp  = ((tmp3 << 5U) | (tmp2 << 10U) | (tmp1 << 15U) | tmp4);
01994     }
01995     else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
01996     {
01997       tmp1 = (tmp1 >> 28U);
01998       tmp2 = (tmp2 >> 20U);
01999       tmp3 = (tmp3 >> 12U);
02000       tmp4 = (tmp4 >> 4U );
02001       tmp  = ((tmp3 << 4U) | (tmp2 << 8U) | (tmp1 << 12U) | tmp4);
02002     }
02003     /* Write to DMA2D OCOLR register */
02004     WRITE_REG(hdma2d->Instance->OCOLR, tmp);
02005   }
02006   else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
02007   {
02008     /* Configure DMA2D source address */
02009     WRITE_REG(hdma2d->Instance->FGMAR, pdata);
02010   }
02011 }
02012 
02013 /**
02014   * @}
02015   */
02016 
02017 /**
02018   * @}
02019   */
02020 
02021 /**
02022   * @}
02023   */
02024 #endif /* DMA2D */
02025 #endif /* HAL_DMA2D_MODULE_ENABLED */
02026 
02027 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/