STM32L486xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_dac.c 00004 * @author MCD Application Team 00005 * @brief DAC HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the Digital to Analog Converter (DAC) peripheral: 00008 * + Initialization and de-initialization functions 00009 * + IO operation functions 00010 * + Peripheral Control functions 00011 * + Peripheral State and Errors functions 00012 * 00013 * 00014 @verbatim 00015 ============================================================================== 00016 ##### DAC Peripheral features ##### 00017 ============================================================================== 00018 [..] 00019 *** DAC Channels *** 00020 ==================== 00021 [..] 00022 STM32L4 devices integrate one or two 12-bit Digital Analog Converters 00023 (i.e. one or 2 channel(s)) 00024 1 channel : STM32L451xx STM32L452xx STM32L462xx 00025 2 channels: STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx 00026 STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx 00027 STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx 00028 00029 When 2 channels are available, the 2 converters (i.e. channel1 & channel2) 00030 can be used independently or simultaneously (dual mode): 00031 (#) DAC channel1 with DAC_OUT1 (PA4) as output or connected to on-chip 00032 peripherals (ex. OPAMPs, comparators). 00033 (#) Whenever present, DAC channel2 with DAC_OUT2 (PA5) as output 00034 or connected to on-chip peripherals (ex. OPAMPs, comparators). 00035 00036 *** DAC Triggers *** 00037 ==================== 00038 [..] 00039 Digital to Analog conversion can be non-triggered using DAC_TRIGGER_NONE 00040 and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. 00041 [..] 00042 Digital to Analog conversion can be triggered by: 00043 (#) External event: EXTI Line 9 (any GPIOx_PIN_9) using DAC_TRIGGER_EXT_IT9. 00044 The used pin (GPIOx_PIN_9) must be configured in input mode. 00045 00046 (#) Timers TRGO: TIM2, TIM3, TIM4, TIM5, TIM6 and TIM7 00047 (DAC_TRIGGER_T2_TRGO, DAC_TRIGGER_T3_TRGO...) 00048 00049 (#) Software using DAC_TRIGGER_SOFTWARE 00050 00051 *** DAC Buffer mode feature *** 00052 =============================== 00053 [..] 00054 Each DAC channel integrates an output buffer that can be used to 00055 reduce the output impedance, and to drive external loads directly 00056 without having to add an external operational amplifier. 00057 To enable, the output buffer use 00058 sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_ENABLE; 00059 [..] 00060 (@) Refer to the device datasheet for more details about output 00061 impedance value with and without output buffer. 00062 00063 *** DAC connect feature *** 00064 =============================== 00065 [..] 00066 Each DAC channel can be connected internally. 00067 To connect, use 00068 sConfig.DAC_ConnectOnChipPeripheral = DAC_CHIPCONNECT_ENABLE; 00069 00070 *** GPIO configurations guidelines *** 00071 ===================== 00072 [..] 00073 When a DAC channel is used (ex channel1 on PA4) and the other is not 00074 (ex channel2 on PA5 is configured in Analog and disabled). 00075 Channel1 may disturb channel2 as coupling effect. 00076 Note that there is no coupling on channel2 as soon as channel2 is turned on. 00077 Coupling on adjacent channel could be avoided as follows: 00078 when unused PA5 is configured as INPUT PULL-UP or DOWN. 00079 PA5 is configured in ANALOG just before it is turned on. 00080 00081 *** DAC Sample and Hold feature *** 00082 ======================== 00083 [..] 00084 For each converter, 2 modes are supported: normal mode and 00085 "sample and hold" mode (i.e. low power mode). 00086 In the sample and hold mode, the DAC core converts data, then holds the 00087 converted voltage on a capacitor. When not converting, the DAC cores and 00088 buffer are completely turned off between samples and the DAC output is 00089 tri-stated, therefore reducing the overall power consumption. A new 00090 stabilization period is needed before each new conversion. 00091 00092 The sample and hold allow setting internal or external voltage @ 00093 low power consumption cost (output value can be at any given rate either 00094 by CPU or DMA). 00095 00096 The Sample and hold block and registers uses either LSI & run in 00097 several power modes: run mode, sleep mode, low power run, low power sleep 00098 mode & stop1 mode. 00099 00100 Low power stop1 mode allows only static conversion. 00101 00102 To enable Sample and Hold mode 00103 Enable LSI using HAL_RCC_OscConfig with RCC_OSCILLATORTYPE_LSI & 00104 RCC_LSI_ON parameters. 00105 00106 Use DAC_InitStructure.DAC_SampleAndHold = DAC_SAMPLEANDHOLD_ENABLE; 00107 & DAC_ChannelConfTypeDef.DAC_SampleAndHoldConfig.DAC_SampleTime, 00108 DAC_HoldTime & DAC_RefreshTime; 00109 00110 00111 00112 *** DAC calibration feature *** 00113 =================================== 00114 [..] 00115 (#) The 2 converters (channel1 & channel2) provide calibration capabilities. 00116 (++) Calibration aims at correcting some offset of output buffer. 00117 (++) The DAC uses either factory calibration settings OR user defined 00118 calibration (trimming) settings (i.e. trimming mode). 00119 (++) The user defined settings can be figured out using self calibration 00120 handled by HAL_DACEx_SelfCalibrate. 00121 (++) HAL_DACEx_SelfCalibrate: 00122 (+++) Runs automatically the calibration. 00123 (+++) Enables the user trimming mode 00124 (+++) Updates a structure with trimming values with fresh calibration 00125 results. 00126 The user may store the calibration results for larger 00127 (ex monitoring the trimming as a function of temperature 00128 for instance) 00129 00130 *** DAC wave generation feature *** 00131 =================================== 00132 [..] 00133 Both DAC channels can be used to generate 00134 (#) Noise wave 00135 (#) Triangle wave 00136 00137 *** DAC data format *** 00138 ======================= 00139 [..] 00140 The DAC data format can be: 00141 (#) 8-bit right alignment using DAC_ALIGN_8B_R 00142 (#) 12-bit left alignment using DAC_ALIGN_12B_L 00143 (#) 12-bit right alignment using DAC_ALIGN_12B_R 00144 00145 *** DAC data value to voltage correspondence *** 00146 ================================================ 00147 [..] 00148 The analog output voltage on each DAC channel pin is determined 00149 by the following equation: 00150 [..] 00151 DAC_OUTx = VREF+ * DOR / 4095 00152 (+) with DOR is the Data Output Register 00153 [..] 00154 VEF+ is the input voltage reference (refer to the device datasheet) 00155 [..] 00156 e.g. To set DAC_OUT1 to 0.7V, use 00157 (+) Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V 00158 00159 *** DMA requests *** 00160 ===================== 00161 [..] 00162 A DMA1 request can be generated when an external trigger (but not a software trigger) 00163 occurs if DMA1 requests are enabled using HAL_DAC_Start_DMA(). 00164 DMA requests are mapped as following: 00165 (#) DAC channel1: mapped either on 00166 (++) DMA1 request 6 channel3 00167 (++) or DMA2 request channel4 which must be already configured 00168 (#) DAC channel2 (whenever present): mapped either on 00169 (++) DMA1 request 5 channel4 00170 (++) or DMA2 request 3 channel5 which must be already configured 00171 [..] 00172 (@) For Dual mode and specific signal (Triangle and noise) generation please 00173 refer to Extended Features Driver description 00174 00175 ##### How to use this driver ##### 00176 ============================================================================== 00177 [..] 00178 (+) DAC APB clock must be enabled to get write access to DAC 00179 registers using HAL_DAC_Init() 00180 (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode. 00181 (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function. 00182 (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA() functions. 00183 00184 *** Calibration mode IO operation *** 00185 ====================================== 00186 [..] 00187 (+) Retrieve the factory trimming (calibration settings) using HAL_DACEx_GetTrimOffset() 00188 (+) Run the calibration using HAL_DACEx_SelfCalibrate() 00189 (+) Update the trimming while DAC running using HAL_DACEx_SetUserTrimming() 00190 00191 *** Polling mode IO operation *** 00192 ================================= 00193 [..] 00194 (+) Start the DAC peripheral using HAL_DAC_Start() 00195 (+) To read the DAC last data output value, use the HAL_DAC_GetValue() function. 00196 (+) Stop the DAC peripheral using HAL_DAC_Stop() 00197 00198 *** DMA mode IO operation *** 00199 ============================== 00200 [..] 00201 (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length 00202 of data to be transferred at each end of conversion 00203 (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() 00204 function is executed and user can add his own code by customization of function pointer 00205 HAL_DAC_ConvHalfCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() 00206 (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() 00207 function is executed and user can add his own code by customization of function pointer 00208 HAL_DAC_ConvCpltCallbackCh1() or HAL_DACEx_ConvHalfCpltCallbackCh2() 00209 (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can 00210 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1 00211 (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler. 00212 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() 00213 function is executed and user can add his own code by customization of function pointer 00214 HAL_DAC_DMAUnderrunCallbackCh1() or HAL_DACEx_DMAUnderrunCallbackCh2() and 00215 add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1() 00216 (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA() 00217 00218 *** Callback registration *** 00219 ============================================= 00220 [..] 00221 The compilation define USE_HAL_DAC_REGISTER_CALLBACKS when set to 1 00222 allows the user to configure dynamically the driver callbacks. 00223 00224 Use Functions @ref HAL_DAC_RegisterCallback() to register a user callback, 00225 it allows to register following callbacks: 00226 (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. 00227 (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. 00228 (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. 00229 (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. 00230 (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. 00231 (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. 00232 (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. 00233 (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. 00234 (+) MspInitCallback : DAC MspInit. 00235 (+) MspDeInitCallback : DAC MspdeInit. 00236 This function takes as parameters the HAL peripheral handle, the Callback ID 00237 and a pointer to the user callback function. 00238 00239 Use function @ref HAL_DAC_UnRegisterCallback() to reset a callback to the default 00240 weak (surcharged) function. It allows to reset following callbacks: 00241 (+) ConvCpltCallbackCh1 : callback when a half transfer is completed on Ch1. 00242 (+) ConvHalfCpltCallbackCh1 : callback when a transfer is completed on Ch1. 00243 (+) ErrorCallbackCh1 : callback when an error occurs on Ch1. 00244 (+) DMAUnderrunCallbackCh1 : callback when an underrun error occurs on Ch1. 00245 (+) ConvCpltCallbackCh2 : callback when a half transfer is completed on Ch2. 00246 (+) ConvHalfCpltCallbackCh2 : callback when a transfer is completed on Ch2. 00247 (+) ErrorCallbackCh2 : callback when an error occurs on Ch2. 00248 (+) DMAUnderrunCallbackCh2 : callback when an underrun error occurs on Ch2. 00249 (+) MspInitCallback : DAC MspInit. 00250 (+) MspDeInitCallback : DAC MspdeInit. 00251 (+) All Callbacks 00252 This function) takes as parameters the HAL peripheral handle and the Callback ID. 00253 00254 By default, after the @ref HAL_DAC_Init and if the state is HAL_DAC_STATE_RESET 00255 all callbacks are reset to the corresponding legacy weak (surcharged) functions. 00256 Exception done for MspInit and MspDeInit callbacks that are respectively 00257 reset to the legacy weak (surcharged) functions in the @ref HAL_DAC_Init 00258 and @ref HAL_DAC_DeInit only when these callbacks are null (not registered beforehand). 00259 If not, MspInit or MspDeInit are not null, the @ref HAL_DAC_Init and @ref HAL_DAC_DeInit 00260 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) 00261 00262 Callbacks can be registered/unregistered in READY state only. 00263 Exception done for MspInit/MspDeInit callbacks that can be registered/unregistered 00264 in READY or RESET state, thus registered (user) MspInit/DeInit callbacks can be used 00265 during the Init/DeInit. 00266 In that case first register the MspInit/MspDeInit user callbacks 00267 using @ref HAL_DAC_RegisterCallback before calling @ref HAL_DAC_DeInit 00268 or @ref HAL_DAC_Init function. 00269 00270 When The compilation define USE_HAL_DAC_REGISTER_CALLBACKS is set to 0 or 00271 not defined, the callback registering feature is not available 00272 and weak (surcharged) callbacks are used. 00273 00274 00275 00276 *** DAC HAL driver macros list *** 00277 ============================================= 00278 [..] 00279 Below the list of most used macros in DAC HAL driver. 00280 00281 (+) __HAL_DAC_ENABLE : Enable the DAC peripheral 00282 (+) __HAL_DAC_DISABLE : Disable the DAC peripheral 00283 (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags 00284 (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status 00285 00286 [..] 00287 (@) You can refer to the DAC HAL driver header file for more useful macros 00288 00289 @endverbatim 00290 ****************************************************************************** 00291 * @attention 00292 * 00293 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00294 * 00295 * Redistribution and use in source and binary forms, with or without modification, 00296 * are permitted provided that the following conditions are met: 00297 * 1. Redistributions of source code must retain the above copyright notice, 00298 * this list of conditions and the following disclaimer. 00299 * 2. Redistributions in binary form must reproduce the above copyright notice, 00300 * this list of conditions and the following disclaimer in the documentation 00301 * and/or other materials provided with the distribution. 00302 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00303 * may be used to endorse or promote products derived from this software 00304 * without specific prior written permission. 00305 * 00306 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00307 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00308 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00309 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00310 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00311 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00312 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00313 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00314 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00315 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00316 * 00317 ****************************************************************************** 00318 */ 00319 00320 00321 /* Includes ------------------------------------------------------------------*/ 00322 #include "stm32l4xx_hal.h" 00323 00324 /** @addtogroup STM32L4xx_HAL_Driver 00325 * @{ 00326 */ 00327 00328 /** @defgroup DAC DAC 00329 * @brief DAC driver modules 00330 * @{ 00331 */ 00332 00333 #ifdef HAL_DAC_MODULE_ENABLED 00334 00335 /* Private typedef -----------------------------------------------------------*/ 00336 /* Private define ------------------------------------------------------------*/ 00337 /* Private constants ---------------------------------------------------------*/ 00338 /** @addtogroup DAC_Private_Constants DAC Private Constants 00339 * @{ 00340 */ 00341 #define TIMEOUT_DAC_CALIBCONFIG ((uint32_t)1) /* 1 ms */ 00342 #define HFSEL_ENABLE_THRESHOLD_80MHZ ((uint32_t)80000000) /* 80 mHz */ 00343 /** 00344 * @} 00345 */ 00346 00347 /* Private macro -------------------------------------------------------------*/ 00348 /* Private macro -------------------------------------------------------------*/ 00349 /* Private variables ---------------------------------------------------------*/ 00350 /* Private function prototypes -----------------------------------------------*/ 00351 /** @defgroup DAC_Private_Functions DAC Private Functions 00352 * @{ 00353 */ 00354 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma); 00355 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma); 00356 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 00357 /** 00358 * @} 00359 */ 00360 /* Exported functions -------------------------------------------------------*/ 00361 00362 /** @defgroup DAC_Exported_Functions DAC Exported Functions 00363 * @{ 00364 */ 00365 00366 /** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions 00367 * @brief Initialization and Configuration functions 00368 * 00369 @verbatim 00370 ============================================================================== 00371 ##### Initialization and de-initialization functions ##### 00372 ============================================================================== 00373 [..] This section provides functions allowing to: 00374 (+) Initialize and configure the DAC. 00375 (+) De-initialize the DAC. 00376 00377 @endverbatim 00378 * @{ 00379 */ 00380 00381 /** 00382 * @brief Initialize the DAC peripheral according to the specified parameters 00383 * in the DAC_InitStruct and initialize the associated handle. 00384 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 00385 * the configuration information for the specified DAC. 00386 * @retval HAL status 00387 */ 00388 HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac) 00389 { 00390 /* Check DAC handle */ 00391 if(hdac == NULL) 00392 { 00393 return HAL_ERROR; 00394 } 00395 /* Check the parameters */ 00396 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); 00397 00398 if(hdac->State == HAL_DAC_STATE_RESET) 00399 { 00400 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 00401 /* Init the DAC Callback settings */ 00402 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; 00403 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; 00404 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; 00405 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; 00406 00407 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; 00408 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; 00409 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; 00410 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; 00411 00412 if(hdac->MspInitCallback == NULL) 00413 { 00414 hdac->MspInitCallback = HAL_DAC_MspInit; 00415 } 00416 if(hdac->MspDeInitCallback == NULL) 00417 { 00418 hdac->MspDeInitCallback = HAL_DAC_MspDeInit; 00419 } 00420 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 00421 00422 /* Allocate lock resource and initialize it */ 00423 hdac->Lock = HAL_UNLOCKED; 00424 00425 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 00426 /* Init the low level hardware */ 00427 hdac->MspInitCallback(hdac); 00428 #else 00429 /* Init the low level hardware */ 00430 HAL_DAC_MspInit(hdac); 00431 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 00432 } 00433 00434 /* Initialize the DAC state*/ 00435 hdac->State = HAL_DAC_STATE_BUSY; 00436 00437 /* Set DAC error code to none */ 00438 hdac->ErrorCode = HAL_DAC_ERROR_NONE; 00439 00440 /* Initialize the DAC state*/ 00441 hdac->State = HAL_DAC_STATE_READY; 00442 00443 /* Return function status */ 00444 return HAL_OK; 00445 } 00446 00447 /** 00448 * @brief Deinitialize the DAC peripheral registers to their default reset values. 00449 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 00450 * the configuration information for the specified DAC. 00451 * @retval HAL status 00452 */ 00453 HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac) 00454 { 00455 /* Check DAC handle */ 00456 if(hdac == NULL) 00457 { 00458 return HAL_ERROR; 00459 } 00460 00461 /* Check the parameters */ 00462 assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance)); 00463 00464 /* Change DAC state */ 00465 hdac->State = HAL_DAC_STATE_BUSY; 00466 00467 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 00468 if(hdac->MspDeInitCallback == NULL) 00469 { 00470 hdac->MspDeInitCallback = HAL_DAC_MspDeInit; 00471 } 00472 /* DeInit the low level hardware */ 00473 hdac->MspDeInitCallback(hdac); 00474 00475 #else 00476 /* DeInit the low level hardware */ 00477 HAL_DAC_MspDeInit(hdac); 00478 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 00479 00480 /* Set DAC error code to none */ 00481 hdac->ErrorCode = HAL_DAC_ERROR_NONE; 00482 00483 /* Change DAC state */ 00484 hdac->State = HAL_DAC_STATE_RESET; 00485 00486 /* Release Lock */ 00487 __HAL_UNLOCK(hdac); 00488 00489 /* Return function status */ 00490 return HAL_OK; 00491 } 00492 00493 /** 00494 * @brief Initialize the DAC MSP. 00495 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 00496 * the configuration information for the specified DAC. 00497 * @retval None 00498 */ 00499 __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac) 00500 { 00501 /* Prevent unused argument(s) compilation warning */ 00502 UNUSED(hdac); 00503 00504 /* NOTE : This function should not be modified, when the callback is needed, 00505 the HAL_DAC_MspInit could be implemented in the user file 00506 */ 00507 } 00508 00509 /** 00510 * @brief DeInitialize the DAC MSP. 00511 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 00512 * the configuration information for the specified DAC. 00513 * @retval None 00514 */ 00515 __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac) 00516 { 00517 /* Prevent unused argument(s) compilation warning */ 00518 UNUSED(hdac); 00519 00520 /* NOTE : This function should not be modified, when the callback is needed, 00521 the HAL_DAC_MspDeInit could be implemented in the user file 00522 */ 00523 } 00524 00525 /** 00526 * @} 00527 */ 00528 00529 /** @defgroup DAC_Exported_Functions_Group2 IO operation functions 00530 * @brief IO operation functions 00531 * 00532 @verbatim 00533 ============================================================================== 00534 ##### IO operation functions ##### 00535 ============================================================================== 00536 [..] This section provides functions allowing to: 00537 (+) Start conversion. 00538 (+) Stop conversion. 00539 (+) Start conversion and enable DMA transfer. 00540 (+) Stop conversion and disable DMA transfer. 00541 (+) Get result of conversion. 00542 00543 @endverbatim 00544 * @{ 00545 */ 00546 00547 /** 00548 * @brief Enables DAC and starts conversion of channel. 00549 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 00550 * the configuration information for the specified DAC. 00551 * @param Channel: The selected DAC channel. 00552 * This parameter can be one of the following values: 00553 * @arg DAC_CHANNEL_1: DAC Channel1 selected 00554 * @arg DAC_CHANNEL_2: DAC Channel2 selected (when supported) 00555 * @retval HAL status 00556 */ 00557 HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel) 00558 { 00559 /* Check the parameters */ 00560 assert_param(IS_DAC_CHANNEL(Channel)); 00561 00562 /* Process locked */ 00563 __HAL_LOCK(hdac); 00564 00565 /* Change DAC state */ 00566 hdac->State = HAL_DAC_STATE_BUSY; 00567 00568 /* Enable the Peripheral */ 00569 __HAL_DAC_ENABLE(hdac, Channel); 00570 00571 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 00572 if(Channel == DAC_CHANNEL_1) 00573 { 00574 /* Check if software trigger enabled */ 00575 if(((DAC_CR_TEN1 & ~(DAC_CR_TSEL1)) == (hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)))) 00576 { 00577 /* Enable the selected DAC software conversion */ 00578 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 00579 } 00580 } 00581 else 00582 { 00583 /* Check if software trigger enabled */ 00584 if(((DAC_CR_TEN2 & ~(DAC_CR_TSEL2)) == (hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)))) 00585 { 00586 /* Enable the selected DAC software conversion*/ 00587 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 00588 } 00589 } 00590 00591 #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 00592 00593 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ 00594 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) 00595 if(Channel == DAC_CHANNEL_1) 00596 { 00597 /* Check if software trigger enabled */ 00598 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1)) 00599 { 00600 /* Enable the selected DAC software conversion */ 00601 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 00602 } 00603 } 00604 else 00605 { 00606 /* Check if software trigger enabled */ 00607 if((hdac->Instance->CR & (DAC_CR_TEN2 | DAC_CR_TSEL2)) == (DAC_CR_TEN2 | DAC_CR_TSEL2)) 00608 { 00609 /* Enable the selected DAC software conversion*/ 00610 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2); 00611 } 00612 } 00613 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ 00614 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ 00615 00616 00617 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 00618 /* Check if software trigger enabled */ 00619 if((hdac->Instance->CR & (DAC_CR_TEN1 | DAC_CR_TSEL1)) == (DAC_CR_TEN1 | DAC_CR_TSEL1)) 00620 { 00621 /* Enable the selected DAC software conversion */ 00622 SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1); 00623 } 00624 #endif /* STM32L451xx STM32L452xx STM32L462xx */ 00625 /* Change DAC state */ 00626 hdac->State = HAL_DAC_STATE_READY; 00627 00628 /* Process unlocked */ 00629 __HAL_UNLOCK(hdac); 00630 00631 /* Return function status */ 00632 return HAL_OK; 00633 } 00634 00635 /** 00636 * @brief Disables DAC and stop conversion of channel. 00637 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 00638 * the configuration information for the specified DAC. 00639 * @param Channel: The selected DAC channel. 00640 * This parameter can be one of the following values: 00641 * @arg DAC_CHANNEL_1: DAC Channel1 selected 00642 * @arg DAC_CHANNEL_2: DAC Channel2 selected 00643 * @retval HAL status 00644 */ 00645 HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel) 00646 { 00647 /* Check the parameters */ 00648 assert_param(IS_DAC_CHANNEL(Channel)); 00649 00650 /* Disable the Peripheral */ 00651 __HAL_DAC_DISABLE(hdac, Channel); 00652 00653 /* Change DAC state */ 00654 hdac->State = HAL_DAC_STATE_READY; 00655 00656 /* Return function status */ 00657 return HAL_OK; 00658 } 00659 00660 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 00661 /** 00662 * @brief Enables DAC and starts conversion of channel. 00663 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 00664 * the configuration information for the specified DAC. 00665 * @param Channel: The selected DAC channel. 00666 * This parameter can be one of the following values: 00667 * @arg DAC_CHANNEL_1: DAC Channel1 selected 00668 * @param pData: The destination peripheral Buffer address. 00669 * @param Length: The length of data to be transferred from memory to DAC peripheral 00670 * @param Alignment: Specifies the data alignment for DAC channel. 00671 * This parameter can be one of the following values: 00672 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected 00673 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected 00674 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected 00675 * @retval HAL status 00676 */ 00677 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) 00678 { 00679 uint32_t tmpreg = 0; 00680 00681 /* Check the parameters */ 00682 assert_param(IS_DAC_CHANNEL(Channel)); 00683 assert_param(IS_DAC_ALIGN(Alignment)); 00684 00685 /* Process locked */ 00686 __HAL_LOCK(hdac); 00687 00688 /* Change DAC state */ 00689 hdac->State = HAL_DAC_STATE_BUSY; 00690 00691 /* Set the DMA transfer complete callback for channel1 */ 00692 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; 00693 00694 /* Set the DMA half transfer complete callback for channel1 */ 00695 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; 00696 00697 /* Set the DMA error callback for channel1 */ 00698 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; 00699 00700 /* Enable the selected DAC channel1 DMA request */ 00701 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); 00702 00703 /* Case of use of channel 1 */ 00704 switch(Alignment) 00705 { 00706 case DAC_ALIGN_12B_R: 00707 /* Get DHR12R1 address */ 00708 tmpreg = (uint32_t)&hdac->Instance->DHR12R1; 00709 break; 00710 case DAC_ALIGN_12B_L: 00711 /* Get DHR12L1 address */ 00712 tmpreg = (uint32_t)&hdac->Instance->DHR12L1; 00713 break; 00714 case DAC_ALIGN_8B_R: 00715 /* Get DHR8R1 address */ 00716 tmpreg = (uint32_t)&hdac->Instance->DHR8R1; 00717 break; 00718 default: 00719 break; 00720 } 00721 00722 /* Enable the DMA channel */ 00723 /* Enable the DAC DMA underrun interrupt */ 00724 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); 00725 00726 /* Enable the DMA channel */ 00727 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); 00728 00729 /* Process Unlocked */ 00730 __HAL_UNLOCK(hdac); 00731 00732 /* Enable the Peripheral */ 00733 __HAL_DAC_ENABLE(hdac, Channel); 00734 00735 /* Return function status */ 00736 return HAL_OK; 00737 } 00738 #endif /* STM32L451xx STM32L452xx STM32L462xx */ 00739 00740 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ 00741 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00742 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 00743 00744 /** 00745 * @brief Enables DAC and starts conversion of channel. 00746 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 00747 * the configuration information for the specified DAC. 00748 * @param Channel: The selected DAC channel. 00749 * This parameter can be one of the following values: 00750 * @arg DAC_CHANNEL_1: DAC Channel1 selected 00751 * @arg DAC_CHANNEL_2: DAC Channel2 selected 00752 * @param pData: The destination peripheral Buffer address. 00753 * @param Length: The length of data to be transferred from memory to DAC peripheral 00754 * @param Alignment: Specifies the data alignment for DAC channel. 00755 * This parameter can be one of the following values: 00756 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected 00757 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected 00758 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected 00759 * @retval HAL status 00760 */ 00761 HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment) 00762 { 00763 uint32_t tmpreg = 0; 00764 00765 /* Check the parameters */ 00766 assert_param(IS_DAC_CHANNEL(Channel)); 00767 assert_param(IS_DAC_ALIGN(Alignment)); 00768 00769 /* Process locked */ 00770 __HAL_LOCK(hdac); 00771 00772 /* Change DAC state */ 00773 hdac->State = HAL_DAC_STATE_BUSY; 00774 00775 if(Channel == DAC_CHANNEL_1) 00776 { 00777 /* Set the DMA transfer complete callback for channel1 */ 00778 hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1; 00779 00780 /* Set the DMA half transfer complete callback for channel1 */ 00781 hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1; 00782 00783 /* Set the DMA error callback for channel1 */ 00784 hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1; 00785 00786 /* Enable the selected DAC channel1 DMA request */ 00787 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); 00788 00789 /* Case of use of channel 1 */ 00790 switch(Alignment) 00791 { 00792 case DAC_ALIGN_12B_R: 00793 /* Get DHR12R1 address */ 00794 tmpreg = (uint32_t)&hdac->Instance->DHR12R1; 00795 break; 00796 case DAC_ALIGN_12B_L: 00797 /* Get DHR12L1 address */ 00798 tmpreg = (uint32_t)&hdac->Instance->DHR12L1; 00799 break; 00800 case DAC_ALIGN_8B_R: 00801 /* Get DHR8R1 address */ 00802 tmpreg = (uint32_t)&hdac->Instance->DHR8R1; 00803 break; 00804 default: 00805 break; 00806 } 00807 } 00808 else 00809 { 00810 /* Set the DMA transfer complete callback for channel2 */ 00811 hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2; 00812 00813 /* Set the DMA half transfer complete callback for channel2 */ 00814 hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2; 00815 00816 /* Set the DMA error callback for channel2 */ 00817 hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2; 00818 00819 /* Enable the selected DAC channel2 DMA request */ 00820 SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); 00821 00822 /* Case of use of channel 2 */ 00823 switch(Alignment) 00824 { 00825 case DAC_ALIGN_12B_R: 00826 /* Get DHR12R2 address */ 00827 tmpreg = (uint32_t)&hdac->Instance->DHR12R2; 00828 break; 00829 case DAC_ALIGN_12B_L: 00830 /* Get DHR12L2 address */ 00831 tmpreg = (uint32_t)&hdac->Instance->DHR12L2; 00832 break; 00833 case DAC_ALIGN_8B_R: 00834 /* Get DHR8R2 address */ 00835 tmpreg = (uint32_t)&hdac->Instance->DHR8R2; 00836 break; 00837 default: 00838 break; 00839 } 00840 } 00841 00842 /* Enable the DMA channel */ 00843 if(Channel == DAC_CHANNEL_1) 00844 { 00845 /* Enable the DAC DMA underrun interrupt */ 00846 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1); 00847 00848 /* Enable the DMA channel */ 00849 HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length); 00850 } 00851 else 00852 { 00853 /* Enable the DAC DMA underrun interrupt */ 00854 __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2); 00855 00856 /* Enable the DMA channel */ 00857 HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length); 00858 } 00859 00860 /* Process Unlocked */ 00861 __HAL_UNLOCK(hdac); 00862 00863 /* Enable the Peripheral */ 00864 __HAL_DAC_ENABLE(hdac, Channel); 00865 00866 /* Return function status */ 00867 return HAL_OK; 00868 } 00869 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ 00870 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ 00871 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 00872 00873 /** 00874 * @brief Disables DAC and stop conversion of channel. 00875 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 00876 * the configuration information for the specified DAC. 00877 * @param Channel: The selected DAC channel. 00878 * This parameter can be one of the following values: 00879 * @arg DAC_CHANNEL_1: DAC Channel1 selected 00880 * @arg DAC_CHANNEL_2: DAC Channel2 selected 00881 * @retval HAL status 00882 */ 00883 HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel) 00884 { 00885 HAL_StatusTypeDef status = HAL_OK; 00886 00887 /* Check the parameters */ 00888 assert_param(IS_DAC_CHANNEL(Channel)); 00889 00890 /* Disable the selected DAC channel DMA request */ 00891 hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel); 00892 00893 /* Disable the Peripheral */ 00894 __HAL_DAC_DISABLE(hdac, Channel); 00895 00896 /* Disable the DMA channel */ 00897 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ 00898 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00899 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 00900 /* Channel1 is used */ 00901 if (Channel == DAC_CHANNEL_1) 00902 { 00903 /* Disable the DMA channel */ 00904 status = HAL_DMA_Abort(hdac->DMA_Handle1); 00905 00906 /* Disable the DAC DMA underrun interrupt */ 00907 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); 00908 } 00909 else /* Channel2 is used for */ 00910 { 00911 /* Disable the DMA channel */ 00912 status = HAL_DMA_Abort(hdac->DMA_Handle2); 00913 00914 /* Disable the DAC DMA underrun interrupt */ 00915 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR2); 00916 } 00917 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ 00918 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ 00919 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 00920 00921 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 00922 /* Disable the DMA channel */ 00923 status = HAL_DMA_Abort(hdac->DMA_Handle1); 00924 00925 /* Disable the DAC DMA underrun interrupt */ 00926 __HAL_DAC_DISABLE_IT(hdac, DAC_IT_DMAUDR1); 00927 #endif /* STM32L451xx STM32L452xx STM32L462xx */ 00928 00929 /* Check if DMA Channel effectively disabled */ 00930 if (status != HAL_OK) 00931 { 00932 /* Update DAC state machine to error */ 00933 hdac->State = HAL_DAC_STATE_ERROR; 00934 } 00935 else 00936 { 00937 /* Change DAC state */ 00938 hdac->State = HAL_DAC_STATE_READY; 00939 } 00940 00941 /* Return function status */ 00942 return status; 00943 } 00944 00945 /* DAC channel 2 is available on top of DAC channel 1 in */ 00946 /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ 00947 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ 00948 00949 /** 00950 * @brief Handles DAC interrupt request 00951 * This function uses the interruption of DMA 00952 * underrun. 00953 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 00954 * the configuration information for the specified DAC. 00955 * @retval None 00956 */ 00957 void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac) 00958 { 00959 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR1)) 00960 { 00961 /* Check underrun flag of DAC channel 1 */ 00962 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1)) 00963 { 00964 /* Change DAC state to error state */ 00965 hdac->State = HAL_DAC_STATE_ERROR; 00966 00967 /* Set DAC error code to chanel1 DMA underrun error */ 00968 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH1); 00969 00970 /* Clear the underrun flag */ 00971 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1); 00972 00973 /* Disable the selected DAC channel1 DMA request */ 00974 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN1); 00975 00976 /* Error callback */ 00977 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 00978 hdac->DMAUnderrunCallbackCh1(hdac); 00979 #else 00980 HAL_DAC_DMAUnderrunCallbackCh1(hdac); 00981 #endif 00982 } 00983 } 00984 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ 00985 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 00986 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 00987 if(__HAL_DAC_GET_IT_SOURCE(hdac, DAC_IT_DMAUDR2)) 00988 { 00989 /* Check underrun flag of DAC channel 2 */ 00990 if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2)) 00991 { 00992 /* Change DAC state to error state */ 00993 hdac->State = HAL_DAC_STATE_ERROR; 00994 00995 /* Set DAC error code to channel2 DMA underrun error */ 00996 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_DMAUNDERRUNCH2); 00997 00998 /* Clear the underrun flag */ 00999 __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2); 01000 01001 /* Disable the selected DAC channel1 DMA request */ 01002 CLEAR_BIT(hdac->Instance->CR, DAC_CR_DMAEN2); 01003 01004 /* Error callback */ 01005 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 01006 hdac->DMAUnderrunCallbackCh2(hdac); 01007 #else 01008 HAL_DACEx_DMAUnderrunCallbackCh2(hdac); 01009 #endif 01010 } 01011 } 01012 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ 01013 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ 01014 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 01015 } 01016 01017 /** 01018 * @brief Set the specified data holding register value for DAC channel. 01019 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 01020 * the configuration information for the specified DAC. 01021 * @param Channel: The selected DAC channel. 01022 * This parameter can be one of the following values: 01023 * @arg DAC_CHANNEL_1: DAC Channel1 selected 01024 * @arg DAC_CHANNEL_2: DAC Channel2 selected 01025 * @param Alignment: Specifies the data alignment. 01026 * This parameter can be one of the following values: 01027 * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected 01028 * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected 01029 * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected 01030 * @param Data: Data to be loaded in the selected data holding register. 01031 * @retval HAL status 01032 */ 01033 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) 01034 { 01035 __IO uint32_t tmp = 0; 01036 01037 /* Check the parameters */ 01038 assert_param(IS_DAC_CHANNEL(Channel)); 01039 assert_param(IS_DAC_ALIGN(Alignment)); 01040 assert_param(IS_DAC_DATA(Data)); 01041 01042 tmp = (uint32_t)hdac->Instance; 01043 if(Channel == DAC_CHANNEL_1) 01044 { 01045 tmp += DAC_DHR12R1_ALIGNMENT(Alignment); 01046 } 01047 else 01048 { 01049 tmp += DAC_DHR12R2_ALIGNMENT(Alignment); 01050 } 01051 01052 /* Set the DAC channel selected data holding register */ 01053 *(__IO uint32_t *) tmp = Data; 01054 01055 /* Return function status */ 01056 return HAL_OK; 01057 } 01058 01059 /** 01060 * @brief Conversion complete callback in non-blocking mode for Channel1 01061 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 01062 * the configuration information for the specified DAC. 01063 * @retval None 01064 */ 01065 __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac) 01066 { 01067 /* Prevent unused argument(s) compilation warning */ 01068 UNUSED(hdac); 01069 01070 /* NOTE : This function should not be modified, when the callback is needed, 01071 the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file 01072 */ 01073 } 01074 01075 /** 01076 * @brief Conversion half DMA transfer callback in non-blocking mode for Channel1 01077 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 01078 * the configuration information for the specified DAC. 01079 * @retval None 01080 */ 01081 __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac) 01082 { 01083 /* Prevent unused argument(s) compilation warning */ 01084 UNUSED(hdac); 01085 01086 /* NOTE : This function should not be modified, when the callback is needed, 01087 the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file 01088 */ 01089 } 01090 01091 /** 01092 * @brief Error DAC callback for Channel1. 01093 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 01094 * the configuration information for the specified DAC. 01095 * @retval None 01096 */ 01097 __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac) 01098 { 01099 /* Prevent unused argument(s) compilation warning */ 01100 UNUSED(hdac); 01101 01102 /* NOTE : This function should not be modified, when the callback is needed, 01103 the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file 01104 */ 01105 } 01106 01107 /** 01108 * @brief DMA underrun DAC callback for channel1. 01109 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 01110 * the configuration information for the specified DAC. 01111 * @retval None 01112 */ 01113 __weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac) 01114 { 01115 /* Prevent unused argument(s) compilation warning */ 01116 UNUSED(hdac); 01117 01118 /* NOTE : This function should not be modified, when the callback is needed, 01119 the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file 01120 */ 01121 } 01122 01123 /** 01124 * @} 01125 */ 01126 01127 /** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions 01128 * @brief Peripheral Control functions 01129 * 01130 @verbatim 01131 ============================================================================== 01132 ##### Peripheral Control functions ##### 01133 ============================================================================== 01134 [..] This section provides functions allowing to: 01135 (+) Configure channels. 01136 (+) Set the specified data holding register value for DAC channel. 01137 01138 @endverbatim 01139 * @{ 01140 */ 01141 01142 /** 01143 * @brief Returns the last data output value of the selected DAC channel. 01144 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 01145 * the configuration information for the specified DAC. 01146 * @param Channel: The selected DAC channel. 01147 * This parameter can be one of the following values: 01148 * @arg DAC_CHANNEL_1: DAC Channel1 selected 01149 * @arg DAC_CHANNEL_2: DAC Channel2 selected 01150 * @retval The selected DAC channel data output value. 01151 */ 01152 uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel) 01153 { 01154 /* Check the parameters */ 01155 assert_param(IS_DAC_CHANNEL(Channel)); 01156 01157 /* Returns the DAC channel data output register value */ 01158 #if defined (STM32L451xx) || defined (STM32L452xx) || defined (STM32L462xx) 01159 /* Prevent unused argument(s) compilation warning if no assert_param check */ 01160 UNUSED(Channel); 01161 01162 return hdac->Instance->DOR1; 01163 #endif /* STM32L451xx STM32L452xx STM32L462xx */ 01164 01165 #if defined (STM32L431xx) || defined (STM32L432xx) || defined (STM32L433xx) || defined (STM32L442xx) || defined (STM32L443xx) || \ 01166 defined (STM32L471xx) || defined (STM32L475xx) || defined (STM32L476xx) || defined (STM32L485xx) || defined (STM32L486xx) || defined (STM32L496xx) || defined (STM32L4A6xx) || \ 01167 defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 01168 if(Channel == DAC_CHANNEL_1) 01169 { 01170 return hdac->Instance->DOR1; 01171 } 01172 else 01173 { 01174 return hdac->Instance->DOR2; 01175 } 01176 #endif /* STM32L431xx STM32L432xx STM32L433xx STM32L442xx STM32L443xx */ 01177 /* STM32L471xx STM32L475xx STM32L476xx STM32L485xx STM32L486xx STM32L496xx STM32L4A6xx */ 01178 /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 01179 } 01180 01181 /** 01182 * @brief Configures the selected DAC channel. 01183 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 01184 * the configuration information for the specified DAC. 01185 * @param sConfig: DAC configuration structure. 01186 * @param Channel: The selected DAC channel. 01187 * This parameter can be one of the following values: 01188 * @arg DAC_CHANNEL_1: DAC Channel1 selected 01189 * @arg DAC_CHANNEL_2: DAC Channel2 selected (Whenever present) 01190 * @retval HAL status 01191 */ 01192 HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel) 01193 { 01194 uint32_t tmpreg1 = 0, tmpreg2 = 0; 01195 uint32_t tickstart = 0; 01196 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 01197 uint32_t hclkfreq = 0; 01198 #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 01199 01200 /* Check the DAC parameters */ 01201 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 01202 assert_param(IS_DAC_HIGH_FREQUENCY_MODE(sConfig->DAC_HighFrequency)); 01203 #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 01204 assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger)); 01205 assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer)); 01206 assert_param(IS_DAC_CHIP_CONNECTION(sConfig->DAC_ConnectOnChipPeripheral)); 01207 assert_param(IS_DAC_TRIMMING(sConfig->DAC_UserTrimming)); 01208 if ((sConfig->DAC_UserTrimming) == DAC_TRIMMING_USER) 01209 { 01210 assert_param(IS_DAC_TRIMMINGVALUE(sConfig->DAC_TrimmingValue)); 01211 } 01212 assert_param(IS_DAC_SAMPLEANDHOLD(sConfig->DAC_SampleAndHold)); 01213 if ((sConfig->DAC_SampleAndHold) == DAC_SAMPLEANDHOLD_ENABLE) 01214 { 01215 assert_param(IS_DAC_SAMPLETIME(sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime)); 01216 assert_param(IS_DAC_HOLDTIME(sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)); 01217 assert_param(IS_DAC_REFRESHTIME(sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)); 01218 } 01219 assert_param(IS_DAC_CHANNEL(Channel)); 01220 01221 /* Process locked */ 01222 __HAL_LOCK(hdac); 01223 01224 /* Change DAC state */ 01225 hdac->State = HAL_DAC_STATE_BUSY; 01226 01227 if(sConfig->DAC_SampleAndHold == DAC_SAMPLEANDHOLD_ENABLE) 01228 /* Sample on old configuration */ 01229 { 01230 /* SampleTime */ 01231 if (Channel == DAC_CHANNEL_1) 01232 { 01233 /* Get timeout */ 01234 tickstart = HAL_GetTick(); 01235 01236 /* SHSR1 can be written when BWST1 equals RESET */ 01237 while (((hdac->Instance->SR) & DAC_SR_BWST1)!= RESET) 01238 { 01239 /* Check for the Timeout */ 01240 if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 01241 { 01242 /* Update error code */ 01243 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 01244 01245 /* Change the DMA state */ 01246 hdac->State = HAL_DAC_STATE_TIMEOUT; 01247 01248 return HAL_TIMEOUT; 01249 } 01250 } 01251 HAL_Delay(1); 01252 hdac->Instance->SHSR1 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 01253 } 01254 #if !defined (STM32L451xx) & !defined (STM32L452xx) & !defined (STM32L462xx) 01255 else /* Channel 2 */ 01256 { 01257 /* SHSR2 can be written when BWST2 equals RESET */ 01258 01259 while (((hdac->Instance->SR) & DAC_SR_BWST2)!= RESET) 01260 { 01261 /* Check for the Timeout */ 01262 if((HAL_GetTick() - tickstart) > TIMEOUT_DAC_CALIBCONFIG) 01263 { 01264 /* Update error code */ 01265 SET_BIT(hdac->ErrorCode, HAL_DAC_ERROR_TIMEOUT); 01266 01267 /* Change the DMA state */ 01268 hdac->State = HAL_DAC_STATE_TIMEOUT; 01269 01270 return HAL_TIMEOUT; 01271 } 01272 } 01273 HAL_Delay(1); 01274 hdac->Instance->SHSR2 = sConfig->DAC_SampleAndHoldConfig.DAC_SampleTime; 01275 } 01276 #endif /* STM32L451xx STM32L452xx STM32L462xx */ 01277 01278 /* HoldTime */ 01279 MODIFY_REG (hdac->Instance->SHHR, DAC_SHHR_THOLD1<<Channel, (sConfig->DAC_SampleAndHoldConfig.DAC_HoldTime)<<Channel); 01280 /* RefreshTime */ 01281 MODIFY_REG (hdac->Instance->SHRR, DAC_SHRR_TREFRESH1<<Channel, (sConfig->DAC_SampleAndHoldConfig.DAC_RefreshTime)<<Channel); 01282 } 01283 01284 if(sConfig->DAC_UserTrimming == DAC_TRIMMING_USER) 01285 /* USER TRIMMING */ 01286 { 01287 /* Get the DAC CCR value */ 01288 tmpreg1 = hdac->Instance->CCR; 01289 /* Clear trimming value */ 01290 tmpreg1 &= ~(((uint32_t)(DAC_CCR_OTRIM1)) << Channel); 01291 /* Configure for the selected trimming offset */ 01292 tmpreg2 = sConfig->DAC_TrimmingValue; 01293 /* Calculate CCR register value depending on DAC_Channel */ 01294 tmpreg1 |= tmpreg2 << Channel; 01295 /* Write to DAC CCR */ 01296 hdac->Instance->CCR = tmpreg1; 01297 } 01298 /* else factory trimming is used (factory setting are available at reset)*/ 01299 /* SW Nothing has nothing to do */ 01300 01301 /* Get the DAC MCR value */ 01302 tmpreg1 = hdac->Instance->MCR; 01303 /* Clear DAC_MCR_MODE2_0, DAC_MCR_MODE2_1 and DAC_MCR_MODE2_2 bits */ 01304 tmpreg1 &= ~(((uint32_t)(DAC_MCR_MODE1)) << Channel); 01305 /* Configure for the selected DAC channel: mode, buffer output & on chip peripheral connect */ 01306 tmpreg2 = (sConfig->DAC_SampleAndHold | sConfig->DAC_OutputBuffer | sConfig->DAC_ConnectOnChipPeripheral); 01307 /* Calculate MCR register value depending on DAC_Channel */ 01308 tmpreg1 |= tmpreg2 << Channel; 01309 /* Write to DAC MCR */ 01310 hdac->Instance->MCR = tmpreg1; 01311 01312 /* DAC in normal operating mode hence clear DAC_CR_CENx bit */ 01313 CLEAR_BIT (hdac->Instance->CR, DAC_CR_CEN1 << Channel); 01314 01315 /* Get the DAC CR value */ 01316 tmpreg1 = hdac->Instance->CR; 01317 /* Clear TENx, TSELx, WAVEx and MAMPx bits */ 01318 tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1)) << Channel); 01319 /* Configure for the selected DAC channel: trigger */ 01320 /* Set TSELx and TENx bits according to DAC_Trigger value */ 01321 tmpreg2 = (sConfig->DAC_Trigger); 01322 /* Calculate CR register value depending on DAC_Channel */ 01323 tmpreg1 |= tmpreg2 << Channel; 01324 #if defined (STM32L4R5xx) || defined (STM32L4R7xx) || defined (STM32L4R9xx) || defined (STM32L4S5xx) || defined (STM32L4S7xx) || defined(STM32L4S9xx) 01325 if(DAC_HIGH_FREQUENCY_INTERFACE_MODE_ABOVE_80MHZ == sConfig->DAC_HighFrequency) 01326 { 01327 tmpreg1 |= DAC_CR_HFSEL; 01328 } 01329 else 01330 { 01331 if (DAC_HIGH_FREQUENCY_INTERFACE_MODE_DISABLE == sConfig->DAC_HighFrequency) 01332 { 01333 tmpreg1 &= ~(DAC_CR_HFSEL); 01334 } 01335 else /* Automatic selection */ 01336 { 01337 hclkfreq = HAL_RCC_GetHCLKFreq(); 01338 if (hclkfreq > HFSEL_ENABLE_THRESHOLD_80MHZ) 01339 { 01340 /* High frequency enable when HCLK frequency higher than 80 */ 01341 tmpreg1 |= DAC_CR_HFSEL; 01342 } 01343 else 01344 { 01345 /* High frequency disable when HCLK frequency higher than 80 */ 01346 tmpreg1 &= ~(DAC_CR_HFSEL); 01347 } 01348 } 01349 } 01350 01351 #endif /* STM32L4R5xx STM32L4R7xx STM32L4R9xx STM32L4S5xx STM32L4S7xx STM32L4S9xx */ 01352 01353 /* Write to DAC CR */ 01354 hdac->Instance->CR = tmpreg1; 01355 01356 /* Disable wave generation */ 01357 hdac->Instance->CR &= ~(DAC_CR_WAVE1 << Channel); 01358 01359 /* Change DAC state */ 01360 hdac->State = HAL_DAC_STATE_READY; 01361 01362 /* Process unlocked */ 01363 __HAL_UNLOCK(hdac); 01364 01365 /* Return function status */ 01366 return HAL_OK; 01367 } 01368 01369 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 01370 /** 01371 * @brief Register a User DAC Callback 01372 * To be used instead of the weak (surcharged) predefined callback 01373 * @param hdac DAC handle 01374 * @param CallbackID ID of the callback to be registered 01375 * This parameter can be one of the following values: 01376 * @arg @ref HAL_DAC_ERROR_INVALID_CALLBACK DAC Error Callback ID 01377 * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 Complete Callback ID 01378 * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID 01379 * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID 01380 * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID 01381 * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID 01382 * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID 01383 * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID 01384 * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID 01385 * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID 01386 * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID 01387 * 01388 * @param pCallback pointer to the Callback function 01389 * @retval status 01390 */ 01391 HAL_StatusTypeDef HAL_DAC_RegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID, pDAC_CallbackTypeDef pCallback) 01392 { 01393 HAL_StatusTypeDef status = HAL_OK; 01394 01395 if(pCallback == NULL) 01396 { 01397 /* Update the error code */ 01398 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 01399 return HAL_ERROR; 01400 } 01401 01402 /* Process locked */ 01403 __HAL_LOCK(hdac); 01404 01405 if(hdac->State == HAL_DAC_STATE_READY) 01406 { 01407 switch (CallbackID) 01408 { 01409 case HAL_DAC_CH1_COMPLETE_CB_ID : 01410 hdac->ConvCpltCallbackCh1 = pCallback; 01411 break; 01412 case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : 01413 hdac->ConvHalfCpltCallbackCh1 = pCallback; 01414 break; 01415 case HAL_DAC_CH1_ERROR_ID : 01416 hdac->ErrorCallbackCh1 = pCallback; 01417 break; 01418 case HAL_DAC_CH1_UNDERRUN_CB_ID : 01419 hdac->DMAUnderrunCallbackCh1 = pCallback; 01420 break; 01421 case HAL_DAC_CH2_COMPLETE_CB_ID : 01422 hdac->ConvCpltCallbackCh2 = pCallback; 01423 break; 01424 case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : 01425 hdac->ConvHalfCpltCallbackCh2 = pCallback; 01426 break; 01427 case HAL_DAC_CH2_ERROR_ID : 01428 hdac->ErrorCallbackCh2 = pCallback; 01429 break; 01430 case HAL_DAC_CH2_UNDERRUN_CB_ID : 01431 hdac->DMAUnderrunCallbackCh2 = pCallback; 01432 break; 01433 case HAL_DAC_MSP_INIT_CB_ID : 01434 hdac->MspInitCallback = pCallback; 01435 break; 01436 case HAL_DAC_MSP_DEINIT_CB_ID : 01437 hdac->MspDeInitCallback = pCallback; 01438 break; 01439 default : 01440 /* Update the error code */ 01441 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 01442 /* update return status */ 01443 status = HAL_ERROR; 01444 break; 01445 } 01446 } 01447 else if (hdac->State == HAL_DAC_STATE_RESET) 01448 { 01449 switch (CallbackID) 01450 { 01451 case HAL_DAC_MSP_INIT_CB_ID : 01452 hdac->MspInitCallback = pCallback; 01453 break; 01454 case HAL_DAC_MSP_DEINIT_CB_ID : 01455 hdac->MspDeInitCallback = pCallback; 01456 break; 01457 default : 01458 /* Update the error code */ 01459 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 01460 /* update return status */ 01461 status = HAL_ERROR; 01462 break; 01463 } 01464 } 01465 else 01466 { 01467 /* Update the error code */ 01468 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 01469 /* update return status */ 01470 status = HAL_ERROR; 01471 } 01472 01473 /* Release Lock */ 01474 __HAL_UNLOCK(hdac); 01475 return status; 01476 } 01477 01478 /** 01479 * @brief Unregister a User DAC Callback 01480 * DAC Callback is redirected to the weak (surcharged) predefined callback 01481 * @param hdac DAC handle 01482 * @param CallbackID ID of the callback to be unregistered 01483 * This parameter can be one of the following values: 01484 * @arg @ref HAL_DAC_CH1_COMPLETE_CB_ID DAC CH1 tranfer Complete Callback ID 01485 * @arg @ref HAL_DAC_CH1_HALF_COMPLETE_CB_ID DAC CH1 Half Complete Callback ID 01486 * @arg @ref HAL_DAC_CH1_ERROR_ID DAC CH1 Error Callback ID 01487 * @arg @ref HAL_DAC_CH1_UNDERRUN_CB_ID DAC CH1 UnderRun Callback ID 01488 * @arg @ref HAL_DAC_CH2_COMPLETE_CB_ID DAC CH2 Complete Callback ID 01489 * @arg @ref HAL_DAC_CH2_HALF_COMPLETE_CB_ID DAC CH2 Half Complete Callback ID 01490 * @arg @ref HAL_DAC_CH2_ERROR_ID DAC CH2 Error Callback ID 01491 * @arg @ref HAL_DAC_CH2_UNDERRUN_CB_ID DAC CH2 UnderRun Callback ID 01492 * @arg @ref HAL_DAC_MSP_INIT_CB_ID DAC MSP Init Callback ID 01493 * @arg @ref HAL_DAC_MSP_DEINIT_CB_ID DAC MSP DeInit Callback ID 01494 * @arg @ref HAL_DAC_ALL_CB_ID DAC All callbacks 01495 * @retval status 01496 */ 01497 HAL_StatusTypeDef HAL_DAC_UnRegisterCallback (DAC_HandleTypeDef *hdac, HAL_DAC_CallbackIDTypeDef CallbackID) 01498 { 01499 HAL_StatusTypeDef status = HAL_OK; 01500 01501 /* Process locked */ 01502 __HAL_LOCK(hdac); 01503 01504 if(hdac->State == HAL_DAC_STATE_READY) 01505 { 01506 switch (CallbackID) 01507 { 01508 case HAL_DAC_CH1_COMPLETE_CB_ID : 01509 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; 01510 break; 01511 case HAL_DAC_CH1_HALF_COMPLETE_CB_ID : 01512 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; 01513 break; 01514 case HAL_DAC_CH1_ERROR_ID : 01515 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; 01516 break; 01517 case HAL_DAC_CH1_UNDERRUN_CB_ID : 01518 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; 01519 break; 01520 case HAL_DAC_CH2_COMPLETE_CB_ID : 01521 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; 01522 break; 01523 case HAL_DAC_CH2_HALF_COMPLETE_CB_ID : 01524 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; 01525 break; 01526 case HAL_DAC_CH2_ERROR_ID : 01527 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; 01528 break; 01529 case HAL_DAC_CH2_UNDERRUN_CB_ID : 01530 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; 01531 break; 01532 case HAL_DAC_MSP_INIT_CB_ID : 01533 hdac->MspInitCallback = HAL_DAC_MspInit; 01534 break; 01535 case HAL_DAC_MSP_DEINIT_CB_ID : 01536 hdac->MspDeInitCallback = HAL_DAC_MspDeInit; 01537 break; 01538 case HAL_DAC_ALL_CB_ID : 01539 hdac->ConvCpltCallbackCh1 = HAL_DAC_ConvCpltCallbackCh1; 01540 hdac->ConvHalfCpltCallbackCh1 = HAL_DAC_ConvHalfCpltCallbackCh1; 01541 hdac->ErrorCallbackCh1 = HAL_DAC_ErrorCallbackCh1; 01542 hdac->DMAUnderrunCallbackCh1 = HAL_DAC_DMAUnderrunCallbackCh1; 01543 hdac->ConvCpltCallbackCh2 = HAL_DACEx_ConvCpltCallbackCh2; 01544 hdac->ConvHalfCpltCallbackCh2 = HAL_DACEx_ConvHalfCpltCallbackCh2; 01545 hdac->ErrorCallbackCh2 = HAL_DACEx_ErrorCallbackCh2; 01546 hdac->DMAUnderrunCallbackCh2 = HAL_DACEx_DMAUnderrunCallbackCh2; 01547 hdac->MspInitCallback = HAL_DAC_MspInit; 01548 hdac->MspDeInitCallback = HAL_DAC_MspDeInit; 01549 break; 01550 default : 01551 /* Update the error code */ 01552 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 01553 /* update return status */ 01554 status = HAL_ERROR; 01555 break; 01556 } 01557 } 01558 else if (hdac->State == HAL_DAC_STATE_RESET) 01559 { 01560 switch (CallbackID) 01561 { 01562 case HAL_DAC_MSP_INIT_CB_ID : 01563 hdac->MspInitCallback = HAL_DAC_MspInit; 01564 break; 01565 case HAL_DAC_MSP_DEINIT_CB_ID : 01566 hdac->MspDeInitCallback = HAL_DAC_MspDeInit; 01567 break; 01568 default : 01569 /* Update the error code */ 01570 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 01571 /* update return status */ 01572 status = HAL_ERROR; 01573 break; 01574 } 01575 } 01576 else 01577 { 01578 /* Update the error code */ 01579 hdac->ErrorCode |= HAL_DAC_ERROR_INVALID_CALLBACK; 01580 /* update return status */ 01581 status = HAL_ERROR; 01582 } 01583 01584 /* Release Lock */ 01585 __HAL_UNLOCK(hdac); 01586 return status; 01587 } 01588 #endif /* USE_HAL_DAC_REGISTER_CALLBACKS */ 01589 01590 01591 /** 01592 * @} 01593 */ 01594 01595 /** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions 01596 * @brief Peripheral State and Errors functions 01597 * 01598 @verbatim 01599 ============================================================================== 01600 ##### Peripheral State and Errors functions ##### 01601 ============================================================================== 01602 [..] 01603 This subsection provides functions allowing to 01604 (+) Check the DAC state. 01605 (+) Check the DAC Errors. 01606 01607 @endverbatim 01608 * @{ 01609 */ 01610 01611 /** 01612 * @brief return the DAC handle state 01613 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 01614 * the configuration information for the specified DAC. 01615 * @retval HAL state 01616 */ 01617 HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac) 01618 { 01619 /* Return DAC handle state */ 01620 return hdac->State; 01621 } 01622 01623 01624 /** 01625 * @brief Return the DAC error code 01626 * @param hdac: pointer to a DAC_HandleTypeDef structure that contains 01627 * the configuration information for the specified DAC. 01628 * @retval DAC Error Code 01629 */ 01630 uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac) 01631 { 01632 return hdac->ErrorCode; 01633 } 01634 01635 /** 01636 * @} 01637 */ 01638 01639 /** 01640 * @} 01641 */ 01642 01643 /** @addtogroup DAC_Private_Functions 01644 * @{ 01645 */ 01646 01647 /** 01648 * @brief DMA conversion complete callback. 01649 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains 01650 * the configuration information for the specified DMA module. 01651 * @retval None 01652 */ 01653 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma) 01654 { 01655 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01656 01657 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 01658 hdac->ConvCpltCallbackCh1(hdac); 01659 #else 01660 HAL_DAC_ConvCpltCallbackCh1(hdac); 01661 #endif 01662 01663 hdac->State= HAL_DAC_STATE_READY; 01664 } 01665 01666 /** 01667 * @brief DMA half transfer complete callback. 01668 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains 01669 * the configuration information for the specified DMA module. 01670 * @retval None 01671 */ 01672 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma) 01673 { 01674 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01675 01676 /* Conversion complete callback */ 01677 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 01678 hdac->ConvHalfCpltCallbackCh1(hdac); 01679 #else 01680 HAL_DAC_ConvHalfCpltCallbackCh1(hdac); 01681 #endif 01682 } 01683 01684 /** 01685 * @brief DMA error callback 01686 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains 01687 * the configuration information for the specified DMA module. 01688 * @retval None 01689 */ 01690 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma) 01691 { 01692 DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 01693 01694 /* Set DAC error code to DMA error */ 01695 hdac->ErrorCode |= HAL_DAC_ERROR_DMA; 01696 01697 #if (USE_HAL_DAC_REGISTER_CALLBACKS == 1) 01698 hdac->ErrorCallbackCh1(hdac); 01699 #else 01700 HAL_DAC_ErrorCallbackCh1(hdac); 01701 #endif 01702 01703 hdac->State= HAL_DAC_STATE_READY; 01704 } 01705 01706 /** 01707 * @} 01708 */ 01709 01710 #endif /* HAL_DAC_MODULE_ENABLED */ 01711 01712 01713 /** 01714 * @} 01715 */ 01716 01717 /** 01718 * @} 01719 */ 01720 01721 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/