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STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_cortex.h 00004 * @author MCD Application Team 00005 * @brief Header file of CORTEX HAL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32L4xx_HAL_CORTEX_H 00038 #define __STM32L4xx_HAL_CORTEX_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32l4xx_hal_def.h" 00046 00047 /** @addtogroup STM32L4xx_HAL_Driver 00048 * @{ 00049 */ 00050 00051 /** @defgroup CORTEX CORTEX 00052 * @{ 00053 */ 00054 00055 /* Exported types ------------------------------------------------------------*/ 00056 /** @defgroup CORTEX_Exported_Types CORTEX Exported Types 00057 * @{ 00058 */ 00059 00060 #if (__MPU_PRESENT == 1) 00061 /** @defgroup CORTEX_MPU_Region_Initialization_Structure_definition MPU Region Initialization Structure Definition 00062 * @{ 00063 */ 00064 typedef struct 00065 { 00066 uint8_t Enable; /*!< Specifies the status of the region. 00067 This parameter can be a value of @ref CORTEX_MPU_Region_Enable */ 00068 uint8_t Number; /*!< Specifies the number of the region to protect. 00069 This parameter can be a value of @ref CORTEX_MPU_Region_Number */ 00070 uint32_t BaseAddress; /*!< Specifies the base address of the region to protect. */ 00071 uint8_t Size; /*!< Specifies the size of the region to protect. 00072 This parameter can be a value of @ref CORTEX_MPU_Region_Size */ 00073 uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. 00074 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ 00075 uint8_t TypeExtField; /*!< Specifies the TEX field level. 00076 This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ 00077 uint8_t AccessPermission; /*!< Specifies the region access permission type. 00078 This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ 00079 uint8_t DisableExec; /*!< Specifies the instruction access status. 00080 This parameter can be a value of @ref CORTEX_MPU_Instruction_Access */ 00081 uint8_t IsShareable; /*!< Specifies the shareability status of the protected region. 00082 This parameter can be a value of @ref CORTEX_MPU_Access_Shareable */ 00083 uint8_t IsCacheable; /*!< Specifies the cacheable status of the region protected. 00084 This parameter can be a value of @ref CORTEX_MPU_Access_Cacheable */ 00085 uint8_t IsBufferable; /*!< Specifies the bufferable status of the protected region. 00086 This parameter can be a value of @ref CORTEX_MPU_Access_Bufferable */ 00087 }MPU_Region_InitTypeDef; 00088 /** 00089 * @} 00090 */ 00091 #endif /* __MPU_PRESENT */ 00092 00093 /** 00094 * @} 00095 */ 00096 00097 /* Exported constants --------------------------------------------------------*/ 00098 00099 /** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants 00100 * @{ 00101 */ 00102 00103 /** @defgroup CORTEX_Preemption_Priority_Group CORTEX Preemption Priority Group 00104 * @{ 00105 */ 00106 #define NVIC_PRIORITYGROUP_0 ((uint32_t)0x00000007) /*!< 0 bit for pre-emption priority, 00107 4 bits for subpriority */ 00108 #define NVIC_PRIORITYGROUP_1 ((uint32_t)0x00000006) /*!< 1 bit for pre-emption priority, 00109 3 bits for subpriority */ 00110 #define NVIC_PRIORITYGROUP_2 ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority, 00111 2 bits for subpriority */ 00112 #define NVIC_PRIORITYGROUP_3 ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority, 00113 1 bit for subpriority */ 00114 #define NVIC_PRIORITYGROUP_4 ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority, 00115 0 bit for subpriority */ 00116 /** 00117 * @} 00118 */ 00119 00120 /** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source 00121 * @{ 00122 */ 00123 #define SYSTICK_CLKSOURCE_HCLK_DIV8 ((uint32_t)0x00000000) 00124 #define SYSTICK_CLKSOURCE_HCLK ((uint32_t)0x00000004) 00125 /** 00126 * @} 00127 */ 00128 00129 #if (__MPU_PRESENT == 1) 00130 /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control 00131 * @{ 00132 */ 00133 #define MPU_HFNMI_PRIVDEF_NONE ((uint32_t)0x00000000) 00134 #define MPU_HARDFAULT_NMI ((uint32_t)0x00000002) 00135 #define MPU_PRIVILEGED_DEFAULT ((uint32_t)0x00000004) 00136 #define MPU_HFNMI_PRIVDEF ((uint32_t)0x00000006) 00137 /** 00138 * @} 00139 */ 00140 00141 /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable 00142 * @{ 00143 */ 00144 #define MPU_REGION_ENABLE ((uint8_t)0x01) 00145 #define MPU_REGION_DISABLE ((uint8_t)0x00) 00146 /** 00147 * @} 00148 */ 00149 00150 /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access 00151 * @{ 00152 */ 00153 #define MPU_INSTRUCTION_ACCESS_ENABLE ((uint8_t)0x00) 00154 #define MPU_INSTRUCTION_ACCESS_DISABLE ((uint8_t)0x01) 00155 /** 00156 * @} 00157 */ 00158 00159 /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable 00160 * @{ 00161 */ 00162 #define MPU_ACCESS_SHAREABLE ((uint8_t)0x01) 00163 #define MPU_ACCESS_NOT_SHAREABLE ((uint8_t)0x00) 00164 /** 00165 * @} 00166 */ 00167 00168 /** @defgroup CORTEX_MPU_Access_Cacheable CORTEX MPU Instruction Access Cacheable 00169 * @{ 00170 */ 00171 #define MPU_ACCESS_CACHEABLE ((uint8_t)0x01) 00172 #define MPU_ACCESS_NOT_CACHEABLE ((uint8_t)0x00) 00173 /** 00174 * @} 00175 */ 00176 00177 /** @defgroup CORTEX_MPU_Access_Bufferable CORTEX MPU Instruction Access Bufferable 00178 * @{ 00179 */ 00180 #define MPU_ACCESS_BUFFERABLE ((uint8_t)0x01) 00181 #define MPU_ACCESS_NOT_BUFFERABLE ((uint8_t)0x00) 00182 /** 00183 * @} 00184 */ 00185 00186 /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels 00187 * @{ 00188 */ 00189 #define MPU_TEX_LEVEL0 ((uint8_t)0x00) 00190 #define MPU_TEX_LEVEL1 ((uint8_t)0x01) 00191 #define MPU_TEX_LEVEL2 ((uint8_t)0x02) 00192 /** 00193 * @} 00194 */ 00195 00196 /** @defgroup CORTEX_MPU_Region_Size CORTEX MPU Region Size 00197 * @{ 00198 */ 00199 #define MPU_REGION_SIZE_32B ((uint8_t)0x04) 00200 #define MPU_REGION_SIZE_64B ((uint8_t)0x05) 00201 #define MPU_REGION_SIZE_128B ((uint8_t)0x06) 00202 #define MPU_REGION_SIZE_256B ((uint8_t)0x07) 00203 #define MPU_REGION_SIZE_512B ((uint8_t)0x08) 00204 #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) 00205 #define MPU_REGION_SIZE_2KB ((uint8_t)0x0A) 00206 #define MPU_REGION_SIZE_4KB ((uint8_t)0x0B) 00207 #define MPU_REGION_SIZE_8KB ((uint8_t)0x0C) 00208 #define MPU_REGION_SIZE_16KB ((uint8_t)0x0D) 00209 #define MPU_REGION_SIZE_32KB ((uint8_t)0x0E) 00210 #define MPU_REGION_SIZE_64KB ((uint8_t)0x0F) 00211 #define MPU_REGION_SIZE_128KB ((uint8_t)0x10) 00212 #define MPU_REGION_SIZE_256KB ((uint8_t)0x11) 00213 #define MPU_REGION_SIZE_512KB ((uint8_t)0x12) 00214 #define MPU_REGION_SIZE_1MB ((uint8_t)0x13) 00215 #define MPU_REGION_SIZE_2MB ((uint8_t)0x14) 00216 #define MPU_REGION_SIZE_4MB ((uint8_t)0x15) 00217 #define MPU_REGION_SIZE_8MB ((uint8_t)0x16) 00218 #define MPU_REGION_SIZE_16MB ((uint8_t)0x17) 00219 #define MPU_REGION_SIZE_32MB ((uint8_t)0x18) 00220 #define MPU_REGION_SIZE_64MB ((uint8_t)0x19) 00221 #define MPU_REGION_SIZE_128MB ((uint8_t)0x1A) 00222 #define MPU_REGION_SIZE_256MB ((uint8_t)0x1B) 00223 #define MPU_REGION_SIZE_512MB ((uint8_t)0x1C) 00224 #define MPU_REGION_SIZE_1GB ((uint8_t)0x1D) 00225 #define MPU_REGION_SIZE_2GB ((uint8_t)0x1E) 00226 #define MPU_REGION_SIZE_4GB ((uint8_t)0x1F) 00227 /** 00228 * @} 00229 */ 00230 00231 /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes 00232 * @{ 00233 */ 00234 #define MPU_REGION_NO_ACCESS ((uint8_t)0x00) 00235 #define MPU_REGION_PRIV_RW ((uint8_t)0x01) 00236 #define MPU_REGION_PRIV_RW_URO ((uint8_t)0x02) 00237 #define MPU_REGION_FULL_ACCESS ((uint8_t)0x03) 00238 #define MPU_REGION_PRIV_RO ((uint8_t)0x05) 00239 #define MPU_REGION_PRIV_RO_URO ((uint8_t)0x06) 00240 /** 00241 * @} 00242 */ 00243 00244 /** @defgroup CORTEX_MPU_Region_Number CORTEX MPU Region Number 00245 * @{ 00246 */ 00247 #define MPU_REGION_NUMBER0 ((uint8_t)0x00) 00248 #define MPU_REGION_NUMBER1 ((uint8_t)0x01) 00249 #define MPU_REGION_NUMBER2 ((uint8_t)0x02) 00250 #define MPU_REGION_NUMBER3 ((uint8_t)0x03) 00251 #define MPU_REGION_NUMBER4 ((uint8_t)0x04) 00252 #define MPU_REGION_NUMBER5 ((uint8_t)0x05) 00253 #define MPU_REGION_NUMBER6 ((uint8_t)0x06) 00254 #define MPU_REGION_NUMBER7 ((uint8_t)0x07) 00255 /** 00256 * @} 00257 */ 00258 #endif /* __MPU_PRESENT */ 00259 00260 /** 00261 * @} 00262 */ 00263 00264 /* Exported macros -----------------------------------------------------------*/ 00265 /** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros 00266 * @{ 00267 */ 00268 00269 /** 00270 * @} 00271 */ 00272 00273 /* Exported functions --------------------------------------------------------*/ 00274 /** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions 00275 * @{ 00276 */ 00277 00278 /** @defgroup CORTEX_Exported_Functions_Group1 Initialization and Configuration functions 00279 * @brief Initialization and Configuration functions 00280 * @{ 00281 */ 00282 /* Initialization and Configuration functions *****************************/ 00283 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup); 00284 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); 00285 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn); 00286 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn); 00287 void HAL_NVIC_SystemReset(void); 00288 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb); 00289 00290 /** 00291 * @} 00292 */ 00293 00294 /** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions 00295 * @brief Cortex control functions 00296 * @{ 00297 */ 00298 /* Peripheral Control functions ***********************************************/ 00299 uint32_t HAL_NVIC_GetPriorityGrouping(void); 00300 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority); 00301 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn); 00302 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn); 00303 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn); 00304 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn); 00305 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource); 00306 void HAL_SYSTICK_IRQHandler(void); 00307 void HAL_SYSTICK_Callback(void); 00308 00309 #if (__MPU_PRESENT == 1) 00310 void HAL_MPU_Enable(uint32_t MPU_Control); 00311 void HAL_MPU_Disable(void); 00312 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); 00313 #endif /* __MPU_PRESENT */ 00314 /** 00315 * @} 00316 */ 00317 00318 /** 00319 * @} 00320 */ 00321 00322 /* Private types -------------------------------------------------------------*/ 00323 /* Private variables ---------------------------------------------------------*/ 00324 /* Private constants ---------------------------------------------------------*/ 00325 /* Private macros ------------------------------------------------------------*/ 00326 /** @defgroup CORTEX_Private_Macros CORTEX Private Macros 00327 * @{ 00328 */ 00329 #define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \ 00330 ((GROUP) == NVIC_PRIORITYGROUP_1) || \ 00331 ((GROUP) == NVIC_PRIORITYGROUP_2) || \ 00332 ((GROUP) == NVIC_PRIORITYGROUP_3) || \ 00333 ((GROUP) == NVIC_PRIORITYGROUP_4)) 00334 00335 #define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 00336 00337 #define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10) 00338 00339 #define IS_NVIC_DEVICE_IRQ(IRQ) ((IRQ) >= 0x00) 00340 00341 #define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \ 00342 ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8)) 00343 00344 #if (__MPU_PRESENT == 1) 00345 #define IS_MPU_REGION_ENABLE(STATE) (((STATE) == MPU_REGION_ENABLE) || \ 00346 ((STATE) == MPU_REGION_DISABLE)) 00347 00348 #define IS_MPU_INSTRUCTION_ACCESS(STATE) (((STATE) == MPU_INSTRUCTION_ACCESS_ENABLE) || \ 00349 ((STATE) == MPU_INSTRUCTION_ACCESS_DISABLE)) 00350 00351 #define IS_MPU_ACCESS_SHAREABLE(STATE) (((STATE) == MPU_ACCESS_SHAREABLE) || \ 00352 ((STATE) == MPU_ACCESS_NOT_SHAREABLE)) 00353 00354 #define IS_MPU_ACCESS_CACHEABLE(STATE) (((STATE) == MPU_ACCESS_CACHEABLE) || \ 00355 ((STATE) == MPU_ACCESS_NOT_CACHEABLE)) 00356 00357 #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ 00358 ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) 00359 00360 #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ 00361 ((TYPE) == MPU_TEX_LEVEL1) || \ 00362 ((TYPE) == MPU_TEX_LEVEL2)) 00363 00364 #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ 00365 ((TYPE) == MPU_REGION_PRIV_RW) || \ 00366 ((TYPE) == MPU_REGION_PRIV_RW_URO) || \ 00367 ((TYPE) == MPU_REGION_FULL_ACCESS) || \ 00368 ((TYPE) == MPU_REGION_PRIV_RO) || \ 00369 ((TYPE) == MPU_REGION_PRIV_RO_URO)) 00370 00371 #define IS_MPU_REGION_NUMBER(NUMBER) (((NUMBER) == MPU_REGION_NUMBER0) || \ 00372 ((NUMBER) == MPU_REGION_NUMBER1) || \ 00373 ((NUMBER) == MPU_REGION_NUMBER2) || \ 00374 ((NUMBER) == MPU_REGION_NUMBER3) || \ 00375 ((NUMBER) == MPU_REGION_NUMBER4) || \ 00376 ((NUMBER) == MPU_REGION_NUMBER5) || \ 00377 ((NUMBER) == MPU_REGION_NUMBER6) || \ 00378 ((NUMBER) == MPU_REGION_NUMBER7)) 00379 00380 #define IS_MPU_REGION_SIZE(SIZE) (((SIZE) == MPU_REGION_SIZE_32B) || \ 00381 ((SIZE) == MPU_REGION_SIZE_64B) || \ 00382 ((SIZE) == MPU_REGION_SIZE_128B) || \ 00383 ((SIZE) == MPU_REGION_SIZE_256B) || \ 00384 ((SIZE) == MPU_REGION_SIZE_512B) || \ 00385 ((SIZE) == MPU_REGION_SIZE_1KB) || \ 00386 ((SIZE) == MPU_REGION_SIZE_2KB) || \ 00387 ((SIZE) == MPU_REGION_SIZE_4KB) || \ 00388 ((SIZE) == MPU_REGION_SIZE_8KB) || \ 00389 ((SIZE) == MPU_REGION_SIZE_16KB) || \ 00390 ((SIZE) == MPU_REGION_SIZE_32KB) || \ 00391 ((SIZE) == MPU_REGION_SIZE_64KB) || \ 00392 ((SIZE) == MPU_REGION_SIZE_128KB) || \ 00393 ((SIZE) == MPU_REGION_SIZE_256KB) || \ 00394 ((SIZE) == MPU_REGION_SIZE_512KB) || \ 00395 ((SIZE) == MPU_REGION_SIZE_1MB) || \ 00396 ((SIZE) == MPU_REGION_SIZE_2MB) || \ 00397 ((SIZE) == MPU_REGION_SIZE_4MB) || \ 00398 ((SIZE) == MPU_REGION_SIZE_8MB) || \ 00399 ((SIZE) == MPU_REGION_SIZE_16MB) || \ 00400 ((SIZE) == MPU_REGION_SIZE_32MB) || \ 00401 ((SIZE) == MPU_REGION_SIZE_64MB) || \ 00402 ((SIZE) == MPU_REGION_SIZE_128MB) || \ 00403 ((SIZE) == MPU_REGION_SIZE_256MB) || \ 00404 ((SIZE) == MPU_REGION_SIZE_512MB) || \ 00405 ((SIZE) == MPU_REGION_SIZE_1GB) || \ 00406 ((SIZE) == MPU_REGION_SIZE_2GB) || \ 00407 ((SIZE) == MPU_REGION_SIZE_4GB)) 00408 00409 #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FF) 00410 #endif /* __MPU_PRESENT */ 00411 00412 /** 00413 * @} 00414 */ 00415 00416 /* Private functions ---------------------------------------------------------*/ 00417 00418 /** 00419 * @} 00420 */ 00421 00422 /** 00423 * @} 00424 */ 00425 00426 #ifdef __cplusplus 00427 } 00428 #endif 00429 00430 #endif /* __STM32L4xx_HAL_CORTEX_H */ 00431 00432 00433 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1