STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_cortex.c 00004 * @author MCD Application Team 00005 * @brief CORTEX HAL module driver. 00006 * This file provides firmware functions to manage the following 00007 * functionalities of the CORTEX: 00008 * + Initialization and Configuration functions 00009 * + Peripheral Control functions 00010 * 00011 @verbatim 00012 ============================================================================== 00013 ##### How to use this driver ##### 00014 ============================================================================== 00015 00016 [..] 00017 *** How to configure Interrupts using CORTEX HAL driver *** 00018 =========================================================== 00019 [..] 00020 This section provides functions allowing to configure the NVIC interrupts (IRQ). 00021 The Cortex-M4 exceptions are managed by CMSIS functions. 00022 00023 (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping() function. 00024 (#) Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority(). 00025 (#) Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ(). 00026 00027 -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. 00028 The pending IRQ priority will be managed only by the sub priority. 00029 00030 -@- IRQ priority order (sorted by highest to lowest priority): 00031 (+@) Lowest pre-emption priority 00032 (+@) Lowest sub priority 00033 (+@) Lowest hardware priority (IRQ number) 00034 00035 [..] 00036 *** How to configure SysTick using CORTEX HAL driver *** 00037 ======================================================== 00038 [..] 00039 Setup SysTick Timer for time base. 00040 00041 (+) The HAL_SYSTICK_Config() function calls the SysTick_Config() function which 00042 is a CMSIS function that: 00043 (++) Configures the SysTick Reload register with value passed as function parameter. 00044 (++) Configures the SysTick IRQ priority to the lowest value (0x0F). 00045 (++) Resets the SysTick Counter register. 00046 (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK). 00047 (++) Enables the SysTick Interrupt. 00048 (++) Starts the SysTick Counter. 00049 00050 (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro 00051 __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the 00052 HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined 00053 inside the stm32l4xx_hal_cortex.h file. 00054 00055 (+) You can change the SysTick IRQ priority by calling the 00056 HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 00057 call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function. 00058 00059 (+) To adjust the SysTick time base, use the following formula: 00060 00061 Reload Value = SysTick Counter Clock (Hz) x Desired Time base (s) 00062 (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function 00063 (++) Reload Value should not exceed 0xFFFFFF 00064 00065 @endverbatim 00066 ****************************************************************************** 00067 00068 The table below gives the allowed values of the pre-emption priority and subpriority according 00069 to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function. 00070 00071 ========================================================================================================================== 00072 NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description 00073 ========================================================================================================================== 00074 NVIC_PRIORITYGROUP_0 | 0 | 0-15 | 0 bit for pre-emption priority 00075 | | | 4 bits for subpriority 00076 -------------------------------------------------------------------------------------------------------------------------- 00077 NVIC_PRIORITYGROUP_1 | 0-1 | 0-7 | 1 bit for pre-emption priority 00078 | | | 3 bits for subpriority 00079 -------------------------------------------------------------------------------------------------------------------------- 00080 NVIC_PRIORITYGROUP_2 | 0-3 | 0-3 | 2 bits for pre-emption priority 00081 | | | 2 bits for subpriority 00082 -------------------------------------------------------------------------------------------------------------------------- 00083 NVIC_PRIORITYGROUP_3 | 0-7 | 0-1 | 3 bits for pre-emption priority 00084 | | | 1 bit for subpriority 00085 -------------------------------------------------------------------------------------------------------------------------- 00086 NVIC_PRIORITYGROUP_4 | 0-15 | 0 | 4 bits for pre-emption priority 00087 | | | 0 bit for subpriority 00088 ========================================================================================================================== 00089 00090 ****************************************************************************** 00091 * @attention 00092 * 00093 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00094 * 00095 * Redistribution and use in source and binary forms, with or without modification, 00096 * are permitted provided that the following conditions are met: 00097 * 1. Redistributions of source code must retain the above copyright notice, 00098 * this list of conditions and the following disclaimer. 00099 * 2. Redistributions in binary form must reproduce the above copyright notice, 00100 * this list of conditions and the following disclaimer in the documentation 00101 * and/or other materials provided with the distribution. 00102 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00103 * may be used to endorse or promote products derived from this software 00104 * without specific prior written permission. 00105 * 00106 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00107 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00108 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00109 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00110 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00111 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00112 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00113 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00114 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00115 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00116 * 00117 ****************************************************************************** 00118 */ 00119 00120 /* Includes ------------------------------------------------------------------*/ 00121 #include "stm32l4xx_hal.h" 00122 00123 /** @addtogroup STM32L4xx_HAL_Driver 00124 * @{ 00125 */ 00126 00127 /** @addtogroup CORTEX 00128 * @{ 00129 */ 00130 00131 #ifdef HAL_CORTEX_MODULE_ENABLED 00132 00133 /* Private types -------------------------------------------------------------*/ 00134 /* Private variables ---------------------------------------------------------*/ 00135 /* Private constants ---------------------------------------------------------*/ 00136 /* Private macros ------------------------------------------------------------*/ 00137 /* Private functions ---------------------------------------------------------*/ 00138 /* Exported functions --------------------------------------------------------*/ 00139 00140 /** @addtogroup CORTEX_Exported_Functions 00141 * @{ 00142 */ 00143 00144 00145 /** @addtogroup CORTEX_Exported_Functions_Group1 00146 * @brief Initialization and Configuration functions 00147 * 00148 @verbatim 00149 ============================================================================== 00150 ##### Initialization and Configuration functions ##### 00151 ============================================================================== 00152 [..] 00153 This section provides the CORTEX HAL driver functions allowing to configure Interrupts 00154 SysTick functionalities 00155 00156 @endverbatim 00157 * @{ 00158 */ 00159 00160 00161 /** 00162 * @brief Set the priority grouping field (pre-emption priority and subpriority) 00163 * using the required unlock sequence. 00164 * @param PriorityGroup: The priority grouping bits length. 00165 * This parameter can be one of the following values: 00166 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 00167 * 4 bits for subpriority 00168 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 00169 * 3 bits for subpriority 00170 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 00171 * 2 bits for subpriority 00172 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 00173 * 1 bit for subpriority 00174 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 00175 * 0 bit for subpriority 00176 * @note When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 00177 * The pending IRQ priority will be managed only by the subpriority. 00178 * @retval None 00179 */ 00180 void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup) 00181 { 00182 /* Check the parameters */ 00183 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); 00184 00185 /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */ 00186 NVIC_SetPriorityGrouping(PriorityGroup); 00187 } 00188 00189 /** 00190 * @brief Set the priority of an interrupt. 00191 * @param IRQn: External interrupt number. 00192 * This parameter can be an enumerator of IRQn_Type enumeration 00193 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) 00194 * @param PreemptPriority: The pre-emption priority for the IRQn channel. 00195 * This parameter can be a value between 0 and 15 00196 * A lower priority value indicates a higher priority 00197 * @param SubPriority: the subpriority level for the IRQ channel. 00198 * This parameter can be a value between 0 and 15 00199 * A lower priority value indicates a higher priority. 00200 * @retval None 00201 */ 00202 void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) 00203 { 00204 uint32_t prioritygroup = 0x00; 00205 00206 /* Check the parameters */ 00207 assert_param(IS_NVIC_SUB_PRIORITY(SubPriority)); 00208 assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority)); 00209 00210 prioritygroup = NVIC_GetPriorityGrouping(); 00211 00212 NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority)); 00213 } 00214 00215 /** 00216 * @brief Enable a device specific interrupt in the NVIC interrupt controller. 00217 * @note To configure interrupts priority correctly, the NVIC_PriorityGroupConfig() 00218 * function should be called before. 00219 * @param IRQn External interrupt number. 00220 * This parameter can be an enumerator of IRQn_Type enumeration 00221 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) 00222 * @retval None 00223 */ 00224 void HAL_NVIC_EnableIRQ(IRQn_Type IRQn) 00225 { 00226 /* Check the parameters */ 00227 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00228 00229 /* Enable interrupt */ 00230 NVIC_EnableIRQ(IRQn); 00231 } 00232 00233 /** 00234 * @brief Disable a device specific interrupt in the NVIC interrupt controller. 00235 * @param IRQn External interrupt number. 00236 * This parameter can be an enumerator of IRQn_Type enumeration 00237 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) 00238 * @retval None 00239 */ 00240 void HAL_NVIC_DisableIRQ(IRQn_Type IRQn) 00241 { 00242 /* Check the parameters */ 00243 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00244 00245 /* Disable interrupt */ 00246 NVIC_DisableIRQ(IRQn); 00247 } 00248 00249 /** 00250 * @brief Initiate a system reset request to reset the MCU. 00251 * @retval None 00252 */ 00253 void HAL_NVIC_SystemReset(void) 00254 { 00255 /* System Reset */ 00256 NVIC_SystemReset(); 00257 } 00258 00259 /** 00260 * @brief Initialize the System Timer with interrupt enabled and start the System Tick Timer (SysTick): 00261 * Counter is in free running mode to generate periodic interrupts. 00262 * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. 00263 * @retval status: - 0 Function succeeded. 00264 * - 1 Function failed. 00265 */ 00266 uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb) 00267 { 00268 return SysTick_Config(TicksNumb); 00269 } 00270 /** 00271 * @} 00272 */ 00273 00274 /** @addtogroup CORTEX_Exported_Functions_Group2 00275 * @brief Cortex control functions 00276 * 00277 @verbatim 00278 ============================================================================== 00279 ##### Peripheral Control functions ##### 00280 ============================================================================== 00281 [..] 00282 This subsection provides a set of functions allowing to control the CORTEX 00283 (NVIC, SYSTICK, MPU) functionalities. 00284 00285 00286 @endverbatim 00287 * @{ 00288 */ 00289 00290 /** 00291 * @brief Get the priority grouping field from the NVIC Interrupt Controller. 00292 * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field) 00293 */ 00294 uint32_t HAL_NVIC_GetPriorityGrouping(void) 00295 { 00296 /* Get the PRIGROUP[10:8] field value */ 00297 return NVIC_GetPriorityGrouping(); 00298 } 00299 00300 /** 00301 * @brief Get the priority of an interrupt. 00302 * @param IRQn: External interrupt number. 00303 * This parameter can be an enumerator of IRQn_Type enumeration 00304 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) 00305 * @param PriorityGroup: the priority grouping bits length. 00306 * This parameter can be one of the following values: 00307 * @arg NVIC_PRIORITYGROUP_0: 0 bit for pre-emption priority, 00308 * 4 bits for subpriority 00309 * @arg NVIC_PRIORITYGROUP_1: 1 bit for pre-emption priority, 00310 * 3 bits for subpriority 00311 * @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority, 00312 * 2 bits for subpriority 00313 * @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority, 00314 * 1 bit for subpriority 00315 * @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority, 00316 * 0 bit for subpriority 00317 * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). 00318 * @param pSubPriority: Pointer on the Subpriority value (starting from 0). 00319 * @retval None 00320 */ 00321 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) 00322 { 00323 /* Check the parameters */ 00324 assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup)); 00325 /* Get priority for Cortex-M system or device specific interrupts */ 00326 NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority); 00327 } 00328 00329 /** 00330 * @brief Set Pending bit of an external interrupt. 00331 * @param IRQn External interrupt number 00332 * This parameter can be an enumerator of IRQn_Type enumeration 00333 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) 00334 * @retval None 00335 */ 00336 void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn) 00337 { 00338 /* Check the parameters */ 00339 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00340 00341 /* Set interrupt pending */ 00342 NVIC_SetPendingIRQ(IRQn); 00343 } 00344 00345 /** 00346 * @brief Get Pending Interrupt (read the pending register in the NVIC 00347 * and return the pending bit for the specified interrupt). 00348 * @param IRQn External interrupt number. 00349 * This parameter can be an enumerator of IRQn_Type enumeration 00350 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) 00351 * @retval status: - 0 Interrupt status is not pending. 00352 * - 1 Interrupt status is pending. 00353 */ 00354 uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn) 00355 { 00356 /* Check the parameters */ 00357 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00358 00359 /* Return 1 if pending else 0 */ 00360 return NVIC_GetPendingIRQ(IRQn); 00361 } 00362 00363 /** 00364 * @brief Clear the pending bit of an external interrupt. 00365 * @param IRQn External interrupt number. 00366 * This parameter can be an enumerator of IRQn_Type enumeration 00367 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) 00368 * @retval None 00369 */ 00370 void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn) 00371 { 00372 /* Check the parameters */ 00373 assert_param(IS_NVIC_DEVICE_IRQ(IRQn)); 00374 00375 /* Clear pending interrupt */ 00376 NVIC_ClearPendingIRQ(IRQn); 00377 } 00378 00379 /** 00380 * @brief Get active interrupt (read the active register in NVIC and return the active bit). 00381 * @param IRQn External interrupt number 00382 * This parameter can be an enumerator of IRQn_Type enumeration 00383 * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l4xxxx.h)) 00384 * @retval status: - 0 Interrupt status is not pending. 00385 * - 1 Interrupt status is pending. 00386 */ 00387 uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn) 00388 { 00389 /* Return 1 if active else 0 */ 00390 return NVIC_GetActive(IRQn); 00391 } 00392 00393 /** 00394 * @brief Configure the SysTick clock source. 00395 * @param CLKSource: specifies the SysTick clock source. 00396 * This parameter can be one of the following values: 00397 * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. 00398 * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source. 00399 * @retval None 00400 */ 00401 void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource) 00402 { 00403 /* Check the parameters */ 00404 assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource)); 00405 if (CLKSource == SYSTICK_CLKSOURCE_HCLK) 00406 { 00407 SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK; 00408 } 00409 else 00410 { 00411 SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK; 00412 } 00413 } 00414 00415 /** 00416 * @brief Handle SYSTICK interrupt request. 00417 * @retval None 00418 */ 00419 void HAL_SYSTICK_IRQHandler(void) 00420 { 00421 HAL_SYSTICK_Callback(); 00422 } 00423 00424 /** 00425 * @brief SYSTICK callback. 00426 * @retval None 00427 */ 00428 __weak void HAL_SYSTICK_Callback(void) 00429 { 00430 /* NOTE : This function should not be modified, when the callback is needed, 00431 the HAL_SYSTICK_Callback could be implemented in the user file 00432 */ 00433 } 00434 00435 #if (__MPU_PRESENT == 1) 00436 /** 00437 * @brief Disable the MPU. 00438 * @retval None 00439 */ 00440 void HAL_MPU_Disable(void) 00441 { 00442 /* Make sure outstanding transfers are done */ 00443 __DMB(); 00444 00445 /* Disable fault exceptions */ 00446 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; 00447 00448 /* Disable the MPU and clear the control register*/ 00449 MPU->CTRL = 0U; 00450 } 00451 00452 /** 00453 * @brief Enable the MPU. 00454 * @param MPU_Control: Specifies the control mode of the MPU during hard fault, 00455 * NMI, FAULTMASK and privileged accessto the default memory 00456 * This parameter can be one of the following values: 00457 * @arg MPU_HFNMI_PRIVDEF_NONE 00458 * @arg MPU_HARDFAULT_NMI 00459 * @arg MPU_PRIVILEGED_DEFAULT 00460 * @arg MPU_HFNMI_PRIVDEF 00461 * @retval None 00462 */ 00463 void HAL_MPU_Enable(uint32_t MPU_Control) 00464 { 00465 /* Enable the MPU */ 00466 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; 00467 00468 /* Enable fault exceptions */ 00469 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; 00470 00471 /* Ensure MPU settings take effects */ 00472 __DSB(); 00473 __ISB(); 00474 } 00475 00476 /** 00477 * @brief Initialize and configure the Region and the memory to be protected. 00478 * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains 00479 * the initialization and configuration information. 00480 * @retval None 00481 */ 00482 void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init) 00483 { 00484 /* Check the parameters */ 00485 assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number)); 00486 assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable)); 00487 00488 /* Set the Region number */ 00489 MPU->RNR = MPU_Init->Number; 00490 00491 if ((MPU_Init->Enable) != RESET) 00492 { 00493 /* Check the parameters */ 00494 assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec)); 00495 assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission)); 00496 assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField)); 00497 assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable)); 00498 assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable)); 00499 assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable)); 00500 assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable)); 00501 assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size)); 00502 00503 MPU->RBAR = MPU_Init->BaseAddress; 00504 MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) | 00505 ((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) | 00506 ((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) | 00507 ((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) | 00508 ((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) | 00509 ((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) | 00510 ((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) | 00511 ((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) | 00512 ((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos); 00513 } 00514 else 00515 { 00516 MPU->RBAR = 0x00; 00517 MPU->RASR = 0x00; 00518 } 00519 } 00520 #endif /* __MPU_PRESENT */ 00521 00522 /** 00523 * @} 00524 */ 00525 00526 /** 00527 * @} 00528 */ 00529 00530 #endif /* HAL_CORTEX_MODULE_ENABLED */ 00531 /** 00532 * @} 00533 */ 00534 00535 /** 00536 * @} 00537 */ 00538 00539 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/