STM32L486xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32l4xx_hal_adc.c 00004 * @author MCD Application Team 00005 * @brief This file provides firmware functions to manage the following 00006 * functionalities of the Analog to Digital Convertor (ADC) 00007 * peripheral: 00008 * + Initialization and de-initialization functions 00009 * ++ Initialization and Configuration of ADC 00010 * + Operation functions 00011 * ++ Start, stop, get result of conversions of regular 00012 * group, using 3 possible modes: polling, interruption or DMA. 00013 * + Control functions 00014 * ++ Channels configuration on regular group 00015 * ++ Analog Watchdog configuration 00016 * + State functions 00017 * ++ ADC state machine management 00018 * ++ Interrupts and flags management 00019 * Other functions (extended functions) are available in file 00020 * "stm32l4xx_hal_adc_ex.c". 00021 * 00022 @verbatim 00023 ============================================================================== 00024 ##### ADC peripheral features ##### 00025 ============================================================================== 00026 [..] 00027 (+) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution. 00028 00029 (+) Interrupt generation at the end of regular conversion and in case of 00030 analog watchdog or overrun events. 00031 00032 (+) Single and continuous conversion modes. 00033 00034 (+) Scan mode for conversion of several channels sequentially. 00035 00036 (+) Data alignment with in-built data coherency. 00037 00038 (+) Programmable sampling time (channel wise) 00039 00040 (+) External trigger (timer or EXTI) with configurable polarity 00041 00042 (+) DMA request generation for transfer of conversions data of regular group. 00043 00044 (+) Configurable delay between conversions in Dual interleaved mode. 00045 00046 (+) ADC channels selectable single/differential input. 00047 00048 (+) ADC offset shared on 4 offset instances. 00049 (+) ADC calibration 00050 00051 (+) ADC conversion of regular group. 00052 00053 (+) ADC supply requirements: 1.62 V to 3.6 V. 00054 00055 (+) ADC input range: from Vref- (connected to Vssa) to Vref+ (connected to 00056 Vdda or to an external voltage reference). 00057 00058 00059 ##### How to use this driver ##### 00060 ============================================================================== 00061 [..] 00062 00063 *** Configuration of top level parameters related to ADC *** 00064 ============================================================ 00065 [..] 00066 00067 (#) Enable the ADC interface 00068 (++) As prerequisite, ADC clock must be configured at RCC top level. 00069 00070 (++) Two clock settings are mandatory: 00071 (+++) ADC clock (core clock, also possibly conversion clock). 00072 00073 (+++) ADC clock (conversions clock). 00074 Two possible clock sources: synchronous clock derived from APB clock 00075 or asynchronous clock derived from system clock, PLLSAI1 or the PLLSAI2 00076 running up to 80MHz. 00077 00078 (+++) Example: 00079 Into HAL_ADC_MspInit() (recommended code location) or with 00080 other device clock parameters configuration: 00081 (+++) __HAL_RCC_ADC_CLK_ENABLE(); (mandatory) 00082 00083 RCC_ADCCLKSOURCE_PLL enable: (optional: if asynchronous clock selected) 00084 (+++) RCC_PeriphClkInitTypeDef RCC_PeriphClkInit; 00085 (+++) PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_ADC; 00086 (+++) PeriphClkInit.AdcClockSelection = RCC_ADCCLKSOURCE_PLL; 00087 (+++) HAL_RCCEx_PeriphCLKConfig(&PeriphClkInit); 00088 00089 (++) ADC clock source and clock prescaler are configured at ADC level with 00090 parameter "ClockPrescaler" using function HAL_ADC_Init(). 00091 00092 (#) ADC pins configuration 00093 (++) Enable the clock for the ADC GPIOs 00094 using macro __HAL_RCC_GPIOx_CLK_ENABLE() 00095 (++) Configure these ADC pins in analog mode 00096 using function HAL_GPIO_Init() 00097 00098 (#) Optionally, in case of usage of ADC with interruptions: 00099 (++) Configure the NVIC for ADC 00100 using function HAL_NVIC_EnableIRQ(ADCx_IRQn) 00101 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 00102 into the function of corresponding ADC interruption vector 00103 ADCx_IRQHandler(). 00104 00105 (#) Optionally, in case of usage of DMA: 00106 (++) Configure the DMA (DMA channel, mode normal or circular, ...) 00107 using function HAL_DMA_Init(). 00108 (++) Configure the NVIC for DMA 00109 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) 00110 (++) Insert the ADC interruption handler function HAL_ADC_IRQHandler() 00111 into the function of corresponding DMA interruption vector 00112 DMAx_Channelx_IRQHandler(). 00113 00114 *** Configuration of ADC, group regular, channels parameters *** 00115 ================================================================ 00116 [..] 00117 00118 (#) Configure the ADC parameters (resolution, data alignment, ...) 00119 and regular group parameters (conversion trigger, sequencer, ...) 00120 using function HAL_ADC_Init(). 00121 00122 (#) Configure the channels for regular group parameters (channel number, 00123 channel rank into sequencer, ..., into regular group) 00124 using function HAL_ADC_ConfigChannel(). 00125 00126 (#) Optionally, configure the analog watchdog parameters (channels 00127 monitored, thresholds, ...) 00128 using function HAL_ADC_AnalogWDGConfig(). 00129 00130 *** Execution of ADC conversions *** 00131 ==================================== 00132 [..] 00133 00134 (#) Optionally, perform an automatic ADC calibration to improve the 00135 conversion accuracy 00136 using function HAL_ADCEx_Calibration_Start(). 00137 00138 (#) ADC driver can be used among three modes: polling, interruption, 00139 transfer by DMA. 00140 00141 (++) ADC conversion by polling: 00142 (+++) Activate the ADC peripheral and start conversions 00143 using function HAL_ADC_Start() 00144 (+++) Wait for ADC conversion completion 00145 using function HAL_ADC_PollForConversion() 00146 (+++) Retrieve conversion results 00147 using function HAL_ADC_GetValue() 00148 (+++) Stop conversion and disable the ADC peripheral 00149 using function HAL_ADC_Stop() 00150 00151 (++) ADC conversion by interruption: 00152 (+++) Activate the ADC peripheral and start conversions 00153 using function HAL_ADC_Start_IT() 00154 (+++) Wait for ADC conversion completion by call of function 00155 HAL_ADC_ConvCpltCallback() 00156 (this function must be implemented in user program) 00157 (+++) Retrieve conversion results 00158 using function HAL_ADC_GetValue() 00159 (+++) Stop conversion and disable the ADC peripheral 00160 using function HAL_ADC_Stop_IT() 00161 00162 (++) ADC conversion with transfer by DMA: 00163 (+++) Activate the ADC peripheral and start conversions 00164 using function HAL_ADC_Start_DMA() 00165 (+++) Wait for ADC conversion completion by call of function 00166 HAL_ADC_ConvCpltCallback() or HAL_ADC_ConvHalfCpltCallback() 00167 (these functions must be implemented in user program) 00168 (+++) Conversion results are automatically transferred by DMA into 00169 destination variable address. 00170 (+++) Stop conversion and disable the ADC peripheral 00171 using function HAL_ADC_Stop_DMA() 00172 00173 [..] 00174 00175 (@) Callback functions must be implemented in user program: 00176 (+@) HAL_ADC_ErrorCallback() 00177 (+@) HAL_ADC_LevelOutOfWindowCallback() (callback of analog watchdog) 00178 (+@) HAL_ADC_ConvCpltCallback() 00179 (+@) HAL_ADC_ConvHalfCpltCallback 00180 00181 *** Deinitialization of ADC *** 00182 ============================================================ 00183 [..] 00184 00185 (#) Disable the ADC interface 00186 (++) ADC clock can be hard reset and disabled at RCC top level. 00187 (++) Hard reset of ADC peripherals 00188 using macro __ADCx_FORCE_RESET(), __ADCx_RELEASE_RESET(). 00189 (++) ADC clock disable 00190 using the equivalent macro/functions as configuration step. 00191 (+++) Example: 00192 Into HAL_ADC_MspDeInit() (recommended code location) or with 00193 other device clock parameters configuration: 00194 (+++) RCC_OscInitStructure.OscillatorType = RCC_OSCILLATORTYPE_HSI14; 00195 (+++) RCC_OscInitStructure.HSI14State = RCC_HSI14_OFF; (if not used for system clock) 00196 (+++) HAL_RCC_OscConfig(&RCC_OscInitStructure); 00197 00198 (#) ADC pins configuration 00199 (++) Disable the clock for the ADC GPIOs 00200 using macro __HAL_RCC_GPIOx_CLK_DISABLE() 00201 00202 (#) Optionally, in case of usage of ADC with interruptions: 00203 (++) Disable the NVIC for ADC 00204 using function HAL_NVIC_EnableIRQ(ADCx_IRQn) 00205 00206 (#) Optionally, in case of usage of DMA: 00207 (++) Deinitialize the DMA 00208 using function HAL_DMA_Init(). 00209 (++) Disable the NVIC for DMA 00210 using function HAL_NVIC_EnableIRQ(DMAx_Channelx_IRQn) 00211 00212 [..] 00213 00214 *** Callback registration *** 00215 ============================================= 00216 [..] 00217 00218 The compilation flag USE_HAL_ADC_REGISTER_CALLBACKS, when set to 1, 00219 allows the user to configure dynamically the driver callbacks. 00220 Use Functions @ref HAL_ADC_RegisterCallback() 00221 to register an interrupt callback. 00222 [..] 00223 00224 Function @ref HAL_ADC_RegisterCallback() allows to register following callbacks: 00225 (+) ConvCpltCallback : ADC conversion complete callback 00226 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback 00227 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback 00228 (+) ErrorCallback : ADC error callback 00229 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback 00230 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback 00231 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback 00232 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback 00233 (+) EndOfSamplingCallback : ADC end of sampling callback 00234 (+) MspInitCallback : ADC Msp Init callback 00235 (+) MspDeInitCallback : ADC Msp DeInit callback 00236 This function takes as parameters the HAL peripheral handle, the Callback ID 00237 and a pointer to the user callback function. 00238 [..] 00239 00240 Use function @ref HAL_ADC_UnRegisterCallback to reset a callback to the default 00241 weak function. 00242 [..] 00243 00244 @ref HAL_ADC_UnRegisterCallback takes as parameters the HAL peripheral handle, 00245 and the Callback ID. 00246 This function allows to reset following callbacks: 00247 (+) ConvCpltCallback : ADC conversion complete callback 00248 (+) ConvHalfCpltCallback : ADC conversion DMA half-transfer callback 00249 (+) LevelOutOfWindowCallback : ADC analog watchdog 1 callback 00250 (+) ErrorCallback : ADC error callback 00251 (+) InjectedConvCpltCallback : ADC group injected conversion complete callback 00252 (+) InjectedQueueOverflowCallback : ADC group injected context queue overflow callback 00253 (+) LevelOutOfWindow2Callback : ADC analog watchdog 2 callback 00254 (+) LevelOutOfWindow3Callback : ADC analog watchdog 3 callback 00255 (+) EndOfSamplingCallback : ADC end of sampling callback 00256 (+) MspInitCallback : ADC Msp Init callback 00257 (+) MspDeInitCallback : ADC Msp DeInit callback 00258 [..] 00259 00260 By default, after the @ref HAL_ADC_Init() and when the state is @ref HAL_ADC_STATE_RESET 00261 all callbacks are set to the corresponding weak functions: 00262 examples @ref HAL_ADC_ConvCpltCallback(), @ref HAL_ADC_ErrorCallback(). 00263 Exception done for MspInit and MspDeInit functions that are 00264 reset to the legacy weak functions in the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() only when 00265 these callbacks are null (not registered beforehand). 00266 [..] 00267 00268 If MspInit or MspDeInit are not null, the @ref HAL_ADC_Init()/ @ref HAL_ADC_DeInit() 00269 keep and use the user MspInit/MspDeInit callbacks (registered beforehand) whatever the state. 00270 [..] 00271 00272 Callbacks can be registered/unregistered in @ref HAL_ADC_STATE_READY state only. 00273 Exception done MspInit/MspDeInit functions that can be registered/unregistered 00274 in @ref HAL_ADC_STATE_READY or @ref HAL_ADC_STATE_RESET state, 00275 thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit. 00276 [..] 00277 00278 Then, the user first registers the MspInit/MspDeInit user callbacks 00279 using @ref HAL_ADC_RegisterCallback() before calling @ref HAL_ADC_DeInit() 00280 or @ref HAL_ADC_Init() function. 00281 [..] 00282 00283 When the compilation flag USE_HAL_ADC_REGISTER_CALLBACKS is set to 0 or 00284 not defined, the callback registration feature is not available and all callbacks 00285 are set to the corresponding weak functions. 00286 00287 @endverbatim 00288 ****************************************************************************** 00289 * @attention 00290 * 00291 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00292 * 00293 * Redistribution and use in source and binary forms, with or without modification, 00294 * are permitted provided that the following conditions are met: 00295 * 1. Redistributions of source code must retain the above copyright notice, 00296 * this list of conditions and the following disclaimer. 00297 * 2. Redistributions in binary form must reproduce the above copyright notice, 00298 * this list of conditions and the following disclaimer in the documentation 00299 * and/or other materials provided with the distribution. 00300 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00301 * may be used to endorse or promote products derived from this software 00302 * without specific prior written permission. 00303 * 00304 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00305 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00306 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00307 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00308 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00309 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00310 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00311 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00312 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00313 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00314 * 00315 ****************************************************************************** 00316 */ 00317 00318 /* Includes ------------------------------------------------------------------*/ 00319 #include "stm32l4xx_hal.h" 00320 00321 /** @addtogroup STM32L4xx_HAL_Driver 00322 * @{ 00323 */ 00324 00325 /** @defgroup ADC ADC 00326 * @brief ADC HAL module driver 00327 * @{ 00328 */ 00329 00330 #ifdef HAL_ADC_MODULE_ENABLED 00331 00332 /* Private typedef -----------------------------------------------------------*/ 00333 /* Private define ------------------------------------------------------------*/ 00334 00335 /** @defgroup ADC_Private_Constants ADC Private Constants 00336 * @{ 00337 */ 00338 00339 #define ADC_CFGR_FIELDS_1 ((uint32_t)(ADC_CFGR_RES | ADC_CFGR_ALIGN |\ 00340 ADC_CFGR_CONT | ADC_CFGR_OVRMOD |\ 00341 ADC_CFGR_DISCEN | ADC_CFGR_DISCNUM |\ 00342 ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL)) /*!< ADC_CFGR fields of parameters that can be updated 00343 when no regular conversion is on-going */ 00344 00345 /* Timeout values for ADC operations (enable settling time, */ 00346 /* disable settling time, ...). */ 00347 /* Values defined to be higher than worst cases: low clock frequency, */ 00348 /* maximum prescalers. */ 00349 #define ADC_ENABLE_TIMEOUT ((uint32_t) 2) /*!< ADC enable time-out value */ 00350 #define ADC_DISABLE_TIMEOUT ((uint32_t) 2) /*!< ADC disable time-out value */ 00351 00352 /* Timeout to wait for current conversion on going to be completed. */ 00353 /* Timeout fixed to longest ADC conversion possible, for 1 channel: */ 00354 /* - maximum sampling time (640.5 adc_clk) */ 00355 /* - ADC resolution (Tsar 12 bits= 12.5 adc_clk) */ 00356 /* - System clock / ADC clock <= 4096 (hypothesis of maximum clock ratio) */ 00357 /* - ADC oversampling ratio 256 */ 00358 /* Calculation: 653 * 4096 * 256 CPU clock cycles max */ 00359 /* Unit: cycles of CPU clock. */ 00360 #define ADC_CONVERSION_TIME_MAX_CPU_CYCLES ((uint32_t) 653U * 4096U * 256U) /*!< ADC conversion completion time-out value */ 00361 00362 00363 /** 00364 * @} 00365 */ 00366 00367 /* Private macro -------------------------------------------------------------*/ 00368 /* Private variables ---------------------------------------------------------*/ 00369 /* Private function prototypes -----------------------------------------------*/ 00370 /* Exported functions --------------------------------------------------------*/ 00371 00372 /** @defgroup ADC_Exported_Functions ADC Exported Functions 00373 * @{ 00374 */ 00375 00376 /** @defgroup ADC_Exported_Functions_Group1 Initialization and de-initialization functions 00377 * @brief ADC Initialization and Configuration functions 00378 * 00379 @verbatim 00380 =============================================================================== 00381 ##### Initialization and de-initialization functions ##### 00382 =============================================================================== 00383 [..] This section provides functions allowing to: 00384 (+) Initialize and configure the ADC. 00385 (+) De-initialize the ADC. 00386 @endverbatim 00387 * @{ 00388 */ 00389 00390 /** 00391 * @brief Initialize the ADC peripheral and regular group according to 00392 * parameters specified in structure "ADC_InitTypeDef". 00393 * @note As prerequisite, ADC clock must be configured at RCC top level 00394 * (refer to description of RCC configuration for ADC 00395 * in header of this file). 00396 * @note Possibility to update parameters on the fly: 00397 * This function initializes the ADC MSP (HAL_ADC_MspInit()) only when 00398 * coming from ADC state reset. Following calls to this function can 00399 * be used to reconfigure some parameters of ADC_InitTypeDef 00400 * structure on the fly, without modifying MSP configuration. If ADC 00401 * MSP has to be modified again, HAL_ADC_DeInit() must be called 00402 * before HAL_ADC_Init(). 00403 * The setting of these parameters is conditioned to ADC state. 00404 * For parameters constraints, see comments of structure 00405 * "ADC_InitTypeDef". 00406 * @note This function configures the ADC within 2 scopes: scope of entire 00407 * ADC and scope of regular group. For parameters details, see comments 00408 * of structure "ADC_InitTypeDef". 00409 * @note Parameters related to common ADC registers (ADC clock mode) are set 00410 * only if all ADCs are disabled. 00411 * If this is not the case, these common parameters setting are 00412 * bypassed without error reporting: it can be the intended behaviour in 00413 * case of update of a parameter of ADC_InitTypeDef on the fly, 00414 * without disabling the other ADCs. 00415 * @param hadc ADC handle 00416 * @retval HAL status 00417 */ 00418 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc) 00419 { 00420 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 00421 uint32_t tmpCFGR = 0U; 00422 __IO uint32_t wait_loop_index = 0; 00423 00424 /* Check ADC handle */ 00425 if(hadc == NULL) 00426 { 00427 return HAL_ERROR; 00428 } 00429 00430 /* Check the parameters */ 00431 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00432 assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler)); 00433 assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution)); 00434 assert_param(IS_ADC_DFSDMCFG_MODE(hadc)); 00435 assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); 00436 assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode)); 00437 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); 00438 assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); 00439 assert_param(IS_ADC_EXTTRIG(hadc, hadc->Init.ExternalTrigConv)); 00440 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); 00441 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); 00442 assert_param(IS_ADC_OVERRUN(hadc->Init.Overrun)); 00443 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.LowPowerAutoWait)); 00444 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.OversamplingMode)); 00445 00446 if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) 00447 { 00448 assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion)); 00449 assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode)); 00450 00451 if(hadc->Init.DiscontinuousConvMode == ENABLE) 00452 { 00453 assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion)); 00454 } 00455 } 00456 00457 /* DISCEN and CONT bits cannot be set at the same time */ 00458 assert_param(!((hadc->Init.DiscontinuousConvMode == ENABLE) && (hadc->Init.ContinuousConvMode == ENABLE))); 00459 00460 /* Actions performed only if ADC is coming from state reset: */ 00461 /* - Initialization of ADC MSP */ 00462 if(hadc->State == HAL_ADC_STATE_RESET) 00463 { 00464 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00465 /* Init the ADC Callback settings */ 00466 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; /* Legacy weak callback */ 00467 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; /* Legacy weak callback */ 00468 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; /* Legacy weak callback */ 00469 hadc->ErrorCallback = HAL_ADC_ErrorCallback; /* Legacy weak callback */ 00470 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; /* Legacy weak callback */ 00471 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; /* Legacy weak callback */ 00472 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; /* Legacy weak callback */ 00473 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; /* Legacy weak callback */ 00474 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; /* Legacy weak callback */ 00475 00476 if (hadc->MspInitCallback == NULL) 00477 { 00478 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ 00479 } 00480 00481 /* Init the low level hardware */ 00482 hadc->MspInitCallback(hadc); 00483 #else 00484 /* Init the low level hardware */ 00485 HAL_ADC_MspInit(hadc); 00486 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00487 00488 /* Set ADC error code to none */ 00489 ADC_CLEAR_ERRORCODE(hadc); 00490 00491 /* Initialize Lock */ 00492 hadc->Lock = HAL_UNLOCKED; 00493 } 00494 00495 /* - Exit from deep-power-down mode and ADC voltage regulator enable */ 00496 if(LL_ADC_IsDeepPowerDownEnabled(hadc->Instance) != 0U) 00497 { 00498 /* Disable ADC deep power down mode */ 00499 LL_ADC_DisableDeepPowerDown(hadc->Instance); 00500 00501 /* System was in deep power down mode, calibration must 00502 be relaunched or a previously saved calibration factor 00503 re-applied once the ADC voltage regulator is enabled */ 00504 } 00505 00506 if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) 00507 { 00508 /* Enable ADC internal voltage regulator */ 00509 LL_ADC_EnableInternalRegulator(hadc->Instance); 00510 00511 /* Delay for ADC stabilization time */ 00512 /* Wait loop initialization and execution */ 00513 /* Note: Variable divided by 2 to compensate partially */ 00514 /* CPU processing cycles. */ 00515 wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2))); 00516 while(wait_loop_index != 0) 00517 { 00518 wait_loop_index--; 00519 } 00520 } 00521 00522 /* Verification that ADC voltage regulator is correctly enabled, whether */ 00523 /* or not ADC is coming from state reset (if any potential problem of */ 00524 /* clocking, voltage regulator would not be enabled). */ 00525 if(LL_ADC_IsInternalRegulatorEnabled(hadc->Instance) == 0U) 00526 { 00527 /* Update ADC state machine to error */ 00528 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 00529 00530 /* Set ADC error code to ADC IP internal error */ 00531 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 00532 00533 tmp_hal_status = HAL_ERROR; 00534 } 00535 00536 /* Configuration of ADC parameters if previous preliminary actions are */ 00537 /* correctly completed and if there is no conversion on going on regular */ 00538 /* group (ADC may already be enabled at this point if HAL_ADC_Init() is */ 00539 /* called to update a parameter on the fly). */ 00540 if( (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 00541 && (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 00542 ) 00543 { 00544 /* Set ADC state */ 00545 ADC_STATE_CLR_SET(hadc->State, 00546 HAL_ADC_STATE_REG_BUSY, 00547 HAL_ADC_STATE_BUSY_INTERNAL); 00548 00549 /* Configuration of common ADC parameters */ 00550 00551 /* Parameters update conditioned to ADC state: */ 00552 /* Parameters that can be updated only when ADC is disabled: */ 00553 /* - clock configuration */ 00554 if ((ADC_IS_ENABLE(hadc) == RESET) && 00555 (ADC_ANY_OTHER_ENABLED(hadc) == RESET) ) 00556 { 00557 /* Reset configuration of ADC common register CCR: */ 00558 /* */ 00559 /* - ADC clock mode and ACC prescaler (CKMODE and PRESC bits)are set */ 00560 /* according to adc->Init.ClockPrescaler. It selects the clock */ 00561 /* source and sets the clock division factor. */ 00562 /* */ 00563 /* Some parameters of this register are not reset, since they are set */ 00564 /* by other functions and must be kept in case of usage of this */ 00565 /* function on the fly (update of a parameter of ADC_InitTypeDef */ 00566 /* without needing to reconfigure all other ADC groups/channels */ 00567 /* parameters): */ 00568 /* - when multimode feature is available, multimode-related */ 00569 /* parameters: MDMA, DMACFG, DELAY, DUAL (set by API */ 00570 /* HAL_ADCEx_MultiModeConfigChannel() ) */ 00571 /* - internal measurement paths: Vbat, temperature sensor, Vref */ 00572 /* (set into HAL_ADC_ConfigChannel() or */ 00573 /* HAL_ADCEx_InjectedConfigChannel() ) */ 00574 LL_ADC_SetCommonClock(__LL_ADC_COMMON_INSTANCE(hadc->Instance), hadc->Init.ClockPrescaler); 00575 } 00576 00577 /* Configuration of ADC: */ 00578 /* - resolution Init.Resolution */ 00579 /* - data alignment Init.DataAlign */ 00580 /* - external trigger to start conversion Init.ExternalTrigConv */ 00581 /* - external trigger polarity Init.ExternalTrigConvEdge */ 00582 /* - continuous conversion mode Init.ContinuousConvMode */ 00583 /* - overrun Init.Overrun */ 00584 /* - discontinuous mode Init.DiscontinuousConvMode */ 00585 /* - discontinuous mode channel count Init.NbrOfDiscConversion */ 00586 tmpCFGR = (ADC_CFGR_CONTINUOUS(hadc->Init.ContinuousConvMode) | 00587 hadc->Init.Overrun | 00588 hadc->Init.DataAlign | 00589 hadc->Init.Resolution | 00590 ADC_CFGR_REG_DISCONTINUOUS(hadc->Init.DiscontinuousConvMode) ); 00591 00592 if (hadc->Init.DiscontinuousConvMode == ENABLE) 00593 { 00594 tmpCFGR |= ADC_CFGR_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion); 00595 } 00596 00597 /* Enable external trigger if trigger selection is different of software */ 00598 /* start. */ 00599 /* Note: This configuration keeps the hardware feature of parameter */ 00600 /* ExternalTrigConvEdge "trigger edge none" equivalent to */ 00601 /* software start. */ 00602 if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START) 00603 { 00604 tmpCFGR |= ( (hadc->Init.ExternalTrigConv & ADC_CFGR_EXTSEL) 00605 | hadc->Init.ExternalTrigConvEdge 00606 ); 00607 } 00608 00609 /* Update Configuration Register CFGR */ 00610 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_1, tmpCFGR); 00611 00612 /* Parameters update conditioned to ADC state: */ 00613 /* Parameters that can be updated when ADC is disabled or enabled without */ 00614 /* conversion on going on regular and injected groups: */ 00615 /* - DMA continuous request Init.DMAContinuousRequests */ 00616 /* - LowPowerAutoWait feature Init.LowPowerAutoWait */ 00617 /* - Oversampling parameters Init.Oversampling */ 00618 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) 00619 { 00620 tmpCFGR = ( ADC_CFGR_DFSDM(hadc) | 00621 ADC_CFGR_AUTOWAIT(hadc->Init.LowPowerAutoWait) | 00622 ADC_CFGR_DMACONTREQ(hadc->Init.DMAContinuousRequests) ); 00623 00624 MODIFY_REG(hadc->Instance->CFGR, ADC_CFGR_FIELDS_2, tmpCFGR); 00625 00626 if (hadc->Init.OversamplingMode == ENABLE) 00627 { 00628 assert_param(IS_ADC_OVERSAMPLING_RATIO(hadc->Init.Oversampling.Ratio)); 00629 assert_param(IS_ADC_RIGHT_BIT_SHIFT(hadc->Init.Oversampling.RightBitShift)); 00630 assert_param(IS_ADC_TRIGGERED_OVERSAMPLING_MODE(hadc->Init.Oversampling.TriggeredMode)); 00631 assert_param(IS_ADC_REGOVERSAMPLING_MODE(hadc->Init.Oversampling.OversamplingStopReset)); 00632 00633 /* Configuration of Oversampler: */ 00634 /* - Oversampling Ratio */ 00635 /* - Right bit shift */ 00636 /* - Triggered mode */ 00637 /* - Oversampling mode (continued/resumed) */ 00638 MODIFY_REG(hadc->Instance->CFGR2, 00639 ADC_CFGR2_OVSR | 00640 ADC_CFGR2_OVSS | 00641 ADC_CFGR2_TROVS | 00642 ADC_CFGR2_ROVSM, 00643 ADC_CFGR2_ROVSE | 00644 hadc->Init.Oversampling.Ratio | 00645 hadc->Init.Oversampling.RightBitShift | 00646 hadc->Init.Oversampling.TriggeredMode | 00647 hadc->Init.Oversampling.OversamplingStopReset 00648 ); 00649 } 00650 else 00651 { 00652 /* Disable ADC oversampling scope on ADC group regular */ 00653 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSE); 00654 } 00655 00656 } /* if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) */ 00657 00658 /* Configuration of regular group sequencer: */ 00659 /* - if scan mode is disabled, regular channels sequence length is set to */ 00660 /* 0x00: 1 channel converted (channel on regular rank 1) */ 00661 /* Parameter "NbrOfConversion" is discarded. */ 00662 /* Note: Scan mode is not present by hardware on this device, but */ 00663 /* emulated by software for alignment over all STM32 devices. */ 00664 /* - if scan mode is enabled, regular channels sequence length is set to */ 00665 /* parameter "NbrOfConversion". */ 00666 00667 if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE) 00668 { 00669 /* Set number of ranks in regular group sequencer */ 00670 MODIFY_REG(hadc->Instance->SQR1, ADC_SQR1_L, (hadc->Init.NbrOfConversion - (uint8_t)1)); 00671 } 00672 else 00673 { 00674 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_L); 00675 } 00676 00677 /* Initialize the ADC state */ 00678 /* Clear HAL_ADC_STATE_BUSY_INTERNAL bit, set HAL_ADC_STATE_READY bit */ 00679 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL, HAL_ADC_STATE_READY); 00680 } 00681 else 00682 { 00683 /* Update ADC state machine to error */ 00684 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 00685 00686 tmp_hal_status = HAL_ERROR; 00687 } 00688 00689 /* Return function status */ 00690 return tmp_hal_status; 00691 } 00692 00693 /** 00694 * @brief Deinitialize the ADC peripheral registers to their default reset 00695 * values, with deinitialization of the ADC MSP. 00696 * @note For devices with several ADCs: reset of ADC common registers is done 00697 * only if all ADCs sharing the same common group are disabled. 00698 * (function "HAL_ADC_MspDeInit()" is also called under the same conditions: 00699 * all ADC instances use the same core clock at RCC level, disabling 00700 * the core clock reset all ADC instances). 00701 * If this is not the case, reset of these common parameters reset is 00702 * bypassed without error reporting: it can be the intended behavior in 00703 * case of reset of a single ADC while the other ADCs sharing the same 00704 * common group is still running. 00705 * @note By default, HAL_ADC_DeInit() set ADC in mode deep power-down: 00706 * this saves more power by reducing leakage currents 00707 * and is particularly interesting before entering MCU low-power modes. 00708 * @param hadc ADC handle 00709 * @retval HAL status 00710 */ 00711 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc) 00712 { 00713 /* Check ADC handle */ 00714 if(hadc == NULL) 00715 { 00716 return HAL_ERROR; 00717 } 00718 00719 /* Check the parameters */ 00720 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 00721 00722 /* Set ADC state */ 00723 SET_BIT(hadc->State, HAL_ADC_STATE_BUSY_INTERNAL); 00724 00725 /* Stop potential conversion on going, on regular and injected groups */ 00726 /* Note: No check on ADC_ConversionStop() return status, */ 00727 /* if the conversion stop failed, it is up to */ 00728 /* HAL_ADC_MspDeInit() to reset the ADC IP. */ 00729 ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); 00730 00731 /* Disable ADC peripheral if conversions are effectively stopped */ 00732 /* Flush register JSQR: reset the queue sequencer when injected */ 00733 /* queue sequencer is enabled and ADC disabled. */ 00734 /* The software and hardware triggers of the injected sequence are both */ 00735 /* internally disabled just after the completion of the last valid */ 00736 /* injected sequence. */ 00737 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQM); 00738 00739 /* Disable the ADC peripheral */ 00740 /* No check on ADC_Disable() return status, if the ADC disabling process 00741 failed, it is up to HAL_ADC_MspDeInit() to reset the ADC IP */ 00742 ADC_Disable(hadc); 00743 00744 00745 /* ========== Reset ADC registers ========== */ 00746 /* Reset register IER */ 00747 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_AWD3 | ADC_IT_AWD2 | ADC_IT_AWD1 | 00748 ADC_IT_JQOVF | ADC_IT_OVR | 00749 ADC_IT_JEOS | ADC_IT_JEOC | 00750 ADC_IT_EOS | ADC_IT_EOC | 00751 ADC_IT_EOSMP | ADC_IT_RDY ) ); 00752 00753 /* Reset register ISR */ 00754 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD3 | ADC_FLAG_AWD2 | ADC_FLAG_AWD1 | 00755 ADC_FLAG_JQOVF | ADC_FLAG_OVR | 00756 ADC_FLAG_JEOS | ADC_FLAG_JEOC | 00757 ADC_FLAG_EOS | ADC_FLAG_EOC | 00758 ADC_FLAG_EOSMP | ADC_FLAG_RDY ) ); 00759 00760 /* Reset register CR */ 00761 /* Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, 00762 ADC_CR_ADCAL, ADC_CR_ADDIS and ADC_CR_ADEN are in access mode "read-set": 00763 no direct reset applicable. 00764 Update CR register to reset value where doable by software */ 00765 CLEAR_BIT(hadc->Instance->CR, ADC_CR_ADVREGEN | ADC_CR_ADCALDIF); 00766 SET_BIT(hadc->Instance->CR, ADC_CR_DEEPPWD); 00767 00768 /* Reset register CFGR */ 00769 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_FIELDS); 00770 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_JQDIS); 00771 00772 /* Reset register CFGR2 */ 00773 CLEAR_BIT(hadc->Instance->CFGR2, ADC_CFGR2_ROVSM | ADC_CFGR2_TROVS | ADC_CFGR2_OVSS | 00774 ADC_CFGR2_OVSR | ADC_CFGR2_JOVSE | ADC_CFGR2_ROVSE ); 00775 00776 /* Reset register SMPR1 */ 00777 CLEAR_BIT(hadc->Instance->SMPR1, ADC_SMPR1_FIELDS); 00778 00779 /* Reset register SMPR2 */ 00780 CLEAR_BIT(hadc->Instance->SMPR2, ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16 | 00781 ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13 | 00782 ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10 ); 00783 00784 /* Reset register TR1 */ 00785 CLEAR_BIT(hadc->Instance->TR1, ADC_TR1_HT1 | ADC_TR1_LT1); 00786 00787 /* Reset register TR2 */ 00788 CLEAR_BIT(hadc->Instance->TR2, ADC_TR2_HT2 | ADC_TR2_LT2); 00789 00790 /* Reset register TR3 */ 00791 CLEAR_BIT(hadc->Instance->TR3, ADC_TR3_HT3 | ADC_TR3_LT3); 00792 00793 /* Reset register SQR1 */ 00794 CLEAR_BIT(hadc->Instance->SQR1, ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2 | 00795 ADC_SQR1_SQ1 | ADC_SQR1_L); 00796 00797 /* Reset register SQR2 */ 00798 CLEAR_BIT(hadc->Instance->SQR2, ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7 | 00799 ADC_SQR2_SQ6 | ADC_SQR2_SQ5); 00800 00801 /* Reset register SQR3 */ 00802 CLEAR_BIT(hadc->Instance->SQR3, ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12 | 00803 ADC_SQR3_SQ11 | ADC_SQR3_SQ10); 00804 00805 /* Reset register SQR4 */ 00806 CLEAR_BIT(hadc->Instance->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15); 00807 00808 /* Register JSQR was reset when the ADC was disabled */ 00809 00810 /* Reset register DR */ 00811 /* bits in access mode read only, no direct reset applicable*/ 00812 00813 /* Reset register OFR1 */ 00814 CLEAR_BIT(hadc->Instance->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1); 00815 /* Reset register OFR2 */ 00816 CLEAR_BIT(hadc->Instance->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2); 00817 /* Reset register OFR3 */ 00818 CLEAR_BIT(hadc->Instance->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3); 00819 /* Reset register OFR4 */ 00820 CLEAR_BIT(hadc->Instance->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4); 00821 00822 /* Reset registers JDR1, JDR2, JDR3, JDR4 */ 00823 /* bits in access mode read only, no direct reset applicable*/ 00824 00825 /* Reset register AWD2CR */ 00826 CLEAR_BIT(hadc->Instance->AWD2CR, ADC_AWD2CR_AWD2CH); 00827 00828 /* Reset register AWD3CR */ 00829 CLEAR_BIT(hadc->Instance->AWD3CR, ADC_AWD3CR_AWD3CH); 00830 00831 /* Reset register DIFSEL */ 00832 CLEAR_BIT(hadc->Instance->DIFSEL, ADC_DIFSEL_DIFSEL); 00833 00834 /* Reset register CALFACT */ 00835 CLEAR_BIT(hadc->Instance->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S); 00836 00837 00838 /* ========== Reset common ADC registers ========== */ 00839 00840 /* Software is allowed to change common parameters only when all the other 00841 ADCs are disabled. */ 00842 if ((ADC_IS_ENABLE(hadc) == RESET) && 00843 (ADC_ANY_OTHER_ENABLED(hadc) == RESET) ) 00844 { 00845 /* Reset configuration of ADC common register CCR: 00846 - clock mode: CKMODE, PRESCEN 00847 - multimode related parameters (when this feature is available): MDMA, 00848 DMACFG, DELAY, DUAL (set by HAL_ADCEx_MultiModeConfigChannel() API) 00849 - internal measurement paths: Vbat, temperature sensor, Vref (set into 00850 HAL_ADC_ConfigChannel() or HAL_ADCEx_InjectedConfigChannel() ) 00851 */ 00852 ADC_CLEAR_COMMON_CONTROL_REGISTER(hadc); 00853 } 00854 00855 /* DeInit the low level hardware. 00856 00857 For example: 00858 __HAL_RCC_ADC_FORCE_RESET(); 00859 __HAL_RCC_ADC_RELEASE_RESET(); 00860 __HAL_RCC_ADC_CLK_DISABLE(); 00861 00862 Keep in mind that all ADCs use the same clock: disabling 00863 the clock will reset all ADCs. 00864 00865 */ 00866 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00867 if (hadc->MspDeInitCallback == NULL) 00868 { 00869 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ 00870 } 00871 00872 /* DeInit the low level hardware: RCC clock, NVIC */ 00873 hadc->MspDeInitCallback(hadc); 00874 #else 00875 /* DeInit the low level hardware: RCC clock, NVIC */ 00876 HAL_ADC_MspDeInit(hadc); 00877 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 00878 00879 /* Set ADC error code to none */ 00880 ADC_CLEAR_ERRORCODE(hadc); 00881 00882 /* Reset injected channel configuration parameters */ 00883 hadc->InjectionConfig.ContextQueue = 0; 00884 hadc->InjectionConfig.ChannelCount = 0; 00885 00886 /* Set ADC state */ 00887 hadc->State = HAL_ADC_STATE_RESET; 00888 00889 /* Process unlocked */ 00890 __HAL_UNLOCK(hadc); 00891 00892 /* Return function status */ 00893 return HAL_OK; 00894 } 00895 00896 /** 00897 * @brief Initialize the ADC MSP. 00898 * @param hadc ADC handle 00899 * @retval None 00900 */ 00901 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc) 00902 { 00903 /* Prevent unused argument(s) compilation warning */ 00904 UNUSED(hadc); 00905 00906 /* NOTE : This function should not be modified. When the callback is needed, 00907 function HAL_ADC_MspInit must be implemented in the user file. 00908 */ 00909 } 00910 00911 /** 00912 * @brief DeInitialize the ADC MSP. 00913 * @param hadc ADC handle 00914 * @note All ADC instances use the same core clock at RCC level, disabling 00915 * the core clock reset all ADC instances). 00916 * @retval None 00917 */ 00918 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc) 00919 { 00920 /* Prevent unused argument(s) compilation warning */ 00921 UNUSED(hadc); 00922 00923 /* NOTE : This function should not be modified. When the callback is needed, 00924 function HAL_ADC_MspDeInit must be implemented in the user file. 00925 */ 00926 } 00927 00928 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 00929 /** 00930 * @brief Register a User ADC Callback 00931 * To be used instead of the weak predefined callback 00932 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains 00933 * the configuration information for the specified ADC. 00934 * @param CallbackID ID of the callback to be registered 00935 * This parameter can be one of the following values: 00936 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID 00937 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID 00938 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID 00939 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID 00940 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID 00941 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID 00942 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID 00943 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID 00944 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID 00945 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID 00946 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID 00947 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID 00948 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID 00949 * @param pCallback pointer to the Callback function 00950 * @retval HAL status 00951 */ 00952 HAL_StatusTypeDef HAL_ADC_RegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID, pADC_CallbackTypeDef pCallback) 00953 { 00954 HAL_StatusTypeDef status = HAL_OK; 00955 00956 if (pCallback == NULL) 00957 { 00958 /* Update the error code */ 00959 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; 00960 00961 return HAL_ERROR; 00962 } 00963 00964 if ((hadc->State & HAL_ADC_STATE_READY) != 0) 00965 { 00966 switch (CallbackID) 00967 { 00968 case HAL_ADC_CONVERSION_COMPLETE_CB_ID : 00969 hadc->ConvCpltCallback = pCallback; 00970 break; 00971 00972 case HAL_ADC_CONVERSION_HALF_CB_ID : 00973 hadc->ConvHalfCpltCallback = pCallback; 00974 break; 00975 00976 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : 00977 hadc->LevelOutOfWindowCallback = pCallback; 00978 break; 00979 00980 case HAL_ADC_ERROR_CB_ID : 00981 hadc->ErrorCallback = pCallback; 00982 break; 00983 00984 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : 00985 hadc->InjectedConvCpltCallback = pCallback; 00986 break; 00987 00988 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : 00989 hadc->InjectedQueueOverflowCallback = pCallback; 00990 break; 00991 00992 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : 00993 hadc->LevelOutOfWindow2Callback = pCallback; 00994 break; 00995 00996 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : 00997 hadc->LevelOutOfWindow3Callback = pCallback; 00998 break; 00999 01000 case HAL_ADC_END_OF_SAMPLING_CB_ID : 01001 hadc->EndOfSamplingCallback = pCallback; 01002 break; 01003 01004 case HAL_ADC_MSPINIT_CB_ID : 01005 hadc->MspInitCallback = pCallback; 01006 break; 01007 01008 case HAL_ADC_MSPDEINIT_CB_ID : 01009 hadc->MspDeInitCallback = pCallback; 01010 break; 01011 01012 default : 01013 /* Update the error code */ 01014 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; 01015 01016 /* Return error status */ 01017 status = HAL_ERROR; 01018 break; 01019 } 01020 } 01021 else if (HAL_ADC_STATE_RESET == hadc->State) 01022 { 01023 switch (CallbackID) 01024 { 01025 case HAL_ADC_MSPINIT_CB_ID : 01026 hadc->MspInitCallback = pCallback; 01027 break; 01028 01029 case HAL_ADC_MSPDEINIT_CB_ID : 01030 hadc->MspDeInitCallback = pCallback; 01031 break; 01032 01033 default : 01034 /* Update the error code */ 01035 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; 01036 01037 /* Return error status */ 01038 status = HAL_ERROR; 01039 break; 01040 } 01041 } 01042 else 01043 { 01044 /* Update the error code */ 01045 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; 01046 01047 /* Return error status */ 01048 status = HAL_ERROR; 01049 } 01050 01051 return status; 01052 } 01053 01054 /** 01055 * @brief Unregister a ADC Callback 01056 * ADC callback is redirected to the weak predefined callback 01057 * @param hadc Pointer to a ADC_HandleTypeDef structure that contains 01058 * the configuration information for the specified ADC. 01059 * @param CallbackID ID of the callback to be unregistered 01060 * This parameter can be one of the following values: 01061 * @arg @ref HAL_ADC_CONVERSION_COMPLETE_CB_ID ADC conversion complete callback ID 01062 * @arg @ref HAL_ADC_CONVERSION_HALF_CB_ID ADC conversion complete callback ID 01063 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID ADC analog watchdog 1 callback ID 01064 * @arg @ref HAL_ADC_ERROR_CB_ID ADC error callback ID 01065 * @arg @ref HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID ADC group injected conversion complete callback ID 01066 * @arg @ref HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID ADC group injected context queue overflow callback ID 01067 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID ADC analog watchdog 2 callback ID 01068 * @arg @ref HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID ADC analog watchdog 3 callback ID 01069 * @arg @ref HAL_ADC_END_OF_SAMPLING_CB_ID ADC end of sampling callback ID 01070 * @arg @ref HAL_ADC_MSPINIT_CB_ID ADC Msp Init callback ID 01071 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID ADC Msp DeInit callback ID 01072 * @arg @ref HAL_ADC_MSPINIT_CB_ID MspInit callback ID 01073 * @arg @ref HAL_ADC_MSPDEINIT_CB_ID MspDeInit callback ID 01074 * @retval HAL status 01075 */ 01076 HAL_StatusTypeDef HAL_ADC_UnRegisterCallback(ADC_HandleTypeDef *hadc, HAL_ADC_CallbackIDTypeDef CallbackID) 01077 { 01078 HAL_StatusTypeDef status = HAL_OK; 01079 01080 if ((hadc->State & HAL_ADC_STATE_READY) != 0) 01081 { 01082 switch (CallbackID) 01083 { 01084 case HAL_ADC_CONVERSION_COMPLETE_CB_ID : 01085 hadc->ConvCpltCallback = HAL_ADC_ConvCpltCallback; 01086 break; 01087 01088 case HAL_ADC_CONVERSION_HALF_CB_ID : 01089 hadc->ConvHalfCpltCallback = HAL_ADC_ConvHalfCpltCallback; 01090 break; 01091 01092 case HAL_ADC_LEVEL_OUT_OF_WINDOW_1_CB_ID : 01093 hadc->LevelOutOfWindowCallback = HAL_ADC_LevelOutOfWindowCallback; 01094 break; 01095 01096 case HAL_ADC_ERROR_CB_ID : 01097 hadc->ErrorCallback = HAL_ADC_ErrorCallback; 01098 break; 01099 01100 case HAL_ADC_INJ_CONVERSION_COMPLETE_CB_ID : 01101 hadc->InjectedConvCpltCallback = HAL_ADCEx_InjectedConvCpltCallback; 01102 break; 01103 01104 case HAL_ADC_INJ_QUEUE_OVEFLOW_CB_ID : 01105 hadc->InjectedQueueOverflowCallback = HAL_ADCEx_InjectedQueueOverflowCallback; 01106 break; 01107 01108 case HAL_ADC_LEVEL_OUT_OF_WINDOW_2_CB_ID : 01109 hadc->LevelOutOfWindow2Callback = HAL_ADCEx_LevelOutOfWindow2Callback; 01110 break; 01111 01112 case HAL_ADC_LEVEL_OUT_OF_WINDOW_3_CB_ID : 01113 hadc->LevelOutOfWindow3Callback = HAL_ADCEx_LevelOutOfWindow3Callback; 01114 break; 01115 01116 case HAL_ADC_END_OF_SAMPLING_CB_ID : 01117 hadc->EndOfSamplingCallback = HAL_ADCEx_EndOfSamplingCallback; 01118 break; 01119 01120 case HAL_ADC_MSPINIT_CB_ID : 01121 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ 01122 break; 01123 01124 case HAL_ADC_MSPDEINIT_CB_ID : 01125 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ 01126 break; 01127 01128 default : 01129 /* Update the error code */ 01130 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; 01131 01132 /* Return error status */ 01133 status = HAL_ERROR; 01134 break; 01135 } 01136 } 01137 else if (HAL_ADC_STATE_RESET == hadc->State) 01138 { 01139 switch (CallbackID) 01140 { 01141 case HAL_ADC_MSPINIT_CB_ID : 01142 hadc->MspInitCallback = HAL_ADC_MspInit; /* Legacy weak MspInit */ 01143 break; 01144 01145 case HAL_ADC_MSPDEINIT_CB_ID : 01146 hadc->MspDeInitCallback = HAL_ADC_MspDeInit; /* Legacy weak MspDeInit */ 01147 break; 01148 01149 default : 01150 /* Update the error code */ 01151 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; 01152 01153 /* Return error status */ 01154 status = HAL_ERROR; 01155 break; 01156 } 01157 } 01158 else 01159 { 01160 /* Update the error code */ 01161 hadc->ErrorCode |= HAL_ADC_ERROR_INVALID_CALLBACK; 01162 01163 /* Return error status */ 01164 status = HAL_ERROR; 01165 } 01166 01167 return status; 01168 } 01169 01170 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 01171 01172 /** 01173 * @} 01174 */ 01175 01176 /** @defgroup ADC_Exported_Functions_Group2 ADC Input and Output operation functions 01177 * @brief ADC IO operation functions 01178 * 01179 @verbatim 01180 =============================================================================== 01181 ##### IO operation functions ##### 01182 =============================================================================== 01183 [..] This section provides functions allowing to: 01184 (+) Start conversion of regular group. 01185 (+) Stop conversion of regular group. 01186 (+) Poll for conversion complete on regular group. 01187 (+) Poll for conversion event. 01188 (+) Get result of regular channel conversion. 01189 (+) Start conversion of regular group and enable interruptions. 01190 (+) Stop conversion of regular group and disable interruptions. 01191 (+) Handle ADC interrupt request 01192 (+) Start conversion of regular group and enable DMA transfer. 01193 (+) Stop conversion of regular group and disable ADC DMA transfer. 01194 @endverbatim 01195 * @{ 01196 */ 01197 01198 /** 01199 * @brief Enable ADC, start conversion of regular group. 01200 * @note Interruptions enabled in this function: None. 01201 * @note Case of multimode enabled (when multimode feature is available): 01202 * if ADC is Slave, ADC is enabled but conversion is not started, 01203 * if ADC is master, ADC is enabled and multimode conversion is started. 01204 * @param hadc ADC handle 01205 * @retval HAL status 01206 */ 01207 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc) 01208 { 01209 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01210 ADC_TypeDef *tmpADC_Master; 01211 01212 /* Check the parameters */ 01213 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01214 01215 /* Perform ADC enable and conversion start if no conversion is on going */ 01216 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 01217 { 01218 /* Process locked */ 01219 __HAL_LOCK(hadc); 01220 01221 /* Enable the ADC peripheral */ 01222 tmp_hal_status = ADC_Enable(hadc); 01223 01224 /* Start conversion if ADC is effectively enabled */ 01225 if (tmp_hal_status == HAL_OK) 01226 { 01227 /* Set ADC state */ 01228 /* - Clear state bitfield related to regular group conversion results */ 01229 /* - Set state bitfield related to regular operation */ 01230 ADC_STATE_CLR_SET(hadc->State, 01231 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, 01232 HAL_ADC_STATE_REG_BUSY); 01233 01234 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit 01235 - by default if ADC is Master or Independent or if multimode feature is not available 01236 - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ 01237 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 01238 { 01239 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 01240 } 01241 01242 /* Set ADC error code */ 01243 /* Check if a conversion is on going on ADC group injected */ 01244 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 01245 { 01246 /* Reset ADC error code fields related to regular conversions only */ 01247 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 01248 } 01249 else 01250 { 01251 /* Reset all ADC error code fields */ 01252 ADC_CLEAR_ERRORCODE(hadc); 01253 } 01254 01255 /* Clear ADC group regular conversion flag and overrun flag */ 01256 /* (To ensure of no unknown state from potential previous ADC operations) */ 01257 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 01258 01259 /* Process unlocked */ 01260 /* Unlock before starting ADC conversions: in case of potential */ 01261 /* interruption, to let the process to ADC IRQ Handler. */ 01262 __HAL_UNLOCK(hadc); 01263 01264 /* Enable conversion of regular group. */ 01265 /* If software start has been selected, conversion starts immediately. */ 01266 /* If external trigger has been selected, conversion will start at next */ 01267 /* trigger event. */ 01268 /* Case of multimode enabled (when multimode feature is available): */ 01269 /* - if ADC is slave and dual regular conversions are enabled, ADC is */ 01270 /* enabled only (conversion is not started), */ 01271 /* - if ADC is master, ADC is enabled and conversion is started. */ 01272 if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) 01273 { 01274 /* Multimode feature is not available or ADC Instance is Independent or Master, 01275 or is not Slave ADC with dual regular conversions enabled. 01276 Then, set HAL_ADC_STATE_INJ_BUSY bit and reset HAL_ADC_STATE_INJ_EOC bit if JAUTO is set. */ 01277 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) 01278 { 01279 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 01280 } 01281 01282 /* Start ADC group regular conversion */ 01283 LL_ADC_REG_StartConversion(hadc->Instance); 01284 } 01285 else 01286 { 01287 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 01288 /* if Master ADC JAUTO bit is set, update Slave State in setting 01289 HAL_ADC_STATE_INJ_BUSY bit and in resetting HAL_ADC_STATE_INJ_EOC bit */ 01290 tmpADC_Master = ADC_MASTER_REGISTER(hadc); 01291 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) 01292 { 01293 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 01294 } 01295 01296 } 01297 } 01298 else 01299 { 01300 /* Process unlocked */ 01301 __HAL_UNLOCK(hadc); 01302 } 01303 } 01304 else 01305 { 01306 tmp_hal_status = HAL_BUSY; 01307 } 01308 01309 /* Return function status */ 01310 return tmp_hal_status; 01311 } 01312 01313 /** 01314 * @brief Stop ADC conversion of regular group (and injected channels in 01315 * case of auto_injection mode), disable ADC peripheral. 01316 * @note: ADC peripheral disable is forcing stop of potential 01317 * conversion on injected group. If injected group is under use, it 01318 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. 01319 * @param hadc ADC handle 01320 * @retval HAL status. 01321 */ 01322 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc) 01323 { 01324 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01325 01326 /* Check the parameters */ 01327 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01328 01329 /* Process locked */ 01330 __HAL_LOCK(hadc); 01331 01332 /* 1. Stop potential conversion on going, on ADC groups regular and injected */ 01333 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); 01334 01335 /* Disable ADC peripheral if conversions are effectively stopped */ 01336 if (tmp_hal_status == HAL_OK) 01337 { 01338 /* 2. Disable the ADC peripheral */ 01339 tmp_hal_status = ADC_Disable(hadc); 01340 01341 /* Check if ADC is effectively disabled */ 01342 if (tmp_hal_status == HAL_OK) 01343 { 01344 /* Set ADC state */ 01345 ADC_STATE_CLR_SET(hadc->State, 01346 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 01347 HAL_ADC_STATE_READY); 01348 } 01349 } 01350 01351 /* Process unlocked */ 01352 __HAL_UNLOCK(hadc); 01353 01354 /* Return function status */ 01355 return tmp_hal_status; 01356 } 01357 01358 /** 01359 * @brief Wait for regular group conversion to be completed. 01360 * @note ADC conversion flags EOS (end of sequence) and EOC (end of 01361 * conversion) are cleared by this function, with an exception: 01362 * if low power feature "LowPowerAutoWait" is enabled, flags are 01363 * not cleared to not interfere with this feature until data register 01364 * is read using function HAL_ADC_GetValue(). 01365 * @note This function cannot be used in a particular setup: ADC configured 01366 * in DMA mode and polling for end of each conversion (ADC init 01367 * parameter "EOCSelection" set to ADC_EOC_SINGLE_CONV). 01368 * In this case, DMA resets the flag EOC and polling cannot be 01369 * performed on each conversion. Nevertheless, polling can still 01370 * be performed on the complete sequence (ADC init 01371 * parameter "EOCSelection" set to ADC_EOC_SEQ_CONV). 01372 * @param hadc ADC handle 01373 * @param Timeout Timeout value in millisecond. 01374 * @retval HAL status 01375 */ 01376 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) 01377 { 01378 uint32_t tickstart = 0U; 01379 uint32_t tmp_Flag_End = 0U; 01380 uint32_t tmp_cfgr = 0U; 01381 ADC_TypeDef *tmpADC_Master; 01382 01383 /* Check the parameters */ 01384 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01385 01386 /* If end of conversion selected to end of sequence conversions */ 01387 if (hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) 01388 { 01389 tmp_Flag_End = ADC_FLAG_EOS; 01390 } 01391 /* If end of conversion selected to end of unitary conversion */ 01392 else /* ADC_EOC_SINGLE_CONV */ 01393 { 01394 /* Verification that ADC configuration is compliant with polling for */ 01395 /* each conversion: */ 01396 /* Particular case is ADC configured in DMA mode and ADC sequencer with */ 01397 /* several ranks and polling for end of each conversion. */ 01398 /* For code simplicity sake, this particular case is generalized to */ 01399 /* ADC configured in DMA mode and and polling for end of each conversion. */ 01400 if(ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) 01401 { 01402 /* Check ADC DMA mode in independant mode */ 01403 if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN) != RESET) 01404 { 01405 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 01406 return HAL_ERROR; 01407 } 01408 else 01409 { 01410 tmp_Flag_End = (ADC_FLAG_EOC); 01411 } 01412 } 01413 else 01414 { 01415 /* Check ADC DMA mode in multimode */ 01416 if(ADC_MULTIMODE_DMA_ENABLED(hadc)) 01417 { 01418 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 01419 return HAL_ERROR; 01420 } 01421 else 01422 { 01423 tmp_Flag_End = (ADC_FLAG_EOC); 01424 } 01425 } 01426 } 01427 01428 /* Get tick count */ 01429 tickstart = HAL_GetTick(); 01430 01431 /* Wait until End of unitary conversion or sequence conversions flag is raised */ 01432 while(HAL_IS_BIT_CLR(hadc->Instance->ISR, tmp_Flag_End)) 01433 { 01434 /* Check if timeout is disabled (set to infinite wait) */ 01435 if(Timeout != HAL_MAX_DELAY) 01436 { 01437 if((Timeout == 0) || ((HAL_GetTick()-tickstart) > Timeout)) 01438 { 01439 /* Update ADC state machine to timeout */ 01440 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 01441 01442 /* Process unlocked */ 01443 __HAL_UNLOCK(hadc); 01444 01445 return HAL_TIMEOUT; 01446 } 01447 } 01448 } 01449 01450 /* Update ADC state machine */ 01451 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 01452 01453 /* Determine whether any further conversion upcoming on group regular */ 01454 /* by external trigger, continuous mode or scan sequence on going. */ 01455 if(ADC_IS_SOFTWARE_START_REGULAR(hadc) && 01456 (hadc->Init.ContinuousConvMode == DISABLE) ) 01457 { 01458 /* Check whether end of sequence is reached */ 01459 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) 01460 { 01461 /* Set ADC state */ 01462 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 01463 01464 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 01465 { 01466 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 01467 } 01468 } 01469 } 01470 01471 /* Get relevant register CFGR in ADC instance of ADC master or slave */ 01472 /* in function of multimode state (for devices with multimode */ 01473 /* available). */ 01474 if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) 01475 { 01476 /* Retrieve handle ADC CFGR register */ 01477 tmp_cfgr = READ_REG(hadc->Instance->CFGR); 01478 } 01479 else 01480 { 01481 /* Retrieve Master ADC CFGR register */ 01482 tmpADC_Master = ADC_MASTER_REGISTER(hadc); 01483 tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 01484 } 01485 01486 /* Clear polled flag */ 01487 if (tmp_Flag_End == ADC_FLAG_EOS) 01488 { 01489 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOS); 01490 } 01491 else 01492 { 01493 /* Clear end of conversion EOC flag of regular group if low power feature */ 01494 /* "LowPowerAutoWait " is disabled, to not interfere with this feature */ 01495 /* until data register is read using function HAL_ADC_GetValue(). */ 01496 if (READ_BIT(tmp_cfgr, ADC_CFGR_AUTDLY) == RESET) 01497 { 01498 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS)); 01499 } 01500 } 01501 01502 /* Return function status */ 01503 return HAL_OK; 01504 } 01505 01506 /** 01507 * @brief Poll for ADC event. 01508 * @param hadc ADC handle 01509 * @param EventType the ADC event type. 01510 * This parameter can be one of the following values: 01511 * @arg @ref ADC_EOSMP_EVENT ADC End of Sampling event 01512 * @arg @ref ADC_AWD1_EVENT ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices) 01513 * @arg @ref ADC_AWD2_EVENT ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families) 01514 * @arg @ref ADC_AWD3_EVENT ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families) 01515 * @arg @ref ADC_OVR_EVENT ADC Overrun event 01516 * @arg @ref ADC_JQOVF_EVENT ADC Injected context queue overflow event 01517 * @param Timeout Timeout value in millisecond. 01518 * @note The relevant flag is cleared if found to be set, except for ADC_FLAG_OVR. 01519 * Indeed, the latter is reset only if hadc->Init.Overrun field is set 01520 * to ADC_OVR_DATA_OVERWRITTEN. Otherwise, data register may be potentially overwritten 01521 * by a new converted data as soon as OVR is cleared. 01522 * To reset OVR flag once the preserved data is retrieved, the user can resort 01523 * to macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 01524 * @retval HAL status 01525 */ 01526 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) 01527 { 01528 uint32_t tickstart = 0; 01529 01530 /* Check the parameters */ 01531 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01532 assert_param(IS_ADC_EVENT_TYPE(EventType)); 01533 01534 /* Get tick count */ 01535 tickstart = HAL_GetTick(); 01536 01537 /* Check selected event flag */ 01538 while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET) 01539 { 01540 /* Check if timeout is disabled (set to infinite wait) */ 01541 if(Timeout != HAL_MAX_DELAY) 01542 { 01543 if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout)) 01544 { 01545 /* Update ADC state machine to timeout */ 01546 SET_BIT(hadc->State, HAL_ADC_STATE_TIMEOUT); 01547 01548 /* Process unlocked */ 01549 __HAL_UNLOCK(hadc); 01550 01551 return HAL_TIMEOUT; 01552 } 01553 } 01554 } 01555 01556 switch(EventType) 01557 { 01558 /* End Of Sampling event */ 01559 case ADC_EOSMP_EVENT: 01560 /* Set ADC state */ 01561 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); 01562 01563 /* Clear the End Of Sampling flag */ 01564 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP); 01565 01566 break; 01567 01568 /* Analog watchdog (level out of window) event */ 01569 /* Note: In case of several analog watchdog enabled, if needed to know */ 01570 /* which one triggered and on which ADCx, test ADC state of analog watchdog */ 01571 /* flags HAL_ADC_STATE_AWD1/2/3 using function "HAL_ADC_GetState()". */ 01572 /* For example: */ 01573 /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)) " */ 01574 /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD2)) " */ 01575 /* " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD3)) " */ 01576 /* Check analog watchdog 1 flag */ 01577 case ADC_AWD_EVENT: 01578 /* Set ADC state */ 01579 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 01580 01581 /* Clear ADC analog watchdog flag */ 01582 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); 01583 01584 break; 01585 01586 /* Check analog watchdog 2 flag */ 01587 case ADC_AWD2_EVENT: 01588 /* Set ADC state */ 01589 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); 01590 01591 /* Clear ADC analog watchdog flag */ 01592 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); 01593 01594 break; 01595 01596 /* Check analog watchdog 3 flag */ 01597 case ADC_AWD3_EVENT: 01598 /* Set ADC state */ 01599 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); 01600 01601 /* Clear ADC analog watchdog flag */ 01602 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); 01603 01604 break; 01605 01606 /* Injected context queue overflow event */ 01607 case ADC_JQOVF_EVENT: 01608 /* Set ADC state */ 01609 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); 01610 01611 /* Set ADC error code to Injected context queue overflow */ 01612 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); 01613 01614 /* Clear ADC Injected context queue overflow flag */ 01615 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); 01616 01617 break; 01618 01619 /* Overrun event */ 01620 default: /* Case ADC_OVR_EVENT */ 01621 /* If overrun is set to overwrite previous data, overrun event is not */ 01622 /* considered as an error. */ 01623 /* (cf ref manual "Managing conversions without using the DMA and without */ 01624 /* overrun ") */ 01625 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) 01626 { 01627 /* Set ADC state */ 01628 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); 01629 01630 /* Set ADC error code to overrun */ 01631 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); 01632 } 01633 else 01634 { 01635 /* Clear ADC Overrun flag only if Overrun is set to ADC_OVR_DATA_OVERWRITTEN 01636 otherwise, data register is potentially overwritten by new converted data as soon 01637 as OVR is cleared. */ 01638 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 01639 } 01640 break; 01641 } 01642 01643 /* Return function status */ 01644 return HAL_OK; 01645 } 01646 01647 /** 01648 * @brief Enable ADC, start conversion of regular group with interruption. 01649 * @note Interruptions enabled in this function according to initialization 01650 * setting : EOC (end of conversion), EOS (end of sequence), 01651 * OVR overrun. 01652 * Each of these interruptions has its dedicated callback function. 01653 * @note Case of multimode enabled (when multimode feature is available): 01654 * HAL_ADC_Start_IT() must be called for ADC Slave first, then for 01655 * ADC Master. 01656 * For ADC Slave, ADC is enabled only (conversion is not started). 01657 * For ADC Master, ADC is enabled and multimode conversion is started. 01658 * @note To guarantee a proper reset of all interruptions once all the needed 01659 * conversions are obtained, HAL_ADC_Stop_IT() must be called to ensure 01660 * a correct stop of the IT-based conversions. 01661 * @note By default, HAL_ADC_Start_IT() does not enable the End Of Sampling 01662 * interruption. If required (e.g. in case of oversampling with trigger 01663 * mode), the user must: 01664 * 1. first clear the EOSMP flag if set with macro __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP) 01665 * 2. then enable the EOSMP interrupt with macro __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOSMP) 01666 * before calling HAL_ADC_Start_IT(). 01667 * @param hadc ADC handle 01668 * @retval HAL status 01669 */ 01670 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) 01671 { 01672 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01673 ADC_TypeDef *tmpADC_Master; 01674 01675 /* Check the parameters */ 01676 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01677 01678 /* Perform ADC enable and conversion start if no conversion is on going */ 01679 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 01680 { 01681 /* Process locked */ 01682 __HAL_LOCK(hadc); 01683 01684 /* Enable the ADC peripheral */ 01685 tmp_hal_status = ADC_Enable(hadc); 01686 01687 /* Start conversion if ADC is effectively enabled */ 01688 if (tmp_hal_status == HAL_OK) 01689 { 01690 /* Set ADC state */ 01691 /* - Clear state bitfield related to regular group conversion results */ 01692 /* - Set state bitfield related to regular operation */ 01693 ADC_STATE_CLR_SET(hadc->State, 01694 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, 01695 HAL_ADC_STATE_REG_BUSY); 01696 01697 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit 01698 - by default if ADC is Master or Independent or if multimode feature is not available 01699 - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ 01700 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 01701 { 01702 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 01703 } 01704 01705 /* Set ADC error code */ 01706 /* Check if a conversion is on going on ADC group injected */ 01707 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 01708 { 01709 /* Reset ADC error code fields related to regular conversions only */ 01710 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR|HAL_ADC_ERROR_DMA)); 01711 } 01712 else 01713 { 01714 /* Reset all ADC error code fields */ 01715 ADC_CLEAR_ERRORCODE(hadc); 01716 } 01717 01718 /* Clear ADC group regular conversion flag and overrun flag */ 01719 /* (To ensure of no unknown state from potential previous ADC operations) */ 01720 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 01721 01722 /* Process unlocked */ 01723 /* Unlock before starting ADC conversions: in case of potential */ 01724 /* interruption, to let the process to ADC IRQ Handler. */ 01725 __HAL_UNLOCK(hadc); 01726 01727 /* Disable all interruptions before enabling the desired ones */ 01728 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); 01729 01730 /* Enable ADC end of conversion interrupt */ 01731 switch(hadc->Init.EOCSelection) 01732 { 01733 case ADC_EOC_SEQ_CONV: 01734 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOS); 01735 break; 01736 /* case ADC_EOC_SINGLE_CONV */ 01737 default: 01738 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); 01739 break; 01740 } 01741 01742 /* Enable ADC overrun interrupt */ 01743 /* If hadc->Init.Overrun is set to ADC_OVR_DATA_PRESERVED, only then is 01744 ADC_IT_OVR enabled; otherwise data overwrite is considered as normal 01745 behavior and no CPU time is lost for a non-processed interruption */ 01746 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) 01747 { 01748 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 01749 } 01750 01751 /* Enable conversion of regular group. */ 01752 /* If software start has been selected, conversion starts immediately. */ 01753 /* If external trigger has been selected, conversion will start at next */ 01754 /* trigger event. */ 01755 /* Case of multimode enabled (when multimode feature is available): */ 01756 /* - if ADC is slave and dual regular conversions are enabled, ADC is */ 01757 /* enabled only (conversion is not started), */ 01758 /* - if ADC is master, ADC is enabled and conversion is started. */ 01759 if(ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) 01760 { 01761 /* Multimode feature is not available or ADC Instance is Independent or Master, 01762 or is not Slave ADC with dual regular conversions enabled. 01763 Then set HAL_ADC_STATE_INJ_BUSY and reset HAL_ADC_STATE_INJ_EOC if JAUTO is set. */ 01764 if (READ_BIT(hadc->Instance->CFGR, ADC_CFGR_JAUTO) != RESET) 01765 { 01766 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 01767 01768 /* Enable as well injected interruptions in case 01769 HAL_ADCEx_InjectedStart_IT() has not been called beforehand. This 01770 allows to start regular and injected conversions when JAUTO is 01771 set with a single call to HAL_ADC_Start_IT() */ 01772 switch(hadc->Init.EOCSelection) 01773 { 01774 case ADC_EOC_SEQ_CONV: 01775 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 01776 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); 01777 break; 01778 /* case ADC_EOC_SINGLE_CONV */ 01779 default: 01780 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); 01781 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); 01782 break; 01783 } 01784 } 01785 01786 /* Start ADC group regular conversion */ 01787 LL_ADC_REG_StartConversion(hadc->Instance); 01788 } 01789 else 01790 { 01791 /* hadc is the handle of a Slave ADC with dual regular conversions 01792 enabled. Therefore, ADC_CR_ADSTART is NOT set */ 01793 SET_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 01794 /* if Master ADC JAUTO bit is set, Slave injected interruptions 01795 are enabled nevertheless (for same reason as above) */ 01796 tmpADC_Master = ADC_MASTER_REGISTER(hadc); 01797 if (READ_BIT(tmpADC_Master->CFGR, ADC_CFGR_JAUTO) != RESET) 01798 { 01799 /* First, update Slave State in setting HAL_ADC_STATE_INJ_BUSY bit 01800 and in resetting HAL_ADC_STATE_INJ_EOC bit */ 01801 ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); 01802 /* Next, set Slave injected interruptions */ 01803 switch(hadc->Init.EOCSelection) 01804 { 01805 case ADC_EOC_SEQ_CONV: 01806 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); 01807 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOS); 01808 break; 01809 /* case ADC_EOC_SINGLE_CONV */ 01810 default: 01811 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOS); 01812 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC); 01813 break; 01814 } 01815 } 01816 } 01817 } 01818 else 01819 { 01820 /* Process unlocked */ 01821 __HAL_UNLOCK(hadc); 01822 } 01823 01824 } 01825 else 01826 { 01827 tmp_hal_status = HAL_BUSY; 01828 } 01829 01830 /* Return function status */ 01831 return tmp_hal_status; 01832 } 01833 01834 /** 01835 * @brief Stop ADC conversion of regular group (and injected group in 01836 * case of auto_injection mode), disable interrution of 01837 * end-of-conversion, disable ADC peripheral. 01838 * @param hadc ADC handle 01839 * @retval HAL status. 01840 */ 01841 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc) 01842 { 01843 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01844 01845 /* Check the parameters */ 01846 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01847 01848 /* Process locked */ 01849 __HAL_LOCK(hadc); 01850 01851 /* 1. Stop potential conversion on going, on ADC groups regular and injected */ 01852 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); 01853 01854 /* Disable ADC peripheral if conversions are effectively stopped */ 01855 if (tmp_hal_status == HAL_OK) 01856 { 01857 /* Disable ADC end of conversion interrupt for regular group */ 01858 /* Disable ADC overrun interrupt */ 01859 __HAL_ADC_DISABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_EOS | ADC_IT_OVR)); 01860 01861 /* 2. Disable the ADC peripheral */ 01862 tmp_hal_status = ADC_Disable(hadc); 01863 01864 /* Check if ADC is effectively disabled */ 01865 if (tmp_hal_status == HAL_OK) 01866 { 01867 /* Set ADC state */ 01868 ADC_STATE_CLR_SET(hadc->State, 01869 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 01870 HAL_ADC_STATE_READY); 01871 } 01872 } 01873 01874 /* Process unlocked */ 01875 __HAL_UNLOCK(hadc); 01876 01877 /* Return function status */ 01878 return tmp_hal_status; 01879 } 01880 01881 /** 01882 * @brief Enable ADC, start conversion of regular group and transfer result through DMA. 01883 * @note Interruptions enabled in this function: 01884 * overrun (if applicable), DMA half transfer, DMA transfer complete. 01885 * Each of these interruptions has its dedicated callback function. 01886 * @note Case of multimode enabled (when multimode feature is available): HAL_ADC_Start_DMA() 01887 * is designed for single-ADC mode only. For multimode, the dedicated 01888 * HAL_ADCEx_MultiModeStart_DMA() function must be used. 01889 * @param hadc ADC handle 01890 * @param pData Destination Buffer address. 01891 * @param Length Number of data to be transferred from ADC peripheral to memory 01892 * @retval HAL status. 01893 */ 01894 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) 01895 { 01896 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 01897 01898 /* Check the parameters */ 01899 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 01900 01901 /* Perform ADC enable and conversion start if no conversion is on going */ 01902 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 01903 { 01904 /* Process locked */ 01905 __HAL_LOCK(hadc); 01906 01907 /* Ensure that dual regular conversions are not enabled or unavailable. */ 01908 /* Otherwise, dedicated API HAL_ADCEx_MultiModeStart_DMA() must be used. */ 01909 if (ADC_IS_DUAL_REGULAR_CONVERSION_ENABLE(hadc) == RESET) 01910 { 01911 /* Enable the ADC peripheral */ 01912 tmp_hal_status = ADC_Enable(hadc); 01913 01914 /* Start conversion if ADC is effectively enabled */ 01915 if (tmp_hal_status == HAL_OK) 01916 { 01917 /* Set ADC state */ 01918 /* - Clear state bitfield related to regular group conversion results */ 01919 /* - Set state bitfield related to regular operation */ 01920 ADC_STATE_CLR_SET(hadc->State, 01921 HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR | HAL_ADC_STATE_REG_EOSMP, 01922 HAL_ADC_STATE_REG_BUSY); 01923 01924 /* Reset HAL_ADC_STATE_MULTIMODE_SLAVE bit 01925 - by default if ADC is Master or Independent or if multimode feature is not available 01926 - if multimode setting is set to independent mode (no dual regular or injected conversions are configured) */ 01927 if (ADC_NONMULTIMODE_OR_MULTIMODEMASTER(hadc)) 01928 { 01929 CLEAR_BIT(hadc->State, HAL_ADC_STATE_MULTIMODE_SLAVE); 01930 } 01931 01932 /* Check if a conversion is on going on ADC group injected */ 01933 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 01934 { 01935 /* Reset ADC error code fields related to regular conversions only */ 01936 CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); 01937 } 01938 else 01939 { 01940 /* Reset all ADC error code fields */ 01941 ADC_CLEAR_ERRORCODE(hadc); 01942 } 01943 01944 /* Set the DMA transfer complete callback */ 01945 hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; 01946 01947 /* Set the DMA half transfer complete callback */ 01948 hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; 01949 01950 /* Set the DMA error callback */ 01951 hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; 01952 01953 01954 /* Manage ADC and DMA start: ADC overrun interruption, DMA start, */ 01955 /* ADC start (in case of SW start): */ 01956 01957 /* Clear regular group conversion flag and overrun flag */ 01958 /* (To ensure of no unknown state from potential previous ADC */ 01959 /* operations) */ 01960 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS | ADC_FLAG_OVR)); 01961 01962 /* Process unlocked */ 01963 /* Unlock before starting ADC conversions: in case of potential */ 01964 /* interruption, to let the process to ADC IRQ Handler. */ 01965 __HAL_UNLOCK(hadc); 01966 01967 /* With DMA, overrun event is always considered as an error even if 01968 hadc->Init.Overrun is set to ADC_OVR_DATA_OVERWRITTEN. Therefore, 01969 ADC_IT_OVR is enabled. */ 01970 __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); 01971 01972 /* Enable ADC DMA mode */ 01973 SET_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 01974 01975 /* Start the DMA channel */ 01976 HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); 01977 01978 /* Enable conversion of regular group. */ 01979 /* If software start has been selected, conversion starts immediately. */ 01980 /* If external trigger has been selected, conversion will start at next */ 01981 /* trigger event. */ 01982 /* Start ADC group regular conversion */ 01983 LL_ADC_REG_StartConversion(hadc->Instance); 01984 } 01985 else 01986 { 01987 /* Process unlocked */ 01988 __HAL_UNLOCK(hadc); 01989 } 01990 } 01991 else 01992 { 01993 tmp_hal_status = HAL_ERROR; 01994 /* Process unlocked */ 01995 __HAL_UNLOCK(hadc); 01996 } 01997 } 01998 else 01999 { 02000 tmp_hal_status = HAL_BUSY; 02001 } 02002 02003 /* Return function status */ 02004 return tmp_hal_status; 02005 } 02006 02007 /** 02008 * @brief Stop ADC conversion of regular group (and injected group in 02009 * case of auto_injection mode), disable ADC DMA transfer, disable 02010 * ADC peripheral. 02011 * @note: ADC peripheral disable is forcing stop of potential 02012 * conversion on ADC group injected. If ADC group injected is under use, it 02013 * should be preliminarily stopped using HAL_ADCEx_InjectedStop function. 02014 * @note Case of multimode enabled (when multimode feature is available): 02015 * HAL_ADC_Stop_DMA() function is dedicated to single-ADC mode only. 02016 * For multimode, the dedicated HAL_ADCEx_MultiModeStop_DMA() API must be used. 02017 * @param hadc ADC handle 02018 * @retval HAL status. 02019 */ 02020 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc) 02021 { 02022 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 02023 02024 /* Check the parameters */ 02025 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 02026 02027 /* Process locked */ 02028 __HAL_LOCK(hadc); 02029 02030 /* 1. Stop potential ADC group regular conversion on going */ 02031 tmp_hal_status = ADC_ConversionStop(hadc, ADC_REGULAR_INJECTED_GROUP); 02032 02033 /* Disable ADC peripheral if conversions are effectively stopped */ 02034 if (tmp_hal_status == HAL_OK) 02035 { 02036 /* Disable ADC DMA (ADC DMA configuration of continous requests is kept) */ 02037 CLEAR_BIT(hadc->Instance->CFGR, ADC_CFGR_DMAEN); 02038 02039 /* Disable the DMA channel (in case of DMA in circular mode or stop */ 02040 /* while DMA transfer is on going) */ 02041 tmp_hal_status = HAL_DMA_Abort(hadc->DMA_Handle); 02042 02043 /* Check if DMA channel effectively disabled */ 02044 if (tmp_hal_status != HAL_OK) 02045 { 02046 /* Update ADC state machine to error */ 02047 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 02048 } 02049 02050 /* Disable ADC overrun interrupt */ 02051 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); 02052 02053 /* 2. Disable the ADC peripheral */ 02054 /* Update "tmp_hal_status" only if DMA channel disabling passed, to keep */ 02055 /* in memory a potential failing status. */ 02056 if (tmp_hal_status == HAL_OK) 02057 { 02058 tmp_hal_status = ADC_Disable(hadc); 02059 } 02060 else 02061 { 02062 ADC_Disable(hadc); 02063 } 02064 02065 /* Check if ADC is effectively disabled */ 02066 if (tmp_hal_status == HAL_OK) 02067 { 02068 /* Set ADC state */ 02069 ADC_STATE_CLR_SET(hadc->State, 02070 HAL_ADC_STATE_REG_BUSY | HAL_ADC_STATE_INJ_BUSY, 02071 HAL_ADC_STATE_READY); 02072 } 02073 02074 } 02075 02076 /* Process unlocked */ 02077 __HAL_UNLOCK(hadc); 02078 02079 /* Return function status */ 02080 return tmp_hal_status; 02081 } 02082 02083 /** 02084 * @brief Get ADC regular group conversion result. 02085 * @note Reading register DR automatically clears ADC flag EOC 02086 * (ADC group regular end of unitary conversion). 02087 * @note This function does not clear ADC flag EOS 02088 * (ADC group regular end of sequence conversion). 02089 * Occurrence of flag EOS rising: 02090 * - If sequencer is composed of 1 rank, flag EOS is equivalent 02091 * to flag EOC. 02092 * - If sequencer is composed of several ranks, during the scan 02093 * sequence flag EOC only is raised, at the end of the scan sequence 02094 * both flags EOC and EOS are raised. 02095 * To clear this flag, either use function: 02096 * in programming model IT: @ref HAL_ADC_IRQHandler(), in programming 02097 * model polling: @ref HAL_ADC_PollForConversion() 02098 * or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS). 02099 * @param hadc ADC handle 02100 * @retval ADC group regular conversion data 02101 */ 02102 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc) 02103 { 02104 /* Check the parameters */ 02105 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 02106 02107 /* Note: EOC flag is not cleared here by software because automatically */ 02108 /* cleared by hardware when reading register DR. */ 02109 02110 /* Return ADC converted value */ 02111 return hadc->Instance->DR; 02112 } 02113 02114 /** 02115 * @brief Handle ADC interrupt request. 02116 * @param hadc ADC handle 02117 * @retval None 02118 */ 02119 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) 02120 { 02121 uint32_t overrun_error = 0; /* flag set if overrun occurrence has to be considered as an error */ 02122 uint32_t tmp_isr = hadc->Instance->ISR; 02123 uint32_t tmp_ier = hadc->Instance->IER; 02124 uint32_t tmp_cfgr = 0x0; 02125 ADC_TypeDef *tmpADC_Master; 02126 02127 /* Check the parameters */ 02128 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 02129 assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection)); 02130 02131 /* ========== Check End of Sampling flag for ADC group regular ========== */ 02132 if(((tmp_isr & ADC_FLAG_EOSMP) == ADC_FLAG_EOSMP) && ((tmp_ier & ADC_IT_EOSMP) == ADC_IT_EOSMP)) 02133 { 02134 /* Update state machine on end of sampling status if not in error state */ 02135 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 02136 { 02137 /* Set ADC state */ 02138 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOSMP); 02139 } 02140 02141 /* End Of Sampling callback */ 02142 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 02143 hadc->EndOfSamplingCallback(hadc); 02144 #else 02145 HAL_ADCEx_EndOfSamplingCallback(hadc); 02146 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 02147 02148 /* Clear regular group conversion flag */ 02149 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOSMP ); 02150 } 02151 02152 /* ====== Check ADC group regular end of unitary conversion sequence conversions ===== */ 02153 if((((tmp_isr & ADC_FLAG_EOC) == ADC_FLAG_EOC) && ((tmp_ier & ADC_IT_EOC) == ADC_IT_EOC)) || 02154 (((tmp_isr & ADC_FLAG_EOS) == ADC_FLAG_EOS) && ((tmp_ier & ADC_IT_EOS) == ADC_IT_EOS)) ) 02155 { 02156 /* Update state machine on conversion status if not in error state */ 02157 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 02158 { 02159 /* Set ADC state */ 02160 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 02161 } 02162 02163 /* Determine whether any further conversion upcoming on group regular */ 02164 /* by external trigger, continuous mode or scan sequence on going */ 02165 /* to disable interruption. */ 02166 if(ADC_IS_SOFTWARE_START_REGULAR(hadc)) 02167 { 02168 /* Get relevant register CFGR in ADC instance of ADC master or slave */ 02169 /* in function of multimode state (for devices with multimode */ 02170 /* available). */ 02171 if (ADC_INDEPENDENT_OR_NONMULTIMODEREGULAR_SLAVE(hadc)) 02172 { 02173 /* check CONT bit directly in handle ADC CFGR register */ 02174 tmp_cfgr = READ_REG(hadc->Instance->CFGR); 02175 } 02176 else 02177 { 02178 /* else need to check Master ADC CONT bit */ 02179 tmpADC_Master = ADC_MASTER_REGISTER(hadc); 02180 tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 02181 } 02182 02183 /* Carry on if continuous mode is disabled */ 02184 if (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) != ADC_CFGR_CONT) 02185 { 02186 /* If End of Sequence is reached, disable interrupts */ 02187 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOS) ) 02188 { 02189 /* Allowed to modify bits ADC_IT_EOC/ADC_IT_EOS only if bit */ 02190 /* ADSTART==0 (no conversion on going) */ 02191 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 02192 { 02193 /* Disable ADC end of sequence conversion interrupt */ 02194 /* Note: Overrun interrupt was enabled with EOC interrupt in */ 02195 /* HAL_Start_IT(), but is not disabled here because can be used */ 02196 /* by overrun IRQ process below. */ 02197 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC | ADC_IT_EOS); 02198 02199 /* Set ADC state */ 02200 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 02201 02202 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 02203 { 02204 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 02205 } 02206 } 02207 else 02208 { 02209 /* Change ADC state to error state */ 02210 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 02211 02212 /* Set ADC error code to ADC IP internal error */ 02213 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 02214 } 02215 } 02216 } 02217 } 02218 02219 /* Conversion complete callback */ 02220 /* Note: Into callback function "HAL_ADC_ConvCpltCallback()", */ 02221 /* to determine if conversion has been triggered from EOC or EOS, */ 02222 /* possibility to use: */ 02223 /* " if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_EOS)) " */ 02224 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 02225 hadc->ConvCpltCallback(hadc); 02226 #else 02227 HAL_ADC_ConvCpltCallback(hadc); 02228 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 02229 02230 /* Clear regular group conversion flag */ 02231 /* Note: in case of overrun set to ADC_OVR_DATA_PRESERVED, end of */ 02232 /* conversion flags clear induces the release of the preserved data.*/ 02233 /* Therefore, if the preserved data value is needed, it must be */ 02234 /* read preliminarily into HAL_ADC_ConvCpltCallback(). */ 02235 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOC | ADC_FLAG_EOS) ); 02236 } 02237 02238 /* ====== Check ADC group injected end of unitary conversion sequence conversions ===== */ 02239 if( (((tmp_isr & ADC_FLAG_JEOC) == ADC_FLAG_JEOC) && ((tmp_ier & ADC_IT_JEOC) == ADC_IT_JEOC)) || 02240 (((tmp_isr & ADC_FLAG_JEOS) == ADC_FLAG_JEOS) && ((tmp_ier & ADC_IT_JEOS) == ADC_IT_JEOS)) ) 02241 { 02242 /* Update state machine on conversion status if not in error state */ 02243 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 02244 { 02245 /* Set ADC state */ 02246 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_EOC); 02247 } 02248 02249 /* Get relevant register CFGR in ADC instance of ADC master or slave */ 02250 /* in function of multimode state (for devices with multimode */ 02251 /* available). */ 02252 if (ADC_INDEPENDENT_OR_NONMULTIMODEINJECTED_SLAVE(hadc)) 02253 { 02254 tmp_cfgr = READ_REG(hadc->Instance->CFGR); 02255 } 02256 else 02257 { 02258 tmpADC_Master = ADC_MASTER_REGISTER(hadc); 02259 tmp_cfgr = READ_REG(tmpADC_Master->CFGR); 02260 } 02261 02262 /* Disable interruption if no further conversion upcoming by injected */ 02263 /* external trigger or by automatic injected conversion with regular */ 02264 /* group having no further conversion upcoming (same conditions as */ 02265 /* regular group interruption disabling above), */ 02266 /* and if injected scan sequence is completed. */ 02267 if(ADC_IS_SOFTWARE_START_INJECTED(hadc) || 02268 ((READ_BIT (tmp_cfgr, ADC_CFGR_JAUTO) == RESET) && 02269 (ADC_IS_SOFTWARE_START_REGULAR(hadc) && 02270 (READ_BIT (tmp_cfgr, ADC_CFGR_CONT) == RESET) ) ) ) 02271 { 02272 /* If End of Sequence is reached, disable interrupts */ 02273 if( __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS)) 02274 { 02275 /* Particular case if injected contexts queue is enabled: */ 02276 /* when the last context has been fully processed, JSQR is reset */ 02277 /* by the hardware. Even if no injected conversion is planned to come */ 02278 /* (queue empty, triggers are ignored), it can start again */ 02279 /* immediately after setting a new context (JADSTART is still set). */ 02280 /* Therefore, state of HAL ADC injected group is kept to busy. */ 02281 if(READ_BIT(tmp_cfgr, ADC_CFGR_JQM) == RESET) 02282 { 02283 /* Allowed to modify bits ADC_IT_JEOC/ADC_IT_JEOS only if bit */ 02284 /* JADSTART==0 (no conversion on going) */ 02285 if (ADC_IS_CONVERSION_ONGOING_INJECTED(hadc) == RESET) 02286 { 02287 /* Disable ADC end of sequence conversion interrupt */ 02288 __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC | ADC_IT_JEOS); 02289 02290 /* Set ADC state */ 02291 CLEAR_BIT(hadc->State, HAL_ADC_STATE_INJ_BUSY); 02292 02293 if (HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_REG_BUSY)) 02294 { 02295 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 02296 } 02297 } 02298 else 02299 { 02300 /* Update ADC state machine to error */ 02301 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 02302 02303 /* Set ADC error code to ADC IP internal error */ 02304 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 02305 } 02306 } 02307 } 02308 } 02309 02310 /* Injected Conversion complete callback */ 02311 /* Note: HAL_ADCEx_InjectedConvCpltCallback can resort to 02312 if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOS)) or 02313 if( __HAL_ADC_GET_FLAG(&hadc, ADC_FLAG_JEOC)) to determine whether 02314 interruption has been triggered by end of conversion or end of 02315 sequence. */ 02316 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 02317 hadc->InjectedConvCpltCallback(hadc); 02318 #else 02319 HAL_ADCEx_InjectedConvCpltCallback(hadc); 02320 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 02321 02322 /* Clear injected group conversion flag */ 02323 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC | ADC_FLAG_JEOS); 02324 } 02325 02326 /* ========== Check Analog watchdog 1 flag ========== */ 02327 if (((tmp_isr & ADC_FLAG_AWD1) == ADC_FLAG_AWD1) && ((tmp_ier & ADC_IT_AWD1) == ADC_IT_AWD1)) 02328 { 02329 /* Set ADC state */ 02330 SET_BIT(hadc->State, HAL_ADC_STATE_AWD1); 02331 02332 /* Level out of window 1 callback */ 02333 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 02334 hadc->LevelOutOfWindowCallback(hadc); 02335 #else 02336 HAL_ADC_LevelOutOfWindowCallback(hadc); 02337 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 02338 02339 /* Clear ADC analog watchdog flag */ 02340 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD1); 02341 } 02342 02343 /* ========== Check analog watchdog 2 flag ========== */ 02344 if (((tmp_isr & ADC_FLAG_AWD2) == ADC_FLAG_AWD2) && ((tmp_ier & ADC_IT_AWD2) == ADC_IT_AWD2)) 02345 { 02346 /* Set ADC state */ 02347 SET_BIT(hadc->State, HAL_ADC_STATE_AWD2); 02348 02349 /* Level out of window 2 callback */ 02350 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 02351 hadc->LevelOutOfWindow2Callback(hadc); 02352 #else 02353 HAL_ADCEx_LevelOutOfWindow2Callback(hadc); 02354 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 02355 02356 /* Clear ADC analog watchdog flag */ 02357 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD2); 02358 } 02359 02360 /* ========== Check analog watchdog 3 flag ========== */ 02361 if (((tmp_isr & ADC_FLAG_AWD3) == ADC_FLAG_AWD3) && ((tmp_ier & ADC_IT_AWD3) == ADC_IT_AWD3)) 02362 { 02363 /* Set ADC state */ 02364 SET_BIT(hadc->State, HAL_ADC_STATE_AWD3); 02365 02366 /* Level out of window 3 callback */ 02367 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 02368 hadc->LevelOutOfWindow3Callback(hadc); 02369 #else 02370 HAL_ADCEx_LevelOutOfWindow3Callback(hadc); 02371 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 02372 02373 /* Clear ADC analog watchdog flag */ 02374 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD3); 02375 } 02376 02377 /* ========== Check Overrun flag ========== */ 02378 if (((tmp_isr & ADC_FLAG_OVR) == ADC_FLAG_OVR) && ((tmp_ier & ADC_IT_OVR) == ADC_IT_OVR)) 02379 { 02380 /* If overrun is set to overwrite previous data (default setting), */ 02381 /* overrun event is not considered as an error. */ 02382 /* (cf ref manual "Managing conversions without using the DMA and without */ 02383 /* overrun ") */ 02384 /* Exception for usage with DMA overrun event always considered as an */ 02385 /* error. */ 02386 02387 if (hadc->Init.Overrun == ADC_OVR_DATA_PRESERVED) 02388 { 02389 overrun_error = 1; 02390 } 02391 else 02392 { 02393 /* Check DMA configuration */ 02394 if (ADC_IS_DUAL_CONVERSION_ENABLE(hadc) == RESET) 02395 { 02396 /* Multimode not set or feature not available or ADC independent */ 02397 if (HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_DMAEN)) 02398 { 02399 overrun_error = 1; 02400 } 02401 } 02402 else 02403 { 02404 /* Multimode (when feature is available) is enabled, 02405 Common Control Register MDMA bits must be checked. */ 02406 if (ADC_MULTIMODE_DMA_ENABLED(hadc)) 02407 { 02408 overrun_error = 1; 02409 } 02410 } 02411 } 02412 02413 if (overrun_error == 1) 02414 { 02415 /* Change ADC state to error state */ 02416 SET_BIT(hadc->State, HAL_ADC_STATE_REG_OVR); 02417 02418 /* Set ADC error code to overrun */ 02419 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_OVR); 02420 02421 /* Error callback */ 02422 /* Note: In case of overrun, ADC conversion data is preserved until */ 02423 /* flag OVR is reset. */ 02424 /* Therefore, old ADC conversion data can be retrieved in */ 02425 /* function "HAL_ADC_ErrorCallback()". */ 02426 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 02427 hadc->ErrorCallback(hadc); 02428 #else 02429 HAL_ADC_ErrorCallback(hadc); 02430 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 02431 } 02432 02433 /* Clear ADC overrun flag */ 02434 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR); 02435 } 02436 02437 /* ========== Check Injected context queue overflow flag ========== */ 02438 if (((tmp_isr & ADC_FLAG_JQOVF) == ADC_FLAG_JQOVF) && ((tmp_ier & ADC_IT_JQOVF) == ADC_IT_JQOVF)) 02439 { 02440 /* Change ADC state to overrun state */ 02441 SET_BIT(hadc->State, HAL_ADC_STATE_INJ_JQOVF); 02442 02443 /* Set ADC error code to Injected context queue overflow */ 02444 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_JQOVF); 02445 02446 /* Clear the Injected context queue overflow flag */ 02447 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JQOVF); 02448 02449 /* Injected context queue overflow callback */ 02450 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 02451 hadc->InjectedQueueOverflowCallback(hadc); 02452 #else 02453 HAL_ADCEx_InjectedQueueOverflowCallback(hadc); 02454 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 02455 } 02456 02457 } 02458 02459 /** 02460 * @brief Conversion complete callback in non-blocking mode. 02461 * @param hadc ADC handle 02462 * @retval None 02463 */ 02464 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc) 02465 { 02466 /* Prevent unused argument(s) compilation warning */ 02467 UNUSED(hadc); 02468 02469 /* NOTE : This function should not be modified. When the callback is needed, 02470 function HAL_ADC_ConvCpltCallback must be implemented in the user file. 02471 */ 02472 } 02473 02474 /** 02475 * @brief Conversion DMA half-transfer callback in non-blocking mode. 02476 * @param hadc ADC handle 02477 * @retval None 02478 */ 02479 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc) 02480 { 02481 /* Prevent unused argument(s) compilation warning */ 02482 UNUSED(hadc); 02483 02484 /* NOTE : This function should not be modified. When the callback is needed, 02485 function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file. 02486 */ 02487 } 02488 02489 /** 02490 * @brief Analog watchdog 1 callback in non-blocking mode. 02491 * @param hadc ADC handle 02492 * @retval None 02493 */ 02494 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc) 02495 { 02496 /* Prevent unused argument(s) compilation warning */ 02497 UNUSED(hadc); 02498 02499 /* NOTE : This function should not be modified. When the callback is needed, 02500 function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file. 02501 */ 02502 } 02503 02504 /** 02505 * @brief ADC error callback in non-blocking mode 02506 * (ADC conversion with interruption or transfer by DMA). 02507 * @note In case of error due to overrun when using ADC with DMA transfer 02508 * (HAL ADC handle paramater "ErrorCode" to state "HAL_ADC_ERROR_OVR"): 02509 * - Reinitialize the DMA using function "HAL_ADC_Stop_DMA()". 02510 * - If needed, restart a new ADC conversion using function 02511 * "HAL_ADC_Start_DMA()" 02512 * (this function is also clearing overrun flag) 02513 * @param hadc ADC handle 02514 * @retval None 02515 */ 02516 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc) 02517 { 02518 /* Prevent unused argument(s) compilation warning */ 02519 UNUSED(hadc); 02520 02521 /* NOTE : This function should not be modified. When the callback is needed, 02522 function HAL_ADC_ErrorCallback must be implemented in the user file. 02523 */ 02524 } 02525 02526 /** 02527 * @} 02528 */ 02529 02530 /** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions 02531 * @brief Peripheral Control functions 02532 * 02533 @verbatim 02534 =============================================================================== 02535 ##### Peripheral Control functions ##### 02536 =============================================================================== 02537 [..] This section provides functions allowing to: 02538 (+) Configure channels on regular group 02539 (+) Configure the analog watchdog 02540 02541 @endverbatim 02542 * @{ 02543 */ 02544 02545 /** 02546 * @brief Configure a channel to be assigned to ADC group regular. 02547 * @note In case of usage of internal measurement channels: 02548 * Vbat/VrefInt/TempSensor. 02549 * These internal paths can be disabled using function 02550 * HAL_ADC_DeInit(). 02551 * @note Possibility to update parameters on the fly: 02552 * This function initializes channel into ADC group regular, 02553 * following calls to this function can be used to reconfigure 02554 * some parameters of structure "ADC_ChannelConfTypeDef" on the fly, 02555 * without resetting the ADC. 02556 * The setting of these parameters is conditioned to ADC state: 02557 * Refer to comments of structure "ADC_ChannelConfTypeDef". 02558 * @param hadc ADC handle 02559 * @param sConfig Structure of ADC channel assigned to ADC group regular. 02560 * @retval HAL status 02561 */ 02562 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) 02563 { 02564 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 02565 uint32_t tmpOffsetShifted; 02566 __IO uint32_t wait_loop_index = 0; 02567 02568 /* Check the parameters */ 02569 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 02570 assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank)); 02571 assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime)); 02572 assert_param(IS_ADC_SINGLE_DIFFERENTIAL(sConfig->SingleDiff)); 02573 assert_param(IS_ADC_OFFSET_NUMBER(sConfig->OffsetNumber)); 02574 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), sConfig->Offset)); 02575 02576 /* if ROVSE is set, the value of the OFFSETy_EN bit in ADCx_OFRy register is 02577 ignored (considered as reset) */ 02578 assert_param(!((sConfig->OffsetNumber != ADC_OFFSET_NONE) && (hadc->Init.OversamplingMode == ENABLE))); 02579 02580 /* Verification of channel number */ 02581 if (sConfig->SingleDiff != ADC_DIFFERENTIAL_ENDED) 02582 { 02583 assert_param(IS_ADC_CHANNEL(hadc, sConfig->Channel)); 02584 } 02585 else 02586 { 02587 assert_param(IS_ADC_DIFF_CHANNEL(hadc, sConfig->Channel)); 02588 } 02589 02590 /* Process locked */ 02591 __HAL_LOCK(hadc); 02592 02593 /* Parameters update conditioned to ADC state: */ 02594 /* Parameters that can be updated when ADC is disabled or enabled without */ 02595 /* conversion on going on regular group: */ 02596 /* - Channel number */ 02597 /* - Channel rank */ 02598 if (ADC_IS_CONVERSION_ONGOING_REGULAR(hadc) == RESET) 02599 { 02600 #if !defined (USE_FULL_ASSERT) 02601 /* Correspondance for compatibility with legacy definition of */ 02602 /* sequencer ranks in direct number format. This correspondance can */ 02603 /* be done only on ranks 1 to 5 due to literal values. */ 02604 /* Note: Sequencer ranks in direct number format are no more used */ 02605 /* and are detected by activating USE_FULL_ASSERT feature. */ 02606 if (sConfig->Rank <= 5U) 02607 { 02608 switch (sConfig->Rank) 02609 { 02610 case 2U: sConfig->Rank = ADC_REGULAR_RANK_2; break; 02611 case 3U: sConfig->Rank = ADC_REGULAR_RANK_3; break; 02612 case 4U: sConfig->Rank = ADC_REGULAR_RANK_4; break; 02613 case 5U: sConfig->Rank = ADC_REGULAR_RANK_5; break; 02614 /* case 1U */ 02615 default: sConfig->Rank = ADC_REGULAR_RANK_1; 02616 } 02617 } 02618 #endif 02619 02620 /* Set ADC group regular sequence: channel on the selected scan sequence rank */ 02621 LL_ADC_REG_SetSequencerRanks(hadc->Instance, sConfig->Rank, sConfig->Channel); 02622 02623 /* Parameters update conditioned to ADC state: */ 02624 /* Parameters that can be updated when ADC is disabled or enabled without */ 02625 /* conversion on going on regular group: */ 02626 /* - Channel sampling time */ 02627 /* - Channel offset */ 02628 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) 02629 { 02630 #if defined(ADC_SMPR1_SMPPLUS) 02631 /* Manage specific case of sampling time 3.5 cycles replacing 2.5 cyles */ 02632 if(sConfig->SamplingTime == ADC_SAMPLETIME_3CYCLES_5) 02633 { 02634 /* Set sampling time of the selected ADC channel */ 02635 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, LL_ADC_SAMPLINGTIME_2CYCLES_5); 02636 02637 /* Set ADC sampling time common configuration */ 02638 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_3C5_REPL_2C5); 02639 } 02640 else 02641 { 02642 /* Set sampling time of the selected ADC channel */ 02643 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 02644 02645 /* Set ADC sampling time common configuration */ 02646 LL_ADC_SetSamplingTimeCommonConfig(hadc->Instance, LL_ADC_SAMPLINGTIME_COMMON_DEFAULT); 02647 } 02648 #else 02649 /* Set sampling time of the selected ADC channel */ 02650 LL_ADC_SetChannelSamplingTime(hadc->Instance, sConfig->Channel, sConfig->SamplingTime); 02651 #endif 02652 02653 /* Configure the offset: offset enable/disable, channel, offset value */ 02654 02655 /* Shift the offset with respect to the selected ADC resolution. */ 02656 /* Offset has to be left-aligned on bit 11, the LSB (right bits) are set to 0 */ 02657 tmpOffsetShifted = ADC_OFFSET_SHIFT_RESOLUTION(hadc, sConfig->Offset); 02658 02659 if(sConfig->OffsetNumber != ADC_OFFSET_NONE) 02660 { 02661 /* Set ADC selected offset number */ 02662 LL_ADC_SetOffset(hadc->Instance, sConfig->OffsetNumber, sConfig->Channel, tmpOffsetShifted); 02663 02664 } 02665 else 02666 { 02667 /* Scan each offset register to check if the selected channel is targeted. */ 02668 /* If this is the case, the corresponding offset number is disabled. */ 02669 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_1)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 02670 { 02671 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_1, LL_ADC_OFFSET_DISABLE); 02672 } 02673 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_2)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 02674 { 02675 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_2, LL_ADC_OFFSET_DISABLE); 02676 } 02677 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_3)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 02678 { 02679 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_3, LL_ADC_OFFSET_DISABLE); 02680 } 02681 if(__LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_GetOffsetChannel(hadc->Instance, LL_ADC_OFFSET_4)) == __LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel)) 02682 { 02683 LL_ADC_SetOffsetState(hadc->Instance, LL_ADC_OFFSET_4, LL_ADC_OFFSET_DISABLE); 02684 } 02685 } 02686 } 02687 02688 /* Parameters update conditioned to ADC state: */ 02689 /* Parameters that can be updated only when ADC is disabled: */ 02690 /* - Single or differential mode */ 02691 if (ADC_IS_ENABLE(hadc) == RESET) 02692 { 02693 /* Set mode single-ended or differential input of the selected ADC channel */ 02694 LL_ADC_SetChannelSingleDiff(hadc->Instance, sConfig->Channel, sConfig->SingleDiff); 02695 02696 /* Configuration of differential mode */ 02697 if (sConfig->SingleDiff == ADC_DIFFERENTIAL_ENDED) 02698 { 02699 /* Set sampling time of the selected ADC channel */ 02700 LL_ADC_SetChannelSamplingTime(hadc->Instance, __LL_ADC_DECIMAL_NB_TO_CHANNEL(__LL_ADC_CHANNEL_TO_DECIMAL_NB(sConfig->Channel) + 1), sConfig->SamplingTime); 02701 } 02702 02703 } 02704 02705 /* Management of internal measurement channels: Vbat/VrefInt/TempSensor. */ 02706 /* If internal channel selected, enable dedicated internal buffers and */ 02707 /* paths. */ 02708 /* Note: these internal measurement paths can be disabled using */ 02709 /* HAL_ADC_DeInit(). */ 02710 02711 /* Configuration of common ADC parameters */ 02712 /* If the requested internal measurement path has already been enabled, */ 02713 /* bypass the configuration processing. */ 02714 if (( (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) && 02715 ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_TEMPSENSOR) == 0U)) || 02716 ( (sConfig->Channel == ADC_CHANNEL_VBAT) && 02717 ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VBAT) == 0U)) || 02718 ( (sConfig->Channel == ADC_CHANNEL_VREFINT) && 02719 ((LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance)) & LL_ADC_PATH_INTERNAL_VREFINT) == 0U)) 02720 ) 02721 { 02722 /* Configuration of common ADC parameters (continuation) */ 02723 02724 if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) 02725 { 02726 if (ADC_TEMPERATURE_SENSOR_INSTANCE(hadc)) 02727 { 02728 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_TEMPSENSOR | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); 02729 02730 /* Delay for temperature sensor stabilization time */ 02731 /* Wait loop initialization and execution */ 02732 /* Note: Variable divided by 2 to compensate partially */ 02733 /* CPU processing cycles. */ 02734 wait_loop_index = (LL_ADC_DELAY_TEMPSENSOR_STAB_US * (SystemCoreClock / (1000000 * 2))); 02735 while(wait_loop_index != 0) 02736 { 02737 wait_loop_index--; 02738 } 02739 } 02740 } 02741 else if (sConfig->Channel == ADC_CHANNEL_VBAT) 02742 { 02743 if (ADC_BATTERY_VOLTAGE_INSTANCE(hadc)) 02744 { 02745 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VBAT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); 02746 } 02747 } 02748 else if (sConfig->Channel == ADC_CHANNEL_VREFINT) 02749 { 02750 if (ADC_VREFINT_INSTANCE(hadc)) 02751 { 02752 LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance), LL_ADC_PATH_INTERNAL_VREFINT | LL_ADC_GetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(hadc->Instance))); 02753 } 02754 } 02755 } 02756 } 02757 02758 /* If a conversion is on going on regular group, no update on regular */ 02759 /* channel could be done on neither of the channel configuration structure */ 02760 /* parameters. */ 02761 else 02762 { 02763 /* Update ADC state machine to error */ 02764 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 02765 02766 tmp_hal_status = HAL_ERROR; 02767 } 02768 02769 /* Process unlocked */ 02770 __HAL_UNLOCK(hadc); 02771 02772 /* Return function status */ 02773 return tmp_hal_status; 02774 } 02775 02776 /** 02777 * @brief Configure the analog watchdog. 02778 * @note Possibility to update parameters on the fly: 02779 * This function initializes the selected analog watchdog, successive 02780 * calls to this function can be used to reconfigure some parameters 02781 * of structure "ADC_AnalogWDGConfTypeDef" on the fly, without resetting 02782 * the ADC. 02783 * The setting of these parameters is conditioned to ADC state. 02784 * For parameters constraints, see comments of structure 02785 * "ADC_AnalogWDGConfTypeDef". 02786 * @note On this STM32 serie, analog watchdog thresholds cannot be modified 02787 * while ADC conversion is on going. 02788 * @param hadc ADC handle 02789 * @param AnalogWDGConfig Structure of ADC analog watchdog configuration 02790 * @retval HAL status 02791 */ 02792 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig) 02793 { 02794 HAL_StatusTypeDef tmp_hal_status = HAL_OK; 02795 uint32_t tmpAWDHighThresholdShifted = 0U; 02796 uint32_t tmpAWDLowThresholdShifted = 0U; 02797 02798 /* Check the parameters */ 02799 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 02800 assert_param(IS_ADC_ANALOG_WATCHDOG_NUMBER(AnalogWDGConfig->WatchdogNumber)); 02801 assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode)); 02802 assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode)); 02803 02804 if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG) || 02805 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || 02806 (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) ) 02807 { 02808 assert_param(IS_ADC_CHANNEL(hadc, AnalogWDGConfig->Channel)); 02809 } 02810 02811 /* Verify if threshold is within the selected ADC resolution */ 02812 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->HighThreshold)); 02813 assert_param(IS_ADC_RANGE(ADC_GET_RESOLUTION(hadc), AnalogWDGConfig->LowThreshold)); 02814 02815 /* Process locked */ 02816 __HAL_LOCK(hadc); 02817 02818 /* Parameters update conditioned to ADC state: */ 02819 /* Parameters that can be updated when ADC is disabled or enabled without */ 02820 /* conversion on going on ADC groups regular and injected: */ 02821 /* - Analog watchdog channels */ 02822 /* - Analog watchdog thresholds */ 02823 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc) == RESET) 02824 { 02825 /* Analog watchdog configuration */ 02826 if(AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_1) 02827 { 02828 /* Configuration of analog watchdog: */ 02829 /* - Set the analog watchdog enable mode: one or overall group of */ 02830 /* channels, on groups regular and-or injected. */ 02831 switch(AnalogWDGConfig->WatchdogMode) 02832 { 02833 case ADC_ANALOGWATCHDOG_SINGLE_REG: 02834 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR)); 02835 break; 02836 02837 case ADC_ANALOGWATCHDOG_SINGLE_INJEC: 02838 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_INJECTED)); 02839 break; 02840 02841 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: 02842 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, __LL_ADC_ANALOGWD_CHANNEL_GROUP(AnalogWDGConfig->Channel, LL_ADC_GROUP_REGULAR_INJECTED)); 02843 break; 02844 02845 case ADC_ANALOGWATCHDOG_ALL_REG: 02846 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG); 02847 break; 02848 02849 case ADC_ANALOGWATCHDOG_ALL_INJEC: 02850 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_INJ); 02851 break; 02852 02853 case ADC_ANALOGWATCHDOG_ALL_REGINJEC: 02854 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); 02855 break; 02856 02857 default: /* ADC_ANALOGWATCHDOG_NONE */ 02858 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, LL_ADC_AWD1, LL_ADC_AWD_DISABLE); 02859 break; 02860 } 02861 02862 /* Shift the offset in function of the selected ADC resolution: */ 02863 /* Thresholds have to be left-aligned on bit 11, the LSB (right bits) */ 02864 /* are set to 0 */ 02865 tmpAWDHighThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); 02866 tmpAWDLowThresholdShifted = ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); 02867 02868 /* Set ADC analog watchdog thresholds value of both thresholds high and low */ 02869 LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted); 02870 02871 /* Update state, clear previous result related to AWD1 */ 02872 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD1); 02873 02874 /* Clear flag ADC analog watchdog */ 02875 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ 02876 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ 02877 /* (in case left enabled by previous ADC operations). */ 02878 LL_ADC_ClearFlag_AWD1(hadc->Instance); 02879 02880 /* Configure ADC analog watchdog interrupt */ 02881 if(AnalogWDGConfig->ITMode == ENABLE) 02882 { 02883 LL_ADC_EnableIT_AWD1(hadc->Instance); 02884 } 02885 else 02886 { 02887 LL_ADC_DisableIT_AWD1(hadc->Instance); 02888 } 02889 } 02890 /* Case of ADC_ANALOGWATCHDOG_2 or ADC_ANALOGWATCHDOG_3 */ 02891 else 02892 { 02893 switch(AnalogWDGConfig->WatchdogMode) 02894 { 02895 case ADC_ANALOGWATCHDOG_SINGLE_REG: 02896 case ADC_ANALOGWATCHDOG_SINGLE_INJEC: 02897 case ADC_ANALOGWATCHDOG_SINGLE_REGINJEC: 02898 /* Update AWD by bitfield to keep the possibility to monitor */ 02899 /* several channels by successive calls of this function. */ 02900 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) 02901 { 02902 SET_BIT(hadc->Instance->AWD2CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); 02903 } 02904 else 02905 { 02906 SET_BIT(hadc->Instance->AWD3CR, (1U << __LL_ADC_CHANNEL_TO_DECIMAL_NB(AnalogWDGConfig->Channel))); 02907 } 02908 break; 02909 02910 case ADC_ANALOGWATCHDOG_ALL_REG: 02911 case ADC_ANALOGWATCHDOG_ALL_INJEC: 02912 case ADC_ANALOGWATCHDOG_ALL_REGINJEC: 02913 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_ALL_CHANNELS_REG_INJ); 02914 break; 02915 02916 default: /* ADC_ANALOGWATCHDOG_NONE */ 02917 LL_ADC_SetAnalogWDMonitChannels(hadc->Instance, AnalogWDGConfig->WatchdogNumber, LL_ADC_AWD_DISABLE); 02918 break; 02919 } 02920 02921 /* Shift the thresholds in function of the selected ADC resolution */ 02922 /* have to be left-aligned on bit 7, the LSB (right bits) are set to 0 */ 02923 tmpAWDHighThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->HighThreshold); 02924 tmpAWDLowThresholdShifted = ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(hadc, AnalogWDGConfig->LowThreshold); 02925 02926 /* Set ADC analog watchdog thresholds value of both thresholds high and low */ 02927 LL_ADC_ConfigAnalogWDThresholds(hadc->Instance, AnalogWDGConfig->WatchdogNumber, tmpAWDHighThresholdShifted, tmpAWDLowThresholdShifted); 02928 02929 if (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_2) 02930 { 02931 /* Update state, clear previous result related to AWD2 */ 02932 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD2); 02933 02934 /* Clear flag ADC analog watchdog */ 02935 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ 02936 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ 02937 /* (in case left enabled by previous ADC operations). */ 02938 LL_ADC_ClearFlag_AWD2(hadc->Instance); 02939 02940 /* Configure ADC analog watchdog interrupt */ 02941 if(AnalogWDGConfig->ITMode == ENABLE) 02942 { 02943 LL_ADC_EnableIT_AWD2(hadc->Instance); 02944 } 02945 else 02946 { 02947 LL_ADC_DisableIT_AWD2(hadc->Instance); 02948 } 02949 } 02950 /* (AnalogWDGConfig->WatchdogNumber == ADC_ANALOGWATCHDOG_3) */ 02951 else 02952 { 02953 /* Update state, clear previous result related to AWD3 */ 02954 CLEAR_BIT(hadc->State, HAL_ADC_STATE_AWD3); 02955 02956 /* Clear flag ADC analog watchdog */ 02957 /* Note: Flag cleared Clear the ADC Analog watchdog flag to be ready */ 02958 /* to use for HAL_ADC_IRQHandler() or HAL_ADC_PollForEvent() */ 02959 /* (in case left enabled by previous ADC operations). */ 02960 LL_ADC_ClearFlag_AWD3(hadc->Instance); 02961 02962 /* Configure ADC analog watchdog interrupt */ 02963 if(AnalogWDGConfig->ITMode == ENABLE) 02964 { 02965 LL_ADC_EnableIT_AWD3(hadc->Instance); 02966 } 02967 else 02968 { 02969 LL_ADC_DisableIT_AWD3(hadc->Instance); 02970 } 02971 } 02972 } 02973 02974 } 02975 /* If a conversion is on going on ADC group regular or injected, no update */ 02976 /* could be done on neither of the AWD configuration structure parameters. */ 02977 else 02978 { 02979 /* Update ADC state machine to error */ 02980 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_CONFIG); 02981 02982 tmp_hal_status = HAL_ERROR; 02983 } 02984 /* Process unlocked */ 02985 __HAL_UNLOCK(hadc); 02986 02987 /* Return function status */ 02988 return tmp_hal_status; 02989 } 02990 02991 02992 /** 02993 * @} 02994 */ 02995 02996 /** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions 02997 * @brief ADC Peripheral State functions 02998 * 02999 @verbatim 03000 =============================================================================== 03001 ##### Peripheral state and errors functions ##### 03002 =============================================================================== 03003 [..] 03004 This subsection provides functions to get in run-time the status of the 03005 peripheral. 03006 (+) Check the ADC state 03007 (+) Check the ADC error code 03008 03009 @endverbatim 03010 * @{ 03011 */ 03012 03013 /** 03014 * @brief Return the ADC handle state. 03015 * @note ADC state machine is managed by bitfields, ADC status must be 03016 * compared with states bits. 03017 * For example: 03018 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) " 03019 * " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1) ) " 03020 * @param hadc ADC handle 03021 * @retval ADC handle state (bitfield on 32 bits) 03022 */ 03023 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc) 03024 { 03025 /* Check the parameters */ 03026 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 03027 03028 /* Return ADC handle state */ 03029 return hadc->State; 03030 } 03031 03032 /** 03033 * @brief Return the ADC error code. 03034 * @param hadc ADC handle 03035 * @retval ADC error code (bitfield on 32 bits) 03036 */ 03037 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc) 03038 { 03039 /* Check the parameters */ 03040 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 03041 03042 return hadc->ErrorCode; 03043 } 03044 03045 /** 03046 * @} 03047 */ 03048 03049 /** 03050 * @} 03051 */ 03052 03053 /** @defgroup ADC_Private_Functions ADC Private Functions 03054 * @{ 03055 */ 03056 03057 /** 03058 * @brief Stop ADC conversion. 03059 * @param hadc ADC handle 03060 * @param ConversionGroup ADC group regular and/or injected. 03061 * This parameter can be one of the following values: 03062 * @arg @ref ADC_REGULAR_GROUP ADC regular conversion type. 03063 * @arg @ref ADC_INJECTED_GROUP ADC injected conversion type. 03064 * @arg @ref ADC_REGULAR_INJECTED_GROUP ADC regular and injected conversion type. 03065 * @retval HAL status. 03066 */ 03067 HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t ConversionGroup) 03068 { 03069 uint32_t tmp_ADC_CR_ADSTART_JADSTART = 0; 03070 uint32_t tickstart = 0; 03071 uint32_t Conversion_Timeout_CPU_cycles = 0; 03072 03073 /* Check the parameters */ 03074 assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); 03075 assert_param(IS_ADC_CONVERSION_GROUP(ConversionGroup)); 03076 03077 /* Verification if ADC is not already stopped (on regular and injected */ 03078 /* groups) to bypass this function if not needed. */ 03079 if (ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(hadc)) 03080 { 03081 /* Particular case of continuous auto-injection mode combined with */ 03082 /* auto-delay mode. */ 03083 /* In auto-injection mode, regular group stop ADC_CR_ADSTP is used (not */ 03084 /* injected group stop ADC_CR_JADSTP). */ 03085 /* Procedure to be followed: Wait until JEOS=1, clear JEOS, set ADSTP=1 */ 03086 /* (see reference manual). */ 03087 if ((HAL_IS_BIT_SET(hadc->Instance->CFGR, ADC_CFGR_JAUTO)) 03088 && (hadc->Init.ContinuousConvMode==ENABLE) 03089 && (hadc->Init.LowPowerAutoWait==ENABLE)) 03090 { 03091 /* Use stop of regular group */ 03092 ConversionGroup = ADC_REGULAR_GROUP; 03093 03094 /* Wait until JEOS=1 (maximum Timeout: 4 injected conversions) */ 03095 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOS) == RESET) 03096 { 03097 if (Conversion_Timeout_CPU_cycles >= (ADC_CONVERSION_TIME_MAX_CPU_CYCLES *4)) 03098 { 03099 /* Update ADC state machine to error */ 03100 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 03101 03102 /* Set ADC error code to ADC IP internal error */ 03103 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 03104 03105 return HAL_ERROR; 03106 } 03107 Conversion_Timeout_CPU_cycles ++; 03108 } 03109 03110 /* Clear JEOS */ 03111 __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOS); 03112 } 03113 03114 /* Stop potential conversion on going on regular group */ 03115 if (ConversionGroup != ADC_INJECTED_GROUP) 03116 { 03117 /* Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 */ 03118 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADSTART) && 03119 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) 03120 { 03121 /* Stop conversions on regular group */ 03122 LL_ADC_REG_StopConversion(hadc->Instance); 03123 } 03124 } 03125 03126 /* Stop potential conversion on going on injected group */ 03127 if (ConversionGroup != ADC_REGULAR_GROUP) 03128 { 03129 /* Software is allowed to set JADSTP only when JADSTART=1 and ADDIS=0 */ 03130 if (HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_JADSTART) && 03131 HAL_IS_BIT_CLR(hadc->Instance->CR, ADC_CR_ADDIS) ) 03132 { 03133 /* Stop conversions on injected group */ 03134 SET_BIT(hadc->Instance->CR, ADC_CR_JADSTP); 03135 } 03136 } 03137 03138 /* Selection of start and stop bits with respect to the regular or injected group */ 03139 switch(ConversionGroup) 03140 { 03141 case ADC_REGULAR_INJECTED_GROUP: 03142 tmp_ADC_CR_ADSTART_JADSTART = (ADC_CR_ADSTART | ADC_CR_JADSTART); 03143 break; 03144 case ADC_INJECTED_GROUP: 03145 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_JADSTART; 03146 break; 03147 /* Case ADC_REGULAR_GROUP only*/ 03148 default: 03149 tmp_ADC_CR_ADSTART_JADSTART = ADC_CR_ADSTART; 03150 break; 03151 } 03152 03153 /* Wait for conversion effectively stopped */ 03154 03155 03156 tickstart = HAL_GetTick(); 03157 03158 while((hadc->Instance->CR & tmp_ADC_CR_ADSTART_JADSTART) != RESET) 03159 { 03160 if((HAL_GetTick()-tickstart) > ADC_STOP_CONVERSION_TIMEOUT) 03161 { 03162 /* Update ADC state machine to error */ 03163 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 03164 03165 /* Set ADC error code to ADC IP internal error */ 03166 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 03167 03168 return HAL_ERROR; 03169 } 03170 } 03171 03172 } 03173 03174 /* Return HAL status */ 03175 return HAL_OK; 03176 } 03177 03178 03179 03180 /** 03181 * @brief Enable the selected ADC. 03182 * @note Prerequisite condition to use this function: ADC must be disabled 03183 * and voltage regulator must be enabled (done into HAL_ADC_Init()). 03184 * @param hadc ADC handle 03185 * @retval HAL status. 03186 */ 03187 HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc) 03188 { 03189 uint32_t tickstart = 0; 03190 __IO uint32_t wait_loop_index = 0; 03191 03192 /* ADC enable and wait for ADC ready (in case of ADC is disabled or */ 03193 /* enabling phase not yet completed: flag ADC ready not yet set). */ 03194 /* Timeout implemented to not be stuck if ADC cannot be enabled (possible */ 03195 /* causes: ADC clock not running, ...). */ 03196 if (ADC_IS_ENABLE(hadc) == RESET) 03197 { 03198 /* Check if conditions to enable the ADC are fulfilled */ 03199 if (ADC_ENABLING_CONDITIONS(hadc) == RESET) 03200 { 03201 /* Update ADC state machine to error */ 03202 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 03203 03204 /* Set ADC error code to ADC IP internal error */ 03205 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 03206 03207 return HAL_ERROR; 03208 } 03209 03210 /* Enable the ADC peripheral */ 03211 LL_ADC_Enable(hadc->Instance); 03212 03213 /* Delay for ADC stabilization time */ 03214 /* Wait loop initialization and execution */ 03215 /* Note: Variable divided by 2 to compensate partially */ 03216 /* CPU processing cycles. */ 03217 wait_loop_index = (LL_ADC_DELAY_INTERNAL_REGUL_STAB_US * (SystemCoreClock / (1000000 * 2))); 03218 while(wait_loop_index != 0) 03219 { 03220 wait_loop_index--; 03221 } 03222 03223 /* Wait for ADC effectively enabled */ 03224 tickstart = HAL_GetTick(); 03225 03226 while(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_RDY) == RESET) 03227 { 03228 /* If ADEN bit is set less than 4 ADC clock cycles after the ADCAL bit 03229 has been cleared (after a calibration), ADEN bit is reset by the 03230 calibration logic. 03231 The workaround is to continue setting ADEN until ADRDY is becomes 1. 03232 Additionally, ADC_ENABLE_TIMEOUT is defined to encompass this 03233 4 ADC clock cycle duration */ 03234 /* Note: Test of ADC enabled required due to hardware constraint to */ 03235 /* not enable ADC if already enabled. */ 03236 if(LL_ADC_IsEnabled(hadc->Instance) == 0) 03237 { 03238 LL_ADC_Enable(hadc->Instance); 03239 } 03240 03241 if((HAL_GetTick() - tickstart) > ADC_ENABLE_TIMEOUT) 03242 { 03243 /* Update ADC state machine to error */ 03244 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 03245 03246 /* Set ADC error code to ADC IP internal error */ 03247 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 03248 03249 return HAL_ERROR; 03250 } 03251 } 03252 } 03253 03254 /* Return HAL status */ 03255 return HAL_OK; 03256 } 03257 03258 /** 03259 * @brief Disable the selected ADC. 03260 * @note Prerequisite condition to use this function: ADC conversions must be 03261 * stopped. 03262 * @param hadc ADC handle 03263 * @retval HAL status. 03264 */ 03265 HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc) 03266 { 03267 uint32_t tickstart = 0; 03268 03269 /* Verification if ADC is not already disabled: */ 03270 /* Note: forbidden to disable ADC (set bit ADC_CR_ADDIS) if ADC is already */ 03271 /* disabled. */ 03272 if (ADC_IS_ENABLE(hadc) != RESET) 03273 { 03274 /* Check if conditions to disable the ADC are fulfilled */ 03275 if (ADC_DISABLING_CONDITIONS(hadc) != RESET) 03276 { 03277 /* Disable the ADC peripheral */ 03278 LL_ADC_Disable(hadc->Instance); 03279 __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_EOSMP | ADC_FLAG_RDY)); 03280 } 03281 else 03282 { 03283 /* Update ADC state machine to error */ 03284 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 03285 03286 /* Set ADC error code to ADC IP internal error */ 03287 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 03288 03289 return HAL_ERROR; 03290 } 03291 03292 /* Wait for ADC effectively disabled */ 03293 /* Get tick count */ 03294 tickstart = HAL_GetTick(); 03295 03296 while(HAL_IS_BIT_SET(hadc->Instance->CR, ADC_CR_ADEN)) 03297 { 03298 if((HAL_GetTick() - tickstart) > ADC_DISABLE_TIMEOUT) 03299 { 03300 /* Update ADC state machine to error */ 03301 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL); 03302 03303 /* Set ADC error code to ADC IP internal error */ 03304 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_INTERNAL); 03305 03306 return HAL_ERROR; 03307 } 03308 } 03309 } 03310 03311 /* Return HAL status */ 03312 return HAL_OK; 03313 } 03314 03315 /** 03316 * @brief DMA transfer complete callback. 03317 * @param hdma pointer to DMA handle. 03318 * @retval None 03319 */ 03320 void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma) 03321 { 03322 /* Retrieve ADC handle corresponding to current DMA handle */ 03323 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 03324 03325 /* Update state machine on conversion status if not in error state */ 03326 if(HAL_IS_BIT_CLR(hadc->State, (HAL_ADC_STATE_ERROR_INTERNAL | HAL_ADC_STATE_ERROR_DMA))) 03327 { 03328 /* Set ADC state */ 03329 SET_BIT(hadc->State, HAL_ADC_STATE_REG_EOC); 03330 03331 /* Determine whether any further conversion upcoming on group regular */ 03332 /* by external trigger, continuous mode or scan sequence on going */ 03333 /* to disable interruption. */ 03334 /* Is it the end of the regular sequence ? */ 03335 if(HAL_IS_BIT_SET(hadc->Instance->ISR, ADC_FLAG_EOS)) 03336 { 03337 /* Are conversions software-triggered ? */ 03338 if(ADC_IS_SOFTWARE_START_REGULAR(hadc)) 03339 { 03340 /* Is CONT bit set ? */ 03341 if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_CONT) == RESET) 03342 { 03343 /* CONT bit is not set, no more conversions expected */ 03344 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 03345 if(HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 03346 { 03347 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 03348 } 03349 } 03350 } 03351 } 03352 else 03353 { 03354 /* DMA End of Transfer interrupt was triggered but conversions sequence 03355 is not over. If DMACFG is set to 0, conversions are stopped. */ 03356 if(READ_BIT(hadc->Instance->CFGR, ADC_CFGR_DMACFG) == RESET) 03357 { 03358 /* DMACFG bit is not set, conversions are stopped. */ 03359 CLEAR_BIT(hadc->State, HAL_ADC_STATE_REG_BUSY); 03360 if(HAL_IS_BIT_CLR(hadc->State, HAL_ADC_STATE_INJ_BUSY)) 03361 { 03362 SET_BIT(hadc->State, HAL_ADC_STATE_READY); 03363 } 03364 } 03365 } 03366 03367 /* Conversion complete callback */ 03368 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 03369 hadc->ConvCpltCallback(hadc); 03370 #else 03371 HAL_ADC_ConvCpltCallback(hadc); 03372 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 03373 } 03374 else /* DMA and-or internal error occurred */ 03375 { 03376 if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_ERROR_INTERNAL)) 03377 { 03378 /* Call HAL ADC Error Callback function */ 03379 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 03380 hadc->ErrorCallback(hadc); 03381 #else 03382 HAL_ADC_ErrorCallback(hadc); 03383 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 03384 } 03385 else 03386 { 03387 /* Call ADC DMA error callback */ 03388 hadc->DMA_Handle->XferErrorCallback(hdma); 03389 } 03390 } 03391 } 03392 03393 /** 03394 * @brief DMA half transfer complete callback. 03395 * @param hdma pointer to DMA handle. 03396 * @retval None 03397 */ 03398 void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma) 03399 { 03400 /* Retrieve ADC handle corresponding to current DMA handle */ 03401 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 03402 03403 /* Half conversion callback */ 03404 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 03405 hadc->ConvHalfCpltCallback(hadc); 03406 #else 03407 HAL_ADC_ConvHalfCpltCallback(hadc); 03408 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 03409 } 03410 03411 /** 03412 * @brief DMA error callback. 03413 * @param hdma pointer to DMA handle. 03414 * @retval None 03415 */ 03416 void ADC_DMAError(DMA_HandleTypeDef *hdma) 03417 { 03418 /* Retrieve ADC handle corresponding to current DMA handle */ 03419 ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent; 03420 03421 /* Set ADC state */ 03422 SET_BIT(hadc->State, HAL_ADC_STATE_ERROR_DMA); 03423 03424 /* Set ADC error code to DMA error */ 03425 SET_BIT(hadc->ErrorCode, HAL_ADC_ERROR_DMA); 03426 03427 /* Error callback */ 03428 #if (USE_HAL_ADC_REGISTER_CALLBACKS == 1) 03429 hadc->ErrorCallback(hadc); 03430 #else 03431 HAL_ADC_ErrorCallback(hadc); 03432 #endif /* USE_HAL_ADC_REGISTER_CALLBACKS */ 03433 } 03434 03435 /** 03436 * @} 03437 */ 03438 03439 #endif /* HAL_ADC_MODULE_ENABLED */ 03440 /** 03441 * @} 03442 */ 03443 03444 /** 03445 * @} 03446 */ 03447 03448 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/