STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_tim.c 00004 * @author MCD Application Team 00005 * @brief TIM LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 #if defined(USE_FULL_LL_DRIVER) 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f4xx_ll_tim.h" 00039 #include "stm32f4xx_ll_bus.h" 00040 00041 #ifdef USE_FULL_ASSERT 00042 #include "stm32_assert.h" 00043 #else 00044 #define assert_param(expr) ((void)0U) 00045 #endif 00046 00047 /** @addtogroup STM32F4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) 00052 00053 /** @addtogroup TIM_LL 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /* Private constants ---------------------------------------------------------*/ 00060 /* Private macros ------------------------------------------------------------*/ 00061 /** @addtogroup TIM_LL_Private_Macros 00062 * @{ 00063 */ 00064 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ 00065 || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ 00066 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ 00067 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ 00068 || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) 00069 00070 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ 00071 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ 00072 || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) 00073 00074 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ 00075 || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ 00076 || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ 00077 || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ 00078 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ 00079 || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ 00080 || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ 00081 || ((__VALUE__) == LL_TIM_OCMODE_PWM2)) 00082 00083 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ 00084 || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) 00085 00086 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ 00087 || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) 00088 00089 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ 00090 || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) 00091 00092 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ 00093 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ 00094 || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) 00095 00096 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ 00097 || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ 00098 || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ 00099 || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) 00100 00101 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ 00102 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ 00103 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ 00104 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ 00105 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ 00106 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ 00107 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ 00108 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ 00109 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ 00110 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ 00111 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ 00112 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ 00113 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ 00114 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ 00115 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ 00116 || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) 00117 00118 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ 00119 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \ 00120 || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE)) 00121 00122 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ 00123 || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ 00124 || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) 00125 00126 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ 00127 || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) 00128 00129 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ 00130 || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) 00131 00132 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ 00133 || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) 00134 00135 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ 00136 || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ 00137 || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ 00138 || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) 00139 00140 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ 00141 || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) 00142 00143 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ 00144 || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) 00145 00146 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ 00147 || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) 00148 /** 00149 * @} 00150 */ 00151 00152 00153 /* Private function prototypes -----------------------------------------------*/ 00154 /** @defgroup TIM_LL_Private_Functions TIM Private Functions 00155 * @{ 00156 */ 00157 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); 00158 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); 00159 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); 00160 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); 00161 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 00162 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 00163 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 00164 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); 00165 /** 00166 * @} 00167 */ 00168 00169 /* Exported functions --------------------------------------------------------*/ 00170 /** @addtogroup TIM_LL_Exported_Functions 00171 * @{ 00172 */ 00173 00174 /** @addtogroup TIM_LL_EF_Init 00175 * @{ 00176 */ 00177 00178 /** 00179 * @brief Set TIMx registers to their reset values. 00180 * @param TIMx Timer instance 00181 * @retval An ErrorStatus enumeration value: 00182 * - SUCCESS: TIMx registers are de-initialized 00183 * - ERROR: invalid TIMx instance 00184 */ 00185 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) 00186 { 00187 ErrorStatus result = SUCCESS; 00188 00189 /* Check the parameters */ 00190 assert_param(IS_TIM_INSTANCE(TIMx)); 00191 00192 if (TIMx == TIM1) 00193 { 00194 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1); 00195 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1); 00196 } 00197 #if defined(TIM2) 00198 else if (TIMx == TIM2) 00199 { 00200 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); 00201 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); 00202 } 00203 #endif 00204 #if defined(TIM3) 00205 else if (TIMx == TIM3) 00206 { 00207 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); 00208 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); 00209 } 00210 #endif 00211 #if defined(TIM4) 00212 else if (TIMx == TIM4) 00213 { 00214 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); 00215 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); 00216 } 00217 #endif 00218 #if defined(TIM5) 00219 else if (TIMx == TIM5) 00220 { 00221 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); 00222 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); 00223 } 00224 #endif 00225 #if defined(TIM6) 00226 else if (TIMx == TIM6) 00227 { 00228 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); 00229 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); 00230 } 00231 #endif 00232 #if defined (TIM7) 00233 else if (TIMx == TIM7) 00234 { 00235 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); 00236 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); 00237 } 00238 #endif 00239 #if defined(TIM8) 00240 else if (TIMx == TIM8) 00241 { 00242 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8); 00243 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8); 00244 } 00245 #endif 00246 #if defined(TIM9) 00247 else if (TIMx == TIM9) 00248 { 00249 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9); 00250 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9); 00251 } 00252 #endif 00253 #if defined(TIM10) 00254 else if (TIMx == TIM10) 00255 { 00256 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10); 00257 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10); 00258 } 00259 #endif 00260 #if defined(TIM11) 00261 else if (TIMx == TIM11) 00262 { 00263 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11); 00264 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11); 00265 } 00266 #endif 00267 #if defined(TIM12) 00268 else if (TIMx == TIM12) 00269 { 00270 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); 00271 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); 00272 } 00273 #endif 00274 #if defined(TIM13) 00275 else if (TIMx == TIM13) 00276 { 00277 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); 00278 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); 00279 } 00280 #endif 00281 #if defined(TIM14) 00282 else if (TIMx == TIM14) 00283 { 00284 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14); 00285 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14); 00286 } 00287 #endif 00288 else 00289 { 00290 result = ERROR; 00291 } 00292 00293 return result; 00294 } 00295 00296 /** 00297 * @brief Set the fields of the time base unit configuration data structure 00298 * to their default values. 00299 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) 00300 * @retval None 00301 */ 00302 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) 00303 { 00304 /* Set the default configuration */ 00305 TIM_InitStruct->Prescaler = (uint16_t)0x0000U; 00306 TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; 00307 TIM_InitStruct->Autoreload = 0xFFFFFFFFU; 00308 TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; 00309 TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U; 00310 } 00311 00312 /** 00313 * @brief Configure the TIMx time base unit. 00314 * @param TIMx Timer Instance 00315 * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) 00316 * @retval An ErrorStatus enumeration value: 00317 * - SUCCESS: TIMx registers are de-initialized 00318 * - ERROR: not applicable 00319 */ 00320 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) 00321 { 00322 uint32_t tmpcr1 = 0U; 00323 00324 /* Check the parameters */ 00325 assert_param(IS_TIM_INSTANCE(TIMx)); 00326 assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); 00327 assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); 00328 00329 tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); 00330 00331 if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) 00332 { 00333 /* Select the Counter Mode */ 00334 MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); 00335 } 00336 00337 if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) 00338 { 00339 /* Set the clock division */ 00340 MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); 00341 } 00342 00343 /* Write to TIMx CR1 */ 00344 LL_TIM_WriteReg(TIMx, CR1, tmpcr1); 00345 00346 /* Set the Autoreload value */ 00347 LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); 00348 00349 /* Set the Prescaler value */ 00350 LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); 00351 00352 if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) 00353 { 00354 /* Set the Repetition Counter value */ 00355 LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); 00356 } 00357 00358 /* Generate an update event to reload the Prescaler 00359 and the repetition counter value (if applicable) immediately */ 00360 LL_TIM_GenerateEvent_UPDATE(TIMx); 00361 00362 return SUCCESS; 00363 } 00364 00365 /** 00366 * @brief Set the fields of the TIMx output channel configuration data 00367 * structure to their default values. 00368 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) 00369 * @retval None 00370 */ 00371 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) 00372 { 00373 /* Set the default configuration */ 00374 TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; 00375 TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; 00376 TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; 00377 TIM_OC_InitStruct->CompareValue = 0x00000000U; 00378 TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; 00379 TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; 00380 TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; 00381 TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; 00382 } 00383 00384 /** 00385 * @brief Configure the TIMx output channel. 00386 * @param TIMx Timer Instance 00387 * @param Channel This parameter can be one of the following values: 00388 * @arg @ref LL_TIM_CHANNEL_CH1 00389 * @arg @ref LL_TIM_CHANNEL_CH2 00390 * @arg @ref LL_TIM_CHANNEL_CH3 00391 * @arg @ref LL_TIM_CHANNEL_CH4 00392 * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) 00393 * @retval An ErrorStatus enumeration value: 00394 * - SUCCESS: TIMx output channel is initialized 00395 * - ERROR: TIMx output channel is not initialized 00396 */ 00397 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) 00398 { 00399 ErrorStatus result = ERROR; 00400 00401 switch (Channel) 00402 { 00403 case LL_TIM_CHANNEL_CH1: 00404 result = OC1Config(TIMx, TIM_OC_InitStruct); 00405 break; 00406 case LL_TIM_CHANNEL_CH2: 00407 result = OC2Config(TIMx, TIM_OC_InitStruct); 00408 break; 00409 case LL_TIM_CHANNEL_CH3: 00410 result = OC3Config(TIMx, TIM_OC_InitStruct); 00411 break; 00412 case LL_TIM_CHANNEL_CH4: 00413 result = OC4Config(TIMx, TIM_OC_InitStruct); 00414 break; 00415 default: 00416 break; 00417 } 00418 00419 return result; 00420 } 00421 00422 /** 00423 * @brief Set the fields of the TIMx input channel configuration data 00424 * structure to their default values. 00425 * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) 00426 * @retval None 00427 */ 00428 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) 00429 { 00430 /* Set the default configuration */ 00431 TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; 00432 TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; 00433 TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; 00434 TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; 00435 } 00436 00437 /** 00438 * @brief Configure the TIMx input channel. 00439 * @param TIMx Timer Instance 00440 * @param Channel This parameter can be one of the following values: 00441 * @arg @ref LL_TIM_CHANNEL_CH1 00442 * @arg @ref LL_TIM_CHANNEL_CH2 00443 * @arg @ref LL_TIM_CHANNEL_CH3 00444 * @arg @ref LL_TIM_CHANNEL_CH4 00445 * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) 00446 * @retval An ErrorStatus enumeration value: 00447 * - SUCCESS: TIMx output channel is initialized 00448 * - ERROR: TIMx output channel is not initialized 00449 */ 00450 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) 00451 { 00452 ErrorStatus result = ERROR; 00453 00454 switch (Channel) 00455 { 00456 case LL_TIM_CHANNEL_CH1: 00457 result = IC1Config(TIMx, TIM_IC_InitStruct); 00458 break; 00459 case LL_TIM_CHANNEL_CH2: 00460 result = IC2Config(TIMx, TIM_IC_InitStruct); 00461 break; 00462 case LL_TIM_CHANNEL_CH3: 00463 result = IC3Config(TIMx, TIM_IC_InitStruct); 00464 break; 00465 case LL_TIM_CHANNEL_CH4: 00466 result = IC4Config(TIMx, TIM_IC_InitStruct); 00467 break; 00468 default: 00469 break; 00470 } 00471 00472 return result; 00473 } 00474 00475 /** 00476 * @brief Fills each TIM_EncoderInitStruct field with its default value 00477 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) 00478 * @retval None 00479 */ 00480 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) 00481 { 00482 /* Set the default configuration */ 00483 TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; 00484 TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; 00485 TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; 00486 TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; 00487 TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; 00488 TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; 00489 TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; 00490 TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; 00491 TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; 00492 } 00493 00494 /** 00495 * @brief Configure the encoder interface of the timer instance. 00496 * @param TIMx Timer Instance 00497 * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) 00498 * @retval An ErrorStatus enumeration value: 00499 * - SUCCESS: TIMx registers are de-initialized 00500 * - ERROR: not applicable 00501 */ 00502 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) 00503 { 00504 uint32_t tmpccmr1 = 0U; 00505 uint32_t tmpccer = 0U; 00506 00507 /* Check the parameters */ 00508 assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); 00509 assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); 00510 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); 00511 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); 00512 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); 00513 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); 00514 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); 00515 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); 00516 assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); 00517 assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); 00518 00519 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ 00520 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); 00521 00522 /* Get the TIMx CCMR1 register value */ 00523 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00524 00525 /* Get the TIMx CCER register value */ 00526 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00527 00528 /* Configure TI1 */ 00529 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); 00530 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); 00531 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); 00532 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); 00533 00534 /* Configure TI2 */ 00535 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); 00536 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); 00537 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); 00538 tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); 00539 00540 /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ 00541 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); 00542 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); 00543 tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); 00544 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); 00545 00546 /* Set encoder mode */ 00547 LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); 00548 00549 /* Write to TIMx CCMR1 */ 00550 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00551 00552 /* Write to TIMx CCER */ 00553 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00554 00555 return SUCCESS; 00556 } 00557 00558 /** 00559 * @brief Set the fields of the TIMx Hall sensor interface configuration data 00560 * structure to their default values. 00561 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) 00562 * @retval None 00563 */ 00564 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) 00565 { 00566 /* Set the default configuration */ 00567 TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; 00568 TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; 00569 TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; 00570 TIM_HallSensorInitStruct->CommutationDelay = 0U; 00571 } 00572 00573 /** 00574 * @brief Configure the Hall sensor interface of the timer instance. 00575 * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR 00576 * to the TI1 input channel 00577 * @note TIMx slave mode controller is configured in reset mode. 00578 Selected internal trigger is TI1F_ED. 00579 * @note Channel 1 is configured as input, IC1 is mapped on TRC. 00580 * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed 00581 * between 2 changes on the inputs. It gives information about motor speed. 00582 * @note Channel 2 is configured in output PWM 2 mode. 00583 * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. 00584 * @note OC2REF is selected as trigger output on TRGO. 00585 * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used 00586 * when TIMx operates in Hall sensor interface mode. 00587 * @param TIMx Timer Instance 00588 * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) 00589 * @retval An ErrorStatus enumeration value: 00590 * - SUCCESS: TIMx registers are de-initialized 00591 * - ERROR: not applicable 00592 */ 00593 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) 00594 { 00595 uint32_t tmpcr2 = 0U; 00596 uint32_t tmpccmr1 = 0U; 00597 uint32_t tmpccer = 0U; 00598 uint32_t tmpsmcr = 0U; 00599 00600 /* Check the parameters */ 00601 assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); 00602 assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); 00603 assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); 00604 assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); 00605 00606 /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ 00607 TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); 00608 00609 /* Get the TIMx CR2 register value */ 00610 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00611 00612 /* Get the TIMx CCMR1 register value */ 00613 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00614 00615 /* Get the TIMx CCER register value */ 00616 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00617 00618 /* Get the TIMx SMCR register value */ 00619 tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); 00620 00621 /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ 00622 tmpcr2 |= TIM_CR2_TI1S; 00623 00624 /* OC2REF signal is used as trigger output (TRGO) */ 00625 tmpcr2 |= LL_TIM_TRGO_OC2REF; 00626 00627 /* Configure the slave mode controller */ 00628 tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); 00629 tmpsmcr |= LL_TIM_TS_TI1F_ED; 00630 tmpsmcr |= LL_TIM_SLAVEMODE_RESET; 00631 00632 /* Configure input channel 1 */ 00633 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); 00634 tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); 00635 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); 00636 tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); 00637 00638 /* Configure input channel 2 */ 00639 tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); 00640 tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); 00641 00642 /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ 00643 tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); 00644 tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); 00645 tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); 00646 00647 /* Write to TIMx CR2 */ 00648 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00649 00650 /* Write to TIMx SMCR */ 00651 LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); 00652 00653 /* Write to TIMx CCMR1 */ 00654 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00655 00656 /* Write to TIMx CCER */ 00657 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00658 00659 /* Write to TIMx CCR2 */ 00660 LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); 00661 00662 return SUCCESS; 00663 } 00664 00665 /** 00666 * @brief Set the fields of the Break and Dead Time configuration data structure 00667 * to their default values. 00668 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) 00669 * @retval None 00670 */ 00671 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) 00672 { 00673 /* Set the default configuration */ 00674 TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; 00675 TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; 00676 TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; 00677 TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00U; 00678 TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; 00679 TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; 00680 TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; 00681 } 00682 00683 /** 00684 * @brief Configure the Break and Dead Time feature of the timer instance. 00685 * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked 00686 * depending on the LOCK configuration, it can be necessary to configure all of 00687 * them during the first write access to the TIMx_BDTR register. 00688 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not 00689 * a timer instance provides a break input. 00690 * @param TIMx Timer Instance 00691 * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure(Break and Dead Time configuration data structure) 00692 * @retval An ErrorStatus enumeration value: 00693 * - SUCCESS: Break and Dead Time is initialized 00694 * - ERROR: not applicable 00695 */ 00696 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) 00697 { 00698 uint32_t tmpbdtr = 0; 00699 00700 /* Check the parameters */ 00701 assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); 00702 assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); 00703 assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); 00704 assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); 00705 assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); 00706 assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); 00707 assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); 00708 00709 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, 00710 the OSSI State, the dead time value and the Automatic Output Enable Bit */ 00711 00712 /* Set the BDTR bits */ 00713 MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); 00714 MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); 00715 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); 00716 MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); 00717 MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); 00718 MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); 00719 MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); 00720 MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); 00721 00722 /* Set TIMx_BDTR */ 00723 LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); 00724 00725 return SUCCESS; 00726 } 00727 /** 00728 * @} 00729 */ 00730 00731 /** 00732 * @} 00733 */ 00734 00735 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions 00736 * @brief Private functions 00737 * @{ 00738 */ 00739 /** 00740 * @brief Configure the TIMx output channel 1. 00741 * @param TIMx Timer Instance 00742 * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure 00743 * @retval An ErrorStatus enumeration value: 00744 * - SUCCESS: TIMx registers are de-initialized 00745 * - ERROR: not applicable 00746 */ 00747 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) 00748 { 00749 uint32_t tmpccmr1 = 0U; 00750 uint32_t tmpccer = 0U; 00751 uint32_t tmpcr2 = 0U; 00752 00753 /* Check the parameters */ 00754 assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 00755 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); 00756 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); 00757 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); 00758 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); 00759 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); 00760 00761 /* Disable the Channel 1: Reset the CC1E Bit */ 00762 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); 00763 00764 /* Get the TIMx CCER register value */ 00765 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00766 00767 /* Get the TIMx CR2 register value */ 00768 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00769 00770 /* Get the TIMx CCMR1 register value */ 00771 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00772 00773 /* Reset Capture/Compare selection Bits */ 00774 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); 00775 00776 /* Set the Output Compare Mode */ 00777 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); 00778 00779 /* Set the Output Compare Polarity */ 00780 MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); 00781 00782 /* Set the Output State */ 00783 MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); 00784 00785 if (IS_TIM_BREAK_INSTANCE(TIMx)) 00786 { 00787 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); 00788 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); 00789 00790 /* Set the complementary output Polarity */ 00791 MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); 00792 00793 /* Set the complementary output State */ 00794 MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); 00795 00796 /* Set the Output Idle state */ 00797 MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); 00798 00799 /* Set the complementary output Idle state */ 00800 MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); 00801 } 00802 00803 /* Write to TIMx CR2 */ 00804 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00805 00806 /* Write to TIMx CCMR1 */ 00807 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00808 00809 /* Set the Capture Compare Register value */ 00810 LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); 00811 00812 /* Write to TIMx CCER */ 00813 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00814 00815 return SUCCESS; 00816 } 00817 00818 /** 00819 * @brief Configure the TIMx output channel 2. 00820 * @param TIMx Timer Instance 00821 * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure 00822 * @retval An ErrorStatus enumeration value: 00823 * - SUCCESS: TIMx registers are de-initialized 00824 * - ERROR: not applicable 00825 */ 00826 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) 00827 { 00828 uint32_t tmpccmr1 = 0U; 00829 uint32_t tmpccer = 0U; 00830 uint32_t tmpcr2 = 0U; 00831 00832 /* Check the parameters */ 00833 assert_param(IS_TIM_CC2_INSTANCE(TIMx)); 00834 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); 00835 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); 00836 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); 00837 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); 00838 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); 00839 00840 /* Disable the Channel 2: Reset the CC2E Bit */ 00841 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); 00842 00843 /* Get the TIMx CCER register value */ 00844 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00845 00846 /* Get the TIMx CR2 register value */ 00847 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00848 00849 /* Get the TIMx CCMR1 register value */ 00850 tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); 00851 00852 /* Reset Capture/Compare selection Bits */ 00853 CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); 00854 00855 /* Select the Output Compare Mode */ 00856 MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); 00857 00858 /* Set the Output Compare Polarity */ 00859 MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); 00860 00861 /* Set the Output State */ 00862 MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); 00863 00864 if (IS_TIM_BREAK_INSTANCE(TIMx)) 00865 { 00866 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); 00867 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); 00868 00869 /* Set the complementary output Polarity */ 00870 MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); 00871 00872 /* Set the complementary output State */ 00873 MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); 00874 00875 /* Set the Output Idle state */ 00876 MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); 00877 00878 /* Set the complementary output Idle state */ 00879 MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); 00880 } 00881 00882 /* Write to TIMx CR2 */ 00883 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00884 00885 /* Write to TIMx CCMR1 */ 00886 LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); 00887 00888 /* Set the Capture Compare Register value */ 00889 LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); 00890 00891 /* Write to TIMx CCER */ 00892 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00893 00894 return SUCCESS; 00895 } 00896 00897 /** 00898 * @brief Configure the TIMx output channel 3. 00899 * @param TIMx Timer Instance 00900 * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure 00901 * @retval An ErrorStatus enumeration value: 00902 * - SUCCESS: TIMx registers are de-initialized 00903 * - ERROR: not applicable 00904 */ 00905 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) 00906 { 00907 uint32_t tmpccmr2 = 0U; 00908 uint32_t tmpccer = 0U; 00909 uint32_t tmpcr2 = 0U; 00910 00911 /* Check the parameters */ 00912 assert_param(IS_TIM_CC3_INSTANCE(TIMx)); 00913 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); 00914 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); 00915 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); 00916 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); 00917 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); 00918 00919 /* Disable the Channel 3: Reset the CC3E Bit */ 00920 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); 00921 00922 /* Get the TIMx CCER register value */ 00923 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 00924 00925 /* Get the TIMx CR2 register value */ 00926 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 00927 00928 /* Get the TIMx CCMR2 register value */ 00929 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); 00930 00931 /* Reset Capture/Compare selection Bits */ 00932 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); 00933 00934 /* Select the Output Compare Mode */ 00935 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); 00936 00937 /* Set the Output Compare Polarity */ 00938 MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); 00939 00940 /* Set the Output State */ 00941 MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); 00942 00943 if (IS_TIM_BREAK_INSTANCE(TIMx)) 00944 { 00945 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); 00946 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); 00947 00948 /* Set the complementary output Polarity */ 00949 MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); 00950 00951 /* Set the complementary output State */ 00952 MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); 00953 00954 /* Set the Output Idle state */ 00955 MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); 00956 00957 /* Set the complementary output Idle state */ 00958 MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); 00959 } 00960 00961 /* Write to TIMx CR2 */ 00962 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 00963 00964 /* Write to TIMx CCMR2 */ 00965 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); 00966 00967 /* Set the Capture Compare Register value */ 00968 LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); 00969 00970 /* Write to TIMx CCER */ 00971 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 00972 00973 return SUCCESS; 00974 } 00975 00976 /** 00977 * @brief Configure the TIMx output channel 4. 00978 * @param TIMx Timer Instance 00979 * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure 00980 * @retval An ErrorStatus enumeration value: 00981 * - SUCCESS: TIMx registers are de-initialized 00982 * - ERROR: not applicable 00983 */ 00984 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) 00985 { 00986 uint32_t tmpccmr2 = 0U; 00987 uint32_t tmpccer = 0U; 00988 uint32_t tmpcr2 = 0U; 00989 00990 /* Check the parameters */ 00991 assert_param(IS_TIM_CC4_INSTANCE(TIMx)); 00992 assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); 00993 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); 00994 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); 00995 assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); 00996 assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); 00997 00998 /* Disable the Channel 4: Reset the CC4E Bit */ 00999 CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); 01000 01001 /* Get the TIMx CCER register value */ 01002 tmpccer = LL_TIM_ReadReg(TIMx, CCER); 01003 01004 /* Get the TIMx CR2 register value */ 01005 tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); 01006 01007 /* Get the TIMx CCMR2 register value */ 01008 tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); 01009 01010 /* Reset Capture/Compare selection Bits */ 01011 CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); 01012 01013 /* Select the Output Compare Mode */ 01014 MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); 01015 01016 /* Set the Output Compare Polarity */ 01017 MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); 01018 01019 /* Set the Output State */ 01020 MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); 01021 01022 if (IS_TIM_BREAK_INSTANCE(TIMx)) 01023 { 01024 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); 01025 assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); 01026 01027 /* Set the Output Idle state */ 01028 MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); 01029 } 01030 01031 /* Write to TIMx CR2 */ 01032 LL_TIM_WriteReg(TIMx, CR2, tmpcr2); 01033 01034 /* Write to TIMx CCMR2 */ 01035 LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); 01036 01037 /* Set the Capture Compare Register value */ 01038 LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); 01039 01040 /* Write to TIMx CCER */ 01041 LL_TIM_WriteReg(TIMx, CCER, tmpccer); 01042 01043 return SUCCESS; 01044 } 01045 01046 01047 /** 01048 * @brief Configure the TIMx input channel 1. 01049 * @param TIMx Timer Instance 01050 * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure 01051 * @retval An ErrorStatus enumeration value: 01052 * - SUCCESS: TIMx registers are de-initialized 01053 * - ERROR: not applicable 01054 */ 01055 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) 01056 { 01057 /* Check the parameters */ 01058 assert_param(IS_TIM_CC1_INSTANCE(TIMx)); 01059 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); 01060 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); 01061 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); 01062 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); 01063 01064 /* Disable the Channel 1: Reset the CC1E Bit */ 01065 TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; 01066 01067 /* Select the Input and set the filter and the prescaler value */ 01068 MODIFY_REG(TIMx->CCMR1, 01069 (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), 01070 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); 01071 01072 /* Select the Polarity and set the CC1E Bit */ 01073 MODIFY_REG(TIMx->CCER, 01074 (TIM_CCER_CC1P | TIM_CCER_CC1NP), 01075 (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); 01076 01077 return SUCCESS; 01078 } 01079 01080 /** 01081 * @brief Configure the TIMx input channel 2. 01082 * @param TIMx Timer Instance 01083 * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure 01084 * @retval An ErrorStatus enumeration value: 01085 * - SUCCESS: TIMx registers are de-initialized 01086 * - ERROR: not applicable 01087 */ 01088 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) 01089 { 01090 /* Check the parameters */ 01091 assert_param(IS_TIM_CC2_INSTANCE(TIMx)); 01092 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); 01093 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); 01094 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); 01095 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); 01096 01097 /* Disable the Channel 2: Reset the CC2E Bit */ 01098 TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; 01099 01100 /* Select the Input and set the filter and the prescaler value */ 01101 MODIFY_REG(TIMx->CCMR1, 01102 (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), 01103 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); 01104 01105 /* Select the Polarity and set the CC2E Bit */ 01106 MODIFY_REG(TIMx->CCER, 01107 (TIM_CCER_CC2P | TIM_CCER_CC2NP), 01108 ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); 01109 01110 return SUCCESS; 01111 } 01112 01113 /** 01114 * @brief Configure the TIMx input channel 3. 01115 * @param TIMx Timer Instance 01116 * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure 01117 * @retval An ErrorStatus enumeration value: 01118 * - SUCCESS: TIMx registers are de-initialized 01119 * - ERROR: not applicable 01120 */ 01121 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) 01122 { 01123 /* Check the parameters */ 01124 assert_param(IS_TIM_CC3_INSTANCE(TIMx)); 01125 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); 01126 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); 01127 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); 01128 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); 01129 01130 /* Disable the Channel 3: Reset the CC3E Bit */ 01131 TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; 01132 01133 /* Select the Input and set the filter and the prescaler value */ 01134 MODIFY_REG(TIMx->CCMR2, 01135 (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), 01136 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); 01137 01138 /* Select the Polarity and set the CC3E Bit */ 01139 MODIFY_REG(TIMx->CCER, 01140 (TIM_CCER_CC3P | TIM_CCER_CC3NP), 01141 ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); 01142 01143 return SUCCESS; 01144 } 01145 01146 /** 01147 * @brief Configure the TIMx input channel 4. 01148 * @param TIMx Timer Instance 01149 * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure 01150 * @retval An ErrorStatus enumeration value: 01151 * - SUCCESS: TIMx registers are de-initialized 01152 * - ERROR: not applicable 01153 */ 01154 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) 01155 { 01156 /* Check the parameters */ 01157 assert_param(IS_TIM_CC4_INSTANCE(TIMx)); 01158 assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); 01159 assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); 01160 assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); 01161 assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); 01162 01163 /* Disable the Channel 4: Reset the CC4E Bit */ 01164 TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; 01165 01166 /* Select the Input and set the filter and the prescaler value */ 01167 MODIFY_REG(TIMx->CCMR2, 01168 (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), 01169 (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); 01170 01171 /* Select the Polarity and set the CC2E Bit */ 01172 MODIFY_REG(TIMx->CCER, 01173 (TIM_CCER_CC4P | TIM_CCER_CC4NP), 01174 ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); 01175 01176 return SUCCESS; 01177 } 01178 01179 01180 /** 01181 * @} 01182 */ 01183 01184 /** 01185 * @} 01186 */ 01187 01188 #endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 */ 01189 01190 /** 01191 * @} 01192 */ 01193 01194 #endif /* USE_FULL_LL_DRIVER */ 01195 01196 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/