STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_spi.h 00004 * @author MCD Application Team 00005 * @brief Header file of SPI LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_LL_SPI_H 00038 #define __STM32F4xx_LL_SPI_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx.h" 00046 00047 /** @addtogroup STM32F4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) 00052 00053 /** @defgroup SPI_LL SPI 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /* Private macros ------------------------------------------------------------*/ 00060 00061 /* Exported types ------------------------------------------------------------*/ 00062 #if defined(USE_FULL_LL_DRIVER) 00063 /** @defgroup SPI_LL_ES_INIT SPI Exported Init structure 00064 * @{ 00065 */ 00066 00067 /** 00068 * @brief SPI Init structures definition 00069 */ 00070 typedef struct 00071 { 00072 uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. 00073 This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. 00074 00075 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ 00076 00077 uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). 00078 This parameter can be a value of @ref SPI_LL_EC_MODE. 00079 00080 This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ 00081 00082 uint32_t DataWidth; /*!< Specifies the SPI data width. 00083 This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. 00084 00085 This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ 00086 00087 uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. 00088 This parameter can be a value of @ref SPI_LL_EC_POLARITY. 00089 00090 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ 00091 00092 uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. 00093 This parameter can be a value of @ref SPI_LL_EC_PHASE. 00094 00095 This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ 00096 00097 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. 00098 This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. 00099 00100 This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ 00101 00102 uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. 00103 This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. 00104 @note The communication clock is derived from the master clock. The slave clock does not need to be set. 00105 00106 This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ 00107 00108 uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. 00109 This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. 00110 00111 This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ 00112 00113 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. 00114 This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. 00115 00116 This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ 00117 00118 uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. 00119 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. 00120 00121 This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ 00122 00123 } LL_SPI_InitTypeDef; 00124 00125 /** 00126 * @} 00127 */ 00128 #endif /* USE_FULL_LL_DRIVER */ 00129 00130 /* Exported constants --------------------------------------------------------*/ 00131 /** @defgroup SPI_LL_Exported_Constants SPI Exported Constants 00132 * @{ 00133 */ 00134 00135 /** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines 00136 * @brief Flags defines which can be used with LL_SPI_ReadReg function 00137 * @{ 00138 */ 00139 #define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ 00140 #define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ 00141 #define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ 00142 #define LL_SPI_SR_CRCERR SPI_SR_CRCERR /*!< CRC error flag */ 00143 #define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ 00144 #define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ 00145 #define LL_SPI_SR_FRE SPI_SR_FRE /*!< TI mode frame format error flag */ 00146 /** 00147 * @} 00148 */ 00149 00150 /** @defgroup SPI_LL_EC_IT IT Defines 00151 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions 00152 * @{ 00153 */ 00154 #define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ 00155 #define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ 00156 #define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ 00157 /** 00158 * @} 00159 */ 00160 00161 /** @defgroup SPI_LL_EC_MODE Operation Mode 00162 * @{ 00163 */ 00164 #define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ 00165 #define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ 00166 /** 00167 * @} 00168 */ 00169 00170 /** @defgroup SPI_LL_EC_PROTOCOL Serial Protocol 00171 * @{ 00172 */ 00173 #define LL_SPI_PROTOCOL_MOTOROLA 0x00000000U /*!< Motorola mode. Used as default value */ 00174 #define LL_SPI_PROTOCOL_TI (SPI_CR2_FRF) /*!< TI mode */ 00175 /** 00176 * @} 00177 */ 00178 00179 /** @defgroup SPI_LL_EC_PHASE Clock Phase 00180 * @{ 00181 */ 00182 #define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ 00183 #define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ 00184 /** 00185 * @} 00186 */ 00187 00188 /** @defgroup SPI_LL_EC_POLARITY Clock Polarity 00189 * @{ 00190 */ 00191 #define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ 00192 #define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ 00193 /** 00194 * @} 00195 */ 00196 00197 /** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler 00198 * @{ 00199 */ 00200 #define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ 00201 #define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ 00202 #define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ 00203 #define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ 00204 #define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ 00205 #define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ 00206 #define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ 00207 #define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ 00208 /** 00209 * @} 00210 */ 00211 00212 /** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order 00213 * @{ 00214 */ 00215 #define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ 00216 #define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ 00217 /** 00218 * @} 00219 */ 00220 00221 /** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode 00222 * @{ 00223 */ 00224 #define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ 00225 #define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ 00226 #define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ 00227 #define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode 00233 * @{ 00234 */ 00235 #define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ 00236 #define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ 00237 #define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ 00238 /** 00239 * @} 00240 */ 00241 00242 /** @defgroup SPI_LL_EC_DATAWIDTH Datawidth 00243 * @{ 00244 */ 00245 #define LL_SPI_DATAWIDTH_8BIT 0x00000000U /*!< Data length for SPI transfer: 8 bits */ 00246 #define LL_SPI_DATAWIDTH_16BIT (SPI_CR1_DFF) /*!< Data length for SPI transfer: 16 bits */ 00247 /** 00248 * @} 00249 */ 00250 #if defined(USE_FULL_LL_DRIVER) 00251 00252 /** @defgroup SPI_LL_EC_CRC_CALCULATION CRC Calculation 00253 * @{ 00254 */ 00255 #define LL_SPI_CRCCALCULATION_DISABLE 0x00000000U /*!< CRC calculation disabled */ 00256 #define LL_SPI_CRCCALCULATION_ENABLE (SPI_CR1_CRCEN) /*!< CRC calculation enabled */ 00257 /** 00258 * @} 00259 */ 00260 #endif /* USE_FULL_LL_DRIVER */ 00261 00262 /** 00263 * @} 00264 */ 00265 00266 /* Exported macro ------------------------------------------------------------*/ 00267 /** @defgroup SPI_LL_Exported_Macros SPI Exported Macros 00268 * @{ 00269 */ 00270 00271 /** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros 00272 * @{ 00273 */ 00274 00275 /** 00276 * @brief Write a value in SPI register 00277 * @param __INSTANCE__ SPI Instance 00278 * @param __REG__ Register to be written 00279 * @param __VALUE__ Value to be written in the register 00280 * @retval None 00281 */ 00282 #define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00283 00284 /** 00285 * @brief Read a value in SPI register 00286 * @param __INSTANCE__ SPI Instance 00287 * @param __REG__ Register to be read 00288 * @retval Register value 00289 */ 00290 #define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00291 /** 00292 * @} 00293 */ 00294 00295 /** 00296 * @} 00297 */ 00298 00299 /* Exported functions --------------------------------------------------------*/ 00300 /** @defgroup SPI_LL_Exported_Functions SPI Exported Functions 00301 * @{ 00302 */ 00303 00304 /** @defgroup SPI_LL_EF_Configuration Configuration 00305 * @{ 00306 */ 00307 00308 /** 00309 * @brief Enable SPI peripheral 00310 * @rmtoll CR1 SPE LL_SPI_Enable 00311 * @param SPIx SPI Instance 00312 * @retval None 00313 */ 00314 __STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) 00315 { 00316 SET_BIT(SPIx->CR1, SPI_CR1_SPE); 00317 } 00318 00319 /** 00320 * @brief Disable SPI peripheral 00321 * @note When disabling the SPI, follow the procedure described in the Reference Manual. 00322 * @rmtoll CR1 SPE LL_SPI_Disable 00323 * @param SPIx SPI Instance 00324 * @retval None 00325 */ 00326 __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) 00327 { 00328 CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 00329 } 00330 00331 /** 00332 * @brief Check if SPI peripheral is enabled 00333 * @rmtoll CR1 SPE LL_SPI_IsEnabled 00334 * @param SPIx SPI Instance 00335 * @retval State of bit (1 or 0). 00336 */ 00337 __STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) 00338 { 00339 return (READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)); 00340 } 00341 00342 /** 00343 * @brief Set SPI operation mode to Master or Slave 00344 * @note This bit should not be changed when communication is ongoing. 00345 * @rmtoll CR1 MSTR LL_SPI_SetMode\n 00346 * CR1 SSI LL_SPI_SetMode 00347 * @param SPIx SPI Instance 00348 * @param Mode This parameter can be one of the following values: 00349 * @arg @ref LL_SPI_MODE_MASTER 00350 * @arg @ref LL_SPI_MODE_SLAVE 00351 * @retval None 00352 */ 00353 __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) 00354 { 00355 MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); 00356 } 00357 00358 /** 00359 * @brief Get SPI operation mode (Master or Slave) 00360 * @rmtoll CR1 MSTR LL_SPI_GetMode\n 00361 * CR1 SSI LL_SPI_GetMode 00362 * @param SPIx SPI Instance 00363 * @retval Returned value can be one of the following values: 00364 * @arg @ref LL_SPI_MODE_MASTER 00365 * @arg @ref LL_SPI_MODE_SLAVE 00366 */ 00367 __STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) 00368 { 00369 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); 00370 } 00371 00372 /** 00373 * @brief Set serial protocol used 00374 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00375 * @rmtoll CR2 FRF LL_SPI_SetStandard 00376 * @param SPIx SPI Instance 00377 * @param Standard This parameter can be one of the following values: 00378 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 00379 * @arg @ref LL_SPI_PROTOCOL_TI 00380 * @retval None 00381 */ 00382 __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) 00383 { 00384 MODIFY_REG(SPIx->CR2, SPI_CR2_FRF, Standard); 00385 } 00386 00387 /** 00388 * @brief Get serial protocol used 00389 * @rmtoll CR2 FRF LL_SPI_GetStandard 00390 * @param SPIx SPI Instance 00391 * @retval Returned value can be one of the following values: 00392 * @arg @ref LL_SPI_PROTOCOL_MOTOROLA 00393 * @arg @ref LL_SPI_PROTOCOL_TI 00394 */ 00395 __STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) 00396 { 00397 return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); 00398 } 00399 00400 /** 00401 * @brief Set clock phase 00402 * @note This bit should not be changed when communication is ongoing. 00403 * This bit is not used in SPI TI mode. 00404 * @rmtoll CR1 CPHA LL_SPI_SetClockPhase 00405 * @param SPIx SPI Instance 00406 * @param ClockPhase This parameter can be one of the following values: 00407 * @arg @ref LL_SPI_PHASE_1EDGE 00408 * @arg @ref LL_SPI_PHASE_2EDGE 00409 * @retval None 00410 */ 00411 __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) 00412 { 00413 MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); 00414 } 00415 00416 /** 00417 * @brief Get clock phase 00418 * @rmtoll CR1 CPHA LL_SPI_GetClockPhase 00419 * @param SPIx SPI Instance 00420 * @retval Returned value can be one of the following values: 00421 * @arg @ref LL_SPI_PHASE_1EDGE 00422 * @arg @ref LL_SPI_PHASE_2EDGE 00423 */ 00424 __STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) 00425 { 00426 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); 00427 } 00428 00429 /** 00430 * @brief Set clock polarity 00431 * @note This bit should not be changed when communication is ongoing. 00432 * This bit is not used in SPI TI mode. 00433 * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity 00434 * @param SPIx SPI Instance 00435 * @param ClockPolarity This parameter can be one of the following values: 00436 * @arg @ref LL_SPI_POLARITY_LOW 00437 * @arg @ref LL_SPI_POLARITY_HIGH 00438 * @retval None 00439 */ 00440 __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) 00441 { 00442 MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); 00443 } 00444 00445 /** 00446 * @brief Get clock polarity 00447 * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity 00448 * @param SPIx SPI Instance 00449 * @retval Returned value can be one of the following values: 00450 * @arg @ref LL_SPI_POLARITY_LOW 00451 * @arg @ref LL_SPI_POLARITY_HIGH 00452 */ 00453 __STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) 00454 { 00455 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); 00456 } 00457 00458 /** 00459 * @brief Set baud rate prescaler 00460 * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. 00461 * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler 00462 * @param SPIx SPI Instance 00463 * @param BaudRate This parameter can be one of the following values: 00464 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 00465 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 00466 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 00467 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 00468 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 00469 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 00470 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 00471 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 00472 * @retval None 00473 */ 00474 __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) 00475 { 00476 MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); 00477 } 00478 00479 /** 00480 * @brief Get baud rate prescaler 00481 * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler 00482 * @param SPIx SPI Instance 00483 * @retval Returned value can be one of the following values: 00484 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 00485 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 00486 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 00487 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 00488 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 00489 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 00490 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 00491 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 00492 */ 00493 __STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) 00494 { 00495 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); 00496 } 00497 00498 /** 00499 * @brief Set transfer bit order 00500 * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. 00501 * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder 00502 * @param SPIx SPI Instance 00503 * @param BitOrder This parameter can be one of the following values: 00504 * @arg @ref LL_SPI_LSB_FIRST 00505 * @arg @ref LL_SPI_MSB_FIRST 00506 * @retval None 00507 */ 00508 __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) 00509 { 00510 MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); 00511 } 00512 00513 /** 00514 * @brief Get transfer bit order 00515 * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder 00516 * @param SPIx SPI Instance 00517 * @retval Returned value can be one of the following values: 00518 * @arg @ref LL_SPI_LSB_FIRST 00519 * @arg @ref LL_SPI_MSB_FIRST 00520 */ 00521 __STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) 00522 { 00523 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); 00524 } 00525 00526 /** 00527 * @brief Set transfer direction mode 00528 * @note For Half-Duplex mode, Rx Direction is set by default. 00529 * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. 00530 * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n 00531 * CR1 BIDIMODE LL_SPI_SetTransferDirection\n 00532 * CR1 BIDIOE LL_SPI_SetTransferDirection 00533 * @param SPIx SPI Instance 00534 * @param TransferDirection This parameter can be one of the following values: 00535 * @arg @ref LL_SPI_FULL_DUPLEX 00536 * @arg @ref LL_SPI_SIMPLEX_RX 00537 * @arg @ref LL_SPI_HALF_DUPLEX_RX 00538 * @arg @ref LL_SPI_HALF_DUPLEX_TX 00539 * @retval None 00540 */ 00541 __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) 00542 { 00543 MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); 00544 } 00545 00546 /** 00547 * @brief Get transfer direction mode 00548 * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n 00549 * CR1 BIDIMODE LL_SPI_GetTransferDirection\n 00550 * CR1 BIDIOE LL_SPI_GetTransferDirection 00551 * @param SPIx SPI Instance 00552 * @retval Returned value can be one of the following values: 00553 * @arg @ref LL_SPI_FULL_DUPLEX 00554 * @arg @ref LL_SPI_SIMPLEX_RX 00555 * @arg @ref LL_SPI_HALF_DUPLEX_RX 00556 * @arg @ref LL_SPI_HALF_DUPLEX_TX 00557 */ 00558 __STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) 00559 { 00560 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); 00561 } 00562 00563 /** 00564 * @brief Set frame data width 00565 * @rmtoll CR1 DFF LL_SPI_SetDataWidth 00566 * @param SPIx SPI Instance 00567 * @param DataWidth This parameter can be one of the following values: 00568 * @arg @ref LL_SPI_DATAWIDTH_8BIT 00569 * @arg @ref LL_SPI_DATAWIDTH_16BIT 00570 * @retval None 00571 */ 00572 __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) 00573 { 00574 MODIFY_REG(SPIx->CR1, SPI_CR1_DFF, DataWidth); 00575 } 00576 00577 /** 00578 * @brief Get frame data width 00579 * @rmtoll CR1 DFF LL_SPI_GetDataWidth 00580 * @param SPIx SPI Instance 00581 * @retval Returned value can be one of the following values: 00582 * @arg @ref LL_SPI_DATAWIDTH_8BIT 00583 * @arg @ref LL_SPI_DATAWIDTH_16BIT 00584 */ 00585 __STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) 00586 { 00587 return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_DFF)); 00588 } 00589 00590 /** 00591 * @} 00592 */ 00593 00594 /** @defgroup SPI_LL_EF_CRC_Management CRC Management 00595 * @{ 00596 */ 00597 00598 /** 00599 * @brief Enable CRC 00600 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00601 * @rmtoll CR1 CRCEN LL_SPI_EnableCRC 00602 * @param SPIx SPI Instance 00603 * @retval None 00604 */ 00605 __STATIC_INLINE void LL_SPI_EnableCRC(SPI_TypeDef *SPIx) 00606 { 00607 SET_BIT(SPIx->CR1, SPI_CR1_CRCEN); 00608 } 00609 00610 /** 00611 * @brief Disable CRC 00612 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00613 * @rmtoll CR1 CRCEN LL_SPI_DisableCRC 00614 * @param SPIx SPI Instance 00615 * @retval None 00616 */ 00617 __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) 00618 { 00619 CLEAR_BIT(SPIx->CR1, SPI_CR1_CRCEN); 00620 } 00621 00622 /** 00623 * @brief Check if CRC is enabled 00624 * @note This bit should be written only when SPI is disabled (SPE = 0) for correct operation. 00625 * @rmtoll CR1 CRCEN LL_SPI_IsEnabledCRC 00626 * @param SPIx SPI Instance 00627 * @retval State of bit (1 or 0). 00628 */ 00629 __STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) 00630 { 00631 return (READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)); 00632 } 00633 00634 /** 00635 * @brief Set CRCNext to transfer CRC on the line 00636 * @note This bit has to be written as soon as the last data is written in the SPIx_DR register. 00637 * @rmtoll CR1 CRCNEXT LL_SPI_SetCRCNext 00638 * @param SPIx SPI Instance 00639 * @retval None 00640 */ 00641 __STATIC_INLINE void LL_SPI_SetCRCNext(SPI_TypeDef *SPIx) 00642 { 00643 SET_BIT(SPIx->CR1, SPI_CR1_CRCNEXT); 00644 } 00645 00646 /** 00647 * @brief Set polynomial for CRC calculation 00648 * @rmtoll CRCPR CRCPOLY LL_SPI_SetCRCPolynomial 00649 * @param SPIx SPI Instance 00650 * @param CRCPoly This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00651 * @retval None 00652 */ 00653 __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly) 00654 { 00655 WRITE_REG(SPIx->CRCPR, (uint16_t)CRCPoly); 00656 } 00657 00658 /** 00659 * @brief Get polynomial for CRC calculation 00660 * @rmtoll CRCPR CRCPOLY LL_SPI_GetCRCPolynomial 00661 * @param SPIx SPI Instance 00662 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00663 */ 00664 __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) 00665 { 00666 return (uint32_t)(READ_REG(SPIx->CRCPR)); 00667 } 00668 00669 /** 00670 * @brief Get Rx CRC 00671 * @rmtoll RXCRCR RXCRC LL_SPI_GetRxCRC 00672 * @param SPIx SPI Instance 00673 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00674 */ 00675 __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) 00676 { 00677 return (uint32_t)(READ_REG(SPIx->RXCRCR)); 00678 } 00679 00680 /** 00681 * @brief Get Tx CRC 00682 * @rmtoll TXCRCR TXCRC LL_SPI_GetTxCRC 00683 * @param SPIx SPI Instance 00684 * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF 00685 */ 00686 __STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) 00687 { 00688 return (uint32_t)(READ_REG(SPIx->TXCRCR)); 00689 } 00690 00691 /** 00692 * @} 00693 */ 00694 00695 /** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management 00696 * @{ 00697 */ 00698 00699 /** 00700 * @brief Set NSS mode 00701 * @note LL_SPI_NSS_SOFT Mode is not used in SPI TI mode. 00702 * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n 00703 * @rmtoll CR2 SSOE LL_SPI_SetNSSMode 00704 * @param SPIx SPI Instance 00705 * @param NSS This parameter can be one of the following values: 00706 * @arg @ref LL_SPI_NSS_SOFT 00707 * @arg @ref LL_SPI_NSS_HARD_INPUT 00708 * @arg @ref LL_SPI_NSS_HARD_OUTPUT 00709 * @retval None 00710 */ 00711 __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) 00712 { 00713 MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); 00714 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); 00715 } 00716 00717 /** 00718 * @brief Get NSS mode 00719 * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n 00720 * @rmtoll CR2 SSOE LL_SPI_GetNSSMode 00721 * @param SPIx SPI Instance 00722 * @retval Returned value can be one of the following values: 00723 * @arg @ref LL_SPI_NSS_SOFT 00724 * @arg @ref LL_SPI_NSS_HARD_INPUT 00725 * @arg @ref LL_SPI_NSS_HARD_OUTPUT 00726 */ 00727 __STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) 00728 { 00729 register uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); 00730 register uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); 00731 return (Ssm | Ssoe); 00732 } 00733 00734 /** 00735 * @} 00736 */ 00737 00738 /** @defgroup SPI_LL_EF_FLAG_Management FLAG Management 00739 * @{ 00740 */ 00741 00742 /** 00743 * @brief Check if Rx buffer is not empty 00744 * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE 00745 * @param SPIx SPI Instance 00746 * @retval State of bit (1 or 0). 00747 */ 00748 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) 00749 { 00750 return (READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)); 00751 } 00752 00753 /** 00754 * @brief Check if Tx buffer is empty 00755 * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE 00756 * @param SPIx SPI Instance 00757 * @retval State of bit (1 or 0). 00758 */ 00759 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) 00760 { 00761 return (READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)); 00762 } 00763 00764 /** 00765 * @brief Get CRC error flag 00766 * @rmtoll SR CRCERR LL_SPI_IsActiveFlag_CRCERR 00767 * @param SPIx SPI Instance 00768 * @retval State of bit (1 or 0). 00769 */ 00770 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) 00771 { 00772 return (READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)); 00773 } 00774 00775 /** 00776 * @brief Get mode fault error flag 00777 * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF 00778 * @param SPIx SPI Instance 00779 * @retval State of bit (1 or 0). 00780 */ 00781 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) 00782 { 00783 return (READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)); 00784 } 00785 00786 /** 00787 * @brief Get overrun error flag 00788 * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR 00789 * @param SPIx SPI Instance 00790 * @retval State of bit (1 or 0). 00791 */ 00792 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) 00793 { 00794 return (READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)); 00795 } 00796 00797 /** 00798 * @brief Get busy flag 00799 * @note The BSY flag is cleared under any one of the following conditions: 00800 * -When the SPI is correctly disabled 00801 * -When a fault is detected in Master mode (MODF bit set to 1) 00802 * -In Master mode, when it finishes a data transmission and no new data is ready to be 00803 * sent 00804 * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between 00805 * each data transfer. 00806 * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY 00807 * @param SPIx SPI Instance 00808 * @retval State of bit (1 or 0). 00809 */ 00810 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) 00811 { 00812 return (READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)); 00813 } 00814 00815 /** 00816 * @brief Get frame format error flag 00817 * @rmtoll SR FRE LL_SPI_IsActiveFlag_FRE 00818 * @param SPIx SPI Instance 00819 * @retval State of bit (1 or 0). 00820 */ 00821 __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) 00822 { 00823 return (READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)); 00824 } 00825 00826 /** 00827 * @brief Clear CRC error flag 00828 * @rmtoll SR CRCERR LL_SPI_ClearFlag_CRCERR 00829 * @param SPIx SPI Instance 00830 * @retval None 00831 */ 00832 __STATIC_INLINE void LL_SPI_ClearFlag_CRCERR(SPI_TypeDef *SPIx) 00833 { 00834 CLEAR_BIT(SPIx->SR, SPI_SR_CRCERR); 00835 } 00836 00837 /** 00838 * @brief Clear mode fault error flag 00839 * @note Clearing this flag is done by a read access to the SPIx_SR 00840 * register followed by a write access to the SPIx_CR1 register 00841 * @rmtoll SR MODF LL_SPI_ClearFlag_MODF 00842 * @param SPIx SPI Instance 00843 * @retval None 00844 */ 00845 __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) 00846 { 00847 __IO uint32_t tmpreg; 00848 tmpreg = SPIx->SR; 00849 (void) tmpreg; 00850 tmpreg = CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); 00851 (void) tmpreg; 00852 } 00853 00854 /** 00855 * @brief Clear overrun error flag 00856 * @note Clearing this flag is done by a read access to the SPIx_DR 00857 * register followed by a read access to the SPIx_SR register 00858 * @rmtoll SR OVR LL_SPI_ClearFlag_OVR 00859 * @param SPIx SPI Instance 00860 * @retval None 00861 */ 00862 __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) 00863 { 00864 __IO uint32_t tmpreg; 00865 tmpreg = SPIx->DR; 00866 (void) tmpreg; 00867 tmpreg = SPIx->SR; 00868 (void) tmpreg; 00869 } 00870 00871 /** 00872 * @brief Clear frame format error flag 00873 * @note Clearing this flag is done by reading SPIx_SR register 00874 * @rmtoll SR FRE LL_SPI_ClearFlag_FRE 00875 * @param SPIx SPI Instance 00876 * @retval None 00877 */ 00878 __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) 00879 { 00880 __IO uint32_t tmpreg; 00881 tmpreg = SPIx->SR; 00882 (void) tmpreg; 00883 } 00884 00885 /** 00886 * @} 00887 */ 00888 00889 /** @defgroup SPI_LL_EF_IT_Management Interrupt Management 00890 * @{ 00891 */ 00892 00893 /** 00894 * @brief Enable error interrupt 00895 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). 00896 * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR 00897 * @param SPIx SPI Instance 00898 * @retval None 00899 */ 00900 __STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) 00901 { 00902 SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); 00903 } 00904 00905 /** 00906 * @brief Enable Rx buffer not empty interrupt 00907 * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE 00908 * @param SPIx SPI Instance 00909 * @retval None 00910 */ 00911 __STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) 00912 { 00913 SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 00914 } 00915 00916 /** 00917 * @brief Enable Tx buffer empty interrupt 00918 * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE 00919 * @param SPIx SPI Instance 00920 * @retval None 00921 */ 00922 __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) 00923 { 00924 SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); 00925 } 00926 00927 /** 00928 * @brief Disable error interrupt 00929 * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). 00930 * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR 00931 * @param SPIx SPI Instance 00932 * @retval None 00933 */ 00934 __STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) 00935 { 00936 CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); 00937 } 00938 00939 /** 00940 * @brief Disable Rx buffer not empty interrupt 00941 * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE 00942 * @param SPIx SPI Instance 00943 * @retval None 00944 */ 00945 __STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) 00946 { 00947 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); 00948 } 00949 00950 /** 00951 * @brief Disable Tx buffer empty interrupt 00952 * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE 00953 * @param SPIx SPI Instance 00954 * @retval None 00955 */ 00956 __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) 00957 { 00958 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); 00959 } 00960 00961 /** 00962 * @brief Check if error interrupt is enabled 00963 * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR 00964 * @param SPIx SPI Instance 00965 * @retval State of bit (1 or 0). 00966 */ 00967 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) 00968 { 00969 return (READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)); 00970 } 00971 00972 /** 00973 * @brief Check if Rx buffer not empty interrupt is enabled 00974 * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE 00975 * @param SPIx SPI Instance 00976 * @retval State of bit (1 or 0). 00977 */ 00978 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) 00979 { 00980 return (READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)); 00981 } 00982 00983 /** 00984 * @brief Check if Tx buffer empty interrupt 00985 * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE 00986 * @param SPIx SPI Instance 00987 * @retval State of bit (1 or 0). 00988 */ 00989 __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) 00990 { 00991 return (READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)); 00992 } 00993 00994 /** 00995 * @} 00996 */ 00997 00998 /** @defgroup SPI_LL_EF_DMA_Management DMA Management 00999 * @{ 01000 */ 01001 01002 /** 01003 * @brief Enable DMA Rx 01004 * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX 01005 * @param SPIx SPI Instance 01006 * @retval None 01007 */ 01008 __STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) 01009 { 01010 SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 01011 } 01012 01013 /** 01014 * @brief Disable DMA Rx 01015 * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX 01016 * @param SPIx SPI Instance 01017 * @retval None 01018 */ 01019 __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) 01020 { 01021 CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); 01022 } 01023 01024 /** 01025 * @brief Check if DMA Rx is enabled 01026 * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX 01027 * @param SPIx SPI Instance 01028 * @retval State of bit (1 or 0). 01029 */ 01030 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) 01031 { 01032 return (READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)); 01033 } 01034 01035 /** 01036 * @brief Enable DMA Tx 01037 * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX 01038 * @param SPIx SPI Instance 01039 * @retval None 01040 */ 01041 __STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) 01042 { 01043 SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 01044 } 01045 01046 /** 01047 * @brief Disable DMA Tx 01048 * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX 01049 * @param SPIx SPI Instance 01050 * @retval None 01051 */ 01052 __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) 01053 { 01054 CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); 01055 } 01056 01057 /** 01058 * @brief Check if DMA Tx is enabled 01059 * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX 01060 * @param SPIx SPI Instance 01061 * @retval State of bit (1 or 0). 01062 */ 01063 __STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) 01064 { 01065 return (READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)); 01066 } 01067 01068 /** 01069 * @brief Get the data register address used for DMA transfer 01070 * @rmtoll DR DR LL_SPI_DMA_GetRegAddr 01071 * @param SPIx SPI Instance 01072 * @retval Address of data register 01073 */ 01074 __STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) 01075 { 01076 return (uint32_t) & (SPIx->DR); 01077 } 01078 01079 /** 01080 * @} 01081 */ 01082 01083 /** @defgroup SPI_LL_EF_DATA_Management DATA Management 01084 * @{ 01085 */ 01086 01087 /** 01088 * @brief Read 8-Bits in the data register 01089 * @rmtoll DR DR LL_SPI_ReceiveData8 01090 * @param SPIx SPI Instance 01091 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF 01092 */ 01093 __STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) 01094 { 01095 return (uint8_t)(READ_REG(SPIx->DR)); 01096 } 01097 01098 /** 01099 * @brief Read 16-Bits in the data register 01100 * @rmtoll DR DR LL_SPI_ReceiveData16 01101 * @param SPIx SPI Instance 01102 * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF 01103 */ 01104 __STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) 01105 { 01106 return (uint16_t)(READ_REG(SPIx->DR)); 01107 } 01108 01109 /** 01110 * @brief Write 8-Bits in the data register 01111 * @rmtoll DR DR LL_SPI_TransmitData8 01112 * @param SPIx SPI Instance 01113 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF 01114 * @retval None 01115 */ 01116 __STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) 01117 { 01118 SPIx->DR = TxData; 01119 } 01120 01121 /** 01122 * @brief Write 16-Bits in the data register 01123 * @rmtoll DR DR LL_SPI_TransmitData16 01124 * @param SPIx SPI Instance 01125 * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF 01126 * @retval None 01127 */ 01128 __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) 01129 { 01130 SPIx->DR = TxData; 01131 } 01132 01133 /** 01134 * @} 01135 */ 01136 #if defined(USE_FULL_LL_DRIVER) 01137 /** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions 01138 * @{ 01139 */ 01140 01141 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); 01142 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); 01143 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); 01144 01145 /** 01146 * @} 01147 */ 01148 #endif /* USE_FULL_LL_DRIVER */ 01149 /** 01150 * @} 01151 */ 01152 01153 /** 01154 * @} 01155 */ 01156 01157 /** @defgroup I2S_LL I2S 01158 * @{ 01159 */ 01160 01161 /* Private variables ---------------------------------------------------------*/ 01162 /* Private constants ---------------------------------------------------------*/ 01163 /* Private macros ------------------------------------------------------------*/ 01164 01165 /* Exported types ------------------------------------------------------------*/ 01166 #if defined(USE_FULL_LL_DRIVER) 01167 /** @defgroup I2S_LL_ES_INIT I2S Exported Init structure 01168 * @{ 01169 */ 01170 01171 /** 01172 * @brief I2S Init structure definition 01173 */ 01174 01175 typedef struct 01176 { 01177 uint32_t Mode; /*!< Specifies the I2S operating mode. 01178 This parameter can be a value of @ref I2S_LL_EC_MODE 01179 01180 This feature can be modified afterwards using unitary function @ref LL_I2S_SetTransferMode().*/ 01181 01182 uint32_t Standard; /*!< Specifies the standard used for the I2S communication. 01183 This parameter can be a value of @ref I2S_LL_EC_STANDARD 01184 01185 This feature can be modified afterwards using unitary function @ref LL_I2S_SetStandard().*/ 01186 01187 01188 uint32_t DataFormat; /*!< Specifies the data format for the I2S communication. 01189 This parameter can be a value of @ref I2S_LL_EC_DATA_FORMAT 01190 01191 This feature can be modified afterwards using unitary function @ref LL_I2S_SetDataFormat().*/ 01192 01193 01194 uint32_t MCLKOutput; /*!< Specifies whether the I2S MCLK output is enabled or not. 01195 This parameter can be a value of @ref I2S_LL_EC_MCLK_OUTPUT 01196 01197 This feature can be modified afterwards using unitary functions @ref LL_I2S_EnableMasterClock() or @ref LL_I2S_DisableMasterClock.*/ 01198 01199 01200 uint32_t AudioFreq; /*!< Specifies the frequency selected for the I2S communication. 01201 This parameter can be a value of @ref I2S_LL_EC_AUDIO_FREQ 01202 01203 Audio Frequency can be modified afterwards using Reference manual formulas to calculate Prescaler Linear, Parity 01204 and unitary functions @ref LL_I2S_SetPrescalerLinear() and @ref LL_I2S_SetPrescalerParity() to set it.*/ 01205 01206 01207 uint32_t ClockPolarity; /*!< Specifies the idle state of the I2S clock. 01208 This parameter can be a value of @ref I2S_LL_EC_POLARITY 01209 01210 This feature can be modified afterwards using unitary function @ref LL_I2S_SetClockPolarity().*/ 01211 01212 } LL_I2S_InitTypeDef; 01213 01214 /** 01215 * @} 01216 */ 01217 #endif /*USE_FULL_LL_DRIVER*/ 01218 01219 /* Exported constants --------------------------------------------------------*/ 01220 /** @defgroup I2S_LL_Exported_Constants I2S Exported Constants 01221 * @{ 01222 */ 01223 01224 /** @defgroup I2S_LL_EC_GET_FLAG Get Flags Defines 01225 * @brief Flags defines which can be used with LL_I2S_ReadReg function 01226 * @{ 01227 */ 01228 #define LL_I2S_SR_RXNE LL_SPI_SR_RXNE /*!< Rx buffer not empty flag */ 01229 #define LL_I2S_SR_TXE LL_SPI_SR_TXE /*!< Tx buffer empty flag */ 01230 #define LL_I2S_SR_BSY LL_SPI_SR_BSY /*!< Busy flag */ 01231 #define LL_I2S_SR_UDR SPI_SR_UDR /*!< Underrun flag */ 01232 #define LL_I2S_SR_OVR LL_SPI_SR_OVR /*!< Overrun flag */ 01233 #define LL_I2S_SR_FRE LL_SPI_SR_FRE /*!< TI mode frame format error flag */ 01234 /** 01235 * @} 01236 */ 01237 01238 /** @defgroup SPI_LL_EC_IT IT Defines 01239 * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions 01240 * @{ 01241 */ 01242 #define LL_I2S_CR2_RXNEIE LL_SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ 01243 #define LL_I2S_CR2_TXEIE LL_SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ 01244 #define LL_I2S_CR2_ERRIE LL_SPI_CR2_ERRIE /*!< Error interrupt enable */ 01245 /** 01246 * @} 01247 */ 01248 01249 /** @defgroup I2S_LL_EC_DATA_FORMAT Data format 01250 * @{ 01251 */ 01252 #define LL_I2S_DATAFORMAT_16B 0x00000000U /*!< Data length 16 bits, Channel lenght 16bit */ 01253 #define LL_I2S_DATAFORMAT_16B_EXTENDED (SPI_I2SCFGR_CHLEN) /*!< Data length 16 bits, Channel lenght 32bit */ 01254 #define LL_I2S_DATAFORMAT_24B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0) /*!< Data length 24 bits, Channel lenght 32bit */ 01255 #define LL_I2S_DATAFORMAT_32B (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1) /*!< Data length 16 bits, Channel lenght 32bit */ 01256 /** 01257 * @} 01258 */ 01259 01260 /** @defgroup I2S_LL_EC_POLARITY Clock Polarity 01261 * @{ 01262 */ 01263 #define LL_I2S_POLARITY_LOW 0x00000000U /*!< Clock steady state is low level */ 01264 #define LL_I2S_POLARITY_HIGH (SPI_I2SCFGR_CKPOL) /*!< Clock steady state is high level */ 01265 /** 01266 * @} 01267 */ 01268 01269 /** @defgroup I2S_LL_EC_STANDARD I2s Standard 01270 * @{ 01271 */ 01272 #define LL_I2S_STANDARD_PHILIPS 0x00000000U /*!< I2S standard philips */ 01273 #define LL_I2S_STANDARD_MSB (SPI_I2SCFGR_I2SSTD_0) /*!< MSB justified standard (left justified) */ 01274 #define LL_I2S_STANDARD_LSB (SPI_I2SCFGR_I2SSTD_1) /*!< LSB justified standard (right justified) */ 01275 #define LL_I2S_STANDARD_PCM_SHORT (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1) /*!< PCM standard, short frame synchronization */ 01276 #define LL_I2S_STANDARD_PCM_LONG (SPI_I2SCFGR_I2SSTD_0 | SPI_I2SCFGR_I2SSTD_1 | SPI_I2SCFGR_PCMSYNC) /*!< PCM standard, long frame synchronization */ 01277 /** 01278 * @} 01279 */ 01280 01281 /** @defgroup I2S_LL_EC_MODE Operation Mode 01282 * @{ 01283 */ 01284 #define LL_I2S_MODE_SLAVE_TX 0x00000000U /*!< Slave Tx configuration */ 01285 #define LL_I2S_MODE_SLAVE_RX (SPI_I2SCFGR_I2SCFG_0) /*!< Slave Rx configuration */ 01286 #define LL_I2S_MODE_MASTER_TX (SPI_I2SCFGR_I2SCFG_1) /*!< Master Tx configuration */ 01287 #define LL_I2S_MODE_MASTER_RX (SPI_I2SCFGR_I2SCFG_0 | SPI_I2SCFGR_I2SCFG_1) /*!< Master Rx configuration */ 01288 /** 01289 * @} 01290 */ 01291 01292 /** @defgroup I2S_LL_EC_PRESCALER_FACTOR Prescaler Factor 01293 * @{ 01294 */ 01295 #define LL_I2S_PRESCALER_PARITY_EVEN 0x00000000U /*!< Odd factor: Real divider value is = I2SDIV * 2 */ 01296 #define LL_I2S_PRESCALER_PARITY_ODD (SPI_I2SPR_ODD >> 8U) /*!< Odd factor: Real divider value is = (I2SDIV * 2)+1 */ 01297 /** 01298 * @} 01299 */ 01300 01301 #if defined(USE_FULL_LL_DRIVER) 01302 01303 /** @defgroup I2S_LL_EC_MCLK_OUTPUT MCLK Output 01304 * @{ 01305 */ 01306 #define LL_I2S_MCLK_OUTPUT_DISABLE 0x00000000U /*!< Master clock output is disabled */ 01307 #define LL_I2S_MCLK_OUTPUT_ENABLE (SPI_I2SPR_MCKOE) /*!< Master clock output is enabled */ 01308 /** 01309 * @} 01310 */ 01311 01312 /** @defgroup I2S_LL_EC_AUDIO_FREQ Audio Frequency 01313 * @{ 01314 */ 01315 01316 #define LL_I2S_AUDIOFREQ_192K 192000U /*!< Audio Frequency configuration 192000 Hz */ 01317 #define LL_I2S_AUDIOFREQ_96K 96000U /*!< Audio Frequency configuration 96000 Hz */ 01318 #define LL_I2S_AUDIOFREQ_48K 48000U /*!< Audio Frequency configuration 48000 Hz */ 01319 #define LL_I2S_AUDIOFREQ_44K 44100U /*!< Audio Frequency configuration 44100 Hz */ 01320 #define LL_I2S_AUDIOFREQ_32K 32000U /*!< Audio Frequency configuration 32000 Hz */ 01321 #define LL_I2S_AUDIOFREQ_22K 22050U /*!< Audio Frequency configuration 22050 Hz */ 01322 #define LL_I2S_AUDIOFREQ_16K 16000U /*!< Audio Frequency configuration 16000 Hz */ 01323 #define LL_I2S_AUDIOFREQ_11K 11025U /*!< Audio Frequency configuration 11025 Hz */ 01324 #define LL_I2S_AUDIOFREQ_8K 8000U /*!< Audio Frequency configuration 8000 Hz */ 01325 #define LL_I2S_AUDIOFREQ_DEFAULT 2U /*!< Audio Freq not specified. Register I2SDIV = 2 */ 01326 /** 01327 * @} 01328 */ 01329 #endif /* USE_FULL_LL_DRIVER */ 01330 01331 /** 01332 * @} 01333 */ 01334 01335 /* Exported macro ------------------------------------------------------------*/ 01336 /** @defgroup I2S_LL_Exported_Macros I2S Exported Macros 01337 * @{ 01338 */ 01339 01340 /** @defgroup I2S_LL_EM_WRITE_READ Common Write and read registers Macros 01341 * @{ 01342 */ 01343 01344 /** 01345 * @brief Write a value in I2S register 01346 * @param __INSTANCE__ I2S Instance 01347 * @param __REG__ Register to be written 01348 * @param __VALUE__ Value to be written in the register 01349 * @retval None 01350 */ 01351 #define LL_I2S_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 01352 01353 /** 01354 * @brief Read a value in I2S register 01355 * @param __INSTANCE__ I2S Instance 01356 * @param __REG__ Register to be read 01357 * @retval Register value 01358 */ 01359 #define LL_I2S_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 01360 /** 01361 * @} 01362 */ 01363 01364 /** 01365 * @} 01366 */ 01367 01368 01369 /* Exported functions --------------------------------------------------------*/ 01370 01371 /** @defgroup I2S_LL_Exported_Functions I2S Exported Functions 01372 * @{ 01373 */ 01374 01375 /** @defgroup I2S_LL_EF_Configuration Configuration 01376 * @{ 01377 */ 01378 01379 /** 01380 * @brief Select I2S mode and Enable I2S peripheral 01381 * @rmtoll I2SCFGR I2SMOD LL_I2S_Enable\n 01382 * I2SCFGR I2SE LL_I2S_Enable 01383 * @param SPIx SPI Instance 01384 * @retval None 01385 */ 01386 __STATIC_INLINE void LL_I2S_Enable(SPI_TypeDef *SPIx) 01387 { 01388 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); 01389 } 01390 01391 /** 01392 * @brief Disable I2S peripheral 01393 * @rmtoll I2SCFGR I2SE LL_I2S_Disable 01394 * @param SPIx SPI Instance 01395 * @retval None 01396 */ 01397 __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) 01398 { 01399 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD | SPI_I2SCFGR_I2SE); 01400 } 01401 01402 /** 01403 * @brief Check if I2S peripheral is enabled 01404 * @rmtoll I2SCFGR I2SE LL_I2S_IsEnabled 01405 * @param SPIx SPI Instance 01406 * @retval State of bit (1 or 0). 01407 */ 01408 __STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) 01409 { 01410 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)); 01411 } 01412 01413 /** 01414 * @brief Set I2S data frame length 01415 * @rmtoll I2SCFGR DATLEN LL_I2S_SetDataFormat\n 01416 * I2SCFGR CHLEN LL_I2S_SetDataFormat 01417 * @param SPIx SPI Instance 01418 * @param DataFormat This parameter can be one of the following values: 01419 * @arg @ref LL_I2S_DATAFORMAT_16B 01420 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED 01421 * @arg @ref LL_I2S_DATAFORMAT_24B 01422 * @arg @ref LL_I2S_DATAFORMAT_32B 01423 * @retval None 01424 */ 01425 __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat) 01426 { 01427 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN, DataFormat); 01428 } 01429 01430 /** 01431 * @brief Get I2S data frame length 01432 * @rmtoll I2SCFGR DATLEN LL_I2S_GetDataFormat\n 01433 * I2SCFGR CHLEN LL_I2S_GetDataFormat 01434 * @param SPIx SPI Instance 01435 * @retval Returned value can be one of the following values: 01436 * @arg @ref LL_I2S_DATAFORMAT_16B 01437 * @arg @ref LL_I2S_DATAFORMAT_16B_EXTENDED 01438 * @arg @ref LL_I2S_DATAFORMAT_24B 01439 * @arg @ref LL_I2S_DATAFORMAT_32B 01440 */ 01441 __STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) 01442 { 01443 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); 01444 } 01445 01446 /** 01447 * @brief Set I2S clock polarity 01448 * @rmtoll I2SCFGR CKPOL LL_I2S_SetClockPolarity 01449 * @param SPIx SPI Instance 01450 * @param ClockPolarity This parameter can be one of the following values: 01451 * @arg @ref LL_I2S_POLARITY_LOW 01452 * @arg @ref LL_I2S_POLARITY_HIGH 01453 * @retval None 01454 */ 01455 __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) 01456 { 01457 SET_BIT(SPIx->I2SCFGR, ClockPolarity); 01458 } 01459 01460 /** 01461 * @brief Get I2S clock polarity 01462 * @rmtoll I2SCFGR CKPOL LL_I2S_GetClockPolarity 01463 * @param SPIx SPI Instance 01464 * @retval Returned value can be one of the following values: 01465 * @arg @ref LL_I2S_POLARITY_LOW 01466 * @arg @ref LL_I2S_POLARITY_HIGH 01467 */ 01468 __STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) 01469 { 01470 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); 01471 } 01472 01473 /** 01474 * @brief Set I2S standard protocol 01475 * @rmtoll I2SCFGR I2SSTD LL_I2S_SetStandard\n 01476 * I2SCFGR PCMSYNC LL_I2S_SetStandard 01477 * @param SPIx SPI Instance 01478 * @param Standard This parameter can be one of the following values: 01479 * @arg @ref LL_I2S_STANDARD_PHILIPS 01480 * @arg @ref LL_I2S_STANDARD_MSB 01481 * @arg @ref LL_I2S_STANDARD_LSB 01482 * @arg @ref LL_I2S_STANDARD_PCM_SHORT 01483 * @arg @ref LL_I2S_STANDARD_PCM_LONG 01484 * @retval None 01485 */ 01486 __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) 01487 { 01488 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC, Standard); 01489 } 01490 01491 /** 01492 * @brief Get I2S standard protocol 01493 * @rmtoll I2SCFGR I2SSTD LL_I2S_GetStandard\n 01494 * I2SCFGR PCMSYNC LL_I2S_GetStandard 01495 * @param SPIx SPI Instance 01496 * @retval Returned value can be one of the following values: 01497 * @arg @ref LL_I2S_STANDARD_PHILIPS 01498 * @arg @ref LL_I2S_STANDARD_MSB 01499 * @arg @ref LL_I2S_STANDARD_LSB 01500 * @arg @ref LL_I2S_STANDARD_PCM_SHORT 01501 * @arg @ref LL_I2S_STANDARD_PCM_LONG 01502 */ 01503 __STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) 01504 { 01505 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); 01506 } 01507 01508 /** 01509 * @brief Set I2S transfer mode 01510 * @rmtoll I2SCFGR I2SCFG LL_I2S_SetTransferMode 01511 * @param SPIx SPI Instance 01512 * @param Mode This parameter can be one of the following values: 01513 * @arg @ref LL_I2S_MODE_SLAVE_TX 01514 * @arg @ref LL_I2S_MODE_SLAVE_RX 01515 * @arg @ref LL_I2S_MODE_MASTER_TX 01516 * @arg @ref LL_I2S_MODE_MASTER_RX 01517 * @retval None 01518 */ 01519 __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) 01520 { 01521 MODIFY_REG(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG, Mode); 01522 } 01523 01524 /** 01525 * @brief Get I2S transfer mode 01526 * @rmtoll I2SCFGR I2SCFG LL_I2S_GetTransferMode 01527 * @param SPIx SPI Instance 01528 * @retval Returned value can be one of the following values: 01529 * @arg @ref LL_I2S_MODE_SLAVE_TX 01530 * @arg @ref LL_I2S_MODE_SLAVE_RX 01531 * @arg @ref LL_I2S_MODE_MASTER_TX 01532 * @arg @ref LL_I2S_MODE_MASTER_RX 01533 */ 01534 __STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) 01535 { 01536 return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); 01537 } 01538 01539 /** 01540 * @brief Set I2S linear prescaler 01541 * @rmtoll I2SPR I2SDIV LL_I2S_SetPrescalerLinear 01542 * @param SPIx SPI Instance 01543 * @param PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF 01544 * @retval None 01545 */ 01546 __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t PrescalerLinear) 01547 { 01548 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV, PrescalerLinear); 01549 } 01550 01551 /** 01552 * @brief Get I2S linear prescaler 01553 * @rmtoll I2SPR I2SDIV LL_I2S_GetPrescalerLinear 01554 * @param SPIx SPI Instance 01555 * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF 01556 */ 01557 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) 01558 { 01559 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); 01560 } 01561 01562 /** 01563 * @brief Set I2S parity prescaler 01564 * @rmtoll I2SPR ODD LL_I2S_SetPrescalerParity 01565 * @param SPIx SPI Instance 01566 * @param PrescalerParity This parameter can be one of the following values: 01567 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN 01568 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD 01569 * @retval None 01570 */ 01571 __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t PrescalerParity) 01572 { 01573 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_ODD, PrescalerParity << 8U); 01574 } 01575 01576 /** 01577 * @brief Get I2S parity prescaler 01578 * @rmtoll I2SPR ODD LL_I2S_GetPrescalerParity 01579 * @param SPIx SPI Instance 01580 * @retval Returned value can be one of the following values: 01581 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN 01582 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD 01583 */ 01584 __STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) 01585 { 01586 return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); 01587 } 01588 01589 /** 01590 * @brief Enable the master clock ouput (Pin MCK) 01591 * @rmtoll I2SPR MCKOE LL_I2S_EnableMasterClock 01592 * @param SPIx SPI Instance 01593 * @retval None 01594 */ 01595 __STATIC_INLINE void LL_I2S_EnableMasterClock(SPI_TypeDef *SPIx) 01596 { 01597 SET_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); 01598 } 01599 01600 /** 01601 * @brief Disable the master clock ouput (Pin MCK) 01602 * @rmtoll I2SPR MCKOE LL_I2S_DisableMasterClock 01603 * @param SPIx SPI Instance 01604 * @retval None 01605 */ 01606 __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) 01607 { 01608 CLEAR_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE); 01609 } 01610 01611 /** 01612 * @brief Check if the master clock ouput (Pin MCK) is enabled 01613 * @rmtoll I2SPR MCKOE LL_I2S_IsEnabledMasterClock 01614 * @param SPIx SPI Instance 01615 * @retval State of bit (1 or 0). 01616 */ 01617 __STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) 01618 { 01619 return (READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)); 01620 } 01621 01622 #if defined(SPI_I2SCFGR_ASTRTEN) 01623 /** 01624 * @brief Enable asynchronous start 01625 * @rmtoll I2SCFGR ASTRTEN LL_I2S_EnableAsyncStart 01626 * @param SPIx SPI Instance 01627 * @retval None 01628 */ 01629 __STATIC_INLINE void LL_I2S_EnableAsyncStart(SPI_TypeDef *SPIx) 01630 { 01631 SET_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); 01632 } 01633 01634 /** 01635 * @brief Disable asynchronous start 01636 * @rmtoll I2SCFGR ASTRTEN LL_I2S_DisableAsyncStart 01637 * @param SPIx SPI Instance 01638 * @retval None 01639 */ 01640 __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) 01641 { 01642 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN); 01643 } 01644 01645 /** 01646 * @brief Check if asynchronous start is enabled 01647 * @rmtoll I2SCFGR ASTRTEN LL_I2S_IsEnabledAsyncStart 01648 * @param SPIx SPI Instance 01649 * @retval State of bit (1 or 0). 01650 */ 01651 __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) 01652 { 01653 return (READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)); 01654 } 01655 #endif /* SPI_I2SCFGR_ASTRTEN */ 01656 01657 /** 01658 * @} 01659 */ 01660 01661 /** @defgroup I2S_LL_EF_FLAG FLAG Management 01662 * @{ 01663 */ 01664 01665 /** 01666 * @brief Check if Rx buffer is not empty 01667 * @rmtoll SR RXNE LL_I2S_IsActiveFlag_RXNE 01668 * @param SPIx SPI Instance 01669 * @retval State of bit (1 or 0). 01670 */ 01671 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) 01672 { 01673 return LL_SPI_IsActiveFlag_RXNE(SPIx); 01674 } 01675 01676 /** 01677 * @brief Check if Tx buffer is empty 01678 * @rmtoll SR TXE LL_I2S_IsActiveFlag_TXE 01679 * @param SPIx SPI Instance 01680 * @retval State of bit (1 or 0). 01681 */ 01682 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) 01683 { 01684 return LL_SPI_IsActiveFlag_TXE(SPIx); 01685 } 01686 01687 /** 01688 * @brief Get busy flag 01689 * @rmtoll SR BSY LL_I2S_IsActiveFlag_BSY 01690 * @param SPIx SPI Instance 01691 * @retval State of bit (1 or 0). 01692 */ 01693 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) 01694 { 01695 return LL_SPI_IsActiveFlag_BSY(SPIx); 01696 } 01697 01698 /** 01699 * @brief Get overrun error flag 01700 * @rmtoll SR OVR LL_I2S_IsActiveFlag_OVR 01701 * @param SPIx SPI Instance 01702 * @retval State of bit (1 or 0). 01703 */ 01704 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) 01705 { 01706 return LL_SPI_IsActiveFlag_OVR(SPIx); 01707 } 01708 01709 /** 01710 * @brief Get underrun error flag 01711 * @rmtoll SR UDR LL_I2S_IsActiveFlag_UDR 01712 * @param SPIx SPI Instance 01713 * @retval State of bit (1 or 0). 01714 */ 01715 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) 01716 { 01717 return (READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)); 01718 } 01719 01720 /** 01721 * @brief Get frame format error flag 01722 * @rmtoll SR FRE LL_I2S_IsActiveFlag_FRE 01723 * @param SPIx SPI Instance 01724 * @retval State of bit (1 or 0). 01725 */ 01726 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) 01727 { 01728 return LL_SPI_IsActiveFlag_FRE(SPIx); 01729 } 01730 01731 /** 01732 * @brief Get channel side flag. 01733 * @note 0: Channel Left has to be transmitted or has been received\n 01734 * 1: Channel Right has to be transmitted or has been received\n 01735 * It has no significance in PCM mode. 01736 * @rmtoll SR CHSIDE LL_I2S_IsActiveFlag_CHSIDE 01737 * @param SPIx SPI Instance 01738 * @retval State of bit (1 or 0). 01739 */ 01740 __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) 01741 { 01742 return (READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)); 01743 } 01744 01745 /** 01746 * @brief Clear overrun error flag 01747 * @rmtoll SR OVR LL_I2S_ClearFlag_OVR 01748 * @param SPIx SPI Instance 01749 * @retval None 01750 */ 01751 __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) 01752 { 01753 LL_SPI_ClearFlag_OVR(SPIx); 01754 } 01755 01756 /** 01757 * @brief Clear underrun error flag 01758 * @rmtoll SR UDR LL_I2S_ClearFlag_UDR 01759 * @param SPIx SPI Instance 01760 * @retval None 01761 */ 01762 __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) 01763 { 01764 __IO uint32_t tmpreg; 01765 tmpreg = SPIx->SR; 01766 (void)tmpreg; 01767 } 01768 01769 /** 01770 * @brief Clear frame format error flag 01771 * @rmtoll SR FRE LL_I2S_ClearFlag_FRE 01772 * @param SPIx SPI Instance 01773 * @retval None 01774 */ 01775 __STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) 01776 { 01777 LL_SPI_ClearFlag_FRE(SPIx); 01778 } 01779 01780 /** 01781 * @} 01782 */ 01783 01784 /** @defgroup I2S_LL_EF_IT Interrupt Management 01785 * @{ 01786 */ 01787 01788 /** 01789 * @brief Enable error IT 01790 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). 01791 * @rmtoll CR2 ERRIE LL_I2S_EnableIT_ERR 01792 * @param SPIx SPI Instance 01793 * @retval None 01794 */ 01795 __STATIC_INLINE void LL_I2S_EnableIT_ERR(SPI_TypeDef *SPIx) 01796 { 01797 LL_SPI_EnableIT_ERR(SPIx); 01798 } 01799 01800 /** 01801 * @brief Enable Rx buffer not empty IT 01802 * @rmtoll CR2 RXNEIE LL_I2S_EnableIT_RXNE 01803 * @param SPIx SPI Instance 01804 * @retval None 01805 */ 01806 __STATIC_INLINE void LL_I2S_EnableIT_RXNE(SPI_TypeDef *SPIx) 01807 { 01808 LL_SPI_EnableIT_RXNE(SPIx); 01809 } 01810 01811 /** 01812 * @brief Enable Tx buffer empty IT 01813 * @rmtoll CR2 TXEIE LL_I2S_EnableIT_TXE 01814 * @param SPIx SPI Instance 01815 * @retval None 01816 */ 01817 __STATIC_INLINE void LL_I2S_EnableIT_TXE(SPI_TypeDef *SPIx) 01818 { 01819 LL_SPI_EnableIT_TXE(SPIx); 01820 } 01821 01822 /** 01823 * @brief Disable error IT 01824 * @note This bit controls the generation of an interrupt when an error condition occurs (OVR, UDR and FRE in I2S mode). 01825 * @rmtoll CR2 ERRIE LL_I2S_DisableIT_ERR 01826 * @param SPIx SPI Instance 01827 * @retval None 01828 */ 01829 __STATIC_INLINE void LL_I2S_DisableIT_ERR(SPI_TypeDef *SPIx) 01830 { 01831 LL_SPI_DisableIT_ERR(SPIx); 01832 } 01833 01834 /** 01835 * @brief Disable Rx buffer not empty IT 01836 * @rmtoll CR2 RXNEIE LL_I2S_DisableIT_RXNE 01837 * @param SPIx SPI Instance 01838 * @retval None 01839 */ 01840 __STATIC_INLINE void LL_I2S_DisableIT_RXNE(SPI_TypeDef *SPIx) 01841 { 01842 LL_SPI_DisableIT_RXNE(SPIx); 01843 } 01844 01845 /** 01846 * @brief Disable Tx buffer empty IT 01847 * @rmtoll CR2 TXEIE LL_I2S_DisableIT_TXE 01848 * @param SPIx SPI Instance 01849 * @retval None 01850 */ 01851 __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) 01852 { 01853 LL_SPI_DisableIT_TXE(SPIx); 01854 } 01855 01856 /** 01857 * @brief Check if ERR IT is enabled 01858 * @rmtoll CR2 ERRIE LL_I2S_IsEnabledIT_ERR 01859 * @param SPIx SPI Instance 01860 * @retval State of bit (1 or 0). 01861 */ 01862 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) 01863 { 01864 return LL_SPI_IsEnabledIT_ERR(SPIx); 01865 } 01866 01867 /** 01868 * @brief Check if RXNE IT is enabled 01869 * @rmtoll CR2 RXNEIE LL_I2S_IsEnabledIT_RXNE 01870 * @param SPIx SPI Instance 01871 * @retval State of bit (1 or 0). 01872 */ 01873 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) 01874 { 01875 return LL_SPI_IsEnabledIT_RXNE(SPIx); 01876 } 01877 01878 /** 01879 * @brief Check if TXE IT is enabled 01880 * @rmtoll CR2 TXEIE LL_I2S_IsEnabledIT_TXE 01881 * @param SPIx SPI Instance 01882 * @retval State of bit (1 or 0). 01883 */ 01884 __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) 01885 { 01886 return LL_SPI_IsEnabledIT_TXE(SPIx); 01887 } 01888 01889 /** 01890 * @} 01891 */ 01892 01893 /** @defgroup I2S_LL_EF_DMA DMA Management 01894 * @{ 01895 */ 01896 01897 /** 01898 * @brief Enable DMA Rx 01899 * @rmtoll CR2 RXDMAEN LL_I2S_EnableDMAReq_RX 01900 * @param SPIx SPI Instance 01901 * @retval None 01902 */ 01903 __STATIC_INLINE void LL_I2S_EnableDMAReq_RX(SPI_TypeDef *SPIx) 01904 { 01905 LL_SPI_EnableDMAReq_RX(SPIx); 01906 } 01907 01908 /** 01909 * @brief Disable DMA Rx 01910 * @rmtoll CR2 RXDMAEN LL_I2S_DisableDMAReq_RX 01911 * @param SPIx SPI Instance 01912 * @retval None 01913 */ 01914 __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) 01915 { 01916 LL_SPI_DisableDMAReq_RX(SPIx); 01917 } 01918 01919 /** 01920 * @brief Check if DMA Rx is enabled 01921 * @rmtoll CR2 RXDMAEN LL_I2S_IsEnabledDMAReq_RX 01922 * @param SPIx SPI Instance 01923 * @retval State of bit (1 or 0). 01924 */ 01925 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) 01926 { 01927 return LL_SPI_IsEnabledDMAReq_RX(SPIx); 01928 } 01929 01930 /** 01931 * @brief Enable DMA Tx 01932 * @rmtoll CR2 TXDMAEN LL_I2S_EnableDMAReq_TX 01933 * @param SPIx SPI Instance 01934 * @retval None 01935 */ 01936 __STATIC_INLINE void LL_I2S_EnableDMAReq_TX(SPI_TypeDef *SPIx) 01937 { 01938 LL_SPI_EnableDMAReq_TX(SPIx); 01939 } 01940 01941 /** 01942 * @brief Disable DMA Tx 01943 * @rmtoll CR2 TXDMAEN LL_I2S_DisableDMAReq_TX 01944 * @param SPIx SPI Instance 01945 * @retval None 01946 */ 01947 __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) 01948 { 01949 LL_SPI_DisableDMAReq_TX(SPIx); 01950 } 01951 01952 /** 01953 * @brief Check if DMA Tx is enabled 01954 * @rmtoll CR2 TXDMAEN LL_I2S_IsEnabledDMAReq_TX 01955 * @param SPIx SPI Instance 01956 * @retval State of bit (1 or 0). 01957 */ 01958 __STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) 01959 { 01960 return LL_SPI_IsEnabledDMAReq_TX(SPIx); 01961 } 01962 01963 /** 01964 * @} 01965 */ 01966 01967 /** @defgroup I2S_LL_EF_DATA DATA Management 01968 * @{ 01969 */ 01970 01971 /** 01972 * @brief Read 16-Bits in data register 01973 * @rmtoll DR DR LL_I2S_ReceiveData16 01974 * @param SPIx SPI Instance 01975 * @retval RxData Value between Min_Data=0x0000 and Max_Data=0xFFFF 01976 */ 01977 __STATIC_INLINE uint16_t LL_I2S_ReceiveData16(SPI_TypeDef *SPIx) 01978 { 01979 return LL_SPI_ReceiveData16(SPIx); 01980 } 01981 01982 /** 01983 * @brief Write 16-Bits in data register 01984 * @rmtoll DR DR LL_I2S_TransmitData16 01985 * @param SPIx SPI Instance 01986 * @param TxData Value between Min_Data=0x0000 and Max_Data=0xFFFF 01987 * @retval None 01988 */ 01989 __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) 01990 { 01991 LL_SPI_TransmitData16(SPIx, TxData); 01992 } 01993 01994 /** 01995 * @} 01996 */ 01997 01998 #if defined(USE_FULL_LL_DRIVER) 01999 /** @defgroup I2S_LL_EF_Init Initialization and de-initialization functions 02000 * @{ 02001 */ 02002 02003 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); 02004 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); 02005 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); 02006 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); 02007 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) 02008 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct); 02009 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ 02010 02011 /** 02012 * @} 02013 */ 02014 #endif /* USE_FULL_LL_DRIVER */ 02015 02016 /** 02017 * @} 02018 */ 02019 02020 /** 02021 * @} 02022 */ 02023 02024 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */ 02025 02026 /** 02027 * @} 02028 */ 02029 02030 #ifdef __cplusplus 02031 } 02032 #endif 02033 02034 #endif /* __STM32F4xx_LL_SPI_H */ 02035 02036 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/