STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_spi.c 00004 * @author MCD Application Team 00005 * @brief SPI LL module driver. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 #if defined(USE_FULL_LL_DRIVER) 00036 00037 /* Includes ------------------------------------------------------------------*/ 00038 #include "stm32f4xx_ll_spi.h" 00039 #include "stm32f4xx_ll_bus.h" 00040 #include "stm32f4xx_ll_rcc.h" 00041 00042 #ifdef USE_FULL_ASSERT 00043 #include "stm32_assert.h" 00044 #else 00045 #define assert_param(expr) ((void)0U) 00046 #endif 00047 00048 /** @addtogroup STM32F4xx_LL_Driver 00049 * @{ 00050 */ 00051 00052 #if defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) 00053 00054 /** @addtogroup SPI_LL 00055 * @{ 00056 */ 00057 00058 /* Private types -------------------------------------------------------------*/ 00059 /* Private variables ---------------------------------------------------------*/ 00060 00061 /* Private constants ---------------------------------------------------------*/ 00062 /** @defgroup SPI_LL_Private_Constants SPI Private Constants 00063 * @{ 00064 */ 00065 /* SPI registers Masks */ 00066 #define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ 00067 SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ 00068 SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_DFF | \ 00069 SPI_CR1_CRCNEXT | SPI_CR1_CRCEN | SPI_CR1_BIDIOE | \ 00070 SPI_CR1_BIDIMODE) 00071 /** 00072 * @} 00073 */ 00074 00075 /* Private macros ------------------------------------------------------------*/ 00076 /** @defgroup SPI_LL_Private_Macros SPI Private Macros 00077 * @{ 00078 */ 00079 #define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ 00080 || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ 00081 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ 00082 || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) 00083 00084 #define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ 00085 || ((__VALUE__) == LL_SPI_MODE_SLAVE)) 00086 00087 #define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ 00088 || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) 00089 00090 #define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ 00091 || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) 00092 00093 #define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ 00094 || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) 00095 00096 #define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ 00097 || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ 00098 || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) 00099 00100 #define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ 00101 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ 00102 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ 00103 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ 00104 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ 00105 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ 00106 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ 00107 || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) 00108 00109 #define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ 00110 || ((__VALUE__) == LL_SPI_MSB_FIRST)) 00111 00112 #define IS_LL_SPI_CRCCALCULATION(__VALUE__) (((__VALUE__) == LL_SPI_CRCCALCULATION_ENABLE) \ 00113 || ((__VALUE__) == LL_SPI_CRCCALCULATION_DISABLE)) 00114 00115 #define IS_LL_SPI_CRC_POLYNOMIAL(__VALUE__) ((__VALUE__) >= 0x1U) 00116 00117 /** 00118 * @} 00119 */ 00120 00121 /* Private function prototypes -----------------------------------------------*/ 00122 00123 /* Exported functions --------------------------------------------------------*/ 00124 /** @addtogroup SPI_LL_Exported_Functions 00125 * @{ 00126 */ 00127 00128 /** @addtogroup SPI_LL_EF_Init 00129 * @{ 00130 */ 00131 00132 /** 00133 * @brief De-initialize the SPI registers to their default reset values. 00134 * @param SPIx SPI Instance 00135 * @retval An ErrorStatus enumeration value: 00136 * - SUCCESS: SPI registers are de-initialized 00137 * - ERROR: SPI registers are not de-initialized 00138 */ 00139 ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) 00140 { 00141 ErrorStatus status = ERROR; 00142 00143 /* Check the parameters */ 00144 assert_param(IS_SPI_ALL_INSTANCE(SPIx)); 00145 00146 #if defined(SPI1) 00147 if (SPIx == SPI1) 00148 { 00149 /* Force reset of SPI clock */ 00150 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI1); 00151 00152 /* Release reset of SPI clock */ 00153 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI1); 00154 00155 status = SUCCESS; 00156 } 00157 #endif /* SPI1 */ 00158 #if defined(SPI2) 00159 if (SPIx == SPI2) 00160 { 00161 /* Force reset of SPI clock */ 00162 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); 00163 00164 /* Release reset of SPI clock */ 00165 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); 00166 00167 status = SUCCESS; 00168 } 00169 #endif /* SPI2 */ 00170 #if defined(SPI3) 00171 if (SPIx == SPI3) 00172 { 00173 /* Force reset of SPI clock */ 00174 LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI3); 00175 00176 /* Release reset of SPI clock */ 00177 LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI3); 00178 00179 status = SUCCESS; 00180 } 00181 #endif /* SPI3 */ 00182 #if defined(SPI4) 00183 if (SPIx == SPI4) 00184 { 00185 /* Force reset of SPI clock */ 00186 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI4); 00187 00188 /* Release reset of SPI clock */ 00189 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI4); 00190 00191 status = SUCCESS; 00192 } 00193 #endif /* SPI4 */ 00194 #if defined(SPI5) 00195 if (SPIx == SPI5) 00196 { 00197 /* Force reset of SPI clock */ 00198 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI5); 00199 00200 /* Release reset of SPI clock */ 00201 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI5); 00202 00203 status = SUCCESS; 00204 } 00205 #endif /* SPI5 */ 00206 #if defined(SPI6) 00207 if (SPIx == SPI6) 00208 { 00209 /* Force reset of SPI clock */ 00210 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_SPI6); 00211 00212 /* Release reset of SPI clock */ 00213 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_SPI6); 00214 00215 status = SUCCESS; 00216 } 00217 #endif /* SPI6 */ 00218 00219 return status; 00220 } 00221 00222 /** 00223 * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. 00224 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), 00225 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. 00226 * @param SPIx SPI Instance 00227 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure 00228 * @retval An ErrorStatus enumeration value. (Return always SUCCESS) 00229 */ 00230 ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) 00231 { 00232 ErrorStatus status = ERROR; 00233 00234 /* Check the SPI Instance SPIx*/ 00235 assert_param(IS_SPI_ALL_INSTANCE(SPIx)); 00236 00237 /* Check the SPI parameters from SPI_InitStruct*/ 00238 assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); 00239 assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); 00240 assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); 00241 assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); 00242 assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); 00243 assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); 00244 assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); 00245 assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); 00246 assert_param(IS_LL_SPI_CRCCALCULATION(SPI_InitStruct->CRCCalculation)); 00247 00248 if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) 00249 { 00250 /*---------------------------- SPIx CR1 Configuration ------------------------ 00251 * Configure SPIx CR1 with parameters: 00252 * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits 00253 * - Master/Slave Mode: SPI_CR1_MSTR bit 00254 * - DataWidth: SPI_CR1_DFF bit 00255 * - ClockPolarity: SPI_CR1_CPOL bit 00256 * - ClockPhase: SPI_CR1_CPHA bit 00257 * - NSS management: SPI_CR1_SSM bit 00258 * - BaudRate prescaler: SPI_CR1_BR[2:0] bits 00259 * - BitOrder: SPI_CR1_LSBFIRST bit 00260 * - CRCCalculation: SPI_CR1_CRCEN bit 00261 */ 00262 MODIFY_REG(SPIx->CR1, 00263 SPI_CR1_CLEAR_MASK, 00264 SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | SPI_InitStruct->DataWidth | 00265 SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | 00266 SPI_InitStruct->NSS | SPI_InitStruct->BaudRate | 00267 SPI_InitStruct->BitOrder | SPI_InitStruct->CRCCalculation); 00268 00269 /*---------------------------- SPIx CR2 Configuration ------------------------ 00270 * Configure SPIx CR2 with parameters: 00271 * - NSS management: SSOE bit 00272 */ 00273 MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, (SPI_InitStruct->NSS >> 16U)); 00274 00275 /*---------------------------- SPIx CRCPR Configuration ---------------------- 00276 * Configure SPIx CRCPR with parameters: 00277 * - CRCPoly: CRCPOLY[15:0] bits 00278 */ 00279 if (SPI_InitStruct->CRCCalculation == LL_SPI_CRCCALCULATION_ENABLE) 00280 { 00281 assert_param(IS_LL_SPI_CRC_POLYNOMIAL(SPI_InitStruct->CRCPoly)); 00282 LL_SPI_SetCRCPolynomial(SPIx, SPI_InitStruct->CRCPoly); 00283 } 00284 status = SUCCESS; 00285 } 00286 00287 /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */ 00288 CLEAR_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SMOD); 00289 return status; 00290 } 00291 00292 /** 00293 * @brief Set each @ref LL_SPI_InitTypeDef field to default value. 00294 * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure 00295 * whose fields will be set to default values. 00296 * @retval None 00297 */ 00298 void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) 00299 { 00300 /* Set SPI_InitStruct fields to default values */ 00301 SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; 00302 SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; 00303 SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; 00304 SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; 00305 SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; 00306 SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; 00307 SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; 00308 SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; 00309 SPI_InitStruct->CRCCalculation = LL_SPI_CRCCALCULATION_DISABLE; 00310 SPI_InitStruct->CRCPoly = 7U; 00311 } 00312 00313 /** 00314 * @} 00315 */ 00316 00317 /** 00318 * @} 00319 */ 00320 00321 /** 00322 * @} 00323 */ 00324 00325 /** @addtogroup I2S_LL 00326 * @{ 00327 */ 00328 00329 /* Private types -------------------------------------------------------------*/ 00330 /* Private variables ---------------------------------------------------------*/ 00331 /* Private constants ---------------------------------------------------------*/ 00332 /** @defgroup I2S_LL_Private_Constants I2S Private Constants 00333 * @{ 00334 */ 00335 /* I2S registers Masks */ 00336 #define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ 00337 SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ 00338 SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) 00339 00340 #define I2S_I2SPR_CLEAR_MASK 0x0002U 00341 /** 00342 * @} 00343 */ 00344 /* Private macros ------------------------------------------------------------*/ 00345 /** @defgroup I2S_LL_Private_Macros I2S Private Macros 00346 * @{ 00347 */ 00348 00349 #define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ 00350 || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ 00351 || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ 00352 || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) 00353 00354 #define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ 00355 || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) 00356 00357 #define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ 00358 || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ 00359 || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ 00360 || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ 00361 || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) 00362 00363 #define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ 00364 || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ 00365 || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ 00366 || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) 00367 00368 #define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ 00369 || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) 00370 00371 #define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ 00372 && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ 00373 || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) 00374 00375 #define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) 00376 00377 #define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ 00378 || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) 00379 /** 00380 * @} 00381 */ 00382 00383 /* Private function prototypes -----------------------------------------------*/ 00384 00385 /* Exported functions --------------------------------------------------------*/ 00386 /** @addtogroup I2S_LL_Exported_Functions 00387 * @{ 00388 */ 00389 00390 /** @addtogroup I2S_LL_EF_Init 00391 * @{ 00392 */ 00393 00394 /** 00395 * @brief De-initialize the SPI/I2S registers to their default reset values. 00396 * @param SPIx SPI Instance 00397 * @retval An ErrorStatus enumeration value: 00398 * - SUCCESS: SPI registers are de-initialized 00399 * - ERROR: SPI registers are not de-initialized 00400 */ 00401 ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) 00402 { 00403 return LL_SPI_DeInit(SPIx); 00404 } 00405 00406 /** 00407 * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. 00408 * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), 00409 * SPI IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. 00410 * @param SPIx SPI Instance 00411 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure 00412 * @retval An ErrorStatus enumeration value: 00413 * - SUCCESS: SPI registers are Initialized 00414 * - ERROR: SPI registers are not Initialized 00415 */ 00416 ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) 00417 { 00418 uint16_t i2sdiv = 2U, i2sodd = 0U, packetlength = 1U; 00419 uint32_t tmp = 0U; 00420 uint32_t sourceclock = 0U; 00421 ErrorStatus status = ERROR; 00422 00423 /* Check the I2S parameters */ 00424 assert_param(IS_I2S_ALL_INSTANCE(SPIx)); 00425 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); 00426 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); 00427 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); 00428 assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); 00429 assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); 00430 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); 00431 00432 if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) 00433 { 00434 /*---------------------------- SPIx I2SCFGR Configuration -------------------- 00435 * Configure SPIx I2SCFGR with parameters: 00436 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit 00437 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits 00438 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits 00439 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit 00440 */ 00441 00442 /* Write to SPIx I2SCFGR */ 00443 MODIFY_REG(SPIx->I2SCFGR, 00444 I2S_I2SCFGR_CLEAR_MASK, 00445 I2S_InitStruct->Mode | I2S_InitStruct->Standard | 00446 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | 00447 SPI_I2SCFGR_I2SMOD); 00448 00449 /*---------------------------- SPIx I2SPR Configuration ---------------------- 00450 * Configure SPIx I2SPR with parameters: 00451 * - MCLKOutput: SPI_I2SPR_MCKOE bit 00452 * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits 00453 */ 00454 00455 /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) 00456 * else, default values are used: i2sodd = 0U, i2sdiv = 2U. 00457 */ 00458 if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) 00459 { 00460 /* Check the frame length (For the Prescaler computing) 00461 * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). 00462 */ 00463 if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) 00464 { 00465 /* Packet length is 32 bits */ 00466 packetlength = 2U; 00467 } 00468 00469 /* If an external I2S clock has to be used, the specific define should be set 00470 in the project configuration or in the stm32f4xx_ll_rcc.h file */ 00471 /* Get the I2S source clock value */ 00472 sourceclock = LL_RCC_GetI2SClockFreq(LL_RCC_I2S1_CLKSOURCE); 00473 00474 /* Compute the Real divider depending on the MCLK output state with a floating point */ 00475 if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) 00476 { 00477 /* MCLK output is enabled */ 00478 tmp = (uint16_t)(((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); 00479 } 00480 else 00481 { 00482 /* MCLK output is disabled */ 00483 tmp = (uint16_t)(((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); 00484 } 00485 00486 /* Remove the floating point */ 00487 tmp = tmp / 10U; 00488 00489 /* Check the parity of the divider */ 00490 i2sodd = (uint16_t)(tmp & (uint16_t)0x0001U); 00491 00492 /* Compute the i2sdiv prescaler */ 00493 i2sdiv = (uint16_t)((tmp - i2sodd) / 2U); 00494 00495 /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ 00496 i2sodd = (uint16_t)(i2sodd << 8U); 00497 } 00498 00499 /* Test if the divider is 1 or 0 or greater than 0xFF */ 00500 if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) 00501 { 00502 /* Set the default values */ 00503 i2sdiv = 2U; 00504 i2sodd = 0U; 00505 } 00506 00507 /* Write to SPIx I2SPR register the computed value */ 00508 WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); 00509 00510 status = SUCCESS; 00511 } 00512 return status; 00513 } 00514 00515 /** 00516 * @brief Set each @ref LL_I2S_InitTypeDef field to default value. 00517 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure 00518 * whose fields will be set to default values. 00519 * @retval None 00520 */ 00521 void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) 00522 { 00523 /*--------------- Reset I2S init structure parameters values -----------------*/ 00524 I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; 00525 I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; 00526 I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; 00527 I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; 00528 I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; 00529 I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; 00530 } 00531 00532 /** 00533 * @brief Set linear and parity prescaler. 00534 * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n 00535 * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). 00536 * @param SPIx SPI Instance 00537 * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. 00538 * @param PrescalerParity This parameter can be one of the following values: 00539 * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN 00540 * @arg @ref LL_I2S_PRESCALER_PARITY_ODD 00541 * @retval None 00542 */ 00543 void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) 00544 { 00545 /* Check the I2S parameters */ 00546 assert_param(IS_I2S_ALL_INSTANCE(SPIx)); 00547 assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); 00548 assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); 00549 00550 /* Write to SPIx I2SPR */ 00551 MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); 00552 } 00553 00554 #if defined (SPI_I2S_FULLDUPLEX_SUPPORT) 00555 /** 00556 * @brief Configures the full duplex mode for the I2Sx peripheral using its extension 00557 * I2Sxext according to the specified parameters in the I2S_InitStruct. 00558 * @note The structure pointed by I2S_InitStruct parameter should be the same 00559 * used for the master I2S peripheral. In this case, if the master is 00560 * configured as transmitter, the slave will be receiver and vice versa. 00561 * Or you can force a different mode by modifying the field I2S_Mode to the 00562 * value I2S_SlaveRx or I2S_SlaveTx independently of the master configuration. 00563 * @param I2Sxext SPI Instance 00564 * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure 00565 * @retval An ErrorStatus enumeration value: 00566 * - SUCCESS: I2Sxext registers are Initialized 00567 * - ERROR: I2Sxext registers are not Initialized 00568 */ 00569 ErrorStatus LL_I2S_InitFullDuplex(SPI_TypeDef *I2Sxext, LL_I2S_InitTypeDef *I2S_InitStruct) 00570 { 00571 uint16_t mode = 0U; 00572 ErrorStatus status = ERROR; 00573 00574 /* Check the I2S parameters */ 00575 assert_param(IS_I2S_EXT_ALL_INSTANCE(I2Sxext)); 00576 assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); 00577 assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); 00578 assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); 00579 assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); 00580 00581 if (LL_I2S_IsEnabled(I2Sxext) == 0x00000000U) 00582 { 00583 /*---------------------------- SPIx I2SCFGR Configuration -------------------- 00584 * Configure SPIx I2SCFGR with parameters: 00585 * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit 00586 * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits 00587 * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits 00588 * - ClockPolarity: SPI_I2SCFGR_CKPOL bit 00589 */ 00590 00591 /* Reset I2SPR registers */ 00592 WRITE_REG(I2Sxext->I2SPR, I2S_I2SPR_CLEAR_MASK); 00593 00594 /* Get the mode to be configured for the extended I2S */ 00595 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_TX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_TX)) 00596 { 00597 mode = LL_I2S_MODE_SLAVE_RX; 00598 } 00599 else 00600 { 00601 if ((I2S_InitStruct->Mode == LL_I2S_MODE_MASTER_RX) || (I2S_InitStruct->Mode == LL_I2S_MODE_SLAVE_RX)) 00602 { 00603 mode = LL_I2S_MODE_SLAVE_TX; 00604 } 00605 } 00606 00607 /* Write to SPIx I2SCFGR */ 00608 MODIFY_REG(I2Sxext->I2SCFGR, 00609 I2S_I2SCFGR_CLEAR_MASK, 00610 I2S_InitStruct->Standard | 00611 I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | 00612 SPI_I2SCFGR_I2SMOD | mode); 00613 00614 status = SUCCESS; 00615 } 00616 return status; 00617 } 00618 #endif /* SPI_I2S_FULLDUPLEX_SUPPORT */ 00619 00620 /** 00621 * @} 00622 */ 00623 00624 /** 00625 * @} 00626 */ 00627 00628 /** 00629 * @} 00630 */ 00631 00632 #endif /* defined (SPI1) || defined (SPI2) || defined (SPI3) || defined (SPI4) || defined (SPI5) || defined(SPI6) */ 00633 00634 /** 00635 * @} 00636 */ 00637 00638 #endif /* USE_FULL_LL_DRIVER */ 00639 00640 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/