STM32F439xx HAL User Manual
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Header file of RCC LL module. More...
#include "stm32f4xx.h"
Go to the source code of this file.
Data Structures | |
struct | LL_RCC_ClocksTypeDef |
RCC Clocks Frequency Structure. More... | |
Defines | |
#define | HSE_VALUE 25000000U |
#define | HSI_VALUE 16000000U |
#define | LSE_VALUE 32768U |
#define | LSI_VALUE 32000U |
#define | EXTERNAL_CLOCK_VALUE 12288000U |
#define | LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC |
#define | LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC |
#define | LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC |
#define | LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC |
#define | LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC |
#define | LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC |
#define | LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC |
#define | LL_RCC_CIR_CSSC RCC_CIR_CSSC |
#define | LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF |
#define | LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF |
#define | LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF |
#define | LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF |
#define | LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF |
#define | LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF |
#define | LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF |
#define | LL_RCC_CIR_CSSF RCC_CIR_CSSF |
#define | LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF |
#define | LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF |
#define | LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF |
#define | LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF |
#define | LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF |
#define | LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF |
#define | LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF |
#define | LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE |
#define | LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE |
#define | LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE |
#define | LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE |
#define | LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE |
#define | LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE |
#define | LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE |
#define | LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI |
#define | LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE |
#define | LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL |
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI |
#define | LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE |
#define | LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL |
#define | LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 |
#define | LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 |
#define | LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 |
#define | LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 |
#define | LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 |
#define | LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 |
#define | LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 |
#define | LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 |
#define | LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 |
#define | LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 |
#define | LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 |
#define | LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 |
#define | LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 |
#define | LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 |
#define | LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 |
#define | LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 |
#define | LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 |
#define | LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 |
#define | LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 |
#define | LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) |
#define | LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) |
#define | LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) |
#define | LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) |
#define | LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) |
#define | LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) |
#define | LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) |
#define | LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) |
#define | LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) |
#define | LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) |
#define | LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) |
#define | LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) |
#define | LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) |
#define | LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) |
#define | LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) |
#define | LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) |
#define | LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) |
#define | LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) |
#define | LL_RCC_RTC_NOCLOCK 0x00000000U |
#define | LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 |
#define | LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 |
#define | LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
#define | LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 |
#define | LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) |
#define | LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) |
#define | LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
#define | LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 |
#define | LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) |
#define | LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) |
#define | LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
#define | LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) |
#define | LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) |
#define | LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) |
#define | LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) |
#define | LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) |
#define | LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U |
#define | LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU |
#define | LL_RCC_SAI1_A_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1ASRC | 0x00000000U) |
#define | LL_RCC_SAI1_A_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_0 >> 16)) |
#define | LL_RCC_SAI1_A_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1ASRC | (RCC_DCKCFGR_SAI1ASRC_1 >> 16)) |
#define | LL_RCC_SAI1_B_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR_SAI1BSRC | 0x00000000U) |
#define | LL_RCC_SAI1_B_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_0 >> 16)) |
#define | LL_RCC_SAI1_B_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR_SAI1BSRC | (RCC_DCKCFGR_SAI1BSRC_1 >> 16)) |
#define | LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U |
#define | LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC |
#define | LL_RCC_SAI1_A_CLKSOURCE RCC_DCKCFGR_SAI1ASRC |
#define | LL_RCC_SAI1_B_CLKSOURCE RCC_DCKCFGR_SAI1BSRC |
#define | LL_RCC_SDIO_CLKSOURCE RCC_PLLCFGR_PLLQ |
#define | LL_RCC_RNG_CLKSOURCE RCC_PLLCFGR_PLLQ |
#define | LL_RCC_USB_CLKSOURCE RCC_PLLCFGR_PLLQ |
#define | LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC |
#define | LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR_PLLSAIDIVR |
#define | LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U |
#define | LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 |
#define | LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 |
#define | LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL |
#define | LL_RCC_TIM_PRESCALER_TWICE 0x00000000U |
#define | LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR_TIMPRE |
#define | LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI |
#define | LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE |
#define | LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) |
#define | LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) |
#define | LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) |
#define | LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) |
#define | LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) |
#define | LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) |
#define | LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) |
#define | LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) |
#define | LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) |
#define | LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) |
#define | LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) |
#define | LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) |
#define | LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) |
#define | LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) |
#define | LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) |
#define | LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) |
#define | LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) |
#define | LL_RCC_PLLP_DIV_2 0x00000000U |
#define | LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 |
#define | LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 |
#define | LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) |
#define | LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 |
#define | LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) |
#define | LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 |
#define | LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) |
#define | LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) |
#define | LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) |
#define | LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 |
#define | LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) |
#define | LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) |
#define | LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) |
#define | LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) |
#define | LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) |
#define | LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) |
#define | LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) |
#define | LL_RCC_SPREAD_SELECT_CENTER 0x00000000U |
#define | LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL |
#define | LL_RCC_PLLI2SM_DIV_2 LL_RCC_PLLM_DIV_2 |
#define | LL_RCC_PLLI2SM_DIV_3 LL_RCC_PLLM_DIV_3 |
#define | LL_RCC_PLLI2SM_DIV_4 LL_RCC_PLLM_DIV_4 |
#define | LL_RCC_PLLI2SM_DIV_5 LL_RCC_PLLM_DIV_5 |
#define | LL_RCC_PLLI2SM_DIV_6 LL_RCC_PLLM_DIV_6 |
#define | LL_RCC_PLLI2SM_DIV_7 LL_RCC_PLLM_DIV_7 |
#define | LL_RCC_PLLI2SM_DIV_8 LL_RCC_PLLM_DIV_8 |
#define | LL_RCC_PLLI2SM_DIV_9 LL_RCC_PLLM_DIV_9 |
#define | LL_RCC_PLLI2SM_DIV_10 LL_RCC_PLLM_DIV_10 |
#define | LL_RCC_PLLI2SM_DIV_11 LL_RCC_PLLM_DIV_11 |
#define | LL_RCC_PLLI2SM_DIV_12 LL_RCC_PLLM_DIV_12 |
#define | LL_RCC_PLLI2SM_DIV_13 LL_RCC_PLLM_DIV_13 |
#define | LL_RCC_PLLI2SM_DIV_14 LL_RCC_PLLM_DIV_14 |
#define | LL_RCC_PLLI2SM_DIV_15 LL_RCC_PLLM_DIV_15 |
#define | LL_RCC_PLLI2SM_DIV_16 LL_RCC_PLLM_DIV_16 |
#define | LL_RCC_PLLI2SM_DIV_17 LL_RCC_PLLM_DIV_17 |
#define | LL_RCC_PLLI2SM_DIV_18 LL_RCC_PLLM_DIV_18 |
#define | LL_RCC_PLLI2SM_DIV_19 LL_RCC_PLLM_DIV_19 |
#define | LL_RCC_PLLI2SM_DIV_20 LL_RCC_PLLM_DIV_20 |
#define | LL_RCC_PLLI2SM_DIV_21 LL_RCC_PLLM_DIV_21 |
#define | LL_RCC_PLLI2SM_DIV_22 LL_RCC_PLLM_DIV_22 |
#define | LL_RCC_PLLI2SM_DIV_23 LL_RCC_PLLM_DIV_23 |
#define | LL_RCC_PLLI2SM_DIV_24 LL_RCC_PLLM_DIV_24 |
#define | LL_RCC_PLLI2SM_DIV_25 LL_RCC_PLLM_DIV_25 |
#define | LL_RCC_PLLI2SM_DIV_26 LL_RCC_PLLM_DIV_26 |
#define | LL_RCC_PLLI2SM_DIV_27 LL_RCC_PLLM_DIV_27 |
#define | LL_RCC_PLLI2SM_DIV_28 LL_RCC_PLLM_DIV_28 |
#define | LL_RCC_PLLI2SM_DIV_29 LL_RCC_PLLM_DIV_29 |
#define | LL_RCC_PLLI2SM_DIV_30 LL_RCC_PLLM_DIV_30 |
#define | LL_RCC_PLLI2SM_DIV_31 LL_RCC_PLLM_DIV_31 |
#define | LL_RCC_PLLI2SM_DIV_32 LL_RCC_PLLM_DIV_32 |
#define | LL_RCC_PLLI2SM_DIV_33 LL_RCC_PLLM_DIV_33 |
#define | LL_RCC_PLLI2SM_DIV_34 LL_RCC_PLLM_DIV_34 |
#define | LL_RCC_PLLI2SM_DIV_35 LL_RCC_PLLM_DIV_35 |
#define | LL_RCC_PLLI2SM_DIV_36 LL_RCC_PLLM_DIV_36 |
#define | LL_RCC_PLLI2SM_DIV_37 LL_RCC_PLLM_DIV_37 |
#define | LL_RCC_PLLI2SM_DIV_38 LL_RCC_PLLM_DIV_38 |
#define | LL_RCC_PLLI2SM_DIV_39 LL_RCC_PLLM_DIV_39 |
#define | LL_RCC_PLLI2SM_DIV_40 LL_RCC_PLLM_DIV_40 |
#define | LL_RCC_PLLI2SM_DIV_41 LL_RCC_PLLM_DIV_41 |
#define | LL_RCC_PLLI2SM_DIV_42 LL_RCC_PLLM_DIV_42 |
#define | LL_RCC_PLLI2SM_DIV_43 LL_RCC_PLLM_DIV_43 |
#define | LL_RCC_PLLI2SM_DIV_44 LL_RCC_PLLM_DIV_44 |
#define | LL_RCC_PLLI2SM_DIV_45 LL_RCC_PLLM_DIV_45 |
#define | LL_RCC_PLLI2SM_DIV_46 LL_RCC_PLLM_DIV_46 |
#define | LL_RCC_PLLI2SM_DIV_47 LL_RCC_PLLM_DIV_47 |
#define | LL_RCC_PLLI2SM_DIV_48 LL_RCC_PLLM_DIV_48 |
#define | LL_RCC_PLLI2SM_DIV_49 LL_RCC_PLLM_DIV_49 |
#define | LL_RCC_PLLI2SM_DIV_50 LL_RCC_PLLM_DIV_50 |
#define | LL_RCC_PLLI2SM_DIV_51 LL_RCC_PLLM_DIV_51 |
#define | LL_RCC_PLLI2SM_DIV_52 LL_RCC_PLLM_DIV_52 |
#define | LL_RCC_PLLI2SM_DIV_53 LL_RCC_PLLM_DIV_53 |
#define | LL_RCC_PLLI2SM_DIV_54 LL_RCC_PLLM_DIV_54 |
#define | LL_RCC_PLLI2SM_DIV_55 LL_RCC_PLLM_DIV_55 |
#define | LL_RCC_PLLI2SM_DIV_56 LL_RCC_PLLM_DIV_56 |
#define | LL_RCC_PLLI2SM_DIV_57 LL_RCC_PLLM_DIV_57 |
#define | LL_RCC_PLLI2SM_DIV_58 LL_RCC_PLLM_DIV_58 |
#define | LL_RCC_PLLI2SM_DIV_59 LL_RCC_PLLM_DIV_59 |
#define | LL_RCC_PLLI2SM_DIV_60 LL_RCC_PLLM_DIV_60 |
#define | LL_RCC_PLLI2SM_DIV_61 LL_RCC_PLLM_DIV_61 |
#define | LL_RCC_PLLI2SM_DIV_62 LL_RCC_PLLM_DIV_62 |
#define | LL_RCC_PLLI2SM_DIV_63 LL_RCC_PLLM_DIV_63 |
#define | LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 |
#define | LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) |
#define | LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 |
#define | LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) |
#define | LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) |
#define | LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) |
#define | LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 |
#define | LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) |
#define | LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) |
#define | LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) |
#define | LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) |
#define | LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) |
#define | LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) |
#define | LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U |
#define | LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR_PLLI2SDIVQ_0 |
#define | LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR_PLLI2SDIVQ_1 |
#define | LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR_PLLI2SDIVQ_2 |
#define | LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) |
#define | LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR_PLLI2SDIVQ_3 |
#define | LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) |
#define | LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) |
#define | LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) |
#define | LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR_PLLI2SDIVQ_4 |
#define | LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1) |
#define | LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2) |
#define | LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) |
#define | LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3) |
#define | LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1) |
#define | LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2) |
#define | LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1) |
#define | LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR_PLLI2SDIVQ_4 | RCC_DCKCFGR_PLLI2SDIVQ_3 | RCC_DCKCFGR_PLLI2SDIVQ_2 | RCC_DCKCFGR_PLLI2SDIVQ_1 | RCC_DCKCFGR_PLLI2SDIVQ_0) |
#define | LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 |
#define | LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) |
#define | LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 |
#define | LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) |
#define | LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) |
#define | LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) |
#define | LL_RCC_PLLSAIM_DIV_2 LL_RCC_PLLM_DIV_2 |
#define | LL_RCC_PLLSAIM_DIV_3 LL_RCC_PLLM_DIV_3 |
#define | LL_RCC_PLLSAIM_DIV_4 LL_RCC_PLLM_DIV_4 |
#define | LL_RCC_PLLSAIM_DIV_5 LL_RCC_PLLM_DIV_5 |
#define | LL_RCC_PLLSAIM_DIV_6 LL_RCC_PLLM_DIV_6 |
#define | LL_RCC_PLLSAIM_DIV_7 LL_RCC_PLLM_DIV_7 |
#define | LL_RCC_PLLSAIM_DIV_8 LL_RCC_PLLM_DIV_8 |
#define | LL_RCC_PLLSAIM_DIV_9 LL_RCC_PLLM_DIV_9 |
#define | LL_RCC_PLLSAIM_DIV_10 LL_RCC_PLLM_DIV_10 |
#define | LL_RCC_PLLSAIM_DIV_11 LL_RCC_PLLM_DIV_11 |
#define | LL_RCC_PLLSAIM_DIV_12 LL_RCC_PLLM_DIV_12 |
#define | LL_RCC_PLLSAIM_DIV_13 LL_RCC_PLLM_DIV_13 |
#define | LL_RCC_PLLSAIM_DIV_14 LL_RCC_PLLM_DIV_14 |
#define | LL_RCC_PLLSAIM_DIV_15 LL_RCC_PLLM_DIV_15 |
#define | LL_RCC_PLLSAIM_DIV_16 LL_RCC_PLLM_DIV_16 |
#define | LL_RCC_PLLSAIM_DIV_17 LL_RCC_PLLM_DIV_17 |
#define | LL_RCC_PLLSAIM_DIV_18 LL_RCC_PLLM_DIV_18 |
#define | LL_RCC_PLLSAIM_DIV_19 LL_RCC_PLLM_DIV_19 |
#define | LL_RCC_PLLSAIM_DIV_20 LL_RCC_PLLM_DIV_20 |
#define | LL_RCC_PLLSAIM_DIV_21 LL_RCC_PLLM_DIV_21 |
#define | LL_RCC_PLLSAIM_DIV_22 LL_RCC_PLLM_DIV_22 |
#define | LL_RCC_PLLSAIM_DIV_23 LL_RCC_PLLM_DIV_23 |
#define | LL_RCC_PLLSAIM_DIV_24 LL_RCC_PLLM_DIV_24 |
#define | LL_RCC_PLLSAIM_DIV_25 LL_RCC_PLLM_DIV_25 |
#define | LL_RCC_PLLSAIM_DIV_26 LL_RCC_PLLM_DIV_26 |
#define | LL_RCC_PLLSAIM_DIV_27 LL_RCC_PLLM_DIV_27 |
#define | LL_RCC_PLLSAIM_DIV_28 LL_RCC_PLLM_DIV_28 |
#define | LL_RCC_PLLSAIM_DIV_29 LL_RCC_PLLM_DIV_29 |
#define | LL_RCC_PLLSAIM_DIV_30 LL_RCC_PLLM_DIV_30 |
#define | LL_RCC_PLLSAIM_DIV_31 LL_RCC_PLLM_DIV_31 |
#define | LL_RCC_PLLSAIM_DIV_32 LL_RCC_PLLM_DIV_32 |
#define | LL_RCC_PLLSAIM_DIV_33 LL_RCC_PLLM_DIV_33 |
#define | LL_RCC_PLLSAIM_DIV_34 LL_RCC_PLLM_DIV_34 |
#define | LL_RCC_PLLSAIM_DIV_35 LL_RCC_PLLM_DIV_35 |
#define | LL_RCC_PLLSAIM_DIV_36 LL_RCC_PLLM_DIV_36 |
#define | LL_RCC_PLLSAIM_DIV_37 LL_RCC_PLLM_DIV_37 |
#define | LL_RCC_PLLSAIM_DIV_38 LL_RCC_PLLM_DIV_38 |
#define | LL_RCC_PLLSAIM_DIV_39 LL_RCC_PLLM_DIV_39 |
#define | LL_RCC_PLLSAIM_DIV_40 LL_RCC_PLLM_DIV_40 |
#define | LL_RCC_PLLSAIM_DIV_41 LL_RCC_PLLM_DIV_41 |
#define | LL_RCC_PLLSAIM_DIV_42 LL_RCC_PLLM_DIV_42 |
#define | LL_RCC_PLLSAIM_DIV_43 LL_RCC_PLLM_DIV_43 |
#define | LL_RCC_PLLSAIM_DIV_44 LL_RCC_PLLM_DIV_44 |
#define | LL_RCC_PLLSAIM_DIV_45 LL_RCC_PLLM_DIV_45 |
#define | LL_RCC_PLLSAIM_DIV_46 LL_RCC_PLLM_DIV_46 |
#define | LL_RCC_PLLSAIM_DIV_47 LL_RCC_PLLM_DIV_47 |
#define | LL_RCC_PLLSAIM_DIV_48 LL_RCC_PLLM_DIV_48 |
#define | LL_RCC_PLLSAIM_DIV_49 LL_RCC_PLLM_DIV_49 |
#define | LL_RCC_PLLSAIM_DIV_50 LL_RCC_PLLM_DIV_50 |
#define | LL_RCC_PLLSAIM_DIV_51 LL_RCC_PLLM_DIV_51 |
#define | LL_RCC_PLLSAIM_DIV_52 LL_RCC_PLLM_DIV_52 |
#define | LL_RCC_PLLSAIM_DIV_53 LL_RCC_PLLM_DIV_53 |
#define | LL_RCC_PLLSAIM_DIV_54 LL_RCC_PLLM_DIV_54 |
#define | LL_RCC_PLLSAIM_DIV_55 LL_RCC_PLLM_DIV_55 |
#define | LL_RCC_PLLSAIM_DIV_56 LL_RCC_PLLM_DIV_56 |
#define | LL_RCC_PLLSAIM_DIV_57 LL_RCC_PLLM_DIV_57 |
#define | LL_RCC_PLLSAIM_DIV_58 LL_RCC_PLLM_DIV_58 |
#define | LL_RCC_PLLSAIM_DIV_59 LL_RCC_PLLM_DIV_59 |
#define | LL_RCC_PLLSAIM_DIV_60 LL_RCC_PLLM_DIV_60 |
#define | LL_RCC_PLLSAIM_DIV_61 LL_RCC_PLLM_DIV_61 |
#define | LL_RCC_PLLSAIM_DIV_62 LL_RCC_PLLM_DIV_62 |
#define | LL_RCC_PLLSAIM_DIV_63 LL_RCC_PLLM_DIV_63 |
#define | LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 |
#define | LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) |
#define | LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 |
#define | LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) |
#define | LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) |
#define | LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) |
#define | LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 |
#define | LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) |
#define | LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) |
#define | LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) |
#define | LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) |
#define | LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) |
#define | LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) |
#define | LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U |
#define | LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR_PLLSAIDIVQ_0 |
#define | LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR_PLLSAIDIVQ_1 |
#define | LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR_PLLSAIDIVQ_2 |
#define | LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) |
#define | LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR_PLLSAIDIVQ_3 |
#define | LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) |
#define | LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) |
#define | LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) |
#define | LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR_PLLSAIDIVQ_4 |
#define | LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1) |
#define | LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2) |
#define | LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) |
#define | LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3) |
#define | LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1) |
#define | LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2) |
#define | LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1) |
#define | LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR_PLLSAIDIVQ_4 | RCC_DCKCFGR_PLLSAIDIVQ_3 | RCC_DCKCFGR_PLLSAIDIVQ_2 | RCC_DCKCFGR_PLLSAIDIVQ_1 | RCC_DCKCFGR_PLLSAIDIVQ_0) |
#define | LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 |
#define | LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) |
#define | LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 |
#define | LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) |
#define | LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) |
#define | LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) |
#define | LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U |
#define | LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR_PLLSAIDIVR_0 |
#define | LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR_PLLSAIDIVR_1 |
#define | LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR_PLLSAIDIVR_1 | RCC_DCKCFGR_PLLSAIDIVR_0) |
#define | LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__)) |
Write a value in RCC register. | |
#define | LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) |
Read a value in RCC register. | |
#define | __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) |
Helper macro to calculate the PLLCLK frequency on system domain. | |
#define | __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) |
Helper macro to calculate the PLLCLK frequency used on 48M domain. | |
#define | __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) |
Helper macro to calculate the PLLSAI frequency used for SAI domain. | |
#define | __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) |
Helper macro to calculate the PLLSAI frequency used for LTDC domain. | |
#define | __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ_R__, __PLLI2SDIVQ_R__) |
Helper macro to calculate the PLLI2S frequency used for SAI domain. | |
#define | __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) |
Helper macro to calculate the PLLI2S frequency used for I2S domain. | |
#define | __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos]) |
Helper macro to calculate the HCLK frequency. | |
#define | __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos]) |
Helper macro to calculate the PCLK1 frequency (ABP1) | |
#define | __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos]) |
Helper macro to calculate the PCLK2 frequency (ABP2) | |
Functions | |
__STATIC_INLINE void | LL_RCC_HSE_EnableCSS (void) |
Enable the Clock Security System. | |
__STATIC_INLINE void | LL_RCC_HSE_EnableBypass (void) |
Enable HSE external oscillator (HSE Bypass) | |
__STATIC_INLINE void | LL_RCC_HSE_DisableBypass (void) |
Disable HSE external oscillator (HSE Bypass) | |
__STATIC_INLINE void | LL_RCC_HSE_Enable (void) |
Enable HSE crystal oscillator (HSE ON) | |
__STATIC_INLINE void | LL_RCC_HSE_Disable (void) |
Disable HSE crystal oscillator (HSE ON) | |
__STATIC_INLINE uint32_t | LL_RCC_HSE_IsReady (void) |
Check if HSE oscillator Ready. | |
__STATIC_INLINE void | LL_RCC_HSI_Enable (void) |
Enable HSI oscillator. | |
__STATIC_INLINE void | LL_RCC_HSI_Disable (void) |
Disable HSI oscillator. | |
__STATIC_INLINE uint32_t | LL_RCC_HSI_IsReady (void) |
Check if HSI clock is ready. | |
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibration (void) |
Get HSI Calibration value. | |
__STATIC_INLINE void | LL_RCC_HSI_SetCalibTrimming (uint32_t Value) |
Set HSI Calibration trimming. | |
__STATIC_INLINE uint32_t | LL_RCC_HSI_GetCalibTrimming (void) |
Get HSI Calibration trimming. | |
__STATIC_INLINE void | LL_RCC_LSE_Enable (void) |
Enable Low Speed External (LSE) crystal. | |
__STATIC_INLINE void | LL_RCC_LSE_Disable (void) |
Disable Low Speed External (LSE) crystal. | |
__STATIC_INLINE void | LL_RCC_LSE_EnableBypass (void) |
Enable external clock source (LSE bypass). | |
__STATIC_INLINE void | LL_RCC_LSE_DisableBypass (void) |
Disable external clock source (LSE bypass). | |
__STATIC_INLINE uint32_t | LL_RCC_LSE_IsReady (void) |
Check if LSE oscillator Ready. | |
__STATIC_INLINE void | LL_RCC_LSI_Enable (void) |
Enable LSI Oscillator. | |
__STATIC_INLINE void | LL_RCC_LSI_Disable (void) |
Disable LSI Oscillator. | |
__STATIC_INLINE uint32_t | LL_RCC_LSI_IsReady (void) |
Check if LSI is Ready. | |
__STATIC_INLINE void | LL_RCC_SetSysClkSource (uint32_t Source) |
Configure the system clock source. | |
__STATIC_INLINE uint32_t | LL_RCC_GetSysClkSource (void) |
Get the system clock source. | |
__STATIC_INLINE void | LL_RCC_SetAHBPrescaler (uint32_t Prescaler) |
Set AHB prescaler. | |
__STATIC_INLINE void | LL_RCC_SetAPB1Prescaler (uint32_t Prescaler) |
Set APB1 prescaler. | |
__STATIC_INLINE void | LL_RCC_SetAPB2Prescaler (uint32_t Prescaler) |
Set APB2 prescaler. | |
__STATIC_INLINE uint32_t | LL_RCC_GetAHBPrescaler (void) |
Get AHB prescaler. | |
__STATIC_INLINE uint32_t | LL_RCC_GetAPB1Prescaler (void) |
Get APB1 prescaler. | |
__STATIC_INLINE uint32_t | LL_RCC_GetAPB2Prescaler (void) |
Get APB2 prescaler. | |
__STATIC_INLINE void | LL_RCC_ConfigMCO (uint32_t MCOxSource, uint32_t MCOxPrescaler) |
Configure MCOx. | |
__STATIC_INLINE void | LL_RCC_SetSAIClockSource (uint32_t SAIxSource) |
Configure SAIx clock source. | |
__STATIC_INLINE void | LL_RCC_SetI2SClockSource (uint32_t Source) |
Configure I2S clock source. | |
__STATIC_INLINE uint32_t | LL_RCC_GetSAIClockSource (uint32_t SAIx) |
Get SAIx clock source. | |
__STATIC_INLINE uint32_t | LL_RCC_GetI2SClockSource (uint32_t I2Sx) |
Get I2S Clock Source. | |
__STATIC_INLINE void | LL_RCC_SetRTCClockSource (uint32_t Source) |
Set RTC Clock Source. | |
__STATIC_INLINE uint32_t | LL_RCC_GetRTCClockSource (void) |
Get RTC Clock Source. | |
__STATIC_INLINE void | LL_RCC_EnableRTC (void) |
Enable RTC. | |
__STATIC_INLINE void | LL_RCC_DisableRTC (void) |
Disable RTC. | |
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledRTC (void) |
Check if RTC has been enabled or not. | |
__STATIC_INLINE void | LL_RCC_ForceBackupDomainReset (void) |
Force the Backup domain reset. | |
__STATIC_INLINE void | LL_RCC_ReleaseBackupDomainReset (void) |
Release the Backup domain reset. | |
__STATIC_INLINE void | LL_RCC_SetRTC_HSEPrescaler (uint32_t Prescaler) |
Set HSE Prescalers for RTC Clock. | |
__STATIC_INLINE uint32_t | LL_RCC_GetRTC_HSEPrescaler (void) |
Get HSE Prescalers for RTC Clock. | |
__STATIC_INLINE void | LL_RCC_SetTIMPrescaler (uint32_t Prescaler) |
Set Timers Clock Prescalers. | |
__STATIC_INLINE uint32_t | LL_RCC_GetTIMPrescaler (void) |
Get Timers Clock Prescalers. | |
__STATIC_INLINE void | LL_RCC_PLL_Enable (void) |
Enable PLL. | |
__STATIC_INLINE void | LL_RCC_PLL_Disable (void) |
Disable PLL. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_IsReady (void) |
Check if PLL Ready. | |
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_SYS (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP_R) |
Configure PLL used for SYSCLK Domain. | |
__STATIC_INLINE void | LL_RCC_PLL_ConfigDomain_48M (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ) |
Configure PLL used for 48Mhz domain clock. | |
__STATIC_INLINE void | LL_RCC_PLL_SetMainSource (uint32_t PLLSource) |
Configure PLL clock source. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetMainSource (void) |
Get the oscillator used as PLL clock source. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetN (void) |
Get Main PLL multiplication factor for VCO. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetP (void) |
Get Main PLL division factor for PLLP. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetQ (void) |
Get Main PLL division factor for PLLQ. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetDivider (void) |
Get Division factor for the main PLL and other PLL. | |
__STATIC_INLINE void | LL_RCC_PLL_ConfigSpreadSpectrum (uint32_t Mod, uint32_t Inc, uint32_t Sel) |
Configure Spread Spectrum used for PLL. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetPeriodModulation (void) |
Get Spread Spectrum Modulation Period for PLL. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetStepIncrementation (void) |
Get Spread Spectrum Incrementation Step for PLL. | |
__STATIC_INLINE uint32_t | LL_RCC_PLL_GetSpreadSelection (void) |
Get Spread Spectrum Selection for PLL. | |
__STATIC_INLINE void | LL_RCC_PLL_SpreadSpectrum_Enable (void) |
Enable Spread Spectrum for PLL. | |
__STATIC_INLINE void | LL_RCC_PLL_SpreadSpectrum_Disable (void) |
Disable Spread Spectrum for PLL. | |
__STATIC_INLINE void | LL_RCC_PLLI2S_Enable (void) |
Enable PLLI2S. | |
__STATIC_INLINE void | LL_RCC_PLLI2S_Disable (void) |
Disable PLLI2S. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLI2S_IsReady (void) |
Check if PLLI2S Ready. | |
__STATIC_INLINE void | LL_RCC_PLLI2S_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ_R, uint32_t PLLDIVQ_R) |
Configure PLLI2S used for SAI domain clock. | |
__STATIC_INLINE void | LL_RCC_PLLI2S_ConfigDomain_I2S (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR) |
Configure PLLI2S used for I2S1 domain clock. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLI2S_GetN (void) |
Get I2SPLL multiplication factor for VCO. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLI2S_GetQ (void) |
Get I2SPLL division factor for PLLI2SQ. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLI2S_GetR (void) |
Get I2SPLL division factor for PLLI2SR. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLI2S_GetDIVQ (void) |
Get I2SPLL division factor for PLLI2SDIVQ. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLI2S_GetDivider (void) |
Get division factor for PLLI2S input clock. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLI2S_GetMainSource (void) |
Get the oscillator used as PLL clock source. | |
__STATIC_INLINE void | LL_RCC_PLLSAI_Enable (void) |
Enable PLLSAI. | |
__STATIC_INLINE void | LL_RCC_PLLSAI_Disable (void) |
Disable PLLSAI. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI_IsReady (void) |
Check if PLLSAI Ready. | |
__STATIC_INLINE void | LL_RCC_PLLSAI_ConfigDomain_SAI (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ) |
Configure PLLSAI used for SAI domain clock. | |
__STATIC_INLINE void | LL_RCC_PLLSAI_ConfigDomain_LTDC (uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR) |
Configure PLLSAI used for LTDC domain clock. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI_GetDivider (void) |
Get division factor for PLLSAI input clock. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI_GetN (void) |
Get SAIPLL multiplication factor for VCO. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI_GetQ (void) |
Get SAIPLL division factor for PLLSAIQ. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI_GetR (void) |
Get SAIPLL division factor for PLLSAIR. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI_GetDIVQ (void) |
Get SAIPLL division factor for PLLSAIDIVQ. | |
__STATIC_INLINE uint32_t | LL_RCC_PLLSAI_GetDIVR (void) |
Get SAIPLL division factor for PLLSAIDIVR. | |
__STATIC_INLINE void | LL_RCC_ClearFlag_LSIRDY (void) |
Clear LSI ready interrupt flag. | |
__STATIC_INLINE void | LL_RCC_ClearFlag_LSERDY (void) |
Clear LSE ready interrupt flag. | |
__STATIC_INLINE void | LL_RCC_ClearFlag_HSIRDY (void) |
Clear HSI ready interrupt flag. | |
__STATIC_INLINE void | LL_RCC_ClearFlag_HSERDY (void) |
Clear HSE ready interrupt flag. | |
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLRDY (void) |
Clear PLL ready interrupt flag. | |
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLI2SRDY (void) |
Clear PLLI2S ready interrupt flag. | |
__STATIC_INLINE void | LL_RCC_ClearFlag_PLLSAIRDY (void) |
Clear PLLSAI ready interrupt flag. | |
__STATIC_INLINE void | LL_RCC_ClearFlag_HSECSS (void) |
Clear Clock security system interrupt flag. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSIRDY (void) |
Check if LSI ready interrupt occurred or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LSERDY (void) |
Check if LSE ready interrupt occurred or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSIRDY (void) |
Check if HSI ready interrupt occurred or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSERDY (void) |
Check if HSE ready interrupt occurred or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLRDY (void) |
Check if PLL ready interrupt occurred or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLI2SRDY (void) |
Check if PLLI2S ready interrupt occurred or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PLLSAIRDY (void) |
Check if PLLSAI ready interrupt occurred or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_HSECSS (void) |
Check if Clock security system interrupt occurred or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_IWDGRST (void) |
Check if RCC flag Independent Watchdog reset is set or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_LPWRRST (void) |
Check if RCC flag Low Power reset is set or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PINRST (void) |
Check if RCC flag Pin reset is set or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_PORRST (void) |
Check if RCC flag POR/PDR reset is set or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_SFTRST (void) |
Check if RCC flag Software reset is set or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_WWDGRST (void) |
Check if RCC flag Window Watchdog reset is set or not. | |
__STATIC_INLINE uint32_t | LL_RCC_IsActiveFlag_BORRST (void) |
Check if RCC flag BOR reset is set or not. | |
__STATIC_INLINE void | LL_RCC_ClearResetFlags (void) |
Set RMVF bit to clear the reset flags. | |
__STATIC_INLINE void | LL_RCC_EnableIT_LSIRDY (void) |
Enable LSI ready interrupt. | |
__STATIC_INLINE void | LL_RCC_EnableIT_LSERDY (void) |
Enable LSE ready interrupt. | |
__STATIC_INLINE void | LL_RCC_EnableIT_HSIRDY (void) |
Enable HSI ready interrupt. | |
__STATIC_INLINE void | LL_RCC_EnableIT_HSERDY (void) |
Enable HSE ready interrupt. | |
__STATIC_INLINE void | LL_RCC_EnableIT_PLLRDY (void) |
Enable PLL ready interrupt. | |
__STATIC_INLINE void | LL_RCC_EnableIT_PLLI2SRDY (void) |
Enable PLLI2S ready interrupt. | |
__STATIC_INLINE void | LL_RCC_EnableIT_PLLSAIRDY (void) |
Enable PLLSAI ready interrupt. | |
__STATIC_INLINE void | LL_RCC_DisableIT_LSIRDY (void) |
Disable LSI ready interrupt. | |
__STATIC_INLINE void | LL_RCC_DisableIT_LSERDY (void) |
Disable LSE ready interrupt. | |
__STATIC_INLINE void | LL_RCC_DisableIT_HSIRDY (void) |
Disable HSI ready interrupt. | |
__STATIC_INLINE void | LL_RCC_DisableIT_HSERDY (void) |
Disable HSE ready interrupt. | |
__STATIC_INLINE void | LL_RCC_DisableIT_PLLRDY (void) |
Disable PLL ready interrupt. | |
__STATIC_INLINE void | LL_RCC_DisableIT_PLLI2SRDY (void) |
Disable PLLI2S ready interrupt. | |
__STATIC_INLINE void | LL_RCC_DisableIT_PLLSAIRDY (void) |
Disable PLLSAI ready interrupt. | |
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSIRDY (void) |
Checks if LSI ready interrupt source is enabled or disabled. | |
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_LSERDY (void) |
Checks if LSE ready interrupt source is enabled or disabled. | |
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSIRDY (void) |
Checks if HSI ready interrupt source is enabled or disabled. | |
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_HSERDY (void) |
Checks if HSE ready interrupt source is enabled or disabled. | |
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLRDY (void) |
Checks if PLL ready interrupt source is enabled or disabled. | |
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLI2SRDY (void) |
Checks if PLLI2S ready interrupt source is enabled or disabled. | |
__STATIC_INLINE uint32_t | LL_RCC_IsEnabledIT_PLLSAIRDY (void) |
Checks if PLLSAI ready interrupt source is enabled or disabled. | |
ErrorStatus | LL_RCC_DeInit (void) |
Reset the RCC clock configuration to the default reset state. | |
void | LL_RCC_GetSystemClocksFreq (LL_RCC_ClocksTypeDef *RCC_Clocks) |
Return the frequencies of different on chip clocks; System, AHB, APB1 and APB2 buses clocks. | |
uint32_t | LL_RCC_GetSAIClockFreq (uint32_t SAIxSource) |
Return SAIx clock frequency. | |
uint32_t | LL_RCC_GetSDIOClockFreq (uint32_t SDIOxSource) |
Return SDIOx clock frequency. | |
uint32_t | LL_RCC_GetRNGClockFreq (uint32_t RNGxSource) |
Return RNGx clock frequency. | |
uint32_t | LL_RCC_GetUSBClockFreq (uint32_t USBxSource) |
Return USBx clock frequency. | |
uint32_t | LL_RCC_GetI2SClockFreq (uint32_t I2SxSource) |
Return I2Sx clock frequency. | |
uint32_t | LL_RCC_GetLTDCClockFreq (uint32_t LTDCxSource) |
Return LTDC clock frequency. | |
Variables | |
static const uint8_t | aRCC_PLLSAIDIVRPrescTable [4] = {2, 4, 8, 16} |
Header file of RCC LL module.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met: 1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer. 2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. 3. Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Definition in file stm32f4xx_ll_rcc.h.