STM32F439xx HAL User Manual
|
00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_i2c.h 00004 * @author MCD Application Team 00005 * @brief Header file of I2C LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_LL_I2C_H 00038 #define __STM32F4xx_LL_I2C_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx.h" 00046 00047 /** @addtogroup STM32F4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (I2C1) || defined (I2C2) || defined (I2C3) 00052 00053 /** @defgroup I2C_LL I2C 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 00060 /* Private constants ---------------------------------------------------------*/ 00061 /** @defgroup I2C_LL_Private_Constants I2C Private Constants 00062 * @{ 00063 */ 00064 00065 /* Defines used to perform compute and check in the macros */ 00066 #define LL_I2C_MAX_SPEED_STANDARD 100000U 00067 #define LL_I2C_MAX_SPEED_FAST 400000U 00068 /** 00069 * @} 00070 */ 00071 00072 /* Private macros ------------------------------------------------------------*/ 00073 #if defined(USE_FULL_LL_DRIVER) 00074 /** @defgroup I2C_LL_Private_Macros I2C Private Macros 00075 * @{ 00076 */ 00077 /** 00078 * @} 00079 */ 00080 #endif /*USE_FULL_LL_DRIVER*/ 00081 00082 /* Exported types ------------------------------------------------------------*/ 00083 #if defined(USE_FULL_LL_DRIVER) 00084 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure 00085 * @{ 00086 */ 00087 typedef struct 00088 { 00089 uint32_t PeripheralMode; /*!< Specifies the peripheral mode. 00090 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE 00091 00092 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */ 00093 00094 uint32_t ClockSpeed; /*!< Specifies the clock frequency. 00095 This parameter must be set to a value lower than 400kHz (in Hz) 00096 00097 This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod() 00098 or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */ 00099 00100 uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. 00101 This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE 00102 00103 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */ 00104 00105 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) 00106 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter. 00107 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION 00108 00109 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */ 00110 00111 uint32_t DigitalFilter; /*!< Configures the digital noise filter. 00112 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F 00113 00114 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */ 00115 00116 #endif 00117 uint32_t OwnAddress1; /*!< Specifies the device own address 1. 00118 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF 00119 00120 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ 00121 00122 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. 00123 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE 00124 00125 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ 00126 00127 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit). 00128 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1 00129 00130 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ 00131 } LL_I2C_InitTypeDef; 00132 /** 00133 * @} 00134 */ 00135 #endif /*USE_FULL_LL_DRIVER*/ 00136 00137 /* Exported constants --------------------------------------------------------*/ 00138 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants 00139 * @{ 00140 */ 00141 00142 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines 00143 * @brief Flags defines which can be used with LL_I2C_ReadReg function 00144 * @{ 00145 */ 00146 #define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */ 00147 #define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or 00148 Address matched flag (slave mode) */ 00149 #define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */ 00150 #define LL_I2C_SR1_ADD10 I2C_SR1_ADD10 /*!< 10-bit header sent (master mode) */ 00151 #define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */ 00152 #define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */ 00153 #define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */ 00154 #define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */ 00155 #define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */ 00156 #define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */ 00157 #define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */ 00158 #define LL_I2C_SR1_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */ 00159 #define LL_I2C_SR1_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */ 00160 #define LL_I2C_SR1_SMALERT I2C_ISR_SMALERT /*!< SMBus alert (SMBus mode) */ 00161 #define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */ 00162 #define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */ 00163 #define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */ 00164 #define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */ 00165 #define LL_I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT /*!< SMBus Device default address (Slave mode) */ 00166 #define LL_I2C_SR2_SMBHOST I2C_SR2_SMBHOST /*!< SMBus Host address (Slave mode) */ 00167 #define LL_I2C_SR2_DUALF I2C_SR2_DUALF /*!< Dual flag (Slave mode) */ 00168 /** 00169 * @} 00170 */ 00171 00172 /** @defgroup I2C_LL_EC_IT IT Defines 00173 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions 00174 * @{ 00175 */ 00176 #define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */ 00177 #define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */ 00178 #define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */ 00179 /** 00180 * @} 00181 */ 00182 00183 #if defined(I2C_FLTR_ANOFF) 00184 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection 00185 * @{ 00186 */ 00187 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */ 00188 #define LL_I2C_ANALOGFILTER_DISABLE I2C_FLTR_ANOFF /*!< Analog filter is disabled.*/ 00189 /** 00190 * @} 00191 */ 00192 00193 #endif 00194 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length 00195 * @{ 00196 */ 00197 #define LL_I2C_OWNADDRESS1_7BIT 0x00004000U /*!< Own address 1 is a 7-bit address. */ 00198 #define LL_I2C_OWNADDRESS1_10BIT (uint32_t)(I2C_OAR1_ADDMODE | 0x00004000U) /*!< Own address 1 is a 10-bit address. */ 00199 /** 00200 * @} 00201 */ 00202 00203 /** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle 00204 * @{ 00205 */ 00206 #define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */ 00207 #define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */ 00208 /** 00209 * @} 00210 */ 00211 00212 /** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode 00213 * @{ 00214 */ 00215 #define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */ 00216 #define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */ 00217 /** 00218 * @} 00219 */ 00220 00221 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode 00222 * @{ 00223 */ 00224 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */ 00225 #define LL_I2C_MODE_SMBUS_HOST (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP) /*!< SMBus Host address acknowledge */ 00226 #define LL_I2C_MODE_SMBUS_DEVICE I2C_CR1_SMBUS /*!< SMBus Device default mode (Default address not acknowledge) */ 00227 #define LL_I2C_MODE_SMBUS_DEVICE_ARP (uint32_t)(I2C_CR1_SMBUS | I2C_CR1_ENARP) /*!< SMBus Device Default address acknowledge */ 00228 /** 00229 * @} 00230 */ 00231 00232 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation 00233 * @{ 00234 */ 00235 #define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */ 00236 #define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/ 00237 /** 00238 * @} 00239 */ 00240 00241 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction 00242 * @{ 00243 */ 00244 #define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */ 00245 #define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */ 00246 /** 00247 * @} 00248 */ 00249 00250 /** 00251 * @} 00252 */ 00253 00254 /* Exported macro ------------------------------------------------------------*/ 00255 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros 00256 * @{ 00257 */ 00258 00259 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros 00260 * @{ 00261 */ 00262 00263 /** 00264 * @brief Write a value in I2C register 00265 * @param __INSTANCE__ I2C Instance 00266 * @param __REG__ Register to be written 00267 * @param __VALUE__ Value to be written in the register 00268 * @retval None 00269 */ 00270 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00271 00272 /** 00273 * @brief Read a value in I2C register 00274 * @param __INSTANCE__ I2C Instance 00275 * @param __REG__ Register to be read 00276 * @retval Register value 00277 */ 00278 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00279 /** 00280 * @} 00281 */ 00282 00283 /** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper 00284 * @{ 00285 */ 00286 00287 /** 00288 * @brief Convert Peripheral Clock Frequency in Mhz. 00289 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). 00290 * @retval Value of peripheral clock (in Mhz) 00291 */ 00292 #define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U) 00293 00294 /** 00295 * @brief Convert Peripheral Clock Frequency in Hz. 00296 * @param __PCLK__ This parameter must be a value of peripheral clock (in Mhz). 00297 * @retval Value of peripheral clock (in Hz) 00298 */ 00299 #define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U) 00300 00301 /** 00302 * @brief Compute I2C Clock rising time. 00303 * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in Mhz). 00304 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). 00305 * @retval Value between Min_Data=0x02 and Max_Data=0x3F 00306 */ 00307 #define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) 00308 00309 /** 00310 * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value. 00311 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). 00312 * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). 00313 * @param __DUTYCYCLE__ This parameter can be one of the following values: 00314 * @arg @ref LL_I2C_DUTYCYCLE_2 00315 * @arg @ref LL_I2C_DUTYCYCLE_16_9 00316 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. 00317 */ 00318 #define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \ 00319 (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \ 00320 (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__)))) 00321 00322 /** 00323 * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value. 00324 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). 00325 * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz). 00326 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF. 00327 */ 00328 #define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) 00329 00330 /** 00331 * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value. 00332 * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). 00333 * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz). 00334 * @param __DUTYCYCLE__ This parameter can be one of the following values: 00335 * @arg @ref LL_I2C_DUTYCYCLE_2 00336 * @arg @ref LL_I2C_DUTYCYCLE_16_9 00337 * @retval Value between Min_Data=0x001 and Max_Data=0xFFF 00338 */ 00339 #define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \ 00340 (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \ 00341 (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U)))) 00342 00343 /** 00344 * @brief Get the Least significant bits of a 10-Bits address. 00345 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. 00346 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 00347 */ 00348 #define __LL_I2C_10BIT_ADDRESS(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF)))) 00349 00350 /** 00351 * @brief Convert a 10-Bits address to a 10-Bits header with Write direction. 00352 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. 00353 * @retval Value between Min_Data=0xF0 and Max_Data=0xF6 00354 */ 00355 #define __LL_I2C_10BIT_HEADER_WRITE(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0)))) 00356 00357 /** 00358 * @brief Convert a 10-Bits address to a 10-Bits header with Read direction. 00359 * @param __ADDRESS__ This parameter must be a value of a 10-Bits slave address. 00360 * @retval Value between Min_Data=0xF1 and Max_Data=0xF7 00361 */ 00362 #define __LL_I2C_10BIT_HEADER_READ(__ADDRESS__) ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1)))) 00363 00364 /** 00365 * @} 00366 */ 00367 00368 /** 00369 * @} 00370 */ 00371 00372 /* Exported functions --------------------------------------------------------*/ 00373 00374 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions 00375 * @{ 00376 */ 00377 00378 /** @defgroup I2C_LL_EF_Configuration Configuration 00379 * @{ 00380 */ 00381 00382 /** 00383 * @brief Enable I2C peripheral (PE = 1). 00384 * @rmtoll CR1 PE LL_I2C_Enable 00385 * @param I2Cx I2C Instance. 00386 * @retval None 00387 */ 00388 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) 00389 { 00390 SET_BIT(I2Cx->CR1, I2C_CR1_PE); 00391 } 00392 00393 /** 00394 * @brief Disable I2C peripheral (PE = 0). 00395 * @rmtoll CR1 PE LL_I2C_Disable 00396 * @param I2Cx I2C Instance. 00397 * @retval None 00398 */ 00399 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) 00400 { 00401 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); 00402 } 00403 00404 /** 00405 * @brief Check if the I2C peripheral is enabled or disabled. 00406 * @rmtoll CR1 PE LL_I2C_IsEnabled 00407 * @param I2Cx I2C Instance. 00408 * @retval State of bit (1 or 0). 00409 */ 00410 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) 00411 { 00412 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); 00413 } 00414 00415 #if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF) 00416 /** 00417 * @brief Configure Noise Filters (Analog and Digital). 00418 * @note If the analog filter is also enabled, the digital filter is added to analog filter. 00419 * The filters can only be programmed when the I2C is disabled (PE = 0). 00420 * @rmtoll FLTR ANOFF LL_I2C_ConfigFilters\n 00421 * FLTR DNF LL_I2C_ConfigFilters 00422 * @param I2Cx I2C Instance. 00423 * @param AnalogFilter This parameter can be one of the following values: 00424 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE 00425 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE 00426 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1) 00427 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1. 00428 * @retval None 00429 */ 00430 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter) 00431 { 00432 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_ANOFF | I2C_FLTR_DNF, AnalogFilter | DigitalFilter); 00433 } 00434 #endif 00435 #if defined(I2C_FLTR_DNF) 00436 00437 /** 00438 * @brief Configure Digital Noise Filter. 00439 * @note If the analog filter is also enabled, the digital filter is added to analog filter. 00440 * This filter can only be programmed when the I2C is disabled (PE = 0). 00441 * @rmtoll FLTR DNF LL_I2C_SetDigitalFilter 00442 * @param I2Cx I2C Instance. 00443 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*TPCLK1) 00444 * This parameter is used to configure the digital noise filter on SDA and SCL input. The digital filter will suppress the spikes with a length of up to DNF[3:0]*TPCLK1. 00445 * @retval None 00446 */ 00447 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter) 00448 { 00449 MODIFY_REG(I2Cx->FLTR, I2C_FLTR_DNF, DigitalFilter); 00450 } 00451 00452 /** 00453 * @brief Get the current Digital Noise Filter configuration. 00454 * @rmtoll FLTR DNF LL_I2C_GetDigitalFilter 00455 * @param I2Cx I2C Instance. 00456 * @retval Value between Min_Data=0x0 and Max_Data=0xF 00457 */ 00458 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx) 00459 { 00460 return (uint32_t)(READ_BIT(I2Cx->FLTR, I2C_FLTR_DNF)); 00461 } 00462 #endif 00463 #if defined(I2C_FLTR_ANOFF) 00464 00465 /** 00466 * @brief Enable Analog Noise Filter. 00467 * @note This filter can only be programmed when the I2C is disabled (PE = 0). 00468 * @rmtoll FLTR ANOFF LL_I2C_EnableAnalogFilter 00469 * @param I2Cx I2C Instance. 00470 * @retval None 00471 */ 00472 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx) 00473 { 00474 CLEAR_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF); 00475 } 00476 00477 /** 00478 * @brief Disable Analog Noise Filter. 00479 * @note This filter can only be programmed when the I2C is disabled (PE = 0). 00480 * @rmtoll FLTR ANOFF LL_I2C_DisableAnalogFilter 00481 * @param I2Cx I2C Instance. 00482 * @retval None 00483 */ 00484 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx) 00485 { 00486 SET_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF); 00487 } 00488 00489 /** 00490 * @brief Check if Analog Noise Filter is enabled or disabled. 00491 * @rmtoll FLTR ANOFF LL_I2C_IsEnabledAnalogFilter 00492 * @param I2Cx I2C Instance. 00493 * @retval State of bit (1 or 0). 00494 */ 00495 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx) 00496 { 00497 return (READ_BIT(I2Cx->FLTR, I2C_FLTR_ANOFF) == (I2C_FLTR_ANOFF)); 00498 } 00499 #endif 00500 00501 /** 00502 * @brief Enable DMA transmission requests. 00503 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX 00504 * @param I2Cx I2C Instance. 00505 * @retval None 00506 */ 00507 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) 00508 { 00509 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); 00510 } 00511 00512 /** 00513 * @brief Disable DMA transmission requests. 00514 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX 00515 * @param I2Cx I2C Instance. 00516 * @retval None 00517 */ 00518 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) 00519 { 00520 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); 00521 } 00522 00523 /** 00524 * @brief Check if DMA transmission requests are enabled or disabled. 00525 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX 00526 * @param I2Cx I2C Instance. 00527 * @retval State of bit (1 or 0). 00528 */ 00529 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) 00530 { 00531 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); 00532 } 00533 00534 /** 00535 * @brief Enable DMA reception requests. 00536 * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX 00537 * @param I2Cx I2C Instance. 00538 * @retval None 00539 */ 00540 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) 00541 { 00542 SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); 00543 } 00544 00545 /** 00546 * @brief Disable DMA reception requests. 00547 * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX 00548 * @param I2Cx I2C Instance. 00549 * @retval None 00550 */ 00551 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) 00552 { 00553 CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); 00554 } 00555 00556 /** 00557 * @brief Check if DMA reception requests are enabled or disabled. 00558 * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX 00559 * @param I2Cx I2C Instance. 00560 * @retval State of bit (1 or 0). 00561 */ 00562 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) 00563 { 00564 return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); 00565 } 00566 00567 /** 00568 * @brief Get the data register address used for DMA transfer. 00569 * @rmtoll DR DR LL_I2C_DMA_GetRegAddr 00570 * @param I2Cx I2C Instance. 00571 * @retval Address of data register 00572 */ 00573 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx) 00574 { 00575 return (uint32_t) & (I2Cx->DR); 00576 } 00577 00578 /** 00579 * @brief Enable Clock stretching. 00580 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 00581 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching 00582 * @param I2Cx I2C Instance. 00583 * @retval None 00584 */ 00585 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) 00586 { 00587 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); 00588 } 00589 00590 /** 00591 * @brief Disable Clock stretching. 00592 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 00593 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching 00594 * @param I2Cx I2C Instance. 00595 * @retval None 00596 */ 00597 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) 00598 { 00599 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); 00600 } 00601 00602 /** 00603 * @brief Check if Clock stretching is enabled or disabled. 00604 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching 00605 * @param I2Cx I2C Instance. 00606 * @retval State of bit (1 or 0). 00607 */ 00608 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) 00609 { 00610 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); 00611 } 00612 00613 /** 00614 * @brief Enable General Call. 00615 * @note When enabled the Address 0x00 is ACKed. 00616 * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall 00617 * @param I2Cx I2C Instance. 00618 * @retval None 00619 */ 00620 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) 00621 { 00622 SET_BIT(I2Cx->CR1, I2C_CR1_ENGC); 00623 } 00624 00625 /** 00626 * @brief Disable General Call. 00627 * @note When disabled the Address 0x00 is NACKed. 00628 * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall 00629 * @param I2Cx I2C Instance. 00630 * @retval None 00631 */ 00632 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) 00633 { 00634 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC); 00635 } 00636 00637 /** 00638 * @brief Check if General Call is enabled or disabled. 00639 * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall 00640 * @param I2Cx I2C Instance. 00641 * @retval State of bit (1 or 0). 00642 */ 00643 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) 00644 { 00645 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC)); 00646 } 00647 00648 /** 00649 * @brief Set the Own Address1. 00650 * @rmtoll OAR1 ADD0 LL_I2C_SetOwnAddress1\n 00651 * OAR1 ADD1_7 LL_I2C_SetOwnAddress1\n 00652 * OAR1 ADD8_9 LL_I2C_SetOwnAddress1\n 00653 * OAR1 ADDMODE LL_I2C_SetOwnAddress1 00654 * @param I2Cx I2C Instance. 00655 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. 00656 * @param OwnAddrSize This parameter can be one of the following values: 00657 * @arg @ref LL_I2C_OWNADDRESS1_7BIT 00658 * @arg @ref LL_I2C_OWNADDRESS1_10BIT 00659 * @retval None 00660 */ 00661 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) 00662 { 00663 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD0 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD8_9 | I2C_OAR1_ADDMODE, OwnAddress1 | OwnAddrSize); 00664 } 00665 00666 /** 00667 * @brief Set the 7bits Own Address2. 00668 * @note This action has no effect if own address2 is enabled. 00669 * @rmtoll OAR2 ADD2 LL_I2C_SetOwnAddress2 00670 * @param I2Cx I2C Instance. 00671 * @param OwnAddress2 This parameter must be a value between Min_Data=0 and Max_Data=0x7F. 00672 * @retval None 00673 */ 00674 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2) 00675 { 00676 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_ADD2, OwnAddress2); 00677 } 00678 00679 /** 00680 * @brief Enable acknowledge on Own Address2 match address. 00681 * @rmtoll OAR2 ENDUAL LL_I2C_EnableOwnAddress2 00682 * @param I2Cx I2C Instance. 00683 * @retval None 00684 */ 00685 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx) 00686 { 00687 SET_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL); 00688 } 00689 00690 /** 00691 * @brief Disable acknowledge on Own Address2 match address. 00692 * @rmtoll OAR2 ENDUAL LL_I2C_DisableOwnAddress2 00693 * @param I2Cx I2C Instance. 00694 * @retval None 00695 */ 00696 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx) 00697 { 00698 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL); 00699 } 00700 00701 /** 00702 * @brief Check if Own Address1 acknowledge is enabled or disabled. 00703 * @rmtoll OAR2 ENDUAL LL_I2C_IsEnabledOwnAddress2 00704 * @param I2Cx I2C Instance. 00705 * @retval State of bit (1 or 0). 00706 */ 00707 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx) 00708 { 00709 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_ENDUAL) == (I2C_OAR2_ENDUAL)); 00710 } 00711 00712 /** 00713 * @brief Configure the Peripheral clock frequency. 00714 * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock 00715 * @param I2Cx I2C Instance. 00716 * @param PeriphClock Peripheral Clock (in Hz) 00717 * @retval None 00718 */ 00719 __STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock) 00720 { 00721 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock)); 00722 } 00723 00724 /** 00725 * @brief Get the Peripheral clock frequency. 00726 * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock 00727 * @param I2Cx I2C Instance. 00728 * @retval Value of Peripheral Clock (in Hz) 00729 */ 00730 __STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx) 00731 { 00732 return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ))); 00733 } 00734 00735 /** 00736 * @brief Configure the Duty cycle (Fast mode only). 00737 * @rmtoll CCR DUTY LL_I2C_SetDutyCycle 00738 * @param I2Cx I2C Instance. 00739 * @param DutyCycle This parameter can be one of the following values: 00740 * @arg @ref LL_I2C_DUTYCYCLE_2 00741 * @arg @ref LL_I2C_DUTYCYCLE_16_9 00742 * @retval None 00743 */ 00744 __STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle) 00745 { 00746 MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle); 00747 } 00748 00749 /** 00750 * @brief Get the Duty cycle (Fast mode only). 00751 * @rmtoll CCR DUTY LL_I2C_GetDutyCycle 00752 * @param I2Cx I2C Instance. 00753 * @retval Returned value can be one of the following values: 00754 * @arg @ref LL_I2C_DUTYCYCLE_2 00755 * @arg @ref LL_I2C_DUTYCYCLE_16_9 00756 */ 00757 __STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx) 00758 { 00759 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY)); 00760 } 00761 00762 /** 00763 * @brief Configure the I2C master clock speed mode. 00764 * @rmtoll CCR FS LL_I2C_SetClockSpeedMode 00765 * @param I2Cx I2C Instance. 00766 * @param ClockSpeedMode This parameter can be one of the following values: 00767 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE 00768 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE 00769 * @retval None 00770 */ 00771 __STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode) 00772 { 00773 MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode); 00774 } 00775 00776 /** 00777 * @brief Get the the I2C master speed mode. 00778 * @rmtoll CCR FS LL_I2C_GetClockSpeedMode 00779 * @param I2Cx I2C Instance. 00780 * @retval Returned value can be one of the following values: 00781 * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE 00782 * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE 00783 */ 00784 __STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx) 00785 { 00786 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS)); 00787 } 00788 00789 /** 00790 * @brief Configure the SCL, SDA rising time. 00791 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 00792 * @rmtoll TRISE TRISE LL_I2C_SetRiseTime 00793 * @param I2Cx I2C Instance. 00794 * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F. 00795 * @retval None 00796 */ 00797 __STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime) 00798 { 00799 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime); 00800 } 00801 00802 /** 00803 * @brief Get the SCL, SDA rising time. 00804 * @rmtoll TRISE TRISE LL_I2C_GetRiseTime 00805 * @param I2Cx I2C Instance. 00806 * @retval Value between Min_Data=0x02 and Max_Data=0x3F 00807 */ 00808 __STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx) 00809 { 00810 return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE)); 00811 } 00812 00813 /** 00814 * @brief Configure the SCL high and low period. 00815 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 00816 * @rmtoll CCR CCR LL_I2C_SetClockPeriod 00817 * @param I2Cx I2C Instance. 00818 * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. 00819 * @retval None 00820 */ 00821 __STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod) 00822 { 00823 MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod); 00824 } 00825 00826 /** 00827 * @brief Get the SCL high and low period. 00828 * @rmtoll CCR CCR LL_I2C_GetClockPeriod 00829 * @param I2Cx I2C Instance. 00830 * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. 00831 */ 00832 __STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx) 00833 { 00834 return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR)); 00835 } 00836 00837 /** 00838 * @brief Configure the SCL speed. 00839 * @note This bit can only be programmed when the I2C is disabled (PE = 0). 00840 * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n 00841 * TRISE TRISE LL_I2C_ConfigSpeed\n 00842 * CCR FS LL_I2C_ConfigSpeed\n 00843 * CCR DUTY LL_I2C_ConfigSpeed\n 00844 * CCR CCR LL_I2C_ConfigSpeed 00845 * @param I2Cx I2C Instance. 00846 * @param PeriphClock Peripheral Clock (in Hz) 00847 * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz). 00848 * @param DutyCycle This parameter can be one of the following values: 00849 * @arg @ref LL_I2C_DUTYCYCLE_2 00850 * @arg @ref LL_I2C_DUTYCYCLE_16_9 00851 * @retval None 00852 */ 00853 __STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed, 00854 uint32_t DutyCycle) 00855 { 00856 register uint32_t freqrange = 0x0U; 00857 register uint32_t clockconfig = 0x0U; 00858 00859 /* Compute frequency range */ 00860 freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock); 00861 00862 /* Configure I2Cx: Frequency range register */ 00863 MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange); 00864 00865 /* Configure I2Cx: Rise Time register */ 00866 MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed)); 00867 00868 /* Configure Speed mode, Duty Cycle and Clock control register value */ 00869 if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD) 00870 { 00871 /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */ 00872 clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \ 00873 __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \ 00874 DutyCycle; 00875 } 00876 else 00877 { 00878 /* Set Speed mode at standard for Clock Speed request in standard clock range */ 00879 clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \ 00880 __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed); 00881 } 00882 00883 /* Configure I2Cx: Clock control register */ 00884 MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig); 00885 } 00886 00887 /** 00888 * @brief Configure peripheral mode. 00889 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 00890 * SMBus feature is supported by the I2Cx Instance. 00891 * @rmtoll CR1 SMBUS LL_I2C_SetMode\n 00892 * CR1 SMBTYPE LL_I2C_SetMode\n 00893 * CR1 ENARP LL_I2C_SetMode 00894 * @param I2Cx I2C Instance. 00895 * @param PeripheralMode This parameter can be one of the following values: 00896 * @arg @ref LL_I2C_MODE_I2C 00897 * @arg @ref LL_I2C_MODE_SMBUS_HOST 00898 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE 00899 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP 00900 * @retval None 00901 */ 00902 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode) 00903 { 00904 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP, PeripheralMode); 00905 } 00906 00907 /** 00908 * @brief Get peripheral mode. 00909 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 00910 * SMBus feature is supported by the I2Cx Instance. 00911 * @rmtoll CR1 SMBUS LL_I2C_GetMode\n 00912 * CR1 SMBTYPE LL_I2C_GetMode\n 00913 * CR1 ENARP LL_I2C_GetMode 00914 * @param I2Cx I2C Instance. 00915 * @retval Returned value can be one of the following values: 00916 * @arg @ref LL_I2C_MODE_I2C 00917 * @arg @ref LL_I2C_MODE_SMBUS_HOST 00918 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE 00919 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP 00920 */ 00921 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx) 00922 { 00923 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBUS | I2C_CR1_SMBTYPE | I2C_CR1_ENARP)); 00924 } 00925 00926 /** 00927 * @brief Enable SMBus alert (Host or Device mode) 00928 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 00929 * SMBus feature is supported by the I2Cx Instance. 00930 * @note SMBus Device mode: 00931 * - SMBus Alert pin is drived low and 00932 * Alert Response Address Header acknowledge is enabled. 00933 * SMBus Host mode: 00934 * - SMBus Alert pin management is supported. 00935 * @rmtoll CR1 ALERT LL_I2C_EnableSMBusAlert 00936 * @param I2Cx I2C Instance. 00937 * @retval None 00938 */ 00939 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx) 00940 { 00941 SET_BIT(I2Cx->CR1, I2C_CR1_ALERT); 00942 } 00943 00944 /** 00945 * @brief Disable SMBus alert (Host or Device mode) 00946 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 00947 * SMBus feature is supported by the I2Cx Instance. 00948 * @note SMBus Device mode: 00949 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and 00950 * Alert Response Address Header acknowledge is disabled. 00951 * SMBus Host mode: 00952 * - SMBus Alert pin management is not supported. 00953 * @rmtoll CR1 ALERT LL_I2C_DisableSMBusAlert 00954 * @param I2Cx I2C Instance. 00955 * @retval None 00956 */ 00957 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx) 00958 { 00959 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERT); 00960 } 00961 00962 /** 00963 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled. 00964 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 00965 * SMBus feature is supported by the I2Cx Instance. 00966 * @rmtoll CR1 ALERT LL_I2C_IsEnabledSMBusAlert 00967 * @param I2Cx I2C Instance. 00968 * @retval State of bit (1 or 0). 00969 */ 00970 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx) 00971 { 00972 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERT) == (I2C_CR1_ALERT)); 00973 } 00974 00975 /** 00976 * @brief Enable SMBus Packet Error Calculation (PEC). 00977 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 00978 * SMBus feature is supported by the I2Cx Instance. 00979 * @rmtoll CR1 ENPEC LL_I2C_EnableSMBusPEC 00980 * @param I2Cx I2C Instance. 00981 * @retval None 00982 */ 00983 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx) 00984 { 00985 SET_BIT(I2Cx->CR1, I2C_CR1_ENPEC); 00986 } 00987 00988 /** 00989 * @brief Disable SMBus Packet Error Calculation (PEC). 00990 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 00991 * SMBus feature is supported by the I2Cx Instance. 00992 * @rmtoll CR1 ENPEC LL_I2C_DisableSMBusPEC 00993 * @param I2Cx I2C Instance. 00994 * @retval None 00995 */ 00996 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx) 00997 { 00998 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENPEC); 00999 } 01000 01001 /** 01002 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled. 01003 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01004 * SMBus feature is supported by the I2Cx Instance. 01005 * @rmtoll CR1 ENPEC LL_I2C_IsEnabledSMBusPEC 01006 * @param I2Cx I2C Instance. 01007 * @retval State of bit (1 or 0). 01008 */ 01009 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx) 01010 { 01011 return (READ_BIT(I2Cx->CR1, I2C_CR1_ENPEC) == (I2C_CR1_ENPEC)); 01012 } 01013 01014 /** 01015 * @} 01016 */ 01017 01018 /** @defgroup I2C_LL_EF_IT_Management IT_Management 01019 * @{ 01020 */ 01021 01022 /** 01023 * @brief Enable TXE interrupt. 01024 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n 01025 * CR2 ITBUFEN LL_I2C_EnableIT_TX 01026 * @param I2Cx I2C Instance. 01027 * @retval None 01028 */ 01029 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) 01030 { 01031 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); 01032 } 01033 01034 /** 01035 * @brief Disable TXE interrupt. 01036 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n 01037 * CR2 ITBUFEN LL_I2C_DisableIT_TX 01038 * @param I2Cx I2C Instance. 01039 * @retval None 01040 */ 01041 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) 01042 { 01043 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); 01044 } 01045 01046 /** 01047 * @brief Check if the TXE Interrupt is enabled or disabled. 01048 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n 01049 * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX 01050 * @param I2Cx I2C Instance. 01051 * @retval State of bit (1 or 0). 01052 */ 01053 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) 01054 { 01055 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); 01056 } 01057 01058 /** 01059 * @brief Enable RXNE interrupt. 01060 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n 01061 * CR2 ITBUFEN LL_I2C_EnableIT_RX 01062 * @param I2Cx I2C Instance. 01063 * @retval None 01064 */ 01065 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) 01066 { 01067 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); 01068 } 01069 01070 /** 01071 * @brief Disable RXNE interrupt. 01072 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n 01073 * CR2 ITBUFEN LL_I2C_DisableIT_RX 01074 * @param I2Cx I2C Instance. 01075 * @retval None 01076 */ 01077 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) 01078 { 01079 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); 01080 } 01081 01082 /** 01083 * @brief Check if the RXNE Interrupt is enabled or disabled. 01084 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n 01085 * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX 01086 * @param I2Cx I2C Instance. 01087 * @retval State of bit (1 or 0). 01088 */ 01089 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) 01090 { 01091 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); 01092 } 01093 01094 /** 01095 * @brief Enable Events interrupts. 01096 * @note Any of these events will generate interrupt : 01097 * Start Bit (SB) 01098 * Address sent, Address matched (ADDR) 01099 * 10-bit header sent (ADD10) 01100 * Stop detection (STOPF) 01101 * Byte transfer finished (BTF) 01102 * 01103 * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) : 01104 * Receive buffer not empty (RXNE) 01105 * Transmit buffer empty (TXE) 01106 * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT 01107 * @param I2Cx I2C Instance. 01108 * @retval None 01109 */ 01110 __STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx) 01111 { 01112 SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); 01113 } 01114 01115 /** 01116 * @brief Disable Events interrupts. 01117 * @note Any of these events will generate interrupt : 01118 * Start Bit (SB) 01119 * Address sent, Address matched (ADDR) 01120 * 10-bit header sent (ADD10) 01121 * Stop detection (STOPF) 01122 * Byte transfer finished (BTF) 01123 * Receive buffer not empty (RXNE) 01124 * Transmit buffer empty (TXE) 01125 * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT 01126 * @param I2Cx I2C Instance. 01127 * @retval None 01128 */ 01129 __STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx) 01130 { 01131 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); 01132 } 01133 01134 /** 01135 * @brief Check if Events interrupts are enabled or disabled. 01136 * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT 01137 * @param I2Cx I2C Instance. 01138 * @retval State of bit (1 or 0). 01139 */ 01140 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx) 01141 { 01142 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN)); 01143 } 01144 01145 /** 01146 * @brief Enable Buffer interrupts. 01147 * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) : 01148 * Receive buffer not empty (RXNE) 01149 * Transmit buffer empty (TXE) 01150 * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF 01151 * @param I2Cx I2C Instance. 01152 * @retval None 01153 */ 01154 __STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx) 01155 { 01156 SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); 01157 } 01158 01159 /** 01160 * @brief Disable Buffer interrupts. 01161 * @note Any of these Buffer events will generate interrupt : 01162 * Receive buffer not empty (RXNE) 01163 * Transmit buffer empty (TXE) 01164 * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF 01165 * @param I2Cx I2C Instance. 01166 * @retval None 01167 */ 01168 __STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx) 01169 { 01170 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); 01171 } 01172 01173 /** 01174 * @brief Check if Buffer interrupts are enabled or disabled. 01175 * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF 01176 * @param I2Cx I2C Instance. 01177 * @retval State of bit (1 or 0). 01178 */ 01179 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx) 01180 { 01181 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN)); 01182 } 01183 01184 /** 01185 * @brief Enable Error interrupts. 01186 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01187 * SMBus feature is supported by the I2Cx Instance. 01188 * @note Any of these errors will generate interrupt : 01189 * Bus Error detection (BERR) 01190 * Arbitration Loss (ARLO) 01191 * Acknowledge Failure(AF) 01192 * Overrun/Underrun (OVR) 01193 * SMBus Timeout detection (TIMEOUT) 01194 * SMBus PEC error detection (PECERR) 01195 * SMBus Alert pin event detection (SMBALERT) 01196 * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR 01197 * @param I2Cx I2C Instance. 01198 * @retval None 01199 */ 01200 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) 01201 { 01202 SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN); 01203 } 01204 01205 /** 01206 * @brief Disable Error interrupts. 01207 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01208 * SMBus feature is supported by the I2Cx Instance. 01209 * @note Any of these errors will generate interrupt : 01210 * Bus Error detection (BERR) 01211 * Arbitration Loss (ARLO) 01212 * Acknowledge Failure(AF) 01213 * Overrun/Underrun (OVR) 01214 * SMBus Timeout detection (TIMEOUT) 01215 * SMBus PEC error detection (PECERR) 01216 * SMBus Alert pin event detection (SMBALERT) 01217 * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR 01218 * @param I2Cx I2C Instance. 01219 * @retval None 01220 */ 01221 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) 01222 { 01223 CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN); 01224 } 01225 01226 /** 01227 * @brief Check if Error interrupts are enabled or disabled. 01228 * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR 01229 * @param I2Cx I2C Instance. 01230 * @retval State of bit (1 or 0). 01231 */ 01232 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) 01233 { 01234 return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN)); 01235 } 01236 01237 /** 01238 * @} 01239 */ 01240 01241 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management 01242 * @{ 01243 */ 01244 01245 /** 01246 * @brief Indicate the status of Transmit data register empty flag. 01247 * @note RESET: When next data is written in Transmit data register. 01248 * SET: When Transmit data register is empty. 01249 * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE 01250 * @param I2Cx I2C Instance. 01251 * @retval State of bit (1 or 0). 01252 */ 01253 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) 01254 { 01255 return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE)); 01256 } 01257 01258 /** 01259 * @brief Indicate the status of Byte Transfer Finished flag. 01260 * RESET: When Data byte transfer not done. 01261 * SET: When Data byte transfer succeeded. 01262 * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF 01263 * @param I2Cx I2C Instance. 01264 * @retval State of bit (1 or 0). 01265 */ 01266 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx) 01267 { 01268 return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF)); 01269 } 01270 01271 /** 01272 * @brief Indicate the status of Receive data register not empty flag. 01273 * @note RESET: When Receive data register is read. 01274 * SET: When the received data is copied in Receive data register. 01275 * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE 01276 * @param I2Cx I2C Instance. 01277 * @retval State of bit (1 or 0). 01278 */ 01279 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) 01280 { 01281 return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE)); 01282 } 01283 01284 /** 01285 * @brief Indicate the status of Start Bit (master mode). 01286 * @note RESET: When No Start condition. 01287 * SET: When Start condition is generated. 01288 * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB 01289 * @param I2Cx I2C Instance. 01290 * @retval State of bit (1 or 0). 01291 */ 01292 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx) 01293 { 01294 return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB)); 01295 } 01296 01297 /** 01298 * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode). 01299 * @note RESET: Clear default value. 01300 * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode). 01301 * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR 01302 * @param I2Cx I2C Instance. 01303 * @retval State of bit (1 or 0). 01304 */ 01305 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) 01306 { 01307 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR)); 01308 } 01309 01310 /** 01311 * @brief Indicate the status of 10-bit header sent (master mode). 01312 * @note RESET: When no ADD10 event occured. 01313 * SET: When the master has sent the first address byte (header). 01314 * @rmtoll SR1 ADD10 LL_I2C_IsActiveFlag_ADD10 01315 * @param I2Cx I2C Instance. 01316 * @retval State of bit (1 or 0). 01317 */ 01318 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADD10(I2C_TypeDef *I2Cx) 01319 { 01320 return (READ_BIT(I2Cx->SR1, I2C_SR1_ADD10) == (I2C_SR1_ADD10)); 01321 } 01322 01323 /** 01324 * @brief Indicate the status of Acknowledge failure flag. 01325 * @note RESET: No acknowledge failure. 01326 * SET: When an acknowledge failure is received after a byte transmission. 01327 * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF 01328 * @param I2Cx I2C Instance. 01329 * @retval State of bit (1 or 0). 01330 */ 01331 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx) 01332 { 01333 return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF)); 01334 } 01335 01336 /** 01337 * @brief Indicate the status of Stop detection flag (slave mode). 01338 * @note RESET: Clear default value. 01339 * SET: When a Stop condition is detected. 01340 * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP 01341 * @param I2Cx I2C Instance. 01342 * @retval State of bit (1 or 0). 01343 */ 01344 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) 01345 { 01346 return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF)); 01347 } 01348 01349 /** 01350 * @brief Indicate the status of Bus error flag. 01351 * @note RESET: Clear default value. 01352 * SET: When a misplaced Start or Stop condition is detected. 01353 * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR 01354 * @param I2Cx I2C Instance. 01355 * @retval State of bit (1 or 0). 01356 */ 01357 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) 01358 { 01359 return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR)); 01360 } 01361 01362 /** 01363 * @brief Indicate the status of Arbitration lost flag. 01364 * @note RESET: Clear default value. 01365 * SET: When arbitration lost. 01366 * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO 01367 * @param I2Cx I2C Instance. 01368 * @retval State of bit (1 or 0). 01369 */ 01370 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) 01371 { 01372 return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO)); 01373 } 01374 01375 /** 01376 * @brief Indicate the status of Overrun/Underrun flag. 01377 * @note RESET: Clear default value. 01378 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). 01379 * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR 01380 * @param I2Cx I2C Instance. 01381 * @retval State of bit (1 or 0). 01382 */ 01383 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) 01384 { 01385 return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR)); 01386 } 01387 01388 /** 01389 * @brief Indicate the status of SMBus PEC error flag in reception. 01390 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01391 * SMBus feature is supported by the I2Cx Instance. 01392 * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR 01393 * @param I2Cx I2C Instance. 01394 * @retval State of bit (1 or 0). 01395 */ 01396 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) 01397 { 01398 return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR)); 01399 } 01400 01401 /** 01402 * @brief Indicate the status of SMBus Timeout detection flag. 01403 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01404 * SMBus feature is supported by the I2Cx Instance. 01405 * @rmtoll SR1 TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT 01406 * @param I2Cx I2C Instance. 01407 * @retval State of bit (1 or 0). 01408 */ 01409 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) 01410 { 01411 return (READ_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT) == (I2C_SR1_TIMEOUT)); 01412 } 01413 01414 /** 01415 * @brief Indicate the status of SMBus alert flag. 01416 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01417 * SMBus feature is supported by the I2Cx Instance. 01418 * @rmtoll SR1 SMBALERT LL_I2C_IsActiveSMBusFlag_ALERT 01419 * @param I2Cx I2C Instance. 01420 * @retval State of bit (1 or 0). 01421 */ 01422 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx) 01423 { 01424 return (READ_BIT(I2Cx->SR1, I2C_SR1_SMBALERT) == (I2C_SR1_SMBALERT)); 01425 } 01426 01427 /** 01428 * @brief Indicate the status of Bus Busy flag. 01429 * @note RESET: Clear default value. 01430 * SET: When a Start condition is detected. 01431 * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY 01432 * @param I2Cx I2C Instance. 01433 * @retval State of bit (1 or 0). 01434 */ 01435 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) 01436 { 01437 return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY)); 01438 } 01439 01440 /** 01441 * @brief Indicate the status of Dual flag. 01442 * @note RESET: Received address matched with OAR1. 01443 * SET: Received address matched with OAR2. 01444 * @rmtoll SR2 DUALF LL_I2C_IsActiveFlag_DUAL 01445 * @param I2Cx I2C Instance. 01446 * @retval State of bit (1 or 0). 01447 */ 01448 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_DUAL(I2C_TypeDef *I2Cx) 01449 { 01450 return (READ_BIT(I2Cx->SR2, I2C_SR2_DUALF) == (I2C_SR2_DUALF)); 01451 } 01452 01453 /** 01454 * @brief Indicate the status of SMBus Host address reception (Slave mode). 01455 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01456 * SMBus feature is supported by the I2Cx Instance. 01457 * @note RESET: No SMBus Host address 01458 * SET: SMBus Host address received. 01459 * @note This status is cleared by hardware after a STOP condition or repeated START condition. 01460 * @rmtoll SR2 SMBHOST LL_I2C_IsActiveSMBusFlag_SMBHOST 01461 * @param I2Cx I2C Instance. 01462 * @retval State of bit (1 or 0). 01463 */ 01464 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBHOST(I2C_TypeDef *I2Cx) 01465 { 01466 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBHOST) == (I2C_SR2_SMBHOST)); 01467 } 01468 01469 /** 01470 * @brief Indicate the status of SMBus Device default address reception (Slave mode). 01471 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01472 * SMBus feature is supported by the I2Cx Instance. 01473 * @note RESET: No SMBus Device default address 01474 * SET: SMBus Device default address received. 01475 * @note This status is cleared by hardware after a STOP condition or repeated START condition. 01476 * @rmtoll SR2 SMBDEFAULT LL_I2C_IsActiveSMBusFlag_SMBDEFAULT 01477 * @param I2Cx I2C Instance. 01478 * @retval State of bit (1 or 0). 01479 */ 01480 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_SMBDEFAULT(I2C_TypeDef *I2Cx) 01481 { 01482 return (READ_BIT(I2Cx->SR2, I2C_SR2_SMBDEFAULT) == (I2C_SR2_SMBDEFAULT)); 01483 } 01484 01485 /** 01486 * @brief Indicate the status of General call address reception (Slave mode). 01487 * @note RESET: No Generall call address 01488 * SET: General call address received. 01489 * @note This status is cleared by hardware after a STOP condition or repeated START condition. 01490 * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL 01491 * @param I2Cx I2C Instance. 01492 * @retval State of bit (1 or 0). 01493 */ 01494 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx) 01495 { 01496 return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL)); 01497 } 01498 01499 /** 01500 * @brief Indicate the status of Master/Slave flag. 01501 * @note RESET: Slave Mode. 01502 * SET: Master Mode. 01503 * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL 01504 * @param I2Cx I2C Instance. 01505 * @retval State of bit (1 or 0). 01506 */ 01507 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx) 01508 { 01509 return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL)); 01510 } 01511 01512 /** 01513 * @brief Clear Address Matched flag. 01514 * @note Clearing this flag is done by a read access to the I2Cx_SR1 01515 * register followed by a read access to the I2Cx_SR2 register. 01516 * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR 01517 * @param I2Cx I2C Instance. 01518 * @retval None 01519 */ 01520 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) 01521 { 01522 __IO uint32_t tmpreg; 01523 tmpreg = I2Cx->SR1; 01524 (void) tmpreg; 01525 tmpreg = I2Cx->SR2; 01526 (void) tmpreg; 01527 } 01528 01529 /** 01530 * @brief Clear Acknowledge failure flag. 01531 * @rmtoll SR1 AF LL_I2C_ClearFlag_AF 01532 * @param I2Cx I2C Instance. 01533 * @retval None 01534 */ 01535 __STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx) 01536 { 01537 CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF); 01538 } 01539 01540 /** 01541 * @brief Clear Stop detection flag. 01542 * @note Clearing this flag is done by a read access to the I2Cx_SR1 01543 * register followed by a write access to I2Cx_CR1 register. 01544 * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n 01545 * CR1 PE LL_I2C_ClearFlag_STOP 01546 * @param I2Cx I2C Instance. 01547 * @retval None 01548 */ 01549 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) 01550 { 01551 __IO uint32_t tmpreg; 01552 tmpreg = I2Cx->SR1; 01553 (void) tmpreg; 01554 SET_BIT(I2Cx->CR1, I2C_CR1_PE); 01555 } 01556 01557 /** 01558 * @brief Clear Bus error flag. 01559 * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR 01560 * @param I2Cx I2C Instance. 01561 * @retval None 01562 */ 01563 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) 01564 { 01565 CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR); 01566 } 01567 01568 /** 01569 * @brief Clear Arbitration lost flag. 01570 * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO 01571 * @param I2Cx I2C Instance. 01572 * @retval None 01573 */ 01574 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) 01575 { 01576 CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO); 01577 } 01578 01579 /** 01580 * @brief Clear Overrun/Underrun flag. 01581 * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR 01582 * @param I2Cx I2C Instance. 01583 * @retval None 01584 */ 01585 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) 01586 { 01587 CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR); 01588 } 01589 01590 /** 01591 * @brief Clear SMBus PEC error flag. 01592 * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR 01593 * @param I2Cx I2C Instance. 01594 * @retval None 01595 */ 01596 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) 01597 { 01598 CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR); 01599 } 01600 01601 /** 01602 * @brief Clear SMBus Timeout detection flag. 01603 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01604 * SMBus feature is supported by the I2Cx Instance. 01605 * @rmtoll SR1 TIMEOUT LL_I2C_ClearSMBusFlag_TIMEOUT 01606 * @param I2Cx I2C Instance. 01607 * @retval None 01608 */ 01609 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx) 01610 { 01611 CLEAR_BIT(I2Cx->SR1, I2C_SR1_TIMEOUT); 01612 } 01613 01614 /** 01615 * @brief Clear SMBus Alert flag. 01616 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01617 * SMBus feature is supported by the I2Cx Instance. 01618 * @rmtoll SR1 SMBALERT LL_I2C_ClearSMBusFlag_ALERT 01619 * @param I2Cx I2C Instance. 01620 * @retval None 01621 */ 01622 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx) 01623 { 01624 CLEAR_BIT(I2Cx->SR1, I2C_SR1_SMBALERT); 01625 } 01626 01627 /** 01628 * @} 01629 */ 01630 01631 /** @defgroup I2C_LL_EF_Data_Management Data_Management 01632 * @{ 01633 */ 01634 01635 /** 01636 * @brief Enable Reset of I2C peripheral. 01637 * @rmtoll CR1 SWRST LL_I2C_EnableReset 01638 * @param I2Cx I2C Instance. 01639 * @retval None 01640 */ 01641 __STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx) 01642 { 01643 SET_BIT(I2Cx->CR1, I2C_CR1_SWRST); 01644 } 01645 01646 /** 01647 * @brief Disable Reset of I2C peripheral. 01648 * @rmtoll CR1 SWRST LL_I2C_DisableReset 01649 * @param I2Cx I2C Instance. 01650 * @retval None 01651 */ 01652 __STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx) 01653 { 01654 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST); 01655 } 01656 01657 /** 01658 * @brief Check if the I2C peripheral is under reset state or not. 01659 * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled 01660 * @param I2Cx I2C Instance. 01661 * @retval State of bit (1 or 0). 01662 */ 01663 __STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx) 01664 { 01665 return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST)); 01666 } 01667 01668 /** 01669 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. 01670 * @note Usage in Slave or Master mode. 01671 * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData 01672 * @param I2Cx I2C Instance. 01673 * @param TypeAcknowledge This parameter can be one of the following values: 01674 * @arg @ref LL_I2C_ACK 01675 * @arg @ref LL_I2C_NACK 01676 * @retval None 01677 */ 01678 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) 01679 { 01680 MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge); 01681 } 01682 01683 /** 01684 * @brief Generate a START or RESTART condition 01685 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. 01686 * This action has no effect when RELOAD is set. 01687 * @rmtoll CR1 START LL_I2C_GenerateStartCondition 01688 * @param I2Cx I2C Instance. 01689 * @retval None 01690 */ 01691 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) 01692 { 01693 SET_BIT(I2Cx->CR1, I2C_CR1_START); 01694 } 01695 01696 /** 01697 * @brief Generate a STOP condition after the current byte transfer (master mode). 01698 * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition 01699 * @param I2Cx I2C Instance. 01700 * @retval None 01701 */ 01702 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) 01703 { 01704 SET_BIT(I2Cx->CR1, I2C_CR1_STOP); 01705 } 01706 01707 /** 01708 * @brief Enable bit POS (master/host mode). 01709 * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC. 01710 * @rmtoll CR1 POS LL_I2C_EnableBitPOS 01711 * @param I2Cx I2C Instance. 01712 * @retval None 01713 */ 01714 __STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx) 01715 { 01716 SET_BIT(I2Cx->CR1, I2C_CR1_POS); 01717 } 01718 01719 /** 01720 * @brief Disable bit POS (master/host mode). 01721 * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC. 01722 * @rmtoll CR1 POS LL_I2C_DisableBitPOS 01723 * @param I2Cx I2C Instance. 01724 * @retval None 01725 */ 01726 __STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx) 01727 { 01728 CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS); 01729 } 01730 01731 /** 01732 * @brief Check if bit POS is enabled or disabled. 01733 * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS 01734 * @param I2Cx I2C Instance. 01735 * @retval State of bit (1 or 0). 01736 */ 01737 __STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx) 01738 { 01739 return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS)); 01740 } 01741 01742 /** 01743 * @brief Indicate the value of transfer direction. 01744 * @note RESET: Bus is in read transfer (peripheral point of view). 01745 * SET: Bus is in write transfer (peripheral point of view). 01746 * @rmtoll SR2 TRA LL_I2C_GetTransferDirection 01747 * @param I2Cx I2C Instance. 01748 * @retval Returned value can be one of the following values: 01749 * @arg @ref LL_I2C_DIRECTION_WRITE 01750 * @arg @ref LL_I2C_DIRECTION_READ 01751 */ 01752 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) 01753 { 01754 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA)); 01755 } 01756 01757 /** 01758 * @brief Enable DMA last transfer. 01759 * @note This action mean that next DMA EOT is the last transfer. 01760 * @rmtoll CR2 LAST LL_I2C_EnableLastDMA 01761 * @param I2Cx I2C Instance. 01762 * @retval None 01763 */ 01764 __STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx) 01765 { 01766 SET_BIT(I2Cx->CR2, I2C_CR2_LAST); 01767 } 01768 01769 /** 01770 * @brief Disable DMA last transfer. 01771 * @note This action mean that next DMA EOT is not the last transfer. 01772 * @rmtoll CR2 LAST LL_I2C_DisableLastDMA 01773 * @param I2Cx I2C Instance. 01774 * @retval None 01775 */ 01776 __STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx) 01777 { 01778 CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST); 01779 } 01780 01781 /** 01782 * @brief Check if DMA last transfer is enabled or disabled. 01783 * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA 01784 * @param I2Cx I2C Instance. 01785 * @retval State of bit (1 or 0). 01786 */ 01787 __STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx) 01788 { 01789 return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST)); 01790 } 01791 01792 /** 01793 * @brief Enable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). 01794 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01795 * SMBus feature is supported by the I2Cx Instance. 01796 * @note This feature is cleared by hardware when the PEC byte is transferred or compared, 01797 * or by a START or STOP condition, it is also cleared by software. 01798 * @rmtoll CR1 PEC LL_I2C_EnableSMBusPECCompare 01799 * @param I2Cx I2C Instance. 01800 * @retval None 01801 */ 01802 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx) 01803 { 01804 SET_BIT(I2Cx->CR1, I2C_CR1_PEC); 01805 } 01806 01807 /** 01808 * @brief Disable transfer or internal comparison of the SMBus Packet Error byte (transmission or reception mode). 01809 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01810 * SMBus feature is supported by the I2Cx Instance. 01811 * @rmtoll CR1 PEC LL_I2C_DisableSMBusPECCompare 01812 * @param I2Cx I2C Instance. 01813 * @retval None 01814 */ 01815 __STATIC_INLINE void LL_I2C_DisableSMBusPECCompare(I2C_TypeDef *I2Cx) 01816 { 01817 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PEC); 01818 } 01819 01820 /** 01821 * @brief Check if the SMBus Packet Error byte transfer or internal comparison is requested or not. 01822 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01823 * SMBus feature is supported by the I2Cx Instance. 01824 * @rmtoll CR1 PEC LL_I2C_IsEnabledSMBusPECCompare 01825 * @param I2Cx I2C Instance. 01826 * @retval State of bit (1 or 0). 01827 */ 01828 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx) 01829 { 01830 return (READ_BIT(I2Cx->CR1, I2C_CR1_PEC) == (I2C_CR1_PEC)); 01831 } 01832 01833 /** 01834 * @brief Get the SMBus Packet Error byte calculated. 01835 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not 01836 * SMBus feature is supported by the I2Cx Instance. 01837 * @rmtoll SR2 PEC LL_I2C_GetSMBusPEC 01838 * @param I2Cx I2C Instance. 01839 * @retval Value between Min_Data=0x00 and Max_Data=0xFF 01840 */ 01841 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx) 01842 { 01843 return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_PEC) >> I2C_SR2_PEC_Pos); 01844 } 01845 01846 /** 01847 * @brief Read Receive Data register. 01848 * @rmtoll DR DR LL_I2C_ReceiveData8 01849 * @param I2Cx I2C Instance. 01850 * @retval Value between Min_Data=0x0 and Max_Data=0xFF 01851 */ 01852 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) 01853 { 01854 return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR)); 01855 } 01856 01857 /** 01858 * @brief Write in Transmit Data Register . 01859 * @rmtoll DR DR LL_I2C_TransmitData8 01860 * @param I2Cx I2C Instance. 01861 * @param Data Value between Min_Data=0x0 and Max_Data=0xFF 01862 * @retval None 01863 */ 01864 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) 01865 { 01866 MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data); 01867 } 01868 01869 /** 01870 * @} 01871 */ 01872 01873 #if defined(USE_FULL_LL_DRIVER) 01874 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions 01875 * @{ 01876 */ 01877 01878 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); 01879 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); 01880 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); 01881 01882 01883 /** 01884 * @} 01885 */ 01886 #endif /* USE_FULL_LL_DRIVER */ 01887 01888 /** 01889 * @} 01890 */ 01891 01892 /** 01893 * @} 01894 */ 01895 01896 #endif /* I2C1 || I2C2 || I2C3 */ 01897 01898 /** 01899 * @} 01900 */ 01901 01902 #ifdef __cplusplus 01903 } 01904 #endif 01905 01906 #endif /* __STM32F4xx_LL_I2C_H */ 01907 01908 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/