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STM32F439xx HAL User Manual
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00001 /** 00002 ****************************************************************************** 00003 * @file stm32f4xx_ll_dma.h 00004 * @author MCD Application Team 00005 * @brief Header file of DMA LL module. 00006 ****************************************************************************** 00007 * @attention 00008 * 00009 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> 00010 * 00011 * Redistribution and use in source and binary forms, with or without modification, 00012 * are permitted provided that the following conditions are met: 00013 * 1. Redistributions of source code must retain the above copyright notice, 00014 * this list of conditions and the following disclaimer. 00015 * 2. Redistributions in binary form must reproduce the above copyright notice, 00016 * this list of conditions and the following disclaimer in the documentation 00017 * and/or other materials provided with the distribution. 00018 * 3. Neither the name of STMicroelectronics nor the names of its contributors 00019 * may be used to endorse or promote products derived from this software 00020 * without specific prior written permission. 00021 * 00022 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 00023 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 00024 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 00025 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE 00026 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 00027 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 00028 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 00029 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 00030 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 00031 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 00032 * 00033 ****************************************************************************** 00034 */ 00035 00036 /* Define to prevent recursive inclusion -------------------------------------*/ 00037 #ifndef __STM32F4xx_LL_DMA_H 00038 #define __STM32F4xx_LL_DMA_H 00039 00040 #ifdef __cplusplus 00041 extern "C" { 00042 #endif 00043 00044 /* Includes ------------------------------------------------------------------*/ 00045 #include "stm32f4xx.h" 00046 00047 /** @addtogroup STM32F4xx_LL_Driver 00048 * @{ 00049 */ 00050 00051 #if defined (DMA1) || defined (DMA2) 00052 00053 /** @defgroup DMA_LL DMA 00054 * @{ 00055 */ 00056 00057 /* Private types -------------------------------------------------------------*/ 00058 /* Private variables ---------------------------------------------------------*/ 00059 /** @defgroup DMA_LL_Private_Variables DMA Private Variables 00060 * @{ 00061 */ 00062 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */ 00063 static const uint8_t STREAM_OFFSET_TAB[] = 00064 { 00065 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE), 00066 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE), 00067 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE), 00068 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE), 00069 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE), 00070 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE), 00071 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE), 00072 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE) 00073 }; 00074 00075 /** 00076 * @} 00077 */ 00078 00079 /* Private constants ---------------------------------------------------------*/ 00080 /** @defgroup DMA_LL_Private_Constants DMA Private Constants 00081 * @{ 00082 */ 00083 /** 00084 * @} 00085 */ 00086 00087 00088 /* Private macros ------------------------------------------------------------*/ 00089 /* Exported types ------------------------------------------------------------*/ 00090 #if defined(USE_FULL_LL_DRIVER) 00091 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure 00092 * @{ 00093 */ 00094 typedef struct 00095 { 00096 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer 00097 or as Source base address in case of memory to memory transfer direction. 00098 00099 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00100 00101 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer 00102 or as Destination base address in case of memory to memory transfer direction. 00103 00104 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ 00105 00106 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, 00107 from memory to memory or from peripheral to memory. 00108 This parameter can be a value of @ref DMA_LL_EC_DIRECTION 00109 00110 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ 00111 00112 uint32_t Mode; /*!< Specifies the normal or circular operation mode. 00113 This parameter can be a value of @ref DMA_LL_EC_MODE 00114 @note The circular buffer mode cannot be used if the memory to memory 00115 data transfer direction is configured on the selected Stream 00116 00117 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ 00118 00119 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction 00120 is incremented or not. 00121 This parameter can be a value of @ref DMA_LL_EC_PERIPH 00122 00123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ 00124 00125 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction 00126 is incremented or not. 00127 This parameter can be a value of @ref DMA_LL_EC_MEMORY 00128 00129 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ 00130 00131 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) 00132 in case of memory to memory transfer direction. 00133 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN 00134 00135 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ 00136 00137 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) 00138 in case of memory to memory transfer direction. 00139 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN 00140 00141 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ 00142 00143 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. 00144 The data unit is equal to the source buffer configuration set in PeripheralSize 00145 or MemorySize parameters depending in the transfer direction. 00146 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF 00147 00148 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ 00149 00150 uint32_t Channel; /*!< Specifies the peripheral channel. 00151 This parameter can be a value of @ref DMA_LL_EC_CHANNEL 00152 00153 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */ 00154 00155 uint32_t Priority; /*!< Specifies the channel priority level. 00156 This parameter can be a value of @ref DMA_LL_EC_PRIORITY 00157 00158 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */ 00159 00160 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream. 00161 This parameter can be a value of @ref DMA_LL_FIFOMODE 00162 @note The Direct mode (FIFO mode disabled) cannot be used if the 00163 memory-to-memory data transfer is configured on the selected stream 00164 00165 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */ 00166 00167 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level. 00168 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD 00169 00170 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */ 00171 00172 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers. 00173 It specifies the amount of data to be transferred in a single non interruptible 00174 transaction. 00175 This parameter can be a value of @ref DMA_LL_EC_MBURST 00176 @note The burst mode is possible only if the address Increment mode is enabled. 00177 00178 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */ 00179 00180 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers. 00181 It specifies the amount of data to be transferred in a single non interruptible 00182 transaction. 00183 This parameter can be a value of @ref DMA_LL_EC_PBURST 00184 @note The burst mode is possible only if the address Increment mode is enabled. 00185 00186 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */ 00187 00188 } LL_DMA_InitTypeDef; 00189 /** 00190 * @} 00191 */ 00192 #endif /*USE_FULL_LL_DRIVER*/ 00193 /* Exported constants --------------------------------------------------------*/ 00194 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants 00195 * @{ 00196 */ 00197 00198 /** @defgroup DMA_LL_EC_STREAM STREAM 00199 * @{ 00200 */ 00201 #define LL_DMA_STREAM_0 0x00000000U 00202 #define LL_DMA_STREAM_1 0x00000001U 00203 #define LL_DMA_STREAM_2 0x00000002U 00204 #define LL_DMA_STREAM_3 0x00000003U 00205 #define LL_DMA_STREAM_4 0x00000004U 00206 #define LL_DMA_STREAM_5 0x00000005U 00207 #define LL_DMA_STREAM_6 0x00000006U 00208 #define LL_DMA_STREAM_7 0x00000007U 00209 #define LL_DMA_STREAM_ALL 0xFFFF0000U 00210 /** 00211 * @} 00212 */ 00213 00214 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION 00215 * @{ 00216 */ 00217 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ 00218 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */ 00219 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */ 00220 /** 00221 * @} 00222 */ 00223 00224 /** @defgroup DMA_LL_EC_MODE MODE 00225 * @{ 00226 */ 00227 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ 00228 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */ 00229 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */ 00230 /** 00231 * @} 00232 */ 00233 00234 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLEBUFFER MODE 00235 * @{ 00236 */ 00237 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */ 00238 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */ 00239 /** 00240 * @} 00241 */ 00242 00243 /** @defgroup DMA_LL_EC_PERIPH PERIPH 00244 * @{ 00245 */ 00246 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ 00247 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */ 00248 /** 00249 * @} 00250 */ 00251 00252 /** @defgroup DMA_LL_EC_MEMORY MEMORY 00253 * @{ 00254 */ 00255 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ 00256 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */ 00257 /** 00258 * @} 00259 */ 00260 00261 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN 00262 * @{ 00263 */ 00264 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ 00265 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ 00266 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */ 00267 /** 00268 * @} 00269 */ 00270 00271 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN 00272 * @{ 00273 */ 00274 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ 00275 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ 00276 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */ 00277 /** 00278 * @} 00279 */ 00280 00281 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE 00282 * @{ 00283 */ 00284 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */ 00285 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */ 00286 /** 00287 * @} 00288 */ 00289 00290 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY 00291 * @{ 00292 */ 00293 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ 00294 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */ 00295 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */ 00296 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */ 00297 /** 00298 * @} 00299 */ 00300 00301 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL 00302 * @{ 00303 */ 00304 #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */ 00305 #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */ 00306 #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */ 00307 #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */ 00308 #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */ 00309 #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */ 00310 #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */ 00311 #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */ 00312 /** 00313 * @} 00314 */ 00315 00316 /** @defgroup DMA_LL_EC_MBURST MBURST 00317 * @{ 00318 */ 00319 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */ 00320 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */ 00321 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */ 00322 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */ 00323 /** 00324 * @} 00325 */ 00326 00327 /** @defgroup DMA_LL_EC_PBURST PBURST 00328 * @{ 00329 */ 00330 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */ 00331 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */ 00332 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */ 00333 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */ 00334 /** 00335 * @} 00336 */ 00337 00338 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE 00339 * @{ 00340 */ 00341 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */ 00342 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */ 00343 /** 00344 * @} 00345 */ 00346 00347 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0 00348 * @{ 00349 */ 00350 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */ 00351 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */ 00352 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */ 00353 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */ 00354 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */ 00355 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */ 00356 /** 00357 * @} 00358 */ 00359 00360 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD 00361 * @{ 00362 */ 00363 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */ 00364 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */ 00365 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */ 00366 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */ 00367 /** 00368 * @} 00369 */ 00370 00371 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM 00372 * @{ 00373 */ 00374 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */ 00375 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */ 00376 /** 00377 * @} 00378 */ 00379 00380 /** 00381 * @} 00382 */ 00383 00384 /* Exported macro ------------------------------------------------------------*/ 00385 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros 00386 * @{ 00387 */ 00388 00389 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros 00390 * @{ 00391 */ 00392 /** 00393 * @brief Write a value in DMA register 00394 * @param __INSTANCE__ DMA Instance 00395 * @param __REG__ Register to be written 00396 * @param __VALUE__ Value to be written in the register 00397 * @retval None 00398 */ 00399 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) 00400 00401 /** 00402 * @brief Read a value in DMA register 00403 * @param __INSTANCE__ DMA Instance 00404 * @param __REG__ Register to be read 00405 * @retval Register value 00406 */ 00407 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) 00408 /** 00409 * @} 00410 */ 00411 00412 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy 00413 * @{ 00414 */ 00415 /** 00416 * @brief Convert DMAx_Streamy into DMAx 00417 * @param __STREAM_INSTANCE__ DMAx_Streamy 00418 * @retval DMAx 00419 */ 00420 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \ 00421 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1) 00422 00423 /** 00424 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y 00425 * @param __STREAM_INSTANCE__ DMAx_Streamy 00426 * @retval LL_DMA_CHANNEL_y 00427 */ 00428 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \ 00429 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \ 00430 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \ 00431 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \ 00432 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \ 00433 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \ 00434 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \ 00435 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \ 00436 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \ 00437 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \ 00438 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \ 00439 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \ 00440 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \ 00441 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \ 00442 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \ 00443 LL_DMA_STREAM_7) 00444 00445 /** 00446 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy 00447 * @param __DMA_INSTANCE__ DMAx 00448 * @param __STREAM__ LL_DMA_STREAM_y 00449 * @retval DMAx_Streamy 00450 */ 00451 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \ 00452 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \ 00453 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \ 00454 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \ 00455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \ 00456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \ 00457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \ 00458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \ 00459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \ 00460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \ 00461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \ 00462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \ 00463 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \ 00464 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \ 00465 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \ 00466 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \ 00467 DMA2_Stream7) 00468 00469 /** 00470 * @} 00471 */ 00472 00473 /** 00474 * @} 00475 */ 00476 00477 00478 /* Exported functions --------------------------------------------------------*/ 00479 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions 00480 * @{ 00481 */ 00482 00483 /** @defgroup DMA_LL_EF_Configuration Configuration 00484 * @{ 00485 */ 00486 /** 00487 * @brief Enable DMA stream. 00488 * @rmtoll CR EN LL_DMA_EnableStream 00489 * @param DMAx DMAx Instance 00490 * @param Stream This parameter can be one of the following values: 00491 * @arg @ref LL_DMA_STREAM_0 00492 * @arg @ref LL_DMA_STREAM_1 00493 * @arg @ref LL_DMA_STREAM_2 00494 * @arg @ref LL_DMA_STREAM_3 00495 * @arg @ref LL_DMA_STREAM_4 00496 * @arg @ref LL_DMA_STREAM_5 00497 * @arg @ref LL_DMA_STREAM_6 00498 * @arg @ref LL_DMA_STREAM_7 00499 * @retval None 00500 */ 00501 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream) 00502 { 00503 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); 00504 } 00505 00506 /** 00507 * @brief Disable DMA stream. 00508 * @rmtoll CR EN LL_DMA_DisableStream 00509 * @param DMAx DMAx Instance 00510 * @param Stream This parameter can be one of the following values: 00511 * @arg @ref LL_DMA_STREAM_0 00512 * @arg @ref LL_DMA_STREAM_1 00513 * @arg @ref LL_DMA_STREAM_2 00514 * @arg @ref LL_DMA_STREAM_3 00515 * @arg @ref LL_DMA_STREAM_4 00516 * @arg @ref LL_DMA_STREAM_5 00517 * @arg @ref LL_DMA_STREAM_6 00518 * @arg @ref LL_DMA_STREAM_7 00519 * @retval None 00520 */ 00521 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream) 00522 { 00523 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN); 00524 } 00525 00526 /** 00527 * @brief Check if DMA stream is enabled or disabled. 00528 * @rmtoll CR EN LL_DMA_IsEnabledStream 00529 * @param DMAx DMAx Instance 00530 * @param Stream This parameter can be one of the following values: 00531 * @arg @ref LL_DMA_STREAM_0 00532 * @arg @ref LL_DMA_STREAM_1 00533 * @arg @ref LL_DMA_STREAM_2 00534 * @arg @ref LL_DMA_STREAM_3 00535 * @arg @ref LL_DMA_STREAM_4 00536 * @arg @ref LL_DMA_STREAM_5 00537 * @arg @ref LL_DMA_STREAM_6 00538 * @arg @ref LL_DMA_STREAM_7 00539 * @retval State of bit (1 or 0). 00540 */ 00541 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream) 00542 { 00543 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)); 00544 } 00545 00546 /** 00547 * @brief Configure all parameters linked to DMA transfer. 00548 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n 00549 * CR CIRC LL_DMA_ConfigTransfer\n 00550 * CR PINC LL_DMA_ConfigTransfer\n 00551 * CR MINC LL_DMA_ConfigTransfer\n 00552 * CR PSIZE LL_DMA_ConfigTransfer\n 00553 * CR MSIZE LL_DMA_ConfigTransfer\n 00554 * CR PL LL_DMA_ConfigTransfer\n 00555 * CR PFCTRL LL_DMA_ConfigTransfer 00556 * @param DMAx DMAx Instance 00557 * @param Stream This parameter can be one of the following values: 00558 * @arg @ref LL_DMA_STREAM_0 00559 * @arg @ref LL_DMA_STREAM_1 00560 * @arg @ref LL_DMA_STREAM_2 00561 * @arg @ref LL_DMA_STREAM_3 00562 * @arg @ref LL_DMA_STREAM_4 00563 * @arg @ref LL_DMA_STREAM_5 00564 * @arg @ref LL_DMA_STREAM_6 00565 * @arg @ref LL_DMA_STREAM_7 00566 * @param Configuration This parameter must be a combination of all the following values: 00567 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00568 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL 00569 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT 00570 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT 00571 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD 00572 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD 00573 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH 00574 *@retval None 00575 */ 00576 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration) 00577 { 00578 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, 00579 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL, 00580 Configuration); 00581 } 00582 00583 /** 00584 * @brief Set Data transfer direction (read from peripheral or from memory). 00585 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection 00586 * @param DMAx DMAx Instance 00587 * @param Stream This parameter can be one of the following values: 00588 * @arg @ref LL_DMA_STREAM_0 00589 * @arg @ref LL_DMA_STREAM_1 00590 * @arg @ref LL_DMA_STREAM_2 00591 * @arg @ref LL_DMA_STREAM_3 00592 * @arg @ref LL_DMA_STREAM_4 00593 * @arg @ref LL_DMA_STREAM_5 00594 * @arg @ref LL_DMA_STREAM_6 00595 * @arg @ref LL_DMA_STREAM_7 00596 * @param Direction This parameter can be one of the following values: 00597 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00598 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00599 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00600 * @retval None 00601 */ 00602 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction) 00603 { 00604 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction); 00605 } 00606 00607 /** 00608 * @brief Get Data transfer direction (read from peripheral or from memory). 00609 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection 00610 * @param DMAx DMAx Instance 00611 * @param Stream This parameter can be one of the following values: 00612 * @arg @ref LL_DMA_STREAM_0 00613 * @arg @ref LL_DMA_STREAM_1 00614 * @arg @ref LL_DMA_STREAM_2 00615 * @arg @ref LL_DMA_STREAM_3 00616 * @arg @ref LL_DMA_STREAM_4 00617 * @arg @ref LL_DMA_STREAM_5 00618 * @arg @ref LL_DMA_STREAM_6 00619 * @arg @ref LL_DMA_STREAM_7 00620 * @retval Returned value can be one of the following values: 00621 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 00622 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 00623 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 00624 */ 00625 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream) 00626 { 00627 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR)); 00628 } 00629 00630 /** 00631 * @brief Set DMA mode normal, circular or peripheral flow control. 00632 * @rmtoll CR CIRC LL_DMA_SetMode\n 00633 * CR PFCTRL LL_DMA_SetMode 00634 * @param DMAx DMAx Instance 00635 * @param Stream This parameter can be one of the following values: 00636 * @arg @ref LL_DMA_STREAM_0 00637 * @arg @ref LL_DMA_STREAM_1 00638 * @arg @ref LL_DMA_STREAM_2 00639 * @arg @ref LL_DMA_STREAM_3 00640 * @arg @ref LL_DMA_STREAM_4 00641 * @arg @ref LL_DMA_STREAM_5 00642 * @arg @ref LL_DMA_STREAM_6 00643 * @arg @ref LL_DMA_STREAM_7 00644 * @param Mode This parameter can be one of the following values: 00645 * @arg @ref LL_DMA_MODE_NORMAL 00646 * @arg @ref LL_DMA_MODE_CIRCULAR 00647 * @arg @ref LL_DMA_MODE_PFCTRL 00648 * @retval None 00649 */ 00650 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode) 00651 { 00652 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode); 00653 } 00654 00655 /** 00656 * @brief Get DMA mode normal, circular or peripheral flow control. 00657 * @rmtoll CR CIRC LL_DMA_GetMode\n 00658 * CR PFCTRL LL_DMA_GetMode 00659 * @param DMAx DMAx Instance 00660 * @param Stream This parameter can be one of the following values: 00661 * @arg @ref LL_DMA_STREAM_0 00662 * @arg @ref LL_DMA_STREAM_1 00663 * @arg @ref LL_DMA_STREAM_2 00664 * @arg @ref LL_DMA_STREAM_3 00665 * @arg @ref LL_DMA_STREAM_4 00666 * @arg @ref LL_DMA_STREAM_5 00667 * @arg @ref LL_DMA_STREAM_6 00668 * @arg @ref LL_DMA_STREAM_7 00669 * @retval Returned value can be one of the following values: 00670 * @arg @ref LL_DMA_MODE_NORMAL 00671 * @arg @ref LL_DMA_MODE_CIRCULAR 00672 * @arg @ref LL_DMA_MODE_PFCTRL 00673 */ 00674 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream) 00675 { 00676 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL)); 00677 } 00678 00679 /** 00680 * @brief Set Peripheral increment mode. 00681 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode 00682 * @param DMAx DMAx Instance 00683 * @param Stream This parameter can be one of the following values: 00684 * @arg @ref LL_DMA_STREAM_0 00685 * @arg @ref LL_DMA_STREAM_1 00686 * @arg @ref LL_DMA_STREAM_2 00687 * @arg @ref LL_DMA_STREAM_3 00688 * @arg @ref LL_DMA_STREAM_4 00689 * @arg @ref LL_DMA_STREAM_5 00690 * @arg @ref LL_DMA_STREAM_6 00691 * @arg @ref LL_DMA_STREAM_7 00692 * @param IncrementMode This parameter can be one of the following values: 00693 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00694 * @arg @ref LL_DMA_PERIPH_INCREMENT 00695 * @retval None 00696 */ 00697 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) 00698 { 00699 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode); 00700 } 00701 00702 /** 00703 * @brief Get Peripheral increment mode. 00704 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode 00705 * @param DMAx DMAx Instance 00706 * @param Stream This parameter can be one of the following values: 00707 * @arg @ref LL_DMA_STREAM_0 00708 * @arg @ref LL_DMA_STREAM_1 00709 * @arg @ref LL_DMA_STREAM_2 00710 * @arg @ref LL_DMA_STREAM_3 00711 * @arg @ref LL_DMA_STREAM_4 00712 * @arg @ref LL_DMA_STREAM_5 00713 * @arg @ref LL_DMA_STREAM_6 00714 * @arg @ref LL_DMA_STREAM_7 00715 * @retval Returned value can be one of the following values: 00716 * @arg @ref LL_DMA_PERIPH_NOINCREMENT 00717 * @arg @ref LL_DMA_PERIPH_INCREMENT 00718 */ 00719 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 00720 { 00721 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC)); 00722 } 00723 00724 /** 00725 * @brief Set Memory increment mode. 00726 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode 00727 * @param DMAx DMAx Instance 00728 * @param Stream This parameter can be one of the following values: 00729 * @arg @ref LL_DMA_STREAM_0 00730 * @arg @ref LL_DMA_STREAM_1 00731 * @arg @ref LL_DMA_STREAM_2 00732 * @arg @ref LL_DMA_STREAM_3 00733 * @arg @ref LL_DMA_STREAM_4 00734 * @arg @ref LL_DMA_STREAM_5 00735 * @arg @ref LL_DMA_STREAM_6 00736 * @arg @ref LL_DMA_STREAM_7 00737 * @param IncrementMode This parameter can be one of the following values: 00738 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00739 * @arg @ref LL_DMA_MEMORY_INCREMENT 00740 * @retval None 00741 */ 00742 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode) 00743 { 00744 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode); 00745 } 00746 00747 /** 00748 * @brief Get Memory increment mode. 00749 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode 00750 * @param DMAx DMAx Instance 00751 * @param Stream This parameter can be one of the following values: 00752 * @arg @ref LL_DMA_STREAM_0 00753 * @arg @ref LL_DMA_STREAM_1 00754 * @arg @ref LL_DMA_STREAM_2 00755 * @arg @ref LL_DMA_STREAM_3 00756 * @arg @ref LL_DMA_STREAM_4 00757 * @arg @ref LL_DMA_STREAM_5 00758 * @arg @ref LL_DMA_STREAM_6 00759 * @arg @ref LL_DMA_STREAM_7 00760 * @retval Returned value can be one of the following values: 00761 * @arg @ref LL_DMA_MEMORY_NOINCREMENT 00762 * @arg @ref LL_DMA_MEMORY_INCREMENT 00763 */ 00764 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream) 00765 { 00766 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC)); 00767 } 00768 00769 /** 00770 * @brief Set Peripheral size. 00771 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize 00772 * @param DMAx DMAx Instance 00773 * @param Stream This parameter can be one of the following values: 00774 * @arg @ref LL_DMA_STREAM_0 00775 * @arg @ref LL_DMA_STREAM_1 00776 * @arg @ref LL_DMA_STREAM_2 00777 * @arg @ref LL_DMA_STREAM_3 00778 * @arg @ref LL_DMA_STREAM_4 00779 * @arg @ref LL_DMA_STREAM_5 00780 * @arg @ref LL_DMA_STREAM_6 00781 * @arg @ref LL_DMA_STREAM_7 00782 * @param Size This parameter can be one of the following values: 00783 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00784 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00785 * @arg @ref LL_DMA_PDATAALIGN_WORD 00786 * @retval None 00787 */ 00788 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 00789 { 00790 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size); 00791 } 00792 00793 /** 00794 * @brief Get Peripheral size. 00795 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize 00796 * @param DMAx DMAx Instance 00797 * @param Stream This parameter can be one of the following values: 00798 * @arg @ref LL_DMA_STREAM_0 00799 * @arg @ref LL_DMA_STREAM_1 00800 * @arg @ref LL_DMA_STREAM_2 00801 * @arg @ref LL_DMA_STREAM_3 00802 * @arg @ref LL_DMA_STREAM_4 00803 * @arg @ref LL_DMA_STREAM_5 00804 * @arg @ref LL_DMA_STREAM_6 00805 * @arg @ref LL_DMA_STREAM_7 00806 * @retval Returned value can be one of the following values: 00807 * @arg @ref LL_DMA_PDATAALIGN_BYTE 00808 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD 00809 * @arg @ref LL_DMA_PDATAALIGN_WORD 00810 */ 00811 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream) 00812 { 00813 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE)); 00814 } 00815 00816 /** 00817 * @brief Set Memory size. 00818 * @rmtoll CR MSIZE LL_DMA_SetMemorySize 00819 * @param DMAx DMAx Instance 00820 * @param Stream This parameter can be one of the following values: 00821 * @arg @ref LL_DMA_STREAM_0 00822 * @arg @ref LL_DMA_STREAM_1 00823 * @arg @ref LL_DMA_STREAM_2 00824 * @arg @ref LL_DMA_STREAM_3 00825 * @arg @ref LL_DMA_STREAM_4 00826 * @arg @ref LL_DMA_STREAM_5 00827 * @arg @ref LL_DMA_STREAM_6 00828 * @arg @ref LL_DMA_STREAM_7 00829 * @param Size This parameter can be one of the following values: 00830 * @arg @ref LL_DMA_MDATAALIGN_BYTE 00831 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 00832 * @arg @ref LL_DMA_MDATAALIGN_WORD 00833 * @retval None 00834 */ 00835 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size) 00836 { 00837 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size); 00838 } 00839 00840 /** 00841 * @brief Get Memory size. 00842 * @rmtoll CR MSIZE LL_DMA_GetMemorySize 00843 * @param DMAx DMAx Instance 00844 * @param Stream This parameter can be one of the following values: 00845 * @arg @ref LL_DMA_STREAM_0 00846 * @arg @ref LL_DMA_STREAM_1 00847 * @arg @ref LL_DMA_STREAM_2 00848 * @arg @ref LL_DMA_STREAM_3 00849 * @arg @ref LL_DMA_STREAM_4 00850 * @arg @ref LL_DMA_STREAM_5 00851 * @arg @ref LL_DMA_STREAM_6 00852 * @arg @ref LL_DMA_STREAM_7 00853 * @retval Returned value can be one of the following values: 00854 * @arg @ref LL_DMA_MDATAALIGN_BYTE 00855 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD 00856 * @arg @ref LL_DMA_MDATAALIGN_WORD 00857 */ 00858 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream) 00859 { 00860 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE)); 00861 } 00862 00863 /** 00864 * @brief Set Peripheral increment offset size. 00865 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize 00866 * @param DMAx DMAx Instance 00867 * @param Stream This parameter can be one of the following values: 00868 * @arg @ref LL_DMA_STREAM_0 00869 * @arg @ref LL_DMA_STREAM_1 00870 * @arg @ref LL_DMA_STREAM_2 00871 * @arg @ref LL_DMA_STREAM_3 00872 * @arg @ref LL_DMA_STREAM_4 00873 * @arg @ref LL_DMA_STREAM_5 00874 * @arg @ref LL_DMA_STREAM_6 00875 * @arg @ref LL_DMA_STREAM_7 00876 * @param OffsetSize This parameter can be one of the following values: 00877 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 00878 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 00879 * @retval None 00880 */ 00881 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize) 00882 { 00883 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize); 00884 } 00885 00886 /** 00887 * @brief Get Peripheral increment offset size. 00888 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize 00889 * @param DMAx DMAx Instance 00890 * @param Stream This parameter can be one of the following values: 00891 * @arg @ref LL_DMA_STREAM_0 00892 * @arg @ref LL_DMA_STREAM_1 00893 * @arg @ref LL_DMA_STREAM_2 00894 * @arg @ref LL_DMA_STREAM_3 00895 * @arg @ref LL_DMA_STREAM_4 00896 * @arg @ref LL_DMA_STREAM_5 00897 * @arg @ref LL_DMA_STREAM_6 00898 * @arg @ref LL_DMA_STREAM_7 00899 * @retval Returned value can be one of the following values: 00900 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE 00901 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4 00902 */ 00903 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream) 00904 { 00905 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS)); 00906 } 00907 00908 /** 00909 * @brief Set Stream priority level. 00910 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel 00911 * @param DMAx DMAx Instance 00912 * @param Stream This parameter can be one of the following values: 00913 * @arg @ref LL_DMA_STREAM_0 00914 * @arg @ref LL_DMA_STREAM_1 00915 * @arg @ref LL_DMA_STREAM_2 00916 * @arg @ref LL_DMA_STREAM_3 00917 * @arg @ref LL_DMA_STREAM_4 00918 * @arg @ref LL_DMA_STREAM_5 00919 * @arg @ref LL_DMA_STREAM_6 00920 * @arg @ref LL_DMA_STREAM_7 00921 * @param Priority This parameter can be one of the following values: 00922 * @arg @ref LL_DMA_PRIORITY_LOW 00923 * @arg @ref LL_DMA_PRIORITY_MEDIUM 00924 * @arg @ref LL_DMA_PRIORITY_HIGH 00925 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 00926 * @retval None 00927 */ 00928 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority) 00929 { 00930 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority); 00931 } 00932 00933 /** 00934 * @brief Get Stream priority level. 00935 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel 00936 * @param DMAx DMAx Instance 00937 * @param Stream This parameter can be one of the following values: 00938 * @arg @ref LL_DMA_STREAM_0 00939 * @arg @ref LL_DMA_STREAM_1 00940 * @arg @ref LL_DMA_STREAM_2 00941 * @arg @ref LL_DMA_STREAM_3 00942 * @arg @ref LL_DMA_STREAM_4 00943 * @arg @ref LL_DMA_STREAM_5 00944 * @arg @ref LL_DMA_STREAM_6 00945 * @arg @ref LL_DMA_STREAM_7 00946 * @retval Returned value can be one of the following values: 00947 * @arg @ref LL_DMA_PRIORITY_LOW 00948 * @arg @ref LL_DMA_PRIORITY_MEDIUM 00949 * @arg @ref LL_DMA_PRIORITY_HIGH 00950 * @arg @ref LL_DMA_PRIORITY_VERYHIGH 00951 */ 00952 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream) 00953 { 00954 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL)); 00955 } 00956 00957 /** 00958 * @brief Set Number of data to transfer. 00959 * @rmtoll NDTR NDT LL_DMA_SetDataLength 00960 * @note This action has no effect if 00961 * stream is enabled. 00962 * @param DMAx DMAx Instance 00963 * @param Stream This parameter can be one of the following values: 00964 * @arg @ref LL_DMA_STREAM_0 00965 * @arg @ref LL_DMA_STREAM_1 00966 * @arg @ref LL_DMA_STREAM_2 00967 * @arg @ref LL_DMA_STREAM_3 00968 * @arg @ref LL_DMA_STREAM_4 00969 * @arg @ref LL_DMA_STREAM_5 00970 * @arg @ref LL_DMA_STREAM_6 00971 * @arg @ref LL_DMA_STREAM_7 00972 * @param NbData Between 0 to 0xFFFFFFFF 00973 * @retval None 00974 */ 00975 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData) 00976 { 00977 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData); 00978 } 00979 00980 /** 00981 * @brief Get Number of data to transfer. 00982 * @rmtoll NDTR NDT LL_DMA_GetDataLength 00983 * @note Once the stream is enabled, the return value indicate the 00984 * remaining bytes to be transmitted. 00985 * @param DMAx DMAx Instance 00986 * @param Stream This parameter can be one of the following values: 00987 * @arg @ref LL_DMA_STREAM_0 00988 * @arg @ref LL_DMA_STREAM_1 00989 * @arg @ref LL_DMA_STREAM_2 00990 * @arg @ref LL_DMA_STREAM_3 00991 * @arg @ref LL_DMA_STREAM_4 00992 * @arg @ref LL_DMA_STREAM_5 00993 * @arg @ref LL_DMA_STREAM_6 00994 * @arg @ref LL_DMA_STREAM_7 00995 * @retval Between 0 to 0xFFFFFFFF 00996 */ 00997 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream) 00998 { 00999 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT)); 01000 } 01001 01002 /** 01003 * @brief Select Channel number associated to the Stream. 01004 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection 01005 * @param DMAx DMAx Instance 01006 * @param Stream This parameter can be one of the following values: 01007 * @arg @ref LL_DMA_STREAM_0 01008 * @arg @ref LL_DMA_STREAM_1 01009 * @arg @ref LL_DMA_STREAM_2 01010 * @arg @ref LL_DMA_STREAM_3 01011 * @arg @ref LL_DMA_STREAM_4 01012 * @arg @ref LL_DMA_STREAM_5 01013 * @arg @ref LL_DMA_STREAM_6 01014 * @arg @ref LL_DMA_STREAM_7 01015 * @param Channel This parameter can be one of the following values: 01016 * @arg @ref LL_DMA_CHANNEL_0 01017 * @arg @ref LL_DMA_CHANNEL_1 01018 * @arg @ref LL_DMA_CHANNEL_2 01019 * @arg @ref LL_DMA_CHANNEL_3 01020 * @arg @ref LL_DMA_CHANNEL_4 01021 * @arg @ref LL_DMA_CHANNEL_5 01022 * @arg @ref LL_DMA_CHANNEL_6 01023 * @arg @ref LL_DMA_CHANNEL_7 01024 * @retval None 01025 */ 01026 __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel) 01027 { 01028 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel); 01029 } 01030 01031 /** 01032 * @brief Get the Channel number associated to the Stream. 01033 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection 01034 * @param DMAx DMAx Instance 01035 * @param Stream This parameter can be one of the following values: 01036 * @arg @ref LL_DMA_STREAM_0 01037 * @arg @ref LL_DMA_STREAM_1 01038 * @arg @ref LL_DMA_STREAM_2 01039 * @arg @ref LL_DMA_STREAM_3 01040 * @arg @ref LL_DMA_STREAM_4 01041 * @arg @ref LL_DMA_STREAM_5 01042 * @arg @ref LL_DMA_STREAM_6 01043 * @arg @ref LL_DMA_STREAM_7 01044 * @retval Returned value can be one of the following values: 01045 * @arg @ref LL_DMA_CHANNEL_0 01046 * @arg @ref LL_DMA_CHANNEL_1 01047 * @arg @ref LL_DMA_CHANNEL_2 01048 * @arg @ref LL_DMA_CHANNEL_3 01049 * @arg @ref LL_DMA_CHANNEL_4 01050 * @arg @ref LL_DMA_CHANNEL_5 01051 * @arg @ref LL_DMA_CHANNEL_6 01052 * @arg @ref LL_DMA_CHANNEL_7 01053 */ 01054 __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream) 01055 { 01056 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL)); 01057 } 01058 01059 /** 01060 * @brief Set Memory burst transfer configuration. 01061 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer 01062 * @param DMAx DMAx Instance 01063 * @param Stream This parameter can be one of the following values: 01064 * @arg @ref LL_DMA_STREAM_0 01065 * @arg @ref LL_DMA_STREAM_1 01066 * @arg @ref LL_DMA_STREAM_2 01067 * @arg @ref LL_DMA_STREAM_3 01068 * @arg @ref LL_DMA_STREAM_4 01069 * @arg @ref LL_DMA_STREAM_5 01070 * @arg @ref LL_DMA_STREAM_6 01071 * @arg @ref LL_DMA_STREAM_7 01072 * @param Mburst This parameter can be one of the following values: 01073 * @arg @ref LL_DMA_MBURST_SINGLE 01074 * @arg @ref LL_DMA_MBURST_INC4 01075 * @arg @ref LL_DMA_MBURST_INC8 01076 * @arg @ref LL_DMA_MBURST_INC16 01077 * @retval None 01078 */ 01079 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst) 01080 { 01081 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst); 01082 } 01083 01084 /** 01085 * @brief Get Memory burst transfer configuration. 01086 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer 01087 * @param DMAx DMAx Instance 01088 * @param Stream This parameter can be one of the following values: 01089 * @arg @ref LL_DMA_STREAM_0 01090 * @arg @ref LL_DMA_STREAM_1 01091 * @arg @ref LL_DMA_STREAM_2 01092 * @arg @ref LL_DMA_STREAM_3 01093 * @arg @ref LL_DMA_STREAM_4 01094 * @arg @ref LL_DMA_STREAM_5 01095 * @arg @ref LL_DMA_STREAM_6 01096 * @arg @ref LL_DMA_STREAM_7 01097 * @retval Returned value can be one of the following values: 01098 * @arg @ref LL_DMA_MBURST_SINGLE 01099 * @arg @ref LL_DMA_MBURST_INC4 01100 * @arg @ref LL_DMA_MBURST_INC8 01101 * @arg @ref LL_DMA_MBURST_INC16 01102 */ 01103 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 01104 { 01105 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST)); 01106 } 01107 01108 /** 01109 * @brief Set Peripheral burst transfer configuration. 01110 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer 01111 * @param DMAx DMAx Instance 01112 * @param Stream This parameter can be one of the following values: 01113 * @arg @ref LL_DMA_STREAM_0 01114 * @arg @ref LL_DMA_STREAM_1 01115 * @arg @ref LL_DMA_STREAM_2 01116 * @arg @ref LL_DMA_STREAM_3 01117 * @arg @ref LL_DMA_STREAM_4 01118 * @arg @ref LL_DMA_STREAM_5 01119 * @arg @ref LL_DMA_STREAM_6 01120 * @arg @ref LL_DMA_STREAM_7 01121 * @param Pburst This parameter can be one of the following values: 01122 * @arg @ref LL_DMA_PBURST_SINGLE 01123 * @arg @ref LL_DMA_PBURST_INC4 01124 * @arg @ref LL_DMA_PBURST_INC8 01125 * @arg @ref LL_DMA_PBURST_INC16 01126 * @retval None 01127 */ 01128 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst) 01129 { 01130 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst); 01131 } 01132 01133 /** 01134 * @brief Get Peripheral burst transfer configuration. 01135 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer 01136 * @param DMAx DMAx Instance 01137 * @param Stream This parameter can be one of the following values: 01138 * @arg @ref LL_DMA_STREAM_0 01139 * @arg @ref LL_DMA_STREAM_1 01140 * @arg @ref LL_DMA_STREAM_2 01141 * @arg @ref LL_DMA_STREAM_3 01142 * @arg @ref LL_DMA_STREAM_4 01143 * @arg @ref LL_DMA_STREAM_5 01144 * @arg @ref LL_DMA_STREAM_6 01145 * @arg @ref LL_DMA_STREAM_7 01146 * @retval Returned value can be one of the following values: 01147 * @arg @ref LL_DMA_PBURST_SINGLE 01148 * @arg @ref LL_DMA_PBURST_INC4 01149 * @arg @ref LL_DMA_PBURST_INC8 01150 * @arg @ref LL_DMA_PBURST_INC16 01151 */ 01152 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream) 01153 { 01154 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST)); 01155 } 01156 01157 /** 01158 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 01159 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem 01160 * @param DMAx DMAx Instance 01161 * @param Stream This parameter can be one of the following values: 01162 * @arg @ref LL_DMA_STREAM_0 01163 * @arg @ref LL_DMA_STREAM_1 01164 * @arg @ref LL_DMA_STREAM_2 01165 * @arg @ref LL_DMA_STREAM_3 01166 * @arg @ref LL_DMA_STREAM_4 01167 * @arg @ref LL_DMA_STREAM_5 01168 * @arg @ref LL_DMA_STREAM_6 01169 * @arg @ref LL_DMA_STREAM_7 01170 * @param CurrentMemory This parameter can be one of the following values: 01171 * @arg @ref LL_DMA_CURRENTTARGETMEM0 01172 * @arg @ref LL_DMA_CURRENTTARGETMEM1 01173 * @retval None 01174 */ 01175 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory) 01176 { 01177 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory); 01178 } 01179 01180 /** 01181 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0. 01182 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem 01183 * @param DMAx DMAx Instance 01184 * @param Stream This parameter can be one of the following values: 01185 * @arg @ref LL_DMA_STREAM_0 01186 * @arg @ref LL_DMA_STREAM_1 01187 * @arg @ref LL_DMA_STREAM_2 01188 * @arg @ref LL_DMA_STREAM_3 01189 * @arg @ref LL_DMA_STREAM_4 01190 * @arg @ref LL_DMA_STREAM_5 01191 * @arg @ref LL_DMA_STREAM_6 01192 * @arg @ref LL_DMA_STREAM_7 01193 * @retval Returned value can be one of the following values: 01194 * @arg @ref LL_DMA_CURRENTTARGETMEM0 01195 * @arg @ref LL_DMA_CURRENTTARGETMEM1 01196 */ 01197 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream) 01198 { 01199 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT)); 01200 } 01201 01202 /** 01203 * @brief Enable the double buffer mode. 01204 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode 01205 * @param DMAx DMAx Instance 01206 * @param Stream This parameter can be one of the following values: 01207 * @arg @ref LL_DMA_STREAM_0 01208 * @arg @ref LL_DMA_STREAM_1 01209 * @arg @ref LL_DMA_STREAM_2 01210 * @arg @ref LL_DMA_STREAM_3 01211 * @arg @ref LL_DMA_STREAM_4 01212 * @arg @ref LL_DMA_STREAM_5 01213 * @arg @ref LL_DMA_STREAM_6 01214 * @arg @ref LL_DMA_STREAM_7 01215 * @retval None 01216 */ 01217 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 01218 { 01219 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); 01220 } 01221 01222 /** 01223 * @brief Disable the double buffer mode. 01224 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode 01225 * @param DMAx DMAx Instance 01226 * @param Stream This parameter can be one of the following values: 01227 * @arg @ref LL_DMA_STREAM_0 01228 * @arg @ref LL_DMA_STREAM_1 01229 * @arg @ref LL_DMA_STREAM_2 01230 * @arg @ref LL_DMA_STREAM_3 01231 * @arg @ref LL_DMA_STREAM_4 01232 * @arg @ref LL_DMA_STREAM_5 01233 * @arg @ref LL_DMA_STREAM_6 01234 * @arg @ref LL_DMA_STREAM_7 01235 * @retval None 01236 */ 01237 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream) 01238 { 01239 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM); 01240 } 01241 01242 /** 01243 * @brief Get FIFO status. 01244 * @rmtoll FCR FS LL_DMA_GetFIFOStatus 01245 * @param DMAx DMAx Instance 01246 * @param Stream This parameter can be one of the following values: 01247 * @arg @ref LL_DMA_STREAM_0 01248 * @arg @ref LL_DMA_STREAM_1 01249 * @arg @ref LL_DMA_STREAM_2 01250 * @arg @ref LL_DMA_STREAM_3 01251 * @arg @ref LL_DMA_STREAM_4 01252 * @arg @ref LL_DMA_STREAM_5 01253 * @arg @ref LL_DMA_STREAM_6 01254 * @arg @ref LL_DMA_STREAM_7 01255 * @retval Returned value can be one of the following values: 01256 * @arg @ref LL_DMA_FIFOSTATUS_0_25 01257 * @arg @ref LL_DMA_FIFOSTATUS_25_50 01258 * @arg @ref LL_DMA_FIFOSTATUS_50_75 01259 * @arg @ref LL_DMA_FIFOSTATUS_75_100 01260 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY 01261 * @arg @ref LL_DMA_FIFOSTATUS_FULL 01262 */ 01263 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream) 01264 { 01265 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS)); 01266 } 01267 01268 /** 01269 * @brief Disable Fifo mode. 01270 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode 01271 * @param DMAx DMAx Instance 01272 * @param Stream This parameter can be one of the following values: 01273 * @arg @ref LL_DMA_STREAM_0 01274 * @arg @ref LL_DMA_STREAM_1 01275 * @arg @ref LL_DMA_STREAM_2 01276 * @arg @ref LL_DMA_STREAM_3 01277 * @arg @ref LL_DMA_STREAM_4 01278 * @arg @ref LL_DMA_STREAM_5 01279 * @arg @ref LL_DMA_STREAM_6 01280 * @arg @ref LL_DMA_STREAM_7 01281 * @retval None 01282 */ 01283 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 01284 { 01285 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); 01286 } 01287 01288 /** 01289 * @brief Enable Fifo mode. 01290 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode 01291 * @param DMAx DMAx Instance 01292 * @param Stream This parameter can be one of the following values: 01293 * @arg @ref LL_DMA_STREAM_0 01294 * @arg @ref LL_DMA_STREAM_1 01295 * @arg @ref LL_DMA_STREAM_2 01296 * @arg @ref LL_DMA_STREAM_3 01297 * @arg @ref LL_DMA_STREAM_4 01298 * @arg @ref LL_DMA_STREAM_5 01299 * @arg @ref LL_DMA_STREAM_6 01300 * @arg @ref LL_DMA_STREAM_7 01301 * @retval None 01302 */ 01303 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream) 01304 { 01305 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS); 01306 } 01307 01308 /** 01309 * @brief Select FIFO threshold. 01310 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold 01311 * @param DMAx DMAx Instance 01312 * @param Stream This parameter can be one of the following values: 01313 * @arg @ref LL_DMA_STREAM_0 01314 * @arg @ref LL_DMA_STREAM_1 01315 * @arg @ref LL_DMA_STREAM_2 01316 * @arg @ref LL_DMA_STREAM_3 01317 * @arg @ref LL_DMA_STREAM_4 01318 * @arg @ref LL_DMA_STREAM_5 01319 * @arg @ref LL_DMA_STREAM_6 01320 * @arg @ref LL_DMA_STREAM_7 01321 * @param Threshold This parameter can be one of the following values: 01322 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 01323 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 01324 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 01325 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 01326 * @retval None 01327 */ 01328 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold) 01329 { 01330 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold); 01331 } 01332 01333 /** 01334 * @brief Get FIFO threshold. 01335 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold 01336 * @param DMAx DMAx Instance 01337 * @param Stream This parameter can be one of the following values: 01338 * @arg @ref LL_DMA_STREAM_0 01339 * @arg @ref LL_DMA_STREAM_1 01340 * @arg @ref LL_DMA_STREAM_2 01341 * @arg @ref LL_DMA_STREAM_3 01342 * @arg @ref LL_DMA_STREAM_4 01343 * @arg @ref LL_DMA_STREAM_5 01344 * @arg @ref LL_DMA_STREAM_6 01345 * @arg @ref LL_DMA_STREAM_7 01346 * @retval Returned value can be one of the following values: 01347 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 01348 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 01349 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 01350 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 01351 */ 01352 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream) 01353 { 01354 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH)); 01355 } 01356 01357 /** 01358 * @brief Configure the FIFO . 01359 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n 01360 * FCR DMDIS LL_DMA_ConfigFifo 01361 * @param DMAx DMAx Instance 01362 * @param Stream This parameter can be one of the following values: 01363 * @arg @ref LL_DMA_STREAM_0 01364 * @arg @ref LL_DMA_STREAM_1 01365 * @arg @ref LL_DMA_STREAM_2 01366 * @arg @ref LL_DMA_STREAM_3 01367 * @arg @ref LL_DMA_STREAM_4 01368 * @arg @ref LL_DMA_STREAM_5 01369 * @arg @ref LL_DMA_STREAM_6 01370 * @arg @ref LL_DMA_STREAM_7 01371 * @param FifoMode This parameter can be one of the following values: 01372 * @arg @ref LL_DMA_FIFOMODE_ENABLE 01373 * @arg @ref LL_DMA_FIFOMODE_DISABLE 01374 * @param FifoThreshold This parameter can be one of the following values: 01375 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4 01376 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2 01377 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4 01378 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL 01379 * @retval None 01380 */ 01381 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold) 01382 { 01383 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold); 01384 } 01385 01386 /** 01387 * @brief Configure the Source and Destination addresses. 01388 * @note This API must not be called when the DMA stream is enabled. 01389 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n 01390 * PAR PA LL_DMA_ConfigAddresses 01391 * @param DMAx DMAx Instance 01392 * @param Stream This parameter can be one of the following values: 01393 * @arg @ref LL_DMA_STREAM_0 01394 * @arg @ref LL_DMA_STREAM_1 01395 * @arg @ref LL_DMA_STREAM_2 01396 * @arg @ref LL_DMA_STREAM_3 01397 * @arg @ref LL_DMA_STREAM_4 01398 * @arg @ref LL_DMA_STREAM_5 01399 * @arg @ref LL_DMA_STREAM_6 01400 * @arg @ref LL_DMA_STREAM_7 01401 * @param SrcAddress Between 0 to 0xFFFFFFFF 01402 * @param DstAddress Between 0 to 0xFFFFFFFF 01403 * @param Direction This parameter can be one of the following values: 01404 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY 01405 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH 01406 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY 01407 * @retval None 01408 */ 01409 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) 01410 { 01411 /* Direction Memory to Periph */ 01412 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) 01413 { 01414 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress); 01415 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress); 01416 } 01417 /* Direction Periph to Memory and Memory to Memory */ 01418 else 01419 { 01420 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress); 01421 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress); 01422 } 01423 } 01424 01425 /** 01426 * @brief Set the Memory address. 01427 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress 01428 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01429 * @note This API must not be called when the DMA channel is enabled. 01430 * @param DMAx DMAx Instance 01431 * @param Stream This parameter can be one of the following values: 01432 * @arg @ref LL_DMA_STREAM_0 01433 * @arg @ref LL_DMA_STREAM_1 01434 * @arg @ref LL_DMA_STREAM_2 01435 * @arg @ref LL_DMA_STREAM_3 01436 * @arg @ref LL_DMA_STREAM_4 01437 * @arg @ref LL_DMA_STREAM_5 01438 * @arg @ref LL_DMA_STREAM_6 01439 * @arg @ref LL_DMA_STREAM_7 01440 * @param MemoryAddress Between 0 to 0xFFFFFFFF 01441 * @retval None 01442 */ 01443 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) 01444 { 01445 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); 01446 } 01447 01448 /** 01449 * @brief Set the Peripheral address. 01450 * @rmtoll PAR PA LL_DMA_SetPeriphAddress 01451 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01452 * @note This API must not be called when the DMA channel is enabled. 01453 * @param DMAx DMAx Instance 01454 * @param Stream This parameter can be one of the following values: 01455 * @arg @ref LL_DMA_STREAM_0 01456 * @arg @ref LL_DMA_STREAM_1 01457 * @arg @ref LL_DMA_STREAM_2 01458 * @arg @ref LL_DMA_STREAM_3 01459 * @arg @ref LL_DMA_STREAM_4 01460 * @arg @ref LL_DMA_STREAM_5 01461 * @arg @ref LL_DMA_STREAM_6 01462 * @arg @ref LL_DMA_STREAM_7 01463 * @param PeriphAddress Between 0 to 0xFFFFFFFF 01464 * @retval None 01465 */ 01466 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress) 01467 { 01468 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress); 01469 } 01470 01471 /** 01472 * @brief Get the Memory address. 01473 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress 01474 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01475 * @param DMAx DMAx Instance 01476 * @param Stream This parameter can be one of the following values: 01477 * @arg @ref LL_DMA_STREAM_0 01478 * @arg @ref LL_DMA_STREAM_1 01479 * @arg @ref LL_DMA_STREAM_2 01480 * @arg @ref LL_DMA_STREAM_3 01481 * @arg @ref LL_DMA_STREAM_4 01482 * @arg @ref LL_DMA_STREAM_5 01483 * @arg @ref LL_DMA_STREAM_6 01484 * @arg @ref LL_DMA_STREAM_7 01485 * @retval Between 0 to 0xFFFFFFFF 01486 */ 01487 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream) 01488 { 01489 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); 01490 } 01491 01492 /** 01493 * @brief Get the Peripheral address. 01494 * @rmtoll PAR PA LL_DMA_GetPeriphAddress 01495 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. 01496 * @param DMAx DMAx Instance 01497 * @param Stream This parameter can be one of the following values: 01498 * @arg @ref LL_DMA_STREAM_0 01499 * @arg @ref LL_DMA_STREAM_1 01500 * @arg @ref LL_DMA_STREAM_2 01501 * @arg @ref LL_DMA_STREAM_3 01502 * @arg @ref LL_DMA_STREAM_4 01503 * @arg @ref LL_DMA_STREAM_5 01504 * @arg @ref LL_DMA_STREAM_6 01505 * @arg @ref LL_DMA_STREAM_7 01506 * @retval Between 0 to 0xFFFFFFFF 01507 */ 01508 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream) 01509 { 01510 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); 01511 } 01512 01513 /** 01514 * @brief Set the Memory to Memory Source address. 01515 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress 01516 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01517 * @note This API must not be called when the DMA channel is enabled. 01518 * @param DMAx DMAx Instance 01519 * @param Stream This parameter can be one of the following values: 01520 * @arg @ref LL_DMA_STREAM_0 01521 * @arg @ref LL_DMA_STREAM_1 01522 * @arg @ref LL_DMA_STREAM_2 01523 * @arg @ref LL_DMA_STREAM_3 01524 * @arg @ref LL_DMA_STREAM_4 01525 * @arg @ref LL_DMA_STREAM_5 01526 * @arg @ref LL_DMA_STREAM_6 01527 * @arg @ref LL_DMA_STREAM_7 01528 * @param MemoryAddress Between 0 to 0xFFFFFFFF 01529 * @retval None 01530 */ 01531 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) 01532 { 01533 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress); 01534 } 01535 01536 /** 01537 * @brief Set the Memory to Memory Destination address. 01538 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress 01539 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01540 * @note This API must not be called when the DMA channel is enabled. 01541 * @param DMAx DMAx Instance 01542 * @param Stream This parameter can be one of the following values: 01543 * @arg @ref LL_DMA_STREAM_0 01544 * @arg @ref LL_DMA_STREAM_1 01545 * @arg @ref LL_DMA_STREAM_2 01546 * @arg @ref LL_DMA_STREAM_3 01547 * @arg @ref LL_DMA_STREAM_4 01548 * @arg @ref LL_DMA_STREAM_5 01549 * @arg @ref LL_DMA_STREAM_6 01550 * @arg @ref LL_DMA_STREAM_7 01551 * @param MemoryAddress Between 0 to 0xFFFFFFFF 01552 * @retval None 01553 */ 01554 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress) 01555 { 01556 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress); 01557 } 01558 01559 /** 01560 * @brief Get the Memory to Memory Source address. 01561 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress 01562 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01563 * @param DMAx DMAx Instance 01564 * @param Stream This parameter can be one of the following values: 01565 * @arg @ref LL_DMA_STREAM_0 01566 * @arg @ref LL_DMA_STREAM_1 01567 * @arg @ref LL_DMA_STREAM_2 01568 * @arg @ref LL_DMA_STREAM_3 01569 * @arg @ref LL_DMA_STREAM_4 01570 * @arg @ref LL_DMA_STREAM_5 01571 * @arg @ref LL_DMA_STREAM_6 01572 * @arg @ref LL_DMA_STREAM_7 01573 * @retval Between 0 to 0xFFFFFFFF 01574 */ 01575 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream) 01576 { 01577 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR)); 01578 } 01579 01580 /** 01581 * @brief Get the Memory to Memory Destination address. 01582 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress 01583 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. 01584 * @param DMAx DMAx Instance 01585 * @param Stream This parameter can be one of the following values: 01586 * @arg @ref LL_DMA_STREAM_0 01587 * @arg @ref LL_DMA_STREAM_1 01588 * @arg @ref LL_DMA_STREAM_2 01589 * @arg @ref LL_DMA_STREAM_3 01590 * @arg @ref LL_DMA_STREAM_4 01591 * @arg @ref LL_DMA_STREAM_5 01592 * @arg @ref LL_DMA_STREAM_6 01593 * @arg @ref LL_DMA_STREAM_7 01594 * @retval Between 0 to 0xFFFFFFFF 01595 */ 01596 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream) 01597 { 01598 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR)); 01599 } 01600 01601 /** 01602 * @brief Set Memory 1 address (used in case of Double buffer mode). 01603 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address 01604 * @param DMAx DMAx Instance 01605 * @param Stream This parameter can be one of the following values: 01606 * @arg @ref LL_DMA_STREAM_0 01607 * @arg @ref LL_DMA_STREAM_1 01608 * @arg @ref LL_DMA_STREAM_2 01609 * @arg @ref LL_DMA_STREAM_3 01610 * @arg @ref LL_DMA_STREAM_4 01611 * @arg @ref LL_DMA_STREAM_5 01612 * @arg @ref LL_DMA_STREAM_6 01613 * @arg @ref LL_DMA_STREAM_7 01614 * @param Address Between 0 to 0xFFFFFFFF 01615 * @retval None 01616 */ 01617 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address) 01618 { 01619 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address); 01620 } 01621 01622 /** 01623 * @brief Get Memory 1 address (used in case of Double buffer mode). 01624 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address 01625 * @param DMAx DMAx Instance 01626 * @param Stream This parameter can be one of the following values: 01627 * @arg @ref LL_DMA_STREAM_0 01628 * @arg @ref LL_DMA_STREAM_1 01629 * @arg @ref LL_DMA_STREAM_2 01630 * @arg @ref LL_DMA_STREAM_3 01631 * @arg @ref LL_DMA_STREAM_4 01632 * @arg @ref LL_DMA_STREAM_5 01633 * @arg @ref LL_DMA_STREAM_6 01634 * @arg @ref LL_DMA_STREAM_7 01635 * @retval Between 0 to 0xFFFFFFFF 01636 */ 01637 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream) 01638 { 01639 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR); 01640 } 01641 01642 /** 01643 * @} 01644 */ 01645 01646 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management 01647 * @{ 01648 */ 01649 01650 /** 01651 * @brief Get Stream 0 half transfer flag. 01652 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0 01653 * @param DMAx DMAx Instance 01654 * @retval State of bit (1 or 0). 01655 */ 01656 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx) 01657 { 01658 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0)); 01659 } 01660 01661 /** 01662 * @brief Get Stream 1 half transfer flag. 01663 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1 01664 * @param DMAx DMAx Instance 01665 * @retval State of bit (1 or 0). 01666 */ 01667 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) 01668 { 01669 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1)); 01670 } 01671 01672 /** 01673 * @brief Get Stream 2 half transfer flag. 01674 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2 01675 * @param DMAx DMAx Instance 01676 * @retval State of bit (1 or 0). 01677 */ 01678 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) 01679 { 01680 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2)); 01681 } 01682 01683 /** 01684 * @brief Get Stream 3 half transfer flag. 01685 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3 01686 * @param DMAx DMAx Instance 01687 * @retval State of bit (1 or 0). 01688 */ 01689 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) 01690 { 01691 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3)); 01692 } 01693 01694 /** 01695 * @brief Get Stream 4 half transfer flag. 01696 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4 01697 * @param DMAx DMAx Instance 01698 * @retval State of bit (1 or 0). 01699 */ 01700 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) 01701 { 01702 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4)); 01703 } 01704 01705 /** 01706 * @brief Get Stream 5 half transfer flag. 01707 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5 01708 * @param DMAx DMAx Instance 01709 * @retval State of bit (1 or 0). 01710 */ 01711 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) 01712 { 01713 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5)); 01714 } 01715 01716 /** 01717 * @brief Get Stream 6 half transfer flag. 01718 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6 01719 * @param DMAx DMAx Instance 01720 * @retval State of bit (1 or 0). 01721 */ 01722 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) 01723 { 01724 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6)); 01725 } 01726 01727 /** 01728 * @brief Get Stream 7 half transfer flag. 01729 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7 01730 * @param DMAx DMAx Instance 01731 * @retval State of bit (1 or 0). 01732 */ 01733 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) 01734 { 01735 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7)); 01736 } 01737 01738 /** 01739 * @brief Get Stream 0 transfer complete flag. 01740 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0 01741 * @param DMAx DMAx Instance 01742 * @retval State of bit (1 or 0). 01743 */ 01744 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx) 01745 { 01746 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0)); 01747 } 01748 01749 /** 01750 * @brief Get Stream 1 transfer complete flag. 01751 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1 01752 * @param DMAx DMAx Instance 01753 * @retval State of bit (1 or 0). 01754 */ 01755 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) 01756 { 01757 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1)); 01758 } 01759 01760 /** 01761 * @brief Get Stream 2 transfer complete flag. 01762 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2 01763 * @param DMAx DMAx Instance 01764 * @retval State of bit (1 or 0). 01765 */ 01766 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) 01767 { 01768 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2)); 01769 } 01770 01771 /** 01772 * @brief Get Stream 3 transfer complete flag. 01773 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3 01774 * @param DMAx DMAx Instance 01775 * @retval State of bit (1 or 0). 01776 */ 01777 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) 01778 { 01779 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3)); 01780 } 01781 01782 /** 01783 * @brief Get Stream 4 transfer complete flag. 01784 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4 01785 * @param DMAx DMAx Instance 01786 * @retval State of bit (1 or 0). 01787 */ 01788 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) 01789 { 01790 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4)); 01791 } 01792 01793 /** 01794 * @brief Get Stream 5 transfer complete flag. 01795 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5 01796 * @param DMAx DMAx Instance 01797 * @retval State of bit (1 or 0). 01798 */ 01799 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) 01800 { 01801 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5)); 01802 } 01803 01804 /** 01805 * @brief Get Stream 6 transfer complete flag. 01806 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6 01807 * @param DMAx DMAx Instance 01808 * @retval State of bit (1 or 0). 01809 */ 01810 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) 01811 { 01812 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6)); 01813 } 01814 01815 /** 01816 * @brief Get Stream 7 transfer complete flag. 01817 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7 01818 * @param DMAx DMAx Instance 01819 * @retval State of bit (1 or 0). 01820 */ 01821 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) 01822 { 01823 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7)); 01824 } 01825 01826 /** 01827 * @brief Get Stream 0 transfer error flag. 01828 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0 01829 * @param DMAx DMAx Instance 01830 * @retval State of bit (1 or 0). 01831 */ 01832 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx) 01833 { 01834 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0)); 01835 } 01836 01837 /** 01838 * @brief Get Stream 1 transfer error flag. 01839 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1 01840 * @param DMAx DMAx Instance 01841 * @retval State of bit (1 or 0). 01842 */ 01843 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) 01844 { 01845 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1)); 01846 } 01847 01848 /** 01849 * @brief Get Stream 2 transfer error flag. 01850 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2 01851 * @param DMAx DMAx Instance 01852 * @retval State of bit (1 or 0). 01853 */ 01854 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) 01855 { 01856 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2)); 01857 } 01858 01859 /** 01860 * @brief Get Stream 3 transfer error flag. 01861 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3 01862 * @param DMAx DMAx Instance 01863 * @retval State of bit (1 or 0). 01864 */ 01865 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) 01866 { 01867 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3)); 01868 } 01869 01870 /** 01871 * @brief Get Stream 4 transfer error flag. 01872 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4 01873 * @param DMAx DMAx Instance 01874 * @retval State of bit (1 or 0). 01875 */ 01876 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) 01877 { 01878 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4)); 01879 } 01880 01881 /** 01882 * @brief Get Stream 5 transfer error flag. 01883 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5 01884 * @param DMAx DMAx Instance 01885 * @retval State of bit (1 or 0). 01886 */ 01887 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) 01888 { 01889 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5)); 01890 } 01891 01892 /** 01893 * @brief Get Stream 6 transfer error flag. 01894 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6 01895 * @param DMAx DMAx Instance 01896 * @retval State of bit (1 or 0). 01897 */ 01898 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) 01899 { 01900 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6)); 01901 } 01902 01903 /** 01904 * @brief Get Stream 7 transfer error flag. 01905 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7 01906 * @param DMAx DMAx Instance 01907 * @retval State of bit (1 or 0). 01908 */ 01909 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) 01910 { 01911 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7)); 01912 } 01913 01914 /** 01915 * @brief Get Stream 0 direct mode error flag. 01916 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0 01917 * @param DMAx DMAx Instance 01918 * @retval State of bit (1 or 0). 01919 */ 01920 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx) 01921 { 01922 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0)); 01923 } 01924 01925 /** 01926 * @brief Get Stream 1 direct mode error flag. 01927 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1 01928 * @param DMAx DMAx Instance 01929 * @retval State of bit (1 or 0). 01930 */ 01931 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx) 01932 { 01933 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1)); 01934 } 01935 01936 /** 01937 * @brief Get Stream 2 direct mode error flag. 01938 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2 01939 * @param DMAx DMAx Instance 01940 * @retval State of bit (1 or 0). 01941 */ 01942 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx) 01943 { 01944 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2)); 01945 } 01946 01947 /** 01948 * @brief Get Stream 3 direct mode error flag. 01949 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3 01950 * @param DMAx DMAx Instance 01951 * @retval State of bit (1 or 0). 01952 */ 01953 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx) 01954 { 01955 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3)); 01956 } 01957 01958 /** 01959 * @brief Get Stream 4 direct mode error flag. 01960 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4 01961 * @param DMAx DMAx Instance 01962 * @retval State of bit (1 or 0). 01963 */ 01964 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx) 01965 { 01966 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4)); 01967 } 01968 01969 /** 01970 * @brief Get Stream 5 direct mode error flag. 01971 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5 01972 * @param DMAx DMAx Instance 01973 * @retval State of bit (1 or 0). 01974 */ 01975 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx) 01976 { 01977 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5)); 01978 } 01979 01980 /** 01981 * @brief Get Stream 6 direct mode error flag. 01982 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6 01983 * @param DMAx DMAx Instance 01984 * @retval State of bit (1 or 0). 01985 */ 01986 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx) 01987 { 01988 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6)); 01989 } 01990 01991 /** 01992 * @brief Get Stream 7 direct mode error flag. 01993 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7 01994 * @param DMAx DMAx Instance 01995 * @retval State of bit (1 or 0). 01996 */ 01997 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx) 01998 { 01999 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7)); 02000 } 02001 02002 /** 02003 * @brief Get Stream 0 FIFO error flag. 02004 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0 02005 * @param DMAx DMAx Instance 02006 * @retval State of bit (1 or 0). 02007 */ 02008 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx) 02009 { 02010 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0)); 02011 } 02012 02013 /** 02014 * @brief Get Stream 1 FIFO error flag. 02015 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1 02016 * @param DMAx DMAx Instance 02017 * @retval State of bit (1 or 0). 02018 */ 02019 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx) 02020 { 02021 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1)); 02022 } 02023 02024 /** 02025 * @brief Get Stream 2 FIFO error flag. 02026 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2 02027 * @param DMAx DMAx Instance 02028 * @retval State of bit (1 or 0). 02029 */ 02030 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx) 02031 { 02032 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2)); 02033 } 02034 02035 /** 02036 * @brief Get Stream 3 FIFO error flag. 02037 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3 02038 * @param DMAx DMAx Instance 02039 * @retval State of bit (1 or 0). 02040 */ 02041 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx) 02042 { 02043 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3)); 02044 } 02045 02046 /** 02047 * @brief Get Stream 4 FIFO error flag. 02048 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4 02049 * @param DMAx DMAx Instance 02050 * @retval State of bit (1 or 0). 02051 */ 02052 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx) 02053 { 02054 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4)); 02055 } 02056 02057 /** 02058 * @brief Get Stream 5 FIFO error flag. 02059 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5 02060 * @param DMAx DMAx Instance 02061 * @retval State of bit (1 or 0). 02062 */ 02063 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx) 02064 { 02065 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5)); 02066 } 02067 02068 /** 02069 * @brief Get Stream 6 FIFO error flag. 02070 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6 02071 * @param DMAx DMAx Instance 02072 * @retval State of bit (1 or 0). 02073 */ 02074 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx) 02075 { 02076 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6)); 02077 } 02078 02079 /** 02080 * @brief Get Stream 7 FIFO error flag. 02081 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7 02082 * @param DMAx DMAx Instance 02083 * @retval State of bit (1 or 0). 02084 */ 02085 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx) 02086 { 02087 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7)); 02088 } 02089 02090 /** 02091 * @brief Clear Stream 0 half transfer flag. 02092 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0 02093 * @param DMAx DMAx Instance 02094 * @retval None 02095 */ 02096 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx) 02097 { 02098 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0); 02099 } 02100 02101 /** 02102 * @brief Clear Stream 1 half transfer flag. 02103 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1 02104 * @param DMAx DMAx Instance 02105 * @retval None 02106 */ 02107 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) 02108 { 02109 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1); 02110 } 02111 02112 /** 02113 * @brief Clear Stream 2 half transfer flag. 02114 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2 02115 * @param DMAx DMAx Instance 02116 * @retval None 02117 */ 02118 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) 02119 { 02120 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2); 02121 } 02122 02123 /** 02124 * @brief Clear Stream 3 half transfer flag. 02125 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3 02126 * @param DMAx DMAx Instance 02127 * @retval None 02128 */ 02129 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) 02130 { 02131 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3); 02132 } 02133 02134 /** 02135 * @brief Clear Stream 4 half transfer flag. 02136 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4 02137 * @param DMAx DMAx Instance 02138 * @retval None 02139 */ 02140 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx) 02141 { 02142 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4); 02143 } 02144 02145 /** 02146 * @brief Clear Stream 5 half transfer flag. 02147 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5 02148 * @param DMAx DMAx Instance 02149 * @retval None 02150 */ 02151 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx) 02152 { 02153 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5); 02154 } 02155 02156 /** 02157 * @brief Clear Stream 6 half transfer flag. 02158 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6 02159 * @param DMAx DMAx Instance 02160 * @retval None 02161 */ 02162 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx) 02163 { 02164 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6); 02165 } 02166 02167 /** 02168 * @brief Clear Stream 7 half transfer flag. 02169 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7 02170 * @param DMAx DMAx Instance 02171 * @retval None 02172 */ 02173 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx) 02174 { 02175 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7); 02176 } 02177 02178 /** 02179 * @brief Clear Stream 0 transfer complete flag. 02180 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0 02181 * @param DMAx DMAx Instance 02182 * @retval None 02183 */ 02184 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx) 02185 { 02186 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0); 02187 } 02188 02189 /** 02190 * @brief Clear Stream 1 transfer complete flag. 02191 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1 02192 * @param DMAx DMAx Instance 02193 * @retval None 02194 */ 02195 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) 02196 { 02197 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1); 02198 } 02199 02200 /** 02201 * @brief Clear Stream 2 transfer complete flag. 02202 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2 02203 * @param DMAx DMAx Instance 02204 * @retval None 02205 */ 02206 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) 02207 { 02208 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2); 02209 } 02210 02211 /** 02212 * @brief Clear Stream 3 transfer complete flag. 02213 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3 02214 * @param DMAx DMAx Instance 02215 * @retval None 02216 */ 02217 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) 02218 { 02219 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3); 02220 } 02221 02222 /** 02223 * @brief Clear Stream 4 transfer complete flag. 02224 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4 02225 * @param DMAx DMAx Instance 02226 * @retval None 02227 */ 02228 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx) 02229 { 02230 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4); 02231 } 02232 02233 /** 02234 * @brief Clear Stream 5 transfer complete flag. 02235 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5 02236 * @param DMAx DMAx Instance 02237 * @retval None 02238 */ 02239 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx) 02240 { 02241 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5); 02242 } 02243 02244 /** 02245 * @brief Clear Stream 6 transfer complete flag. 02246 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6 02247 * @param DMAx DMAx Instance 02248 * @retval None 02249 */ 02250 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx) 02251 { 02252 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6); 02253 } 02254 02255 /** 02256 * @brief Clear Stream 7 transfer complete flag. 02257 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7 02258 * @param DMAx DMAx Instance 02259 * @retval None 02260 */ 02261 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx) 02262 { 02263 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7); 02264 } 02265 02266 /** 02267 * @brief Clear Stream 0 transfer error flag. 02268 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0 02269 * @param DMAx DMAx Instance 02270 * @retval None 02271 */ 02272 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx) 02273 { 02274 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0); 02275 } 02276 02277 /** 02278 * @brief Clear Stream 1 transfer error flag. 02279 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1 02280 * @param DMAx DMAx Instance 02281 * @retval None 02282 */ 02283 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) 02284 { 02285 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1); 02286 } 02287 02288 /** 02289 * @brief Clear Stream 2 transfer error flag. 02290 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2 02291 * @param DMAx DMAx Instance 02292 * @retval None 02293 */ 02294 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) 02295 { 02296 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2); 02297 } 02298 02299 /** 02300 * @brief Clear Stream 3 transfer error flag. 02301 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3 02302 * @param DMAx DMAx Instance 02303 * @retval None 02304 */ 02305 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) 02306 { 02307 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3); 02308 } 02309 02310 /** 02311 * @brief Clear Stream 4 transfer error flag. 02312 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4 02313 * @param DMAx DMAx Instance 02314 * @retval None 02315 */ 02316 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx) 02317 { 02318 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4); 02319 } 02320 02321 /** 02322 * @brief Clear Stream 5 transfer error flag. 02323 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5 02324 * @param DMAx DMAx Instance 02325 * @retval None 02326 */ 02327 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx) 02328 { 02329 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5); 02330 } 02331 02332 /** 02333 * @brief Clear Stream 6 transfer error flag. 02334 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6 02335 * @param DMAx DMAx Instance 02336 * @retval None 02337 */ 02338 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx) 02339 { 02340 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6); 02341 } 02342 02343 /** 02344 * @brief Clear Stream 7 transfer error flag. 02345 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7 02346 * @param DMAx DMAx Instance 02347 * @retval None 02348 */ 02349 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) 02350 { 02351 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7); 02352 } 02353 02354 /** 02355 * @brief Clear Stream 0 direct mode error flag. 02356 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0 02357 * @param DMAx DMAx Instance 02358 * @retval None 02359 */ 02360 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx) 02361 { 02362 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0); 02363 } 02364 02365 /** 02366 * @brief Clear Stream 1 direct mode error flag. 02367 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1 02368 * @param DMAx DMAx Instance 02369 * @retval None 02370 */ 02371 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx) 02372 { 02373 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1); 02374 } 02375 02376 /** 02377 * @brief Clear Stream 2 direct mode error flag. 02378 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2 02379 * @param DMAx DMAx Instance 02380 * @retval None 02381 */ 02382 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx) 02383 { 02384 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2); 02385 } 02386 02387 /** 02388 * @brief Clear Stream 3 direct mode error flag. 02389 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3 02390 * @param DMAx DMAx Instance 02391 * @retval None 02392 */ 02393 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx) 02394 { 02395 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3); 02396 } 02397 02398 /** 02399 * @brief Clear Stream 4 direct mode error flag. 02400 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4 02401 * @param DMAx DMAx Instance 02402 * @retval None 02403 */ 02404 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx) 02405 { 02406 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4); 02407 } 02408 02409 /** 02410 * @brief Clear Stream 5 direct mode error flag. 02411 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5 02412 * @param DMAx DMAx Instance 02413 * @retval None 02414 */ 02415 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx) 02416 { 02417 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5); 02418 } 02419 02420 /** 02421 * @brief Clear Stream 6 direct mode error flag. 02422 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6 02423 * @param DMAx DMAx Instance 02424 * @retval None 02425 */ 02426 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx) 02427 { 02428 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6); 02429 } 02430 02431 /** 02432 * @brief Clear Stream 7 direct mode error flag. 02433 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7 02434 * @param DMAx DMAx Instance 02435 * @retval None 02436 */ 02437 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx) 02438 { 02439 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7); 02440 } 02441 02442 /** 02443 * @brief Clear Stream 0 FIFO error flag. 02444 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0 02445 * @param DMAx DMAx Instance 02446 * @retval None 02447 */ 02448 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx) 02449 { 02450 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0); 02451 } 02452 02453 /** 02454 * @brief Clear Stream 1 FIFO error flag. 02455 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1 02456 * @param DMAx DMAx Instance 02457 * @retval None 02458 */ 02459 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx) 02460 { 02461 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1); 02462 } 02463 02464 /** 02465 * @brief Clear Stream 2 FIFO error flag. 02466 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2 02467 * @param DMAx DMAx Instance 02468 * @retval None 02469 */ 02470 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx) 02471 { 02472 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2); 02473 } 02474 02475 /** 02476 * @brief Clear Stream 3 FIFO error flag. 02477 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3 02478 * @param DMAx DMAx Instance 02479 * @retval None 02480 */ 02481 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx) 02482 { 02483 WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3); 02484 } 02485 02486 /** 02487 * @brief Clear Stream 4 FIFO error flag. 02488 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4 02489 * @param DMAx DMAx Instance 02490 * @retval None 02491 */ 02492 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx) 02493 { 02494 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4); 02495 } 02496 02497 /** 02498 * @brief Clear Stream 5 FIFO error flag. 02499 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5 02500 * @param DMAx DMAx Instance 02501 * @retval None 02502 */ 02503 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx) 02504 { 02505 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5); 02506 } 02507 02508 /** 02509 * @brief Clear Stream 6 FIFO error flag. 02510 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6 02511 * @param DMAx DMAx Instance 02512 * @retval None 02513 */ 02514 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx) 02515 { 02516 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6); 02517 } 02518 02519 /** 02520 * @brief Clear Stream 7 FIFO error flag. 02521 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7 02522 * @param DMAx DMAx Instance 02523 * @retval None 02524 */ 02525 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx) 02526 { 02527 WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7); 02528 } 02529 02530 /** 02531 * @} 02532 */ 02533 02534 /** @defgroup DMA_LL_EF_IT_Management IT_Management 02535 * @{ 02536 */ 02537 02538 /** 02539 * @brief Enable Half transfer interrupt. 02540 * @rmtoll CR HTIE LL_DMA_EnableIT_HT 02541 * @param DMAx DMAx Instance 02542 * @param Stream This parameter can be one of the following values: 02543 * @arg @ref LL_DMA_STREAM_0 02544 * @arg @ref LL_DMA_STREAM_1 02545 * @arg @ref LL_DMA_STREAM_2 02546 * @arg @ref LL_DMA_STREAM_3 02547 * @arg @ref LL_DMA_STREAM_4 02548 * @arg @ref LL_DMA_STREAM_5 02549 * @arg @ref LL_DMA_STREAM_6 02550 * @arg @ref LL_DMA_STREAM_7 02551 * @retval None 02552 */ 02553 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 02554 { 02555 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); 02556 } 02557 02558 /** 02559 * @brief Enable Transfer error interrupt. 02560 * @rmtoll CR TEIE LL_DMA_EnableIT_TE 02561 * @param DMAx DMAx Instance 02562 * @param Stream This parameter can be one of the following values: 02563 * @arg @ref LL_DMA_STREAM_0 02564 * @arg @ref LL_DMA_STREAM_1 02565 * @arg @ref LL_DMA_STREAM_2 02566 * @arg @ref LL_DMA_STREAM_3 02567 * @arg @ref LL_DMA_STREAM_4 02568 * @arg @ref LL_DMA_STREAM_5 02569 * @arg @ref LL_DMA_STREAM_6 02570 * @arg @ref LL_DMA_STREAM_7 02571 * @retval None 02572 */ 02573 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 02574 { 02575 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); 02576 } 02577 02578 /** 02579 * @brief Enable Transfer complete interrupt. 02580 * @rmtoll CR TCIE LL_DMA_EnableIT_TC 02581 * @param DMAx DMAx Instance 02582 * @param Stream This parameter can be one of the following values: 02583 * @arg @ref LL_DMA_STREAM_0 02584 * @arg @ref LL_DMA_STREAM_1 02585 * @arg @ref LL_DMA_STREAM_2 02586 * @arg @ref LL_DMA_STREAM_3 02587 * @arg @ref LL_DMA_STREAM_4 02588 * @arg @ref LL_DMA_STREAM_5 02589 * @arg @ref LL_DMA_STREAM_6 02590 * @arg @ref LL_DMA_STREAM_7 02591 * @retval None 02592 */ 02593 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 02594 { 02595 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); 02596 } 02597 02598 /** 02599 * @brief Enable Direct mode error interrupt. 02600 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME 02601 * @param DMAx DMAx Instance 02602 * @param Stream This parameter can be one of the following values: 02603 * @arg @ref LL_DMA_STREAM_0 02604 * @arg @ref LL_DMA_STREAM_1 02605 * @arg @ref LL_DMA_STREAM_2 02606 * @arg @ref LL_DMA_STREAM_3 02607 * @arg @ref LL_DMA_STREAM_4 02608 * @arg @ref LL_DMA_STREAM_5 02609 * @arg @ref LL_DMA_STREAM_6 02610 * @arg @ref LL_DMA_STREAM_7 02611 * @retval None 02612 */ 02613 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 02614 { 02615 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); 02616 } 02617 02618 /** 02619 * @brief Enable FIFO error interrupt. 02620 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE 02621 * @param DMAx DMAx Instance 02622 * @param Stream This parameter can be one of the following values: 02623 * @arg @ref LL_DMA_STREAM_0 02624 * @arg @ref LL_DMA_STREAM_1 02625 * @arg @ref LL_DMA_STREAM_2 02626 * @arg @ref LL_DMA_STREAM_3 02627 * @arg @ref LL_DMA_STREAM_4 02628 * @arg @ref LL_DMA_STREAM_5 02629 * @arg @ref LL_DMA_STREAM_6 02630 * @arg @ref LL_DMA_STREAM_7 02631 * @retval None 02632 */ 02633 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 02634 { 02635 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); 02636 } 02637 02638 /** 02639 * @brief Disable Half transfer interrupt. 02640 * @rmtoll CR HTIE LL_DMA_DisableIT_HT 02641 * @param DMAx DMAx Instance 02642 * @param Stream This parameter can be one of the following values: 02643 * @arg @ref LL_DMA_STREAM_0 02644 * @arg @ref LL_DMA_STREAM_1 02645 * @arg @ref LL_DMA_STREAM_2 02646 * @arg @ref LL_DMA_STREAM_3 02647 * @arg @ref LL_DMA_STREAM_4 02648 * @arg @ref LL_DMA_STREAM_5 02649 * @arg @ref LL_DMA_STREAM_6 02650 * @arg @ref LL_DMA_STREAM_7 02651 * @retval None 02652 */ 02653 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 02654 { 02655 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE); 02656 } 02657 02658 /** 02659 * @brief Disable Transfer error interrupt. 02660 * @rmtoll CR TEIE LL_DMA_DisableIT_TE 02661 * @param DMAx DMAx Instance 02662 * @param Stream This parameter can be one of the following values: 02663 * @arg @ref LL_DMA_STREAM_0 02664 * @arg @ref LL_DMA_STREAM_1 02665 * @arg @ref LL_DMA_STREAM_2 02666 * @arg @ref LL_DMA_STREAM_3 02667 * @arg @ref LL_DMA_STREAM_4 02668 * @arg @ref LL_DMA_STREAM_5 02669 * @arg @ref LL_DMA_STREAM_6 02670 * @arg @ref LL_DMA_STREAM_7 02671 * @retval None 02672 */ 02673 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 02674 { 02675 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE); 02676 } 02677 02678 /** 02679 * @brief Disable Transfer complete interrupt. 02680 * @rmtoll CR TCIE LL_DMA_DisableIT_TC 02681 * @param DMAx DMAx Instance 02682 * @param Stream This parameter can be one of the following values: 02683 * @arg @ref LL_DMA_STREAM_0 02684 * @arg @ref LL_DMA_STREAM_1 02685 * @arg @ref LL_DMA_STREAM_2 02686 * @arg @ref LL_DMA_STREAM_3 02687 * @arg @ref LL_DMA_STREAM_4 02688 * @arg @ref LL_DMA_STREAM_5 02689 * @arg @ref LL_DMA_STREAM_6 02690 * @arg @ref LL_DMA_STREAM_7 02691 * @retval None 02692 */ 02693 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 02694 { 02695 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE); 02696 } 02697 02698 /** 02699 * @brief Disable Direct mode error interrupt. 02700 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME 02701 * @param DMAx DMAx Instance 02702 * @param Stream This parameter can be one of the following values: 02703 * @arg @ref LL_DMA_STREAM_0 02704 * @arg @ref LL_DMA_STREAM_1 02705 * @arg @ref LL_DMA_STREAM_2 02706 * @arg @ref LL_DMA_STREAM_3 02707 * @arg @ref LL_DMA_STREAM_4 02708 * @arg @ref LL_DMA_STREAM_5 02709 * @arg @ref LL_DMA_STREAM_6 02710 * @arg @ref LL_DMA_STREAM_7 02711 * @retval None 02712 */ 02713 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 02714 { 02715 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE); 02716 } 02717 02718 /** 02719 * @brief Disable FIFO error interrupt. 02720 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE 02721 * @param DMAx DMAx Instance 02722 * @param Stream This parameter can be one of the following values: 02723 * @arg @ref LL_DMA_STREAM_0 02724 * @arg @ref LL_DMA_STREAM_1 02725 * @arg @ref LL_DMA_STREAM_2 02726 * @arg @ref LL_DMA_STREAM_3 02727 * @arg @ref LL_DMA_STREAM_4 02728 * @arg @ref LL_DMA_STREAM_5 02729 * @arg @ref LL_DMA_STREAM_6 02730 * @arg @ref LL_DMA_STREAM_7 02731 * @retval None 02732 */ 02733 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 02734 { 02735 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE); 02736 } 02737 02738 /** 02739 * @brief Check if Half transfer interrup is enabled. 02740 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT 02741 * @param DMAx DMAx Instance 02742 * @param Stream This parameter can be one of the following values: 02743 * @arg @ref LL_DMA_STREAM_0 02744 * @arg @ref LL_DMA_STREAM_1 02745 * @arg @ref LL_DMA_STREAM_2 02746 * @arg @ref LL_DMA_STREAM_3 02747 * @arg @ref LL_DMA_STREAM_4 02748 * @arg @ref LL_DMA_STREAM_5 02749 * @arg @ref LL_DMA_STREAM_6 02750 * @arg @ref LL_DMA_STREAM_7 02751 * @retval State of bit (1 or 0). 02752 */ 02753 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream) 02754 { 02755 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE); 02756 } 02757 02758 /** 02759 * @brief Check if Transfer error nterrup is enabled. 02760 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE 02761 * @param DMAx DMAx Instance 02762 * @param Stream This parameter can be one of the following values: 02763 * @arg @ref LL_DMA_STREAM_0 02764 * @arg @ref LL_DMA_STREAM_1 02765 * @arg @ref LL_DMA_STREAM_2 02766 * @arg @ref LL_DMA_STREAM_3 02767 * @arg @ref LL_DMA_STREAM_4 02768 * @arg @ref LL_DMA_STREAM_5 02769 * @arg @ref LL_DMA_STREAM_6 02770 * @arg @ref LL_DMA_STREAM_7 02771 * @retval State of bit (1 or 0). 02772 */ 02773 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream) 02774 { 02775 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE); 02776 } 02777 02778 /** 02779 * @brief Check if Transfer complete interrup is enabled. 02780 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC 02781 * @param DMAx DMAx Instance 02782 * @param Stream This parameter can be one of the following values: 02783 * @arg @ref LL_DMA_STREAM_0 02784 * @arg @ref LL_DMA_STREAM_1 02785 * @arg @ref LL_DMA_STREAM_2 02786 * @arg @ref LL_DMA_STREAM_3 02787 * @arg @ref LL_DMA_STREAM_4 02788 * @arg @ref LL_DMA_STREAM_5 02789 * @arg @ref LL_DMA_STREAM_6 02790 * @arg @ref LL_DMA_STREAM_7 02791 * @retval State of bit (1 or 0). 02792 */ 02793 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream) 02794 { 02795 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE); 02796 } 02797 02798 /** 02799 * @brief Check if Direct mode error interrupt is enabled. 02800 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME 02801 * @param DMAx DMAx Instance 02802 * @param Stream This parameter can be one of the following values: 02803 * @arg @ref LL_DMA_STREAM_0 02804 * @arg @ref LL_DMA_STREAM_1 02805 * @arg @ref LL_DMA_STREAM_2 02806 * @arg @ref LL_DMA_STREAM_3 02807 * @arg @ref LL_DMA_STREAM_4 02808 * @arg @ref LL_DMA_STREAM_5 02809 * @arg @ref LL_DMA_STREAM_6 02810 * @arg @ref LL_DMA_STREAM_7 02811 * @retval State of bit (1 or 0). 02812 */ 02813 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream) 02814 { 02815 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE); 02816 } 02817 02818 /** 02819 * @brief Check if FIFO error interrup is enabled. 02820 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE 02821 * @param DMAx DMAx Instance 02822 * @param Stream This parameter can be one of the following values: 02823 * @arg @ref LL_DMA_STREAM_0 02824 * @arg @ref LL_DMA_STREAM_1 02825 * @arg @ref LL_DMA_STREAM_2 02826 * @arg @ref LL_DMA_STREAM_3 02827 * @arg @ref LL_DMA_STREAM_4 02828 * @arg @ref LL_DMA_STREAM_5 02829 * @arg @ref LL_DMA_STREAM_6 02830 * @arg @ref LL_DMA_STREAM_7 02831 * @retval State of bit (1 or 0). 02832 */ 02833 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream) 02834 { 02835 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE); 02836 } 02837 02838 /** 02839 * @} 02840 */ 02841 02842 #if defined(USE_FULL_LL_DRIVER) 02843 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions 02844 * @{ 02845 */ 02846 02847 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct); 02848 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream); 02849 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); 02850 02851 /** 02852 * @} 02853 */ 02854 #endif /* USE_FULL_LL_DRIVER */ 02855 02856 /** 02857 * @} 02858 */ 02859 02860 /** 02861 * @} 02862 */ 02863 02864 #endif /* DMA1 || DMA2 */ 02865 02866 /** 02867 * @} 02868 */ 02869 02870 #ifdef __cplusplus 02871 } 02872 #endif 02873 02874 #endif /* __STM32F4xx_LL_DMA_H */ 02875 02876 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1.7.6.1